* [PATCH 6.12.y-cip 01/18] clk: renesas: cpg-mssr: Simplify pointer math in cpg_rzt2h_mstp_read()
2026-08-21 13:15 [PATCH 6.12.y-cip 00/18] Add ICU support for RZ/T2H and RZ/N2H SoCs Cosmin Tanislav
@ 2026-08-21 13:15 ` Cosmin Tanislav
2026-08-21 13:15 ` [PATCH 6.12.y-cip 02/18] clk: renesas: cpg-mssr: Handle RZ/T2H register layout in PM callbacks Cosmin Tanislav
` (17 subsequent siblings)
18 siblings, 0 replies; 23+ messages in thread
From: Cosmin Tanislav @ 2026-08-21 13:15 UTC (permalink / raw)
To: cip-dev, pavel, nobuhiro.iwamatsu.x90
commit 21c1d66a1672573c1934734570bd3b05a301af9e upstream.
Private state is available in all places where cpg_rzt2h_mstp_read() is
called, remove the extra pointer math used to find it from clk_hw.
While at it, put these statements on a single line as they do not exceed
the 80 columns limit.
Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20251127145654.3253992-2-cosmin-gabriel.tanislav.xa@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com>
---
drivers/clk/renesas/renesas-cpg-mssr.c | 20 ++++++--------------
1 file changed, 6 insertions(+), 14 deletions(-)
diff --git a/drivers/clk/renesas/renesas-cpg-mssr.c b/drivers/clk/renesas/renesas-cpg-mssr.c
index ab4a1263b9fb..fee13c0bc095 100644
--- a/drivers/clk/renesas/renesas-cpg-mssr.c
+++ b/drivers/clk/renesas/renesas-cpg-mssr.c
@@ -237,20 +237,16 @@ struct mstp_clock {
#define to_mstp_clock(_hw) container_of(_hw, struct mstp_clock, hw)
-static u32 cpg_rzt2h_mstp_read(struct clk_hw *hw, u16 offset)
+static u32 cpg_rzt2h_mstp_read(struct cpg_mssr_priv *priv, u16 offset)
{
- struct mstp_clock *clock = to_mstp_clock(hw);
- struct cpg_mssr_priv *priv = clock->priv;
void __iomem *base =
RZT2H_MSTPCR_BLOCK(offset) ? priv->pub.base1 : priv->pub.base0;
return readl(base + RZT2H_MSTPCR_OFFSET(offset));
}
-static void cpg_rzt2h_mstp_write(struct clk_hw *hw, u16 offset, u32 value)
+static void cpg_rzt2h_mstp_write(struct cpg_mssr_priv *priv, u16 offset, u32 value)
{
- struct mstp_clock *clock = to_mstp_clock(hw);
- struct cpg_mssr_priv *priv = clock->priv;
void __iomem *base =
RZT2H_MSTPCR_BLOCK(offset) ? priv->pub.base1 : priv->pub.base0;
@@ -286,17 +282,14 @@ static int cpg_mstp_clock_endisable(struct clk_hw *hw, bool enable)
barrier_data(priv->pub.base0 + priv->control_regs[reg]);
} else if (priv->reg_layout == CLK_REG_LAYOUT_RZ_T2H) {
- value = cpg_rzt2h_mstp_read(hw,
- priv->control_regs[reg]);
+ value = cpg_rzt2h_mstp_read(priv, priv->control_regs[reg]);
if (enable)
value &= ~bitmask;
else
value |= bitmask;
- cpg_rzt2h_mstp_write(hw,
- priv->control_regs[reg],
- value);
+ cpg_rzt2h_mstp_write(priv, priv->control_regs[reg], value);
} else {
value = readl(priv->pub.base0 + priv->control_regs[reg]);
if (enable)
@@ -318,7 +311,7 @@ static int cpg_mstp_clock_endisable(struct clk_hw *hw, bool enable)
* the IP at least seven times. Instead of memory-mapping the IP
* register, we simply add a delay after the read operation.
*/
- cpg_rzt2h_mstp_read(hw, priv->control_regs[reg]);
+ cpg_rzt2h_mstp_read(priv, priv->control_regs[reg]);
udelay(10);
return 0;
}
@@ -352,8 +345,7 @@ static int cpg_mstp_clock_is_enabled(struct clk_hw *hw)
if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A)
value = readb(priv->pub.base0 + priv->control_regs[reg]);
else if (priv->reg_layout == CLK_REG_LAYOUT_RZ_T2H)
- value = cpg_rzt2h_mstp_read(hw,
- priv->control_regs[reg]);
+ value = cpg_rzt2h_mstp_read(priv, priv->control_regs[reg]);
else
value = readl(priv->pub.base0 + priv->status_regs[reg]);
--
2.55.0
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH 6.12.y-cip 02/18] clk: renesas: cpg-mssr: Handle RZ/T2H register layout in PM callbacks
2026-08-21 13:15 [PATCH 6.12.y-cip 00/18] Add ICU support for RZ/T2H and RZ/N2H SoCs Cosmin Tanislav
2026-08-21 13:15 ` [PATCH 6.12.y-cip 01/18] clk: renesas: cpg-mssr: Simplify pointer math in cpg_rzt2h_mstp_read() Cosmin Tanislav
@ 2026-08-21 13:15 ` Cosmin Tanislav
2026-08-21 13:15 ` [PATCH 6.12.y-cip 03/18] net: phylink: add phylink_prepare_resume() Cosmin Tanislav
` (16 subsequent siblings)
18 siblings, 0 replies; 23+ messages in thread
From: Cosmin Tanislav @ 2026-08-21 13:15 UTC (permalink / raw)
To: cip-dev, pavel, nobuhiro.iwamatsu.x90
commit 3132ec8c8c2c28787d0ad80e53db296713155f12 upstream.
The register layout for RZ/T2H is not handled inside
cpg_mssr_suspend_noirq() and cpg_mssr_resume_noirq(), causing a memory
abort because the wrong code path is taken, as shown below.
Explicitly handle the RZ/T2H register layout in cpg_mssr_suspend_noirq()
and cpg_mssr_resume_noirq(), similar to how it is done inside
cpg_mstp_clock_is_enabled() and cpg_mstp_clock_endisable().
[ 90.052296] Mem abort info:
[ 90.055420] ESR = 0x0000000096000007
[ 90.059553] EC = 0x25: DABT (current EL), IL = 32 bits
[ 90.065697] SET = 0, FnV = 0
[ 90.069211] EA = 0, S1PTW = 0
[ 90.072834] FSC = 0x07: level 3 translation fault
[ 90.078109] Data abort info:
[ 90.081405] ISV = 0, ISS = 0x00000007, ISS2 = 0x00000000
[ 90.087427] CM = 0, WnR = 0, TnD = 0, TagAccess = 0
[ 90.093169] GCS = 0, Overlay = 0, DirtyBit = 0, Xs = 0
[ 90.099008] swapper pgtable: 4k pages, 48-bit VAs, pgdp=00000000c60b4000
[ 90.106756] [ffff800082816318] pgd=0000000000000000, p4d=10000000c69ef003, pud=10000000c69f0003, pmd=100000024002b403, pte=0000000000000000
[ 90.120727] Internal error: Oops: 0000000096000007 [#1] SMP
[ 90.127058] Modules linked in: sha256 cfg80211 spi_nor at24 renesas_usbhs bluetooth ecdh_generic ecc rfkill rzt2h_adc spi_rzv2h_rspi industrialio_adc gpio_keys fuse drm backlight ipv6
[ 90.145201] CPU: 0 UID: 0 PID: 307 Comm: sh Not tainted 6.18.0-rc1-next-20251016+ #47 PREEMPT
[ 90.155006] Hardware name: Renesas RZ/T2H EVK Board based on r9a09g077m44 (DT)
[ 90.163041] pstate: 20400005 (nzCv daif +PAN -UAO -TCO -DIT -SSBS BTYPE=--)
[ 90.170777] pc : cpg_mssr_suspend_noirq+0x4c/0xc0
[ 90.175983] lr : device_suspend_noirq+0x6c/0x22c
[ 90.181309] sp : ffff8000838d3af0
[ 90.185026] x29: ffff8000838d3af0 x28: ffff8000825c016f x27: ffff8000825c01a0
[ 90.192973] x26: ffff8000809feeec x25: ffff8000827bebb8 x24: 0000000000000002
[ 90.200815] x23: ffff8000825c0190 x22: 0000000000000002 x21: 0000000000000000
[ 90.209058] x20: ffff8000827bebb8 x19: ffff000180128010 x18: ffff00033ef92a80
[ 90.217100] x17: ffff000180051700 x16: 0000000000000001 x15: ffff000187afc310
[ 90.224847] x14: 0000000000000254 x13: 0000000000000001 x12: 0000000000000001
[ 90.232793] x11: 00000000000000c0 x10: 0000000000000ab0 x9 : ffff8000838d38b0
[ 90.240540] x8 : ffff000186387410 x7 : 0000000000000001 x6 : 0000000000000000
[ 90.248600] x5 : ffff0001803240d4 x4 : 0000000000000003 x3 : ffff0001803240d0
[ 90.256460] x2 : ffff800082816318 x1 : 000000000000000c x0 : ffff000180324000
[ 90.264208] Call trace:
[ 90.267019] cpg_mssr_suspend_noirq+0x4c/0xc0 (P)
[ 90.272450] device_suspend_noirq+0x6c/0x22c
[ 90.277375] dpm_noirq_suspend_devices+0x1a8/0x2a0
[ 90.282902] dpm_suspend_noirq+0x24/0xa0
[ 90.287428] suspend_devices_and_enter+0x310/0x590
[ 90.292790] pm_suspend+0x1b4/0x200
[ 90.296811] state_store+0x80/0xf4
[ 90.300676] kobj_attr_store+0x18/0x34
[ 90.305002] sysfs_kf_write+0x7c/0x94
[ 90.309232] kernfs_fop_write_iter+0x12c/0x200
[ 90.314115] vfs_write+0x240/0x380
[ 90.318041] ksys_write+0x64/0x100
[ 90.321862] __arm64_sys_write+0x18/0x24
[ 90.326013] invoke_syscall.constprop.0+0x40/0xf0
[ 90.331445] el0_svc_common.constprop.0+0xb8/0xd8
[ 90.336554] do_el0_svc+0x1c/0x28
[ 90.340375] el0_svc+0x34/0xe8
[ 90.343900] el0t_64_sync_handler+0xa0/0xe4
[ 90.348426] el0t_64_sync+0x198/0x19c
[ 90.352609] Code: 8b040042 b9409004 7100049f 54000240 (b9400042)
[ 90.359639] ---[ end trace 0000000000000000 ]---
Fixes: 065fe720eec6 ("clk: renesas: Add support for R9A09G077 SoC")
Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20251127145654.3253992-3-cosmin-gabriel.tanislav.xa@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com>
---
drivers/clk/renesas/renesas-cpg-mssr.c | 26 +++++++++++++++++++++-----
1 file changed, 21 insertions(+), 5 deletions(-)
diff --git a/drivers/clk/renesas/renesas-cpg-mssr.c b/drivers/clk/renesas/renesas-cpg-mssr.c
index fee13c0bc095..1b505de9dcd3 100644
--- a/drivers/clk/renesas/renesas-cpg-mssr.c
+++ b/drivers/clk/renesas/renesas-cpg-mssr.c
@@ -1086,11 +1086,19 @@ static int cpg_mssr_suspend_noirq(struct device *dev)
/* Save module registers with bits under our control */
for (reg = 0; reg < ARRAY_SIZE(priv->smstpcr_saved); reg++) {
- if (priv->smstpcr_saved[reg].mask)
- priv->smstpcr_saved[reg].val =
- priv->reg_layout == CLK_REG_LAYOUT_RZ_A ?
- readb(priv->pub.base0 + priv->control_regs[reg]) :
- readl(priv->pub.base0 + priv->control_regs[reg]);
+ u32 val;
+
+ if (!priv->smstpcr_saved[reg].mask)
+ continue;
+
+ if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A)
+ val = readb(priv->pub.base0 + priv->control_regs[reg]);
+ else if (priv->reg_layout == CLK_REG_LAYOUT_RZ_T2H)
+ val = cpg_rzt2h_mstp_read(priv, priv->control_regs[reg]);
+ else
+ val = readl(priv->pub.base0 + priv->control_regs[reg]);
+
+ priv->smstpcr_saved[reg].val = val;
}
/* Save core clocks */
@@ -1121,6 +1129,8 @@ static int cpg_mssr_resume_noirq(struct device *dev)
if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A)
oldval = readb(priv->pub.base0 + priv->control_regs[reg]);
+ else if (priv->reg_layout == CLK_REG_LAYOUT_RZ_T2H)
+ oldval = cpg_rzt2h_mstp_read(priv, priv->control_regs[reg]);
else
oldval = readl(priv->pub.base0 + priv->control_regs[reg]);
newval = oldval & ~mask;
@@ -1134,6 +1144,12 @@ static int cpg_mssr_resume_noirq(struct device *dev)
readb(priv->pub.base0 + priv->control_regs[reg]);
barrier_data(priv->pub.base0 + priv->control_regs[reg]);
continue;
+ } else if (priv->reg_layout == CLK_REG_LAYOUT_RZ_T2H) {
+ cpg_rzt2h_mstp_write(priv, priv->control_regs[reg], newval);
+ /* See cpg_mstp_clock_endisable() on why this is necessary. */
+ cpg_rzt2h_mstp_read(priv, priv->control_regs[reg]);
+ udelay(10);
+ continue;
} else
writel(newval, priv->pub.base0 + priv->control_regs[reg]);
--
2.55.0
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH 6.12.y-cip 03/18] net: phylink: add phylink_prepare_resume()
2026-08-21 13:15 [PATCH 6.12.y-cip 00/18] Add ICU support for RZ/T2H and RZ/N2H SoCs Cosmin Tanislav
2026-08-21 13:15 ` [PATCH 6.12.y-cip 01/18] clk: renesas: cpg-mssr: Simplify pointer math in cpg_rzt2h_mstp_read() Cosmin Tanislav
2026-08-21 13:15 ` [PATCH 6.12.y-cip 02/18] clk: renesas: cpg-mssr: Handle RZ/T2H register layout in PM callbacks Cosmin Tanislav
@ 2026-08-21 13:15 ` Cosmin Tanislav
2026-08-21 13:15 ` [PATCH 6.12.y-cip 04/18] net: stmmac: simplify phylink_suspend() and phylink_resume() calls Cosmin Tanislav
` (15 subsequent siblings)
18 siblings, 0 replies; 23+ messages in thread
From: Cosmin Tanislav @ 2026-08-21 13:15 UTC (permalink / raw)
To: cip-dev, pavel, nobuhiro.iwamatsu.x90
From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
commit 367f1854d442b33c4a0305b068ae40d67ccd7d6a upstream.
When the system is suspended, the PHY may be placed in low-power mode
by setting the BMCR 0.11 Power down bit. IEEE 802.3 states that the
behaviour of the PHY in this state is implementation specific, and
the PHY is not required to meet the RX_CLK and TX_CLK requirements.
Essentially, this means that a PHY may stop the clocks that it is
generating while in power down state.
However, MACs exist which require the clocks from the PHY to be running
in order to properly resume. phylink_prepare_resume() provides them
with a way to clear the Power down bit early.
Note, however, that IEEE 802.3 gives PHYs up to 500ms grace before the
transmit and receive clocks meet the requirements after clearing the
power down bit.
Add a resume preparation function, which will ensure that the receive
clock from the PHY is appropriately configured while resuming.
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
Link: https://patch.msgid.link/E1tvO6V-008Vjb-AP@rmk-PC.armlinux.org.uk
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com>
---
drivers/net/phy/phylink.c | 25 +++++++++++++++++++++++++
include/linux/phylink.h | 1 +
2 files changed, 26 insertions(+)
diff --git a/drivers/net/phy/phylink.c b/drivers/net/phy/phylink.c
index e6f3963739ad..5f5f032ba630 100644
--- a/drivers/net/phy/phylink.c
+++ b/drivers/net/phy/phylink.c
@@ -2353,6 +2353,31 @@ void phylink_suspend(struct phylink *pl, bool mac_wol)
}
EXPORT_SYMBOL_GPL(phylink_suspend);
+/**
+ * phylink_prepare_resume() - prepare to resume a network device
+ * @pl: a pointer to a &struct phylink returned from phylink_create()
+ *
+ * Optional, but if called must be called prior to phylink_resume().
+ *
+ * Prepare to resume a network device, preparing the PHY as necessary.
+ */
+void phylink_prepare_resume(struct phylink *pl)
+{
+ struct phy_device *phydev = pl->phydev;
+
+ ASSERT_RTNL();
+
+ /* IEEE 802.3 22.2.4.1.5 allows PHYs to stop their receive clock
+ * when PDOWN is set. However, some MACs require RXC to be running
+ * in order to resume. If the MAC requires RXC, and we have a PHY,
+ * then resume the PHY. Note that 802.3 allows PHYs 500ms before
+ * the clock meets requirements. We do not implement this delay.
+ */
+ if (pl->config->mac_requires_rxc && phydev && phydev->suspended)
+ phy_resume(phydev);
+}
+EXPORT_SYMBOL_GPL(phylink_prepare_resume);
+
/**
* phylink_resume() - handle a network device resume event
* @pl: a pointer to a &struct phylink returned from phylink_create()
diff --git a/include/linux/phylink.h b/include/linux/phylink.h
index 5c01048860c4..62d09a7e7869 100644
--- a/include/linux/phylink.h
+++ b/include/linux/phylink.h
@@ -610,6 +610,7 @@ void phylink_start(struct phylink *);
void phylink_stop(struct phylink *);
void phylink_suspend(struct phylink *pl, bool mac_wol);
+void phylink_prepare_resume(struct phylink *pl);
void phylink_resume(struct phylink *pl);
void phylink_ethtool_get_wol(struct phylink *, struct ethtool_wolinfo *);
--
2.55.0
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH 6.12.y-cip 04/18] net: stmmac: simplify phylink_suspend() and phylink_resume() calls
2026-08-21 13:15 [PATCH 6.12.y-cip 00/18] Add ICU support for RZ/T2H and RZ/N2H SoCs Cosmin Tanislav
` (2 preceding siblings ...)
2026-08-21 13:15 ` [PATCH 6.12.y-cip 03/18] net: phylink: add phylink_prepare_resume() Cosmin Tanislav
@ 2026-08-21 13:15 ` Cosmin Tanislav
2026-08-21 13:15 ` [PATCH 6.12.y-cip 05/18] net: stmmac: address non-LPI resume failures properly Cosmin Tanislav
` (14 subsequent siblings)
18 siblings, 0 replies; 23+ messages in thread
From: Cosmin Tanislav @ 2026-08-21 13:15 UTC (permalink / raw)
To: cip-dev, pavel, nobuhiro.iwamatsu.x90
From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
commit f732549eb303d7e382f5101b82bb6852ad4ad642 upstream.
Currently, the calls to phylink's suspend and resume functions are
inside overly complex tests, and boil down to:
if (device_may_wakeup(priv->device) && priv->plat->pmt) {
call phylink
} else {
call phylink and
if (device_may_wakeup(priv->device))
do something else
}
This results in phylink always being called, possibly with differing
arguments for phylink_suspend().
Simplify this code, noting that each site is slightly different due to
the order in which phylink is called and the "something else".
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
Reviewed-by: Simon Horman <horms@kernel.org>
Link: https://patch.msgid.link/E1tpQL1-005St4-Hn@rmk-PC.armlinux.org.uk
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com>
---
.../net/ethernet/stmicro/stmmac/stmmac_main.c | 22 +++++++------------
1 file changed, 8 insertions(+), 14 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
index 6cdf9ddfabfc..8187e6934668 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
@@ -7950,13 +7950,11 @@ int stmmac_suspend(struct device *dev)
mutex_unlock(&priv->lock);
rtnl_lock();
- if (device_may_wakeup(priv->device) && priv->plat->pmt) {
- phylink_suspend(priv->phylink, true);
- } else {
- if (device_may_wakeup(priv->device))
- phylink_speed_down(priv->phylink, false);
- phylink_suspend(priv->phylink, false);
- }
+ if (device_may_wakeup(priv->device) && !priv->plat->pmt)
+ phylink_speed_down(priv->phylink, false);
+
+ phylink_suspend(priv->phylink,
+ device_may_wakeup(priv->device) && priv->plat->pmt);
rtnl_unlock();
if (priv->dma_cap.fpesel)
@@ -8046,13 +8044,9 @@ int stmmac_resume(struct device *dev)
}
rtnl_lock();
- if (device_may_wakeup(priv->device) && priv->plat->pmt) {
- phylink_resume(priv->phylink);
- } else {
- phylink_resume(priv->phylink);
- if (device_may_wakeup(priv->device))
- phylink_speed_up(priv->phylink);
- }
+ phylink_resume(priv->phylink);
+ if (device_may_wakeup(priv->device) && !priv->plat->pmt)
+ phylink_speed_up(priv->phylink);
rtnl_unlock();
rtnl_lock();
--
2.55.0
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH 6.12.y-cip 05/18] net: stmmac: address non-LPI resume failures properly
2026-08-21 13:15 [PATCH 6.12.y-cip 00/18] Add ICU support for RZ/T2H and RZ/N2H SoCs Cosmin Tanislav
` (3 preceding siblings ...)
2026-08-21 13:15 ` [PATCH 6.12.y-cip 04/18] net: stmmac: simplify phylink_suspend() and phylink_resume() calls Cosmin Tanislav
@ 2026-08-21 13:15 ` Cosmin Tanislav
2026-08-21 13:15 ` [PATCH 6.12.y-cip 06/18] dt-bindings: interrupt-controller: Document RZ/{T2H,N2H} ICU Cosmin Tanislav
` (13 subsequent siblings)
18 siblings, 0 replies; 23+ messages in thread
From: Cosmin Tanislav @ 2026-08-21 13:15 UTC (permalink / raw)
To: cip-dev, pavel, nobuhiro.iwamatsu.x90
From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
commit ef43e5132895ad59b45e38855d32e966bb7434d9 upstream.
The Synopsys Designware GMAC core databook requires all clocks to be
active in order to complete software reset, which we perform during
resume.
However, IEEE 802.3 allows a PHY to stop its clocks when placed in
low-power mode, which happens when the system is suspended and WoL
is not enabled.
As an attempt to work around this, commit 36d18b5664ef ("net: stmmac:
start phylink instance before stmmac_hw_setup()") started phylink
early, but this has the side effect that the mac_link_up() method may
be called before or during the initialisation of GMAC hardware.
We also have the socfpga glue driver directly calling phy_resume()
also as an attempt to work around this.
In a previous commit, phylink_prepare_resume() has been introduced
to give MAC drivers a way to ensure that the PHY is resumed prior to
their initialisation of their MAC hardware. This commit adds the call,
and moves the phylink_resume() call back to where it should be before
the aforementioned commit.
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
Link: https://patch.msgid.link/E1tvO6a-008Vjh-FG@rmk-PC.armlinux.org.uk
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com>
---
.../net/ethernet/stmicro/stmmac/stmmac_main.c | 19 ++++++++++++++-----
1 file changed, 14 insertions(+), 5 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
index 8187e6934668..cccf44b47909 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
@@ -8044,12 +8044,12 @@ int stmmac_resume(struct device *dev)
}
rtnl_lock();
- phylink_resume(priv->phylink);
- if (device_may_wakeup(priv->device) && !priv->plat->pmt)
- phylink_speed_up(priv->phylink);
- rtnl_unlock();
- rtnl_lock();
+ /* Prepare the PHY to resume, ensuring that its clocks which are
+ * necessary for the MAC DMA reset to complete are running
+ */
+ phylink_prepare_resume(priv->phylink);
+
mutex_lock(&priv->lock);
stmmac_reset_queues_param(priv);
@@ -8074,6 +8074,15 @@ int stmmac_resume(struct device *dev)
stmmac_enable_all_dma_irq(priv);
mutex_unlock(&priv->lock);
+
+ /* phylink_resume() must be called after the hardware has been
+ * initialised because it may bring the link up immediately in a
+ * workqueue thread, which will race with initialisation.
+ */
+ phylink_resume(priv->phylink);
+ if (device_may_wakeup(priv->device) && !priv->plat->pmt)
+ phylink_speed_up(priv->phylink);
+
rtnl_unlock();
netif_device_attach(ndev);
--
2.55.0
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH 6.12.y-cip 06/18] dt-bindings: interrupt-controller: Document RZ/{T2H,N2H} ICU
2026-08-21 13:15 [PATCH 6.12.y-cip 00/18] Add ICU support for RZ/T2H and RZ/N2H SoCs Cosmin Tanislav
` (4 preceding siblings ...)
2026-08-21 13:15 ` [PATCH 6.12.y-cip 05/18] net: stmmac: address non-LPI resume failures properly Cosmin Tanislav
@ 2026-08-21 13:15 ` Cosmin Tanislav
2026-08-21 13:15 ` [PATCH 6.12.y-cip 07/18] dt-bindings: pinctrl: renesas,r9a09g077-pinctrl: Document GPIO IRQ Cosmin Tanislav
` (12 subsequent siblings)
18 siblings, 0 replies; 23+ messages in thread
From: Cosmin Tanislav @ 2026-08-21 13:15 UTC (permalink / raw)
To: cip-dev, pavel, nobuhiro.iwamatsu.x90
commit a6568d82091d279c8fbcdb1d30b46c23756b9145 upstream.
The Renesas RZ/T2H (R9A09G077) and Renesas RZ/N2H (R9A09G087) SoCs have an
Interrupt Controller (ICU) block that routes external interrupts to the
GIC's SPIs, with the ability of level-translation, and can also produce
software interrupts and aggregate error interrupts.
It has 16 software triggered interrupts (INTCPUn), 16 external pin
interrupts (IRQn), a System error interrupt (SEI), two Cortex-A55 error
interrupts (CA55_ERRn), two Cortex-R52 error interrupts for each of the two
cores (CR52x_ERRn), two Peripheral error interrupts (PERI_ERRn), two DSMIF
error interrupts (DSMIF_ERRn), and two ENCIF error interrupts (ENCIF_ERRn).
The IRQn and SEI interrupts are exposed externally, while the others are
software triggered.
INTCPU0 to INTCPU13, IRQ 0 to IRQ13 are non-safety interrupts, while
INTCPU14, INTCPU15, IRQ14, IRQ15 and SEI are safety interrupts, and are
exposed via a separate register space.
Document them, and use RZ/T2H as a fallback for RZ/N2H as the ICU is
entirely compatible.
Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://patch.msgid.link/20251201112933.488801-2-cosmin-gabriel.tanislav.xa@renesas.com
Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com>
---
.../renesas,r9a09g077-icu.yaml | 236 ++++++++++++++++++
1 file changed, 236 insertions(+)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/renesas,r9a09g077-icu.yaml
diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas,r9a09g077-icu.yaml b/Documentation/devicetree/bindings/interrupt-controller/renesas,r9a09g077-icu.yaml
new file mode 100644
index 000000000000..78c01d14e765
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,r9a09g077-icu.yaml
@@ -0,0 +1,236 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/renesas,r9a09g077-icu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas RZ/{T2H,N2H} Interrupt Controller
+
+maintainers:
+ - Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com>
+
+allOf:
+ - $ref: /schemas/interrupt-controller.yaml#
+
+description:
+ The Interrupt Controller (ICU) handles software-triggered interrupts
+ (INTCPU), external interrupts (IRQ and SEI), error interrupts and DMAC
+ requests.
+
+properties:
+ compatible:
+ oneOf:
+ - const: renesas,r9a09g077-icu # RZ/T2H
+
+ - items:
+ - enum:
+ - renesas,r9a09g087-icu # RZ/N2H
+ - const: renesas,r9a09g077-icu
+
+ reg:
+ items:
+ - description: Non-safety registers (INTCPU0-13, IRQ0-13)
+ - description: Safety registers (INTCPU14-15, IRQ14-15, SEI)
+
+ '#interrupt-cells':
+ description: The first cell is the SPI number of the interrupt, as per user
+ manual. The second cell is used to specify the flag.
+ const: 2
+
+ '#address-cells':
+ const: 0
+
+ interrupt-controller: true
+
+ interrupts:
+ items:
+ - description: Software interrupt 0
+ - description: Software interrupt 1
+ - description: Software interrupt 2
+ - description: Software interrupt 3
+ - description: Software interrupt 4
+ - description: Software interrupt 5
+ - description: Software interrupt 6
+ - description: Software interrupt 7
+ - description: Software interrupt 8
+ - description: Software interrupt 9
+ - description: Software interrupt 10
+ - description: Software interrupt 11
+ - description: Software interrupt 12
+ - description: Software interrupt 13
+ - description: Software interrupt 14
+ - description: Software interrupt 15
+ - description: External pin interrupt 0
+ - description: External pin interrupt 1
+ - description: External pin interrupt 2
+ - description: External pin interrupt 3
+ - description: External pin interrupt 4
+ - description: External pin interrupt 5
+ - description: External pin interrupt 6
+ - description: External pin interrupt 7
+ - description: External pin interrupt 8
+ - description: External pin interrupt 9
+ - description: External pin interrupt 10
+ - description: External pin interrupt 11
+ - description: External pin interrupt 12
+ - description: External pin interrupt 13
+ - description: External pin interrupt 14
+ - description: External pin interrupt 15
+ - description: System error interrupt
+ - description: Cortex-A55 error event 0
+ - description: Cortex-A55 error event 1
+ - description: Cortex-R52 CPU 0 error event 0
+ - description: Cortex-R52 CPU 0 error event 1
+ - description: Cortex-R52 CPU 1 error event 0
+ - description: Cortex-R52 CPU 1 error event 1
+ - description: Peripherals error event 0
+ - description: Peripherals error event 1
+ - description: DSMIF error event 0
+ - description: DSMIF error event 1
+ - description: ENCIF error event 0
+ - description: ENCIF error event 1
+
+ interrupt-names:
+ items:
+ - const: intcpu0
+ - const: intcpu1
+ - const: intcpu2
+ - const: intcpu3
+ - const: intcpu4
+ - const: intcpu5
+ - const: intcpu6
+ - const: intcpu7
+ - const: intcpu8
+ - const: intcpu9
+ - const: intcpu10
+ - const: intcpu11
+ - const: intcpu12
+ - const: intcpu13
+ - const: intcpu14
+ - const: intcpu15
+ - const: irq0
+ - const: irq1
+ - const: irq2
+ - const: irq3
+ - const: irq4
+ - const: irq5
+ - const: irq6
+ - const: irq7
+ - const: irq8
+ - const: irq9
+ - const: irq10
+ - const: irq11
+ - const: irq12
+ - const: irq13
+ - const: irq14
+ - const: irq15
+ - const: sei
+ - const: ca55-err0
+ - const: ca55-err1
+ - const: cr520-err0
+ - const: cr520-err1
+ - const: cr521-err0
+ - const: cr521-err1
+ - const: peri-err0
+ - const: peri-err1
+ - const: dsmif-err0
+ - const: dsmif-err1
+ - const: encif-err0
+ - const: encif-err1
+
+ clocks:
+ maxItems: 1
+
+ power-domains:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - '#interrupt-cells'
+ - '#address-cells'
+ - interrupt-controller
+ - interrupts
+ - interrupt-names
+ - clocks
+ - power-domains
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h>
+
+ icu: interrupt-controller@802a0000 {
+ compatible = "renesas,r9a09g077-icu";
+ reg = <0x802a0000 0x10000>,
+ <0x812a0000 0x50>;
+ #interrupt-cells = <2>;
+ #address-cells = <0>;
+ interrupt-controller;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 1 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 2 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 4 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 5 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 6 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 7 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 8 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 9 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 10 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 11 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 12 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 13 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 14 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 15 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 16 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 17 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 18 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 20 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 23 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 24 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 28 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 29 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 30 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 31 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 406 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 407 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 408 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 409 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 410 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 411 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 412 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 413 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 414 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 415 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 416 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 417 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 418 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "intcpu0", "intcpu1", "intcpu2",
+ "intcpu3", "intcpu4", "intcpu5",
+ "intcpu6", "intcpu7", "intcpu8",
+ "intcpu9", "intcpu10", "intcpu11",
+ "intcpu12", "intcpu13", "intcpu14",
+ "intcpu15",
+ "irq0", "irq1", "irq2", "irq3",
+ "irq4", "irq5", "irq6", "irq7",
+ "irq8", "irq9", "irq10", "irq11",
+ "irq12", "irq13", "irq14", "irq15",
+ "sei",
+ "ca55-err0", "ca55-err1",
+ "cr520-err0", "cr520-err1",
+ "cr521-err0", "cr521-err1",
+ "peri-err0", "peri-err1",
+ "dsmif-err0", "dsmif-err1",
+ "encif-err0", "encif-err1";
+ clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKM>;
+ power-domains = <&cpg>;
+ };
--
2.55.0
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH 6.12.y-cip 07/18] dt-bindings: pinctrl: renesas,r9a09g077-pinctrl: Document GPIO IRQ
2026-08-21 13:15 [PATCH 6.12.y-cip 00/18] Add ICU support for RZ/T2H and RZ/N2H SoCs Cosmin Tanislav
` (5 preceding siblings ...)
2026-08-21 13:15 ` [PATCH 6.12.y-cip 06/18] dt-bindings: interrupt-controller: Document RZ/{T2H,N2H} ICU Cosmin Tanislav
@ 2026-08-21 13:15 ` Cosmin Tanislav
2026-08-21 13:15 ` [PATCH 6.12.y-cip 08/18] dt-bindings: interrupt-controller: renesas,r9a09g077-icu: Fix reg size in example Cosmin Tanislav
` (11 subsequent siblings)
18 siblings, 0 replies; 23+ messages in thread
From: Cosmin Tanislav @ 2026-08-21 13:15 UTC (permalink / raw)
To: cip-dev, pavel, nobuhiro.iwamatsu.x90
commit 8b12070746854a70bd43d5763562561efc1840de upstream.
The Renesas RZ/T2H (R9A09G077) and Renesas RZ/N2H (R9A09G087) SoCs have
IRQ-capable pins handled by the ICU, which forwards them to the GIC.
The ICU supports 16 IRQ lines, the pins map to these lines arbitrarily,
and the mapping is not configurable.
Document the required properties to handle GPIO IRQ.
Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Linus Walleij <linusw@kernel.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20251205150234.2958140-4-cosmin-gabriel.tanislav.xa@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com>
---
.../bindings/pinctrl/renesas,r9a09g077-pinctrl.yaml | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,r9a09g077-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,r9a09g077-pinctrl.yaml
index d622cd94340a..63993b20524f 100644
--- a/Documentation/devicetree/bindings/pinctrl/renesas,r9a09g077-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/renesas,r9a09g077-pinctrl.yaml
@@ -49,6 +49,17 @@ properties:
gpio-ranges:
maxItems: 1
+ interrupt-controller: true
+
+ '#interrupt-cells':
+ const: 2
+ description:
+ The first cell contains the global GPIO port index, constructed using the
+ RZT2H_GPIO() helper macro from <dt-bindings/pinctrl/renesas,r9a09g077-pinctrl.h>
+ and the second cell is used to specify the flag.
+ E.g. "interrupts = <RZT2H_GPIO(8, 6) IRQ_TYPE_EDGE_FALLING>;" if P08_6 is
+ being used as an interrupt.
+
clocks:
maxItems: 1
@@ -156,6 +167,8 @@ examples:
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl 0 0 288>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
power-domains = <&cpg>;
serial0-pins {
--
2.55.0
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH 6.12.y-cip 08/18] dt-bindings: interrupt-controller: renesas,r9a09g077-icu: Fix reg size in example
2026-08-21 13:15 [PATCH 6.12.y-cip 00/18] Add ICU support for RZ/T2H and RZ/N2H SoCs Cosmin Tanislav
` (6 preceding siblings ...)
2026-08-21 13:15 ` [PATCH 6.12.y-cip 07/18] dt-bindings: pinctrl: renesas,r9a09g077-pinctrl: Document GPIO IRQ Cosmin Tanislav
@ 2026-08-21 13:15 ` Cosmin Tanislav
2026-08-21 13:15 ` [PATCH 6.12.y-cip 09/18] irqchip: Add RZ/{T2H,N2H} Interrupt Controller (ICU) driver Cosmin Tanislav
` (10 subsequent siblings)
18 siblings, 0 replies; 23+ messages in thread
From: Cosmin Tanislav @ 2026-08-21 13:15 UTC (permalink / raw)
To: cip-dev, pavel, nobuhiro.iwamatsu.x90
From: Geert Uytterhoeven <geert+renesas@glider.be>
commit 8e45719acdd6bf0bb6bf083957b53e40340dcd41 upstream.
According to Figure 5.1 ("Unified memory map"), the safety register
block is 64 KiB large, just like the non-safety register block.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Link: https://patch.msgid.link/364ff570c8a1845fab24bd89557f06c9e406f8de.1781105007.git.geert+renesas@glider.be
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com>
---
.../bindings/interrupt-controller/renesas,r9a09g077-icu.yaml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas,r9a09g077-icu.yaml b/Documentation/devicetree/bindings/interrupt-controller/renesas,r9a09g077-icu.yaml
index 78c01d14e765..a809bc4f7515 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/renesas,r9a09g077-icu.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,r9a09g077-icu.yaml
@@ -165,7 +165,7 @@ examples:
icu: interrupt-controller@802a0000 {
compatible = "renesas,r9a09g077-icu";
reg = <0x802a0000 0x10000>,
- <0x812a0000 0x50>;
+ <0x812a0000 0x10000>;
#interrupt-cells = <2>;
#address-cells = <0>;
interrupt-controller;
--
2.55.0
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH 6.12.y-cip 09/18] irqchip: Add RZ/{T2H,N2H} Interrupt Controller (ICU) driver
2026-08-21 13:15 [PATCH 6.12.y-cip 00/18] Add ICU support for RZ/T2H and RZ/N2H SoCs Cosmin Tanislav
` (7 preceding siblings ...)
2026-08-21 13:15 ` [PATCH 6.12.y-cip 08/18] dt-bindings: interrupt-controller: renesas,r9a09g077-icu: Fix reg size in example Cosmin Tanislav
@ 2026-08-21 13:15 ` Cosmin Tanislav
2026-08-21 13:15 ` [PATCH 6.12.y-cip 10/18] irqchip/renesas-rzt2h: Use pm_runtime_put_sync() in probe error path Cosmin Tanislav
` (9 subsequent siblings)
18 siblings, 0 replies; 23+ messages in thread
From: Cosmin Tanislav @ 2026-08-21 13:15 UTC (permalink / raw)
To: cip-dev, pavel, nobuhiro.iwamatsu.x90
commit 13e7b3305b647cf58c47c979fe8a04e08caa6098 upstream.
The Renesas RZ/T2H (R9A09G077) and Renesas RZ/N2H (R9A09G087) SoCs have an
Interrupt Controller (ICU) that supports interrupts from external pins IRQ0
to IRQ15, and SEI, and software-triggered interrupts INTCPU0 to INTCPU15.
INTCPU0 to INTCPU13, IRQ0 to IRQ13 are non-safety interrupts, while
INTCPU14, INTCPU15, IRQ14, IRQ15 and SEI are safety interrupts, and are
exposed via a separate register space.
Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Link: https://patch.msgid.link/20251201112933.488801-3-cosmin-gabriel.tanislav.xa@renesas.com
[ctani: adapt to current definition of IRQCHIP_MATCH()]
Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com>
---
drivers/irqchip/Kconfig | 8 +
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-renesas-rzt2h.c | 295 ++++++++++++++++++++++
drivers/soc/renesas/Kconfig | 1 +
include/linux/irqchip/irq-renesas-rzt2h.h | 23 ++
5 files changed, 328 insertions(+)
create mode 100644 drivers/irqchip/irq-renesas-rzt2h.c
create mode 100644 include/linux/irqchip/irq-renesas-rzt2h.h
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index a72943b47a5d..727b69c245cb 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -260,6 +260,14 @@ config RENESAS_RZG2L_IRQC
Enable support for the Renesas RZ/G2L (and alike SoC) Interrupt Controller
for external devices.
+config RENESAS_RZT2H_ICU
+ bool "Renesas RZ/{T2H,N2H} ICU support" if COMPILE_TEST
+ select GENERIC_IRQ_CHIP
+ select IRQ_DOMAIN_HIERARCHY
+ help
+ Enable support for the Renesas RZ/{T2H,N2H} Interrupt Controller
+ (ICU).
+
config RENESAS_RZV2H_ICU
bool "Renesas RZ/V2H(P) ICU support" if COMPILE_TEST
select GENERIC_IRQ_CHIP
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index 94ecaebff37f..76d4793386b1 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -51,6 +51,7 @@ obj-$(CONFIG_RENESAS_INTC_IRQPIN) += irq-renesas-intc-irqpin.o
obj-$(CONFIG_RENESAS_IRQC) += irq-renesas-irqc.o
obj-$(CONFIG_RENESAS_RZA1_IRQC) += irq-renesas-rza1.o
obj-$(CONFIG_RENESAS_RZG2L_IRQC) += irq-renesas-rzg2l.o
+obj-$(CONFIG_RENESAS_RZT2H_ICU) += irq-renesas-rzt2h.o
obj-$(CONFIG_RENESAS_RZV2H_ICU) += irq-renesas-rzv2h.o
obj-$(CONFIG_VERSATILE_FPGA_IRQ) += irq-versatile-fpga.o
obj-$(CONFIG_ARCH_NSPIRE) += irq-zevio.o
diff --git a/drivers/irqchip/irq-renesas-rzt2h.c b/drivers/irqchip/irq-renesas-rzt2h.c
new file mode 100644
index 000000000000..4b0cd5f66c34
--- /dev/null
+++ b/drivers/irqchip/irq-renesas-rzt2h.c
@@ -0,0 +1,295 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <linux/bitfield.h>
+#include <linux/cleanup.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/irqchip.h>
+#include <linux/irqchip/irq-renesas-rzt2h.h>
+#include <linux/irqdomain.h>
+#include <linux/of_platform.h>
+#include <linux/pm_runtime.h>
+#include <linux/reset.h>
+#include <linux/spinlock.h>
+
+#define RZT2H_ICU_INTCPU_NS_START 0
+#define RZT2H_ICU_INTCPU_NS_COUNT 14
+
+#define RZT2H_ICU_INTCPU_S_START (RZT2H_ICU_INTCPU_NS_START + \
+ RZT2H_ICU_INTCPU_NS_COUNT)
+#define RZT2H_ICU_INTCPU_S_COUNT 2
+
+#define RZT2H_ICU_IRQ_NS_START (RZT2H_ICU_INTCPU_S_START + \
+ RZT2H_ICU_INTCPU_S_COUNT)
+#define RZT2H_ICU_IRQ_NS_COUNT 14
+
+#define RZT2H_ICU_IRQ_S_START (RZT2H_ICU_IRQ_NS_START + \
+ RZT2H_ICU_IRQ_NS_COUNT)
+#define RZT2H_ICU_IRQ_S_COUNT 2
+
+#define RZT2H_ICU_SEI_START (RZT2H_ICU_IRQ_S_START + \
+ RZT2H_ICU_IRQ_S_COUNT)
+#define RZT2H_ICU_SEI_COUNT 1
+
+#define RZT2H_ICU_NUM_IRQ (RZT2H_ICU_INTCPU_NS_COUNT + \
+ RZT2H_ICU_INTCPU_S_COUNT + \
+ RZT2H_ICU_IRQ_NS_COUNT + \
+ RZT2H_ICU_IRQ_S_COUNT + \
+ RZT2H_ICU_SEI_COUNT)
+
+#define RZT2H_ICU_IRQ_IN_RANGE(n, type) \
+ ((n) >= RZT2H_ICU_##type##_START && \
+ (n) < RZT2H_ICU_##type##_START + RZT2H_ICU_##type##_COUNT)
+
+#define RZT2H_ICU_PORTNF_MD 0xc
+#define RZT2H_ICU_PORTNF_MDi_MASK(i) (GENMASK(1, 0) << ((i) * 2))
+#define RZT2H_ICU_PORTNF_MDi_PREP(i, val) (FIELD_PREP(GENMASK(1, 0), val) << ((i) * 2))
+
+#define RZT2H_ICU_MD_LOW_LEVEL 0b00
+#define RZT2H_ICU_MD_FALLING_EDGE 0b01
+#define RZT2H_ICU_MD_RISING_EDGE 0b10
+#define RZT2H_ICU_MD_BOTH_EDGES 0b11
+
+#define RZT2H_ICU_DMACn_RSSELi(n, i) (0x7d0 + 0x18 * (n) + 0x4 * (i))
+#define RZT2H_ICU_DMAC_REQ_SELx_MASK(x) (GENMASK(9, 0) << ((x) * 10))
+#define RZT2H_ICU_DMAC_REQ_SELx_PREP(x, val) (FIELD_PREP(GENMASK(9, 0), val) << ((x) * 10))
+
+struct rzt2h_icu_priv {
+ void __iomem *base_ns;
+ void __iomem *base_s;
+ struct irq_fwspec fwspec[RZT2H_ICU_NUM_IRQ];
+ raw_spinlock_t lock;
+};
+
+void rzt2h_icu_register_dma_req(struct platform_device *icu_dev, u8 dmac_index, u8 dmac_channel,
+ u16 req_no)
+{
+ struct rzt2h_icu_priv *priv = platform_get_drvdata(icu_dev);
+ u8 y, upper;
+ u32 val;
+
+ y = dmac_channel / 3;
+ upper = dmac_channel % 3;
+
+ guard(raw_spinlock_irqsave)(&priv->lock);
+ val = readl(priv->base_ns + RZT2H_ICU_DMACn_RSSELi(dmac_index, y));
+ val &= ~RZT2H_ICU_DMAC_REQ_SELx_MASK(upper);
+ val |= RZT2H_ICU_DMAC_REQ_SELx_PREP(upper, req_no);
+ writel(val, priv->base_ns + RZT2H_ICU_DMACn_RSSELi(dmac_index, y));
+}
+EXPORT_SYMBOL_GPL(rzt2h_icu_register_dma_req);
+
+static inline struct rzt2h_icu_priv *irq_data_to_priv(struct irq_data *data)
+{
+ return data->domain->host_data;
+}
+
+static inline int rzt2h_icu_irq_to_offset(struct irq_data *d, void __iomem **base,
+ unsigned int *offset)
+{
+ struct rzt2h_icu_priv *priv = irq_data_to_priv(d);
+ unsigned int hwirq = irqd_to_hwirq(d);
+
+ /*
+ * Safety IRQs and SEI use a separate register space from the non-safety IRQs.
+ * SEI interrupt number follows immediately after the safety IRQs.
+ */
+ if (RZT2H_ICU_IRQ_IN_RANGE(hwirq, IRQ_NS)) {
+ *offset = hwirq - RZT2H_ICU_IRQ_NS_START;
+ *base = priv->base_ns;
+ } else if (RZT2H_ICU_IRQ_IN_RANGE(hwirq, IRQ_S) || RZT2H_ICU_IRQ_IN_RANGE(hwirq, SEI)) {
+ *offset = hwirq - RZT2H_ICU_IRQ_S_START;
+ *base = priv->base_s;
+ } else {
+ return -EINVAL;
+ }
+ return 0;
+}
+
+static int rzt2h_icu_irq_set_type(struct irq_data *d, unsigned int type)
+{
+ struct rzt2h_icu_priv *priv = irq_data_to_priv(d);
+ unsigned int offset, parent_type;
+ void __iomem *base;
+ u32 val, md;
+ int ret;
+
+ ret = rzt2h_icu_irq_to_offset(d, &base, &offset);
+ if (ret)
+ return ret;
+
+ switch (type & IRQ_TYPE_SENSE_MASK) {
+ case IRQ_TYPE_LEVEL_LOW:
+ md = RZT2H_ICU_MD_LOW_LEVEL;
+ parent_type = IRQ_TYPE_LEVEL_HIGH;
+ break;
+ case IRQ_TYPE_EDGE_FALLING:
+ md = RZT2H_ICU_MD_FALLING_EDGE;
+ parent_type = IRQ_TYPE_EDGE_RISING;
+ break;
+ case IRQ_TYPE_EDGE_RISING:
+ md = RZT2H_ICU_MD_RISING_EDGE;
+ parent_type = IRQ_TYPE_EDGE_RISING;
+ break;
+ case IRQ_TYPE_EDGE_BOTH:
+ md = RZT2H_ICU_MD_BOTH_EDGES;
+ parent_type = IRQ_TYPE_EDGE_RISING;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ scoped_guard(raw_spinlock, &priv->lock) {
+ val = readl_relaxed(base + RZT2H_ICU_PORTNF_MD);
+ val &= ~RZT2H_ICU_PORTNF_MDi_MASK(offset);
+ val |= RZT2H_ICU_PORTNF_MDi_PREP(offset, md);
+ writel_relaxed(val, base + RZT2H_ICU_PORTNF_MD);
+ }
+
+ return irq_chip_set_type_parent(d, parent_type);
+}
+
+static int rzt2h_icu_set_type(struct irq_data *d, unsigned int type)
+{
+ unsigned int hw_irq = irqd_to_hwirq(d);
+
+ /* IRQn and SEI are selectable, others are edge-only. */
+ if (RZT2H_ICU_IRQ_IN_RANGE(hw_irq, IRQ_NS) ||
+ RZT2H_ICU_IRQ_IN_RANGE(hw_irq, IRQ_S) ||
+ RZT2H_ICU_IRQ_IN_RANGE(hw_irq, SEI))
+ return rzt2h_icu_irq_set_type(d, type);
+
+ if ((type & IRQ_TYPE_SENSE_MASK) != IRQ_TYPE_EDGE_RISING)
+ return -EINVAL;
+
+ return irq_chip_set_type_parent(d, IRQ_TYPE_EDGE_RISING);
+}
+
+static const struct irq_chip rzt2h_icu_chip = {
+ .name = "rzt2h-icu",
+ .irq_mask = irq_chip_mask_parent,
+ .irq_unmask = irq_chip_unmask_parent,
+ .irq_eoi = irq_chip_eoi_parent,
+ .irq_set_type = rzt2h_icu_set_type,
+ .irq_set_wake = irq_chip_set_wake_parent,
+ .irq_set_affinity = irq_chip_set_affinity_parent,
+ .irq_retrigger = irq_chip_retrigger_hierarchy,
+ .irq_get_irqchip_state = irq_chip_get_parent_state,
+ .irq_set_irqchip_state = irq_chip_set_parent_state,
+ .flags = IRQCHIP_MASK_ON_SUSPEND |
+ IRQCHIP_SET_TYPE_MASKED |
+ IRQCHIP_SKIP_SET_WAKE,
+};
+
+static int rzt2h_icu_alloc(struct irq_domain *domain, unsigned int virq, unsigned int nr_irqs,
+ void *arg)
+{
+ struct rzt2h_icu_priv *priv = domain->host_data;
+ irq_hw_number_t hwirq;
+ unsigned int type;
+ int ret;
+
+ ret = irq_domain_translate_twocell(domain, arg, &hwirq, &type);
+ if (ret)
+ return ret;
+
+ ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq, &rzt2h_icu_chip, NULL);
+ if (ret)
+ return ret;
+
+ return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, &priv->fwspec[hwirq]);
+}
+
+static const struct irq_domain_ops rzt2h_icu_domain_ops = {
+ .alloc = rzt2h_icu_alloc,
+ .free = irq_domain_free_irqs_common,
+ .translate = irq_domain_translate_twocell,
+};
+
+static int rzt2h_icu_parse_interrupts(struct rzt2h_icu_priv *priv, struct device_node *np)
+{
+ struct of_phandle_args map;
+ unsigned int i;
+ int ret;
+
+ for (i = 0; i < RZT2H_ICU_NUM_IRQ; i++) {
+ ret = of_irq_parse_one(np, i, &map);
+ if (ret)
+ return ret;
+
+ of_phandle_args_to_fwspec(np, map.args, map.args_count, &priv->fwspec[i]);
+ }
+
+ return 0;
+}
+
+static int rzt2h_icu_init(struct device_node *node, struct device_node *parent)
+{
+ struct platform_device *pdev = of_find_device_by_node(node);
+ struct device *dev __free(put_device) = pdev ? &pdev->dev : NULL;
+ struct irq_domain *irq_domain, *parent_domain;
+ struct rzt2h_icu_priv *priv;
+ int ret;
+
+ if (!pdev)
+ return -ENODEV;
+
+ parent_domain = irq_find_host(parent);
+ if (!parent_domain)
+ return dev_err_probe(dev, -ENODEV, "cannot find parent domain\n");
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ raw_spin_lock_init(&priv->lock);
+
+ platform_set_drvdata(pdev, priv);
+
+ priv->base_ns = devm_of_iomap(dev, dev->of_node, 0, NULL);
+ if (IS_ERR(priv->base_ns))
+ return PTR_ERR(priv->base_ns);
+
+ priv->base_s = devm_of_iomap(dev, dev->of_node, 1, NULL);
+ if (IS_ERR(priv->base_s))
+ return PTR_ERR(priv->base_s);
+
+ ret = rzt2h_icu_parse_interrupts(priv, node);
+ if (ret)
+ return dev_err_probe(dev, ret, "cannot parse interrupts: %d\n", ret);
+
+ ret = devm_pm_runtime_enable(dev);
+ if (ret)
+ return dev_err_probe(dev, ret, "devm_pm_runtime_enable failed: %d\n", ret);
+
+ ret = pm_runtime_resume_and_get(dev);
+ if (ret)
+ return dev_err_probe(dev, ret, "pm_runtime_resume_and_get failed: %d\n", ret);
+
+ irq_domain = irq_domain_create_hierarchy(parent_domain, 0, RZT2H_ICU_NUM_IRQ,
+ dev_fwnode(dev), &rzt2h_icu_domain_ops, priv);
+ if (!irq_domain) {
+ pm_runtime_put(dev);
+ return -ENOMEM;
+ }
+
+ /*
+ * Prevent the cleanup function from invoking put_device by assigning
+ * NULL to dev.
+ *
+ * make coccicheck will complain about missing put_device calls, but
+ * those are false positives, as dev will be automatically "put" via
+ * __free_put_device on the failing path.
+ * On the successful path we don't actually want to "put" dev.
+ */
+ dev = NULL;
+
+ return 0;
+}
+
+IRQCHIP_PLATFORM_DRIVER_BEGIN(rzt2h_icu)
+IRQCHIP_MATCH("renesas,r9a09g077-icu", rzt2h_icu_init)
+IRQCHIP_PLATFORM_DRIVER_END(rzt2h_icu)
+MODULE_AUTHOR("Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com>");
+MODULE_DESCRIPTION("Renesas RZ/T2H ICU Driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig
index 90ba65072af2..67496adfcb52 100644
--- a/drivers/soc/renesas/Kconfig
+++ b/drivers/soc/renesas/Kconfig
@@ -377,6 +377,7 @@ config ARCH_R9A09G057
config ARCH_R9A09G077
bool "ARM64 Platform support for RZ/T2H"
default y if ARCH_RENESAS
+ select RENESAS_RZT2H_ICU
help
This enables support for the Renesas RZ/T2H SoC variants.
diff --git a/include/linux/irqchip/irq-renesas-rzt2h.h b/include/linux/irqchip/irq-renesas-rzt2h.h
new file mode 100644
index 000000000000..853fd5ee0b22
--- /dev/null
+++ b/include/linux/irqchip/irq-renesas-rzt2h.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Renesas RZ/T2H Interrupt Control Unit (ICU)
+ *
+ * Copyright (C) 2025 Renesas Electronics Corporation.
+ */
+
+#ifndef __LINUX_IRQ_RENESAS_RZT2H
+#define __LINUX_IRQ_RENESAS_RZT2H
+
+#include <linux/platform_device.h>
+
+#define RZT2H_ICU_DMAC_REQ_NO_DEFAULT 0x3ff
+
+#ifdef CONFIG_RENESAS_RZT2H_ICU
+void rzt2h_icu_register_dma_req(struct platform_device *icu_dev, u8 dmac_index, u8 dmac_channel,
+ u16 req_no);
+#else
+static inline void rzt2h_icu_register_dma_req(struct platform_device *icu_dev, u8 dmac_index,
+ u8 dmac_channel, u16 req_no) { }
+#endif
+
+#endif /* __LINUX_IRQ_RENESAS_RZT2H */
--
2.55.0
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH 6.12.y-cip 10/18] irqchip/renesas-rzt2h: Use pm_runtime_put_sync() in probe error path
2026-08-21 13:15 [PATCH 6.12.y-cip 00/18] Add ICU support for RZ/T2H and RZ/N2H SoCs Cosmin Tanislav
` (8 preceding siblings ...)
2026-08-21 13:15 ` [PATCH 6.12.y-cip 09/18] irqchip: Add RZ/{T2H,N2H} Interrupt Controller (ICU) driver Cosmin Tanislav
@ 2026-08-21 13:15 ` Cosmin Tanislav
2026-08-21 13:15 ` [PATCH 6.12.y-cip 11/18] irqchip/renesas-rzt2h: Add software-triggered interrupts support Cosmin Tanislav
` (8 subsequent siblings)
18 siblings, 0 replies; 23+ messages in thread
From: Cosmin Tanislav @ 2026-08-21 13:15 UTC (permalink / raw)
To: cip-dev, pavel, nobuhiro.iwamatsu.x90
commit c9b7598eb013c6dbf2526dc050364bd8dc24f0d3 upstream.
pm_runtime_put() may trigger the idle check after pm_runtime_disable()
is run as part of devm_pm_runtime_enable()'s cleanup action, leaving
runtime PM active.
Use pm_runtime_put_sync() to ensure the idle check runs synchronously.
Fixes: 13e7b3305b64 ("irqchip: Add RZ/{T2H,N2H} Interrupt Controller (ICU) driver")
Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com>
Signed-off-by: Thomas Gleixner <tglx@kernel.org>
Link: https://patch.msgid.link/20260520203117.1516442-2-cosmin-gabriel.tanislav.xa@renesas.com
Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com>
---
drivers/irqchip/irq-renesas-rzt2h.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/irqchip/irq-renesas-rzt2h.c b/drivers/irqchip/irq-renesas-rzt2h.c
index 4b0cd5f66c34..e03eb9f86ef4 100644
--- a/drivers/irqchip/irq-renesas-rzt2h.c
+++ b/drivers/irqchip/irq-renesas-rzt2h.c
@@ -269,7 +269,7 @@ static int rzt2h_icu_init(struct device_node *node, struct device_node *parent)
irq_domain = irq_domain_create_hierarchy(parent_domain, 0, RZT2H_ICU_NUM_IRQ,
dev_fwnode(dev), &rzt2h_icu_domain_ops, priv);
if (!irq_domain) {
- pm_runtime_put(dev);
+ pm_runtime_put_sync(dev);
return -ENOMEM;
}
--
2.55.0
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH 6.12.y-cip 11/18] irqchip/renesas-rzt2h: Add software-triggered interrupts support
2026-08-21 13:15 [PATCH 6.12.y-cip 00/18] Add ICU support for RZ/T2H and RZ/N2H SoCs Cosmin Tanislav
` (9 preceding siblings ...)
2026-08-21 13:15 ` [PATCH 6.12.y-cip 10/18] irqchip/renesas-rzt2h: Use pm_runtime_put_sync() in probe error path Cosmin Tanislav
@ 2026-08-21 13:15 ` Cosmin Tanislav
2026-08-21 13:15 ` [PATCH 6.12.y-cip 12/18] irqchip/renesas-rzt2h: Add error " Cosmin Tanislav
` (7 subsequent siblings)
18 siblings, 0 replies; 23+ messages in thread
From: Cosmin Tanislav @ 2026-08-21 13:15 UTC (permalink / raw)
To: cip-dev, pavel, nobuhiro.iwamatsu.x90
commit a964dabc28a18fe62ff79e734cf54167ed322134 upstream.
The Renesas RZ/T2H ICU supports software-triggerable interrupts.
Add a dedicated rzt2h_icu_intcpu_chip irq_chip which implements
rzt2h_icu_intcpu_set_irqchip_state() to allow injecting these
interrupts.
Request the INTCPU IRQs when IRQ injection is enabled to report them
when they occur.
Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com>
Signed-off-by: Thomas Gleixner <tglx@kernel.org>
Link: https://patch.msgid.link/20260520203117.1516442-3-cosmin-gabriel.tanislav.xa@renesas.com
[ctani: fix conflict caused by changed rzt2h_icu_init() prototype ]
Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com>
---
drivers/irqchip/irq-renesas-rzt2h.c | 124 +++++++++++++++++++++++++++-
1 file changed, 121 insertions(+), 3 deletions(-)
diff --git a/drivers/irqchip/irq-renesas-rzt2h.c b/drivers/irqchip/irq-renesas-rzt2h.c
index e03eb9f86ef4..54d9e82e5de5 100644
--- a/drivers/irqchip/irq-renesas-rzt2h.c
+++ b/drivers/irqchip/irq-renesas-rzt2h.c
@@ -3,6 +3,7 @@
#include <linux/bitfield.h>
#include <linux/cleanup.h>
#include <linux/err.h>
+#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/irqchip.h>
#include <linux/irqchip/irq-renesas-rzt2h.h>
@@ -41,6 +42,9 @@
((n) >= RZT2H_ICU_##type##_START && \
(n) < RZT2H_ICU_##type##_START + RZT2H_ICU_##type##_COUNT)
+#define RZT2H_ICU_SWINT 0x0
+#define RZT2H_ICU_SWINT_IC_MASK(i) BIT(i)
+
#define RZT2H_ICU_PORTNF_MD 0xc
#define RZT2H_ICU_PORTNF_MDi_MASK(i) (GENMASK(1, 0) << ((i) * 2))
#define RZT2H_ICU_PORTNF_MDi_PREP(i, val) (FIELD_PREP(GENMASK(1, 0), val) << ((i) * 2))
@@ -100,6 +104,12 @@ static inline int rzt2h_icu_irq_to_offset(struct irq_data *d, void __iomem **bas
} else if (RZT2H_ICU_IRQ_IN_RANGE(hwirq, IRQ_S) || RZT2H_ICU_IRQ_IN_RANGE(hwirq, SEI)) {
*offset = hwirq - RZT2H_ICU_IRQ_S_START;
*base = priv->base_s;
+ } else if (RZT2H_ICU_IRQ_IN_RANGE(hwirq, INTCPU_NS)) {
+ *offset = hwirq - RZT2H_ICU_INTCPU_NS_START;
+ *base = priv->base_ns;
+ } else if (RZT2H_ICU_IRQ_IN_RANGE(hwirq, INTCPU_S)) {
+ *offset = hwirq - RZT2H_ICU_INTCPU_S_START;
+ *base = priv->base_s;
} else {
return -EINVAL;
}
@@ -165,6 +175,28 @@ static int rzt2h_icu_set_type(struct irq_data *d, unsigned int type)
return irq_chip_set_type_parent(d, IRQ_TYPE_EDGE_RISING);
}
+static int rzt2h_icu_intcpu_set_irqchip_state(struct irq_data *d, enum irqchip_irq_state which,
+ bool state)
+{
+ unsigned int offset;
+ void __iomem *base;
+ int ret;
+
+ if (which != IRQCHIP_STATE_PENDING)
+ return irq_chip_set_parent_state(d, which, state);
+
+ if (!state)
+ return 0;
+
+ ret = rzt2h_icu_irq_to_offset(d, &base, &offset);
+ if (ret)
+ return ret;
+
+ writel_relaxed(RZT2H_ICU_SWINT_IC_MASK(offset), base + RZT2H_ICU_SWINT);
+
+ return 0;
+}
+
static const struct irq_chip rzt2h_icu_chip = {
.name = "rzt2h-icu",
.irq_mask = irq_chip_mask_parent,
@@ -181,10 +213,27 @@ static const struct irq_chip rzt2h_icu_chip = {
IRQCHIP_SKIP_SET_WAKE,
};
+static const struct irq_chip rzt2h_icu_intcpu_chip = {
+ .name = "rzt2h-icu",
+ .irq_mask = irq_chip_mask_parent,
+ .irq_unmask = irq_chip_unmask_parent,
+ .irq_eoi = irq_chip_eoi_parent,
+ .irq_set_type = irq_chip_set_type_parent,
+ .irq_set_wake = irq_chip_set_wake_parent,
+ .irq_set_affinity = irq_chip_set_affinity_parent,
+ .irq_retrigger = irq_chip_retrigger_hierarchy,
+ .irq_get_irqchip_state = irq_chip_get_parent_state,
+ .irq_set_irqchip_state = rzt2h_icu_intcpu_set_irqchip_state,
+ .flags = IRQCHIP_MASK_ON_SUSPEND |
+ IRQCHIP_SET_TYPE_MASKED |
+ IRQCHIP_SKIP_SET_WAKE,
+};
+
static int rzt2h_icu_alloc(struct irq_domain *domain, unsigned int virq, unsigned int nr_irqs,
void *arg)
{
struct rzt2h_icu_priv *priv = domain->host_data;
+ const struct irq_chip *chip;
irq_hw_number_t hwirq;
unsigned int type;
int ret;
@@ -193,7 +242,12 @@ static int rzt2h_icu_alloc(struct irq_domain *domain, unsigned int virq, unsigne
if (ret)
return ret;
- ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq, &rzt2h_icu_chip, NULL);
+ if (RZT2H_ICU_IRQ_IN_RANGE(hwirq, INTCPU_NS) || RZT2H_ICU_IRQ_IN_RANGE(hwirq, INTCPU_S))
+ chip = &rzt2h_icu_intcpu_chip;
+ else
+ chip = &rzt2h_icu_chip;
+
+ ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq, chip, NULL);
if (ret)
return ret;
@@ -223,6 +277,60 @@ static int rzt2h_icu_parse_interrupts(struct rzt2h_icu_priv *priv, struct device
return 0;
}
+static irqreturn_t rzt2h_icu_intcpu_irq(int irq, void *data)
+{
+ unsigned int intcpu = (uintptr_t)data;
+
+ pr_info("INTCPU%u software interrupt\n", intcpu);
+ return IRQ_HANDLED;
+}
+
+static int rzt2h_icu_request_irqs(struct platform_device *pdev, struct irq_domain *irq_domain,
+ unsigned int start, unsigned int count, irq_handler_t handler,
+ void *data)
+{
+ struct device *dev = &pdev->dev;
+ unsigned int offset, virq;
+ struct irq_fwspec fwspec;
+ int ret;
+
+ for (offset = start; offset < start + count; offset++) {
+ fwspec.fwnode = irq_domain->fwnode;
+ fwspec.param_count = 2;
+ fwspec.param[0] = offset;
+ fwspec.param[1] = IRQ_TYPE_EDGE_RISING;
+
+ virq = irq_create_fwspec_mapping(&fwspec);
+ if (!virq)
+ return dev_err_probe(dev, -EINVAL, "Failed to create IRQ %u mapping\n", offset);
+
+ ret = devm_request_irq(dev, virq, handler, 0, dev_name(dev),
+ data ?: (void *)(uintptr_t)offset);
+ if (ret)
+ return dev_err_probe(dev, ret, "Failed to request IRQ %u\n", offset);
+ }
+
+ return 0;
+}
+
+static int rzt2h_icu_setup_irqs(struct platform_device *pdev, struct irq_domain *irq_domain)
+{
+ if (IS_ENABLED(CONFIG_GENERIC_IRQ_INJECTION)) {
+ int ret = rzt2h_icu_request_irqs(pdev, irq_domain, RZT2H_ICU_INTCPU_NS_START,
+ RZT2H_ICU_INTCPU_NS_COUNT, rzt2h_icu_intcpu_irq,
+ NULL);
+ if (ret)
+ return ret;
+
+ ret = rzt2h_icu_request_irqs(pdev, irq_domain, RZT2H_ICU_INTCPU_S_START,
+ RZT2H_ICU_INTCPU_S_COUNT, rzt2h_icu_intcpu_irq, NULL);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
static int rzt2h_icu_init(struct device_node *node, struct device_node *parent)
{
struct platform_device *pdev = of_find_device_by_node(node);
@@ -269,10 +377,14 @@ static int rzt2h_icu_init(struct device_node *node, struct device_node *parent)
irq_domain = irq_domain_create_hierarchy(parent_domain, 0, RZT2H_ICU_NUM_IRQ,
dev_fwnode(dev), &rzt2h_icu_domain_ops, priv);
if (!irq_domain) {
- pm_runtime_put_sync(dev);
- return -ENOMEM;
+ ret = -ENOMEM;
+ goto err_pm_put;
}
+ ret = rzt2h_icu_setup_irqs(pdev, irq_domain);
+ if (ret)
+ goto err_irq_domain_free;
+
/*
* Prevent the cleanup function from invoking put_device by assigning
* NULL to dev.
@@ -285,6 +397,12 @@ static int rzt2h_icu_init(struct device_node *node, struct device_node *parent)
dev = NULL;
return 0;
+
+err_irq_domain_free:
+ irq_domain_remove(irq_domain);
+err_pm_put:
+ pm_runtime_put_sync(dev);
+ return ret;
}
IRQCHIP_PLATFORM_DRIVER_BEGIN(rzt2h_icu)
--
2.55.0
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH 6.12.y-cip 12/18] irqchip/renesas-rzt2h: Add error interrupts support
2026-08-21 13:15 [PATCH 6.12.y-cip 00/18] Add ICU support for RZ/T2H and RZ/N2H SoCs Cosmin Tanislav
` (10 preceding siblings ...)
2026-08-21 13:15 ` [PATCH 6.12.y-cip 11/18] irqchip/renesas-rzt2h: Add software-triggered interrupts support Cosmin Tanislav
@ 2026-08-21 13:15 ` Cosmin Tanislav
2026-08-21 13:15 ` [PATCH 6.12.y-cip 13/18] arm64: dts: renesas: r9a09g077: Add ICU support Cosmin Tanislav
` (6 subsequent siblings)
18 siblings, 0 replies; 23+ messages in thread
From: Cosmin Tanislav @ 2026-08-21 13:15 UTC (permalink / raw)
To: cip-dev, pavel, nobuhiro.iwamatsu.x90
commit 8d721c08dd67af96664ce381f6b2790d15de7213 upstream.
The Renesas RZ/T2H ICU is able to report errors for CA55, GIC, and
various IPs. Unmask these errors, request the IRQs and report them when
they occur.
Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com>
Signed-off-by: Thomas Gleixner <tglx@kernel.org>
Link: https://patch.msgid.link/20260520203117.1516442-4-cosmin-gabriel.tanislav.xa@renesas.com
Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com>
---
drivers/irqchip/irq-renesas-rzt2h.c | 151 +++++++++++++++++++++++++++-
1 file changed, 147 insertions(+), 4 deletions(-)
diff --git a/drivers/irqchip/irq-renesas-rzt2h.c b/drivers/irqchip/irq-renesas-rzt2h.c
index 54d9e82e5de5..a536ebd792ff 100644
--- a/drivers/irqchip/irq-renesas-rzt2h.c
+++ b/drivers/irqchip/irq-renesas-rzt2h.c
@@ -32,11 +32,36 @@
RZT2H_ICU_IRQ_S_COUNT)
#define RZT2H_ICU_SEI_COUNT 1
+#define RZT2H_ICU_CA55_ERR_START (RZT2H_ICU_SEI_START + \
+ RZT2H_ICU_SEI_COUNT)
+#define RZT2H_ICU_CA55_ERR_COUNT 2
+
+#define RZT2H_ICU_CR52_ERR_START (RZT2H_ICU_CA55_ERR_START + \
+ RZT2H_ICU_CA55_ERR_COUNT)
+#define RZT2H_ICU_CR52_ERR_COUNT 4
+
+#define RZT2H_ICU_PERI_ERR_START (RZT2H_ICU_CR52_ERR_START + \
+ RZT2H_ICU_CR52_ERR_COUNT)
+#define RZT2H_ICU_PERI_ERR_COUNT 2
+
+#define RZT2H_ICU_DSMIF_ERR_START (RZT2H_ICU_PERI_ERR_START + \
+ RZT2H_ICU_PERI_ERR_COUNT)
+#define RZT2H_ICU_DSMIF_ERR_COUNT 2
+
+#define RZT2H_ICU_ENCIF_ERR_START (RZT2H_ICU_DSMIF_ERR_START + \
+ RZT2H_ICU_DSMIF_ERR_COUNT)
+#define RZT2H_ICU_ENCIF_ERR_COUNT 2
+
#define RZT2H_ICU_NUM_IRQ (RZT2H_ICU_INTCPU_NS_COUNT + \
RZT2H_ICU_INTCPU_S_COUNT + \
RZT2H_ICU_IRQ_NS_COUNT + \
RZT2H_ICU_IRQ_S_COUNT + \
- RZT2H_ICU_SEI_COUNT)
+ RZT2H_ICU_SEI_COUNT + \
+ RZT2H_ICU_CA55_ERR_COUNT + \
+ RZT2H_ICU_CR52_ERR_COUNT + \
+ RZT2H_ICU_PERI_ERR_COUNT + \
+ RZT2H_ICU_DSMIF_ERR_COUNT + \
+ RZT2H_ICU_ENCIF_ERR_COUNT)
#define RZT2H_ICU_IRQ_IN_RANGE(n, type) \
((n) >= RZT2H_ICU_##type##_START && \
@@ -54,6 +79,29 @@
#define RZT2H_ICU_MD_RISING_EDGE 0b10
#define RZT2H_ICU_MD_BOTH_EDGES 0b11
+#define RZT2H_ICU_CA55ERR_E0MSK 0x50
+#define RZT2H_ICU_CA55ERR_CLR 0x60
+#define RZT2H_ICU_CA55ERR_STAT 0x64
+#define RZT2H_ICU_CA55ERR_MASK GENMASK(12, 0)
+
+#define RZT2H_ICU_PERIERR_E0MSKn(n) (0x98 + 0x4 * (n))
+#define RZT2H_ICU_PERIERR_CLRn(n) (0xc8 + 0x4 * (n))
+#define RZT2H_ICU_PERIERR_STAT 0xd4
+#define RZT2H_ICU_PERIERR_NUM 3
+#define RZT2H_ICU_PERIERR_MASK GENMASK(31, 0)
+
+#define RZT2H_ICU_DSMIFERR_E0MSKn(n) (0xe0 + 0x4 * (n))
+#define RZT2H_ICU_DSMIFERR_CLRn(n) (0x1a0 + 0x4 * (n))
+#define RZT2H_ICU_DSMIFERR_STAT 0x1d0
+#define RZT2H_ICU_DSMIFERR_NUM 12
+#define RZT2H_ICU_DSMIFERR_MASK GENMASK(31, 0)
+
+#define RZT2H_ICU_ENCIFERR_E0MSKn(n) (0x200 + 0x4 * (n))
+#define RZT2H_ICU_ENCIFERR_CLRn(n) (0x250 + 0x4 * (n))
+#define RZT2H_ICU_ENCIFERR_STAT 0x264
+#define RZT2H_ICU_ENCIFERR_NUM 5
+#define RZT2H_ICU_ENCIFERR_MASK GENMASK(31, 0)
+
#define RZT2H_ICU_DMACn_RSSELi(n, i) (0x7d0 + 0x18 * (n) + 0x4 * (i))
#define RZT2H_ICU_DMAC_REQ_SELx_MASK(x) (GENMASK(9, 0) << ((x) * 10))
#define RZT2H_ICU_DMAC_REQ_SELx_PREP(x, val) (FIELD_PREP(GENMASK(9, 0), val) << ((x) * 10))
@@ -285,6 +333,50 @@ static irqreturn_t rzt2h_icu_intcpu_irq(int irq, void *data)
return IRQ_HANDLED;
}
+static irqreturn_t rzt2h_icu_err_irq(struct rzt2h_icu_priv *priv, const char *name,
+ unsigned int num, u32 stat_base, u32 clr_base)
+{
+ bool handled = false;
+
+ for (unsigned int n = 0; n < num; n++) {
+ u32 stat = readl(priv->base_ns + stat_base + n * 0x4);
+
+ if (!stat)
+ continue;
+
+ handled = true;
+
+ pr_err("rzt2h-icu: %s error n=%u status=0x%08x\n", name, n, stat);
+
+ writel_relaxed(stat, priv->base_ns + clr_base + n * 0x4);
+ }
+
+ return handled ? IRQ_HANDLED : IRQ_NONE;
+}
+
+static irqreturn_t rzt2h_icu_ca55_err_irq(int irq, void *data)
+{
+ return rzt2h_icu_err_irq(data, "CA55", 1, RZT2H_ICU_CA55ERR_STAT, RZT2H_ICU_CA55ERR_CLR);
+}
+
+static irqreturn_t rzt2h_icu_peri_err_irq(int irq, void *data)
+{
+ return rzt2h_icu_err_irq(data, "peripheral", RZT2H_ICU_PERIERR_NUM, RZT2H_ICU_PERIERR_STAT,
+ RZT2H_ICU_PERIERR_CLRn(0));
+}
+
+static irqreturn_t rzt2h_icu_dsmif_err_irq(int irq, void *data)
+{
+ return rzt2h_icu_err_irq(data, "DSMIF", RZT2H_ICU_DSMIFERR_NUM, RZT2H_ICU_DSMIFERR_STAT,
+ RZT2H_ICU_DSMIFERR_CLRn(0));
+}
+
+static irqreturn_t rzt2h_icu_encif_err_irq(int irq, void *data)
+{
+ return rzt2h_icu_err_irq(data, "ENCIF", RZT2H_ICU_ENCIFERR_NUM, RZT2H_ICU_ENCIFERR_STAT,
+ RZT2H_ICU_ENCIFERR_CLRn(0));
+}
+
static int rzt2h_icu_request_irqs(struct platform_device *pdev, struct irq_domain *irq_domain,
unsigned int start, unsigned int count, irq_handler_t handler,
void *data)
@@ -315,10 +407,13 @@ static int rzt2h_icu_request_irqs(struct platform_device *pdev, struct irq_domai
static int rzt2h_icu_setup_irqs(struct platform_device *pdev, struct irq_domain *irq_domain)
{
+ struct rzt2h_icu_priv *priv = platform_get_drvdata(pdev);
+ unsigned int n;
+ int ret;
+
if (IS_ENABLED(CONFIG_GENERIC_IRQ_INJECTION)) {
- int ret = rzt2h_icu_request_irqs(pdev, irq_domain, RZT2H_ICU_INTCPU_NS_START,
- RZT2H_ICU_INTCPU_NS_COUNT, rzt2h_icu_intcpu_irq,
- NULL);
+ ret = rzt2h_icu_request_irqs(pdev, irq_domain, RZT2H_ICU_INTCPU_NS_START,
+ RZT2H_ICU_INTCPU_NS_COUNT, rzt2h_icu_intcpu_irq, NULL);
if (ret)
return ret;
@@ -328,6 +423,54 @@ static int rzt2h_icu_setup_irqs(struct platform_device *pdev, struct irq_domain
return ret;
}
+ /*
+ * There are two error interrupts and two error masks that can be used
+ * separately for each error type. It would not be very useful to
+ * receive two interrupts for the same error, so use only the first one.
+ */
+
+ ret = rzt2h_icu_request_irqs(pdev, irq_domain, RZT2H_ICU_CA55_ERR_START, 1,
+ rzt2h_icu_ca55_err_irq, priv);
+ if (ret)
+ return ret;
+
+ ret = rzt2h_icu_request_irqs(pdev, irq_domain, RZT2H_ICU_PERI_ERR_START, 1,
+ rzt2h_icu_peri_err_irq, priv);
+ if (ret)
+ return ret;
+
+ ret = rzt2h_icu_request_irqs(pdev, irq_domain, RZT2H_ICU_DSMIF_ERR_START, 1,
+ rzt2h_icu_dsmif_err_irq, priv);
+ if (ret)
+ return ret;
+
+ ret = rzt2h_icu_request_irqs(pdev, irq_domain, RZT2H_ICU_ENCIF_ERR_START, 1,
+ rzt2h_icu_encif_err_irq, priv);
+ if (ret)
+ return ret;
+
+ /* Clear and unmask CA55 error events */
+ writel_relaxed(RZT2H_ICU_CA55ERR_MASK, priv->base_ns + RZT2H_ICU_CA55ERR_CLR);
+ writel_relaxed(0, priv->base_ns + RZT2H_ICU_CA55ERR_E0MSK);
+
+ /* Clear and unmask peripheral error events */
+ for (n = 0; n < RZT2H_ICU_PERIERR_NUM; n++) {
+ writel_relaxed(RZT2H_ICU_PERIERR_MASK, priv->base_ns + RZT2H_ICU_PERIERR_CLRn(n));
+ writel_relaxed(0, priv->base_ns + RZT2H_ICU_PERIERR_E0MSKn(n));
+ }
+
+ /* Clear and unmask DSMIF error events */
+ for (n = 0; n < RZT2H_ICU_DSMIFERR_NUM; n++) {
+ writel_relaxed(RZT2H_ICU_DSMIFERR_MASK, priv->base_ns + RZT2H_ICU_DSMIFERR_CLRn(n));
+ writel_relaxed(0, priv->base_ns + RZT2H_ICU_DSMIFERR_E0MSKn(n));
+ }
+
+ /* Clear and unmask ENCIF error events */
+ for (n = 0; n < RZT2H_ICU_ENCIFERR_NUM; n++) {
+ writel_relaxed(RZT2H_ICU_ENCIFERR_MASK, priv->base_ns + RZT2H_ICU_ENCIFERR_CLRn(n));
+ writel_relaxed(0, priv->base_ns + RZT2H_ICU_ENCIFERR_E0MSKn(n));
+ }
+
return 0;
}
--
2.55.0
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH 6.12.y-cip 13/18] arm64: dts: renesas: r9a09g077: Add ICU support
2026-08-21 13:15 [PATCH 6.12.y-cip 00/18] Add ICU support for RZ/T2H and RZ/N2H SoCs Cosmin Tanislav
` (11 preceding siblings ...)
2026-08-21 13:15 ` [PATCH 6.12.y-cip 12/18] irqchip/renesas-rzt2h: Add error " Cosmin Tanislav
@ 2026-08-21 13:15 ` Cosmin Tanislav
2026-08-21 13:15 ` [PATCH 6.12.y-cip 14/18] arm64: dts: renesas: r9a09g087: " Cosmin Tanislav
` (5 subsequent siblings)
18 siblings, 0 replies; 23+ messages in thread
From: Cosmin Tanislav @ 2026-08-21 13:15 UTC (permalink / raw)
To: cip-dev, pavel, nobuhiro.iwamatsu.x90
commit f060bbe2c32941acc4738cc27039246593f49a33 upstream.
The Renesas RZ/T2H (R9A09G077) SoC has an Interrupt Controller (ICU)
block that routes external interrupts to the GIC's SPIs, with the
ability of level-translation, and can also produce software and
aggregate error interrupts.
Add support for it.
Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20251201112933.488801-4-cosmin-gabriel.tanislav.xa@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com>
---
arch/arm64/boot/dts/renesas/r9a09g077.dtsi | 73 ++++++++++++++++++++++
1 file changed, 73 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi
index fd0b7e082721..824e1a17050e 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi
@@ -928,6 +928,79 @@ cpg: clock-controller@80280000 {
#power-domain-cells = <0>;
};
+ icu: interrupt-controller@802a0000 {
+ compatible = "renesas,r9a09g077-icu";
+ reg = <0 0x802a0000 0 0x10000>,
+ <0 0x812a0000 0 0x10000>;
+ #interrupt-cells = <2>;
+ #address-cells = <0>;
+ interrupt-controller;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 1 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 2 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 4 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 5 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 6 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 7 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 8 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 9 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 10 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 11 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 12 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 13 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 14 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 15 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 16 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 17 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 18 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 20 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 23 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 24 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 28 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 29 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 30 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 31 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 406 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 407 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 408 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 409 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 410 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 411 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 412 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 413 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 414 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 415 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 416 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 417 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 418 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "intcpu0", "intcpu1", "intcpu2",
+ "intcpu3", "intcpu4", "intcpu5",
+ "intcpu6", "intcpu7", "intcpu8",
+ "intcpu9", "intcpu10", "intcpu11",
+ "intcpu12", "intcpu13", "intcpu14",
+ "intcpu15",
+ "irq0", "irq1", "irq2", "irq3",
+ "irq4", "irq5", "irq6", "irq7",
+ "irq8", "irq9", "irq10", "irq11",
+ "irq12", "irq13", "irq14", "irq15",
+ "sei",
+ "ca55-err0", "ca55-err1",
+ "cr520-err0", "cr520-err1",
+ "cr521-err0", "cr521-err1",
+ "peri-err0", "peri-err1",
+ "dsmif-err0", "dsmif-err1",
+ "encif-err0", "encif-err1";
+ clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKM>;
+ power-domains = <&cpg>;
+ };
+
pinctrl: pinctrl@802c0000 {
compatible = "renesas,r9a09g077-pinctrl";
reg = <0 0x802c0000 0 0x10000>,
--
2.55.0
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH 6.12.y-cip 14/18] arm64: dts: renesas: r9a09g087: Add ICU support
2026-08-21 13:15 [PATCH 6.12.y-cip 00/18] Add ICU support for RZ/T2H and RZ/N2H SoCs Cosmin Tanislav
` (12 preceding siblings ...)
2026-08-21 13:15 ` [PATCH 6.12.y-cip 13/18] arm64: dts: renesas: r9a09g077: Add ICU support Cosmin Tanislav
@ 2026-08-21 13:15 ` Cosmin Tanislav
2026-08-21 13:15 ` [PATCH 6.12.y-cip 15/18] arm64: dts: renesas: r9a09g077: Add GPIO IRQ support Cosmin Tanislav
` (4 subsequent siblings)
18 siblings, 0 replies; 23+ messages in thread
From: Cosmin Tanislav @ 2026-08-21 13:15 UTC (permalink / raw)
To: cip-dev, pavel, nobuhiro.iwamatsu.x90
commit d42c64cf161644929de081e541afbab33acb231a upstream.
The Renesas RZ/N2H (R9A09G087) SoC has an Interrupt Controller (ICU)
block that routes external interrupts to the GIC's SPIs, with the
ability of level-translation, and can also produce software and
aggregate error interrupts.
Add support for it.
Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20251201112933.488801-5-cosmin-gabriel.tanislav.xa@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com>
---
arch/arm64/boot/dts/renesas/r9a09g087.dtsi | 73 ++++++++++++++++++++++
1 file changed, 73 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi
index 64886ab95bc3..48b56a196929 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi
@@ -931,6 +931,79 @@ cpg: clock-controller@80280000 {
#power-domain-cells = <0>;
};
+ icu: interrupt-controller@802a0000 {
+ compatible = "renesas,r9a09g087-icu", "renesas,r9a09g077-icu";
+ reg = <0 0x802a0000 0 0x10000>,
+ <0 0x812a0000 0 0x10000>;
+ #interrupt-cells = <2>;
+ #address-cells = <0>;
+ interrupt-controller;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 1 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 2 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 4 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 5 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 6 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 7 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 8 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 9 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 10 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 11 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 12 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 13 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 14 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 15 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 16 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 17 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 18 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 20 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 23 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 24 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 28 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 29 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 30 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 31 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 406 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 407 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 408 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 409 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 410 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 411 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 412 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 413 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 414 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 415 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 416 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 417 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 418 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "intcpu0", "intcpu1", "intcpu2",
+ "intcpu3", "intcpu4", "intcpu5",
+ "intcpu6", "intcpu7", "intcpu8",
+ "intcpu9", "intcpu10", "intcpu11",
+ "intcpu12", "intcpu13", "intcpu14",
+ "intcpu15",
+ "irq0", "irq1", "irq2", "irq3",
+ "irq4", "irq5", "irq6", "irq7",
+ "irq8", "irq9", "irq10", "irq11",
+ "irq12", "irq13", "irq14", "irq15",
+ "sei",
+ "ca55-err0", "ca55-err1",
+ "cr520-err0", "cr520-err1",
+ "cr521-err0", "cr521-err1",
+ "peri-err0", "peri-err1",
+ "dsmif-err0", "dsmif-err1",
+ "encif-err0", "encif-err1";
+ clocks = <&cpg CPG_CORE R9A09G087_CLK_PCLKM>;
+ power-domains = <&cpg>;
+ };
+
pinctrl: pinctrl@802c0000 {
compatible = "renesas,r9a09g087-pinctrl";
reg = <0 0x802c0000 0 0x10000>,
--
2.55.0
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH 6.12.y-cip 15/18] arm64: dts: renesas: r9a09g077: Add GPIO IRQ support
2026-08-21 13:15 [PATCH 6.12.y-cip 00/18] Add ICU support for RZ/T2H and RZ/N2H SoCs Cosmin Tanislav
` (13 preceding siblings ...)
2026-08-21 13:15 ` [PATCH 6.12.y-cip 14/18] arm64: dts: renesas: r9a09g087: " Cosmin Tanislav
@ 2026-08-21 13:15 ` Cosmin Tanislav
2026-08-21 13:15 ` [PATCH 6.12.y-cip 16/18] arm64: dts: renesas: r9a09g087: " Cosmin Tanislav
` (3 subsequent siblings)
18 siblings, 0 replies; 23+ messages in thread
From: Cosmin Tanislav @ 2026-08-21 13:15 UTC (permalink / raw)
To: cip-dev, pavel, nobuhiro.iwamatsu.x90
commit a0c0b921b63902b3993bf60bd0ab8c3041a23481 upstream.
The Renesas RZ/T2H (R9A09G077) SoC includes pins which can be routed via
the ICU to generate interrupts.
Add support for using the pin controller as an interrupt chip.
Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20251205150234.2958140-6-cosmin-gabriel.tanislav.xa@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com>
---
arch/arm64/boot/dts/renesas/r9a09g077.dtsi | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi
index 824e1a17050e..00a1ef6ac7df 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi
@@ -1011,6 +1011,9 @@ pinctrl: pinctrl@802c0000 {
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl 0 0 288>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ interrupt-parent = <&icu>;
power-domains = <&cpg>;
};
--
2.55.0
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH 6.12.y-cip 16/18] arm64: dts: renesas: r9a09g087: Add GPIO IRQ support
2026-08-21 13:15 [PATCH 6.12.y-cip 00/18] Add ICU support for RZ/T2H and RZ/N2H SoCs Cosmin Tanislav
` (14 preceding siblings ...)
2026-08-21 13:15 ` [PATCH 6.12.y-cip 15/18] arm64: dts: renesas: r9a09g077: Add GPIO IRQ support Cosmin Tanislav
@ 2026-08-21 13:15 ` Cosmin Tanislav
2026-08-21 13:15 ` [PATCH 6.12.y-cip 17/18] arm64: dts: renesas: r9a09g077m44-rzt2h-evk: Add GPIO keys Cosmin Tanislav
` (2 subsequent siblings)
18 siblings, 0 replies; 23+ messages in thread
From: Cosmin Tanislav @ 2026-08-21 13:15 UTC (permalink / raw)
To: cip-dev, pavel, nobuhiro.iwamatsu.x90
commit 7c9cf4eb9d600a51e4770e6ab876e123dd6b5165 upstream.
The Renesas RZ/N2H (R9A09G087) SoC includes pins which can be routed via
the ICU to generate interrupts.
Add support for using the pin controller as an interrupt chip.
Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20251205150234.2958140-7-cosmin-gabriel.tanislav.xa@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com>
---
arch/arm64/boot/dts/renesas/r9a09g087.dtsi | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi
index 48b56a196929..eb405ae6f03e 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi
@@ -1014,6 +1014,9 @@ pinctrl: pinctrl@802c0000 {
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl 0 0 280>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ interrupt-parent = <&icu>;
power-domains = <&cpg>;
};
--
2.55.0
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH 6.12.y-cip 17/18] arm64: dts: renesas: r9a09g077m44-rzt2h-evk: Add GPIO keys
2026-08-21 13:15 [PATCH 6.12.y-cip 00/18] Add ICU support for RZ/T2H and RZ/N2H SoCs Cosmin Tanislav
` (15 preceding siblings ...)
2026-08-21 13:15 ` [PATCH 6.12.y-cip 16/18] arm64: dts: renesas: r9a09g087: " Cosmin Tanislav
@ 2026-08-21 13:15 ` Cosmin Tanislav
2026-08-21 13:15 ` [PATCH 6.12.y-cip 18/18] arm64: dts: renesas: r9a09g087m44-rzn2h-evk: " Cosmin Tanislav
2026-08-22 8:11 ` [PATCH 6.12.y-cip 00/18] Add ICU support for RZ/T2H and RZ/N2H SoCs Pavel Machek
18 siblings, 0 replies; 23+ messages in thread
From: Cosmin Tanislav @ 2026-08-21 13:15 UTC (permalink / raw)
To: cip-dev, pavel, nobuhiro.iwamatsu.x90
commit fcec728e1599f45f7956c1f7694706cf77cdf29e upstream.
The Renesas RZ/T2H Evaluation Kit has three user buttons connected to
GPIOs that can be used as input keys.
Add support for them.
Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20251205150234.2958140-8-cosmin-gabriel.tanislav.xa@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
[ctani: resolve includes conflict]
Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com>
---
.../dts/renesas/r9a09g077m44-rzt2h-evk.dts | 32 +++++++++++++++++++
1 file changed, 32 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts
index d5d3112e6dad..89f3258b8bf6 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts
+++ b/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts
@@ -7,6 +7,7 @@
/dts-v1/;
+#include <dt-bindings/input/input.h>
#include <dt-bindings/pinctrl/renesas,r9a09g077-pinctrl.h>
#include "r9a09g077m44.dtsi"
@@ -59,6 +60,37 @@ / {
model = "Renesas RZ/T2H EVK Board based on r9a09g077m44";
compatible = "renesas,rzt2h-evk", "renesas,r9a09g077m44", "renesas,r9a09g077";
+ keys {
+ compatible = "gpio-keys";
+
+#if (!SD1_MICRO_SD)
+ /* SW2-3: OFF */
+ key-1 {
+ interrupts-extended = <&pinctrl RZT2H_GPIO(8, 6) IRQ_TYPE_EDGE_FALLING>;
+ linux,code = <KEY_1>;
+ label = "SW9";
+ wakeup-source;
+ debounce-interval = <20>;
+ };
+#endif
+
+ key-2 {
+ interrupts-extended = <&pinctrl RZT2H_GPIO(0, 3) IRQ_TYPE_EDGE_FALLING>;
+ linux,code = <KEY_2>;
+ label = "SW10";
+ wakeup-source;
+ debounce-interval = <20>;
+ };
+
+ key-3 {
+ interrupts-extended = <&pinctrl RZT2H_GPIO(8, 7) IRQ_TYPE_EDGE_FALLING>;
+ linux,code = <KEY_3>;
+ label = "SW11";
+ wakeup-source;
+ debounce-interval = <20>;
+ };
+ };
+
leds {
compatible = "gpio-leds";
--
2.55.0
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH 6.12.y-cip 18/18] arm64: dts: renesas: r9a09g087m44-rzn2h-evk: Add GPIO keys
2026-08-21 13:15 [PATCH 6.12.y-cip 00/18] Add ICU support for RZ/T2H and RZ/N2H SoCs Cosmin Tanislav
` (16 preceding siblings ...)
2026-08-21 13:15 ` [PATCH 6.12.y-cip 17/18] arm64: dts: renesas: r9a09g077m44-rzt2h-evk: Add GPIO keys Cosmin Tanislav
@ 2026-08-21 13:15 ` Cosmin Tanislav
2026-08-22 8:11 ` [PATCH 6.12.y-cip 00/18] Add ICU support for RZ/T2H and RZ/N2H SoCs Pavel Machek
18 siblings, 0 replies; 23+ messages in thread
From: Cosmin Tanislav @ 2026-08-21 13:15 UTC (permalink / raw)
To: cip-dev, pavel, nobuhiro.iwamatsu.x90
commit 2c089ad703527f5ae08c7c362a9dfe5a660ab16d upstream.
The Renesas RZ/N2H Evaluation Kit has three user buttons connected to
GPIOs that can be used as input keys.
Add support for them.
Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20251205150234.2958140-9-cosmin-gabriel.tanislav.xa@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com>
---
.../dts/renesas/r9a09g087m44-rzn2h-evk.dts | 30 +++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts
index 06f1c14560da..eb19e3c565ab 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts
+++ b/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts
@@ -7,6 +7,8 @@
/dts-v1/;
+#include <dt-bindings/input/input.h>
+
#include "r9a09g087m44.dtsi"
/*
@@ -81,6 +83,34 @@ / {
model = "Renesas RZ/N2H EVK Board based on r9a09g087m44";
compatible = "renesas,rzn2h-evk", "renesas,r9a09g087m44", "renesas,r9a09g087";
+ keys {
+ compatible = "gpio-keys";
+
+ key-1 {
+ interrupts-extended = <&pinctrl RZT2H_GPIO(18, 2) IRQ_TYPE_EDGE_FALLING>;
+ linux,code = <KEY_1>;
+ label = "SW2";
+ wakeup-source;
+ debounce-interval = <20>;
+ };
+
+ key-2 {
+ interrupts-extended = <&pinctrl RZT2H_GPIO(0, 4) IRQ_TYPE_EDGE_FALLING>;
+ linux,code = <KEY_2>;
+ label = "SW3";
+ wakeup-source;
+ debounce-interval = <20>;
+ };
+
+ key-3 {
+ interrupts-extended = <&pinctrl RZT2H_GPIO(18, 7) IRQ_TYPE_EDGE_FALLING>;
+ linux,code = <KEY_3>;
+ label = "SW4";
+ wakeup-source;
+ debounce-interval = <20>;
+ };
+ };
+
leds {
compatible = "gpio-leds";
--
2.55.0
^ permalink raw reply related [flat|nested] 23+ messages in thread* Re: [PATCH 6.12.y-cip 00/18] Add ICU support for RZ/T2H and RZ/N2H SoCs
2026-08-21 13:15 [PATCH 6.12.y-cip 00/18] Add ICU support for RZ/T2H and RZ/N2H SoCs Cosmin Tanislav
` (17 preceding siblings ...)
2026-08-21 13:15 ` [PATCH 6.12.y-cip 18/18] arm64: dts: renesas: r9a09g087m44-rzn2h-evk: " Cosmin Tanislav
@ 2026-08-22 8:11 ` Pavel Machek
2026-08-24 9:09 ` [cip-dev] " nobuhiro.iwamatsu.x90
18 siblings, 1 reply; 23+ messages in thread
From: Pavel Machek @ 2026-08-22 8:11 UTC (permalink / raw)
To: Cosmin Tanislav; +Cc: cip-dev, pavel, nobuhiro.iwamatsu.x90
[-- Attachment #1: Type: text/plain, Size: 406 bytes --]
Hi!
> This patch series adds support for the ICU block, including
> software-triggered interrupts and error interrupts, as found in the
> Renesas RZ/T2H and RZ/N2H SoCs.
This looks okay to me.
Reviewed-by: Pavel Machek <pavel@nabladev.com>
I can apply the series if it passes testing and there are no other
comments.
Best regards,
Pavel
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 195 bytes --]
^ permalink raw reply [flat|nested] 23+ messages in thread* RE: [cip-dev] [PATCH 6.12.y-cip 00/18] Add ICU support for RZ/T2H and RZ/N2H SoCs
2026-08-22 8:11 ` [PATCH 6.12.y-cip 00/18] Add ICU support for RZ/T2H and RZ/N2H SoCs Pavel Machek
@ 2026-08-24 9:09 ` nobuhiro.iwamatsu.x90
2026-08-24 9:26 ` Pavel Machek
0 siblings, 1 reply; 23+ messages in thread
From: nobuhiro.iwamatsu.x90 @ 2026-08-24 9:09 UTC (permalink / raw)
To: pavel, cosmin-gabriel.tanislav.xa; +Cc: cip-dev
HI all,
> -----Original Message-----
> From: cip-dev@lists.cip-project.org <cip-dev@lists.cip-project.org> On
> Behalf Of Pavel Machek via lists.cip-project.org
> Sent: Saturday, August 22, 2026 5:11 PM
> To: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com>
> Cc: cip-dev@lists.cip-project.org; pavel@nabladev.com; iwamatsu
> nobuhiro(岩松 信洋 □ＤＩＴＣ○ＣＰＴ)
> <nobuhiro.iwamatsu.x90@mail.toshiba>
> Subject: Re: [cip-dev] [PATCH 6.12.y-cip 00/18] Add ICU support for RZ/T2H
> and RZ/N2H SoCs
>
> Hi!
>
> > This patch series adds support for the ICU block, including
> > software-triggered interrupts and error interrupts, as found in the
> > Renesas RZ/T2H and RZ/N2H SoCs.
>
> This looks okay to me.
>
> Reviewed-by: Pavel Machek <pavel@nabladev.com>
>
> I can apply the series if it passes testing and there are no other comments.
I also reviewed this series, look good to me too.
I applied with Pavel's reviewed-by tag.
>
> Best regards,
> Pavel
Best regards,
Nobuhiro
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [cip-dev] [PATCH 6.12.y-cip 00/18] Add ICU support for RZ/T2H and RZ/N2H SoCs
2026-08-24 9:09 ` [cip-dev] " nobuhiro.iwamatsu.x90
@ 2026-08-24 9:26 ` Pavel Machek
2026-08-24 22:34 ` nobuhiro.iwamatsu.x90
0 siblings, 1 reply; 23+ messages in thread
From: Pavel Machek @ 2026-08-24 9:26 UTC (permalink / raw)
To: nobuhiro.iwamatsu.x90; +Cc: pavel, cosmin-gabriel.tanislav.xa, cip-dev
[-- Attachment #1: Type: text/plain, Size: 649 bytes --]
Hi!
> > > This patch series adds support for the ICU block, including
> > > software-triggered interrupts and error interrupts, as found in the
> > > Renesas RZ/T2H and RZ/N2H SoCs.
> >
> > This looks okay to me.
> >
> > Reviewed-by: Pavel Machek <pavel@nabladev.com>
> >
> > I can apply the series if it passes testing and there are no other comments.
>
> I also reviewed this series, look good to me too.
> I applied with Pavel's reviewed-by tag.
Sorry, we were working on the same thing at the same time.
It passed my testing, and I pushed the resulting tree before checking
the emails.
Best regards,
Pavel
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 195 bytes --]
^ permalink raw reply [flat|nested] 23+ messages in thread
* RE: [cip-dev] [PATCH 6.12.y-cip 00/18] Add ICU support for RZ/T2H and RZ/N2H SoCs
2026-08-24 9:26 ` Pavel Machek
@ 2026-08-24 22:34 ` nobuhiro.iwamatsu.x90
0 siblings, 0 replies; 23+ messages in thread
From: nobuhiro.iwamatsu.x90 @ 2026-08-24 22:34 UTC (permalink / raw)
To: pavel; +Cc: cosmin-gabriel.tanislav.xa, cip-dev
Hi Pavel,
> > > > This patch series adds support for the ICU block, including
> > > > software-triggered interrupts and error interrupts, as found in
> > > > the Renesas RZ/T2H and RZ/N2H SoCs.
> > >
> > > This looks okay to me.
> > >
> > > Reviewed-by: Pavel Machek <pavel@nabladev.com>
> > >
> > > I can apply the series if it passes testing and there are no other comments.
> >
> > I also reviewed this series, look good to me too.
> > I applied with Pavel's reviewed-by tag.
>
> Sorry, we were working on the same thing at the same time.
No problem. Thanks for your work!
>
> It passed my testing, and I pushed the resulting tree before checking the
> emails.
>
Great!
Best regards,
Nobuhiro
^ permalink raw reply [flat|nested] 23+ messages in thread