From: Fenghua Yu <fenghua.yu@intel.com>
To: "Vinod Koul" <vkoul@kernel.org>, "Dave Jiang" <dave.jiang@intel.com>
Cc: "linux-kernel" <linux-kernel@vger.kernel.org>,
dmaengine@vger.kernel.org, Fenghua Yu <fenghua.yu@intel.com>
Subject: [PATCH 2/5] dmanegine: idxd: reformat opcap output to match bitmap_parse() input
Date: Sat, 17 Sep 2022 09:12:19 -0700 [thread overview]
Message-ID: <20220917161222.2835172-3-fenghua.yu@intel.com> (raw)
In-Reply-To: <20220917161222.2835172-1-fenghua.yu@intel.com>
From: Dave Jiang <dave.jiang@intel.com>
To make input and output consistent and prepping for the per WQ operation
configuration support, change the output of opcap display to match the
input that is expected by bitmap_parse() helper function. The output will
be a bitmap with field width as the number of bits using the %*pb format
specifier for printk() family.
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
Co-developed-by: Fenghua Yu <fenghua.yu@intel.com>
Signed-off-by: Fenghua Yu <fenghua.yu@intel.com>
---
drivers/dma/idxd/idxd.h | 2 ++
drivers/dma/idxd/init.c | 20 ++++++++++++++++++++
drivers/dma/idxd/registers.h | 2 ++
drivers/dma/idxd/sysfs.c | 9 ++-------
4 files changed, 26 insertions(+), 7 deletions(-)
diff --git a/drivers/dma/idxd/idxd.h b/drivers/dma/idxd/idxd.h
index cda856bfc22a..3ab406d74176 100644
--- a/drivers/dma/idxd/idxd.h
+++ b/drivers/dma/idxd/idxd.h
@@ -308,6 +308,8 @@ struct idxd_device {
struct work_struct work;
struct idxd_pmu *idxd_pmu;
+
+ unsigned long *opcap_bmap;
};
/* IDXD software descriptor */
diff --git a/drivers/dma/idxd/init.c b/drivers/dma/idxd/init.c
index aa3478257ddb..913a55ccb864 100644
--- a/drivers/dma/idxd/init.c
+++ b/drivers/dma/idxd/init.c
@@ -369,6 +369,19 @@ static void idxd_read_table_offsets(struct idxd_device *idxd)
dev_dbg(dev, "IDXD Perfmon Offset: %#x\n", idxd->perfmon_offset);
}
+static void multi_u64_to_bmap(unsigned long *bmap, u64 *val, int count)
+{
+ int i, j, nr;
+
+ for (i = 0, nr = 0; i < count; i++) {
+ for (j = 0; j < BITS_PER_LONG_LONG; j++) {
+ if (val[i] & BIT(j))
+ set_bit(nr, bmap);
+ nr++;
+ }
+ }
+}
+
static void idxd_read_caps(struct idxd_device *idxd)
{
struct device *dev = &idxd->pdev->dev;
@@ -427,6 +440,7 @@ static void idxd_read_caps(struct idxd_device *idxd)
IDXD_OPCAP_OFFSET + i * sizeof(u64));
dev_dbg(dev, "opcap[%d]: %#llx\n", i, idxd->hw.opcap.bits[i]);
}
+ multi_u64_to_bmap(idxd->opcap_bmap, &idxd->hw.opcap.bits[0], 4);
}
static struct idxd_device *idxd_alloc(struct pci_dev *pdev, struct idxd_driver_data *data)
@@ -448,6 +462,12 @@ static struct idxd_device *idxd_alloc(struct pci_dev *pdev, struct idxd_driver_d
if (idxd->id < 0)
return NULL;
+ idxd->opcap_bmap = bitmap_zalloc_node(IDXD_MAX_OPCAP_BITS, GFP_KERNEL, dev_to_node(dev));
+ if (!idxd->opcap_bmap) {
+ ida_free(&idxd_ida, idxd->id);
+ return NULL;
+ }
+
device_initialize(conf_dev);
conf_dev->parent = dev;
conf_dev->bus = &dsa_bus_type;
diff --git a/drivers/dma/idxd/registers.h b/drivers/dma/idxd/registers.h
index 02449aa9c454..4c96ea85f843 100644
--- a/drivers/dma/idxd/registers.h
+++ b/drivers/dma/idxd/registers.h
@@ -90,6 +90,8 @@ struct opcap {
u64 bits[4];
};
+#define IDXD_MAX_OPCAP_BITS 256U
+
#define IDXD_OPCAP_OFFSET 0x40
#define IDXD_TABLE_OFFSET 0x60
diff --git a/drivers/dma/idxd/sysfs.c b/drivers/dma/idxd/sysfs.c
index be9ff9d4cc4b..9998ab4b28c8 100644
--- a/drivers/dma/idxd/sysfs.c
+++ b/drivers/dma/idxd/sysfs.c
@@ -1180,14 +1180,8 @@ static ssize_t op_cap_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct idxd_device *idxd = confdev_to_idxd(dev);
- int i, rc = 0;
-
- for (i = 0; i < 4; i++)
- rc += sysfs_emit_at(buf, rc, "%#llx ", idxd->hw.opcap.bits[i]);
- rc--;
- rc += sysfs_emit_at(buf, rc, "\n");
- return rc;
+ return sysfs_emit(buf, "%*pb\n", IDXD_MAX_OPCAP_BITS, idxd->opcap_bmap);
}
static DEVICE_ATTR_RO(op_cap);
@@ -1411,6 +1405,7 @@ static void idxd_conf_device_release(struct device *dev)
kfree(idxd->wqs);
kfree(idxd->engines);
ida_free(&idxd_ida, idxd->id);
+ bitmap_free(idxd->opcap_bmap);
kfree(idxd);
}
--
2.32.0
next prev parent reply other threads:[~2022-09-17 16:13 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-17 16:12 [PATCH 0/5] Enable a few DSA 2.0 features Fenghua Yu
2022-09-17 16:12 ` [PATCH 1/5] dmaengine: idxd: convert ats_dis to a wq flag Fenghua Yu
2022-09-17 16:12 ` Fenghua Yu [this message]
2022-09-17 16:12 ` [PATCH 3/5] dmaengine: idxd: add WQ operation cap restriction support Fenghua Yu
2022-09-17 16:12 ` [PATCH 4/5] dmaengine: idxd: add configuration for concurrent work descriptor processing Fenghua Yu
2022-09-17 16:12 ` [PATCH 5/5] dmaengine: idxd: add configuration for concurrent batch " Fenghua Yu
2022-09-29 16:29 ` [PATCH 0/5] Enable a few DSA 2.0 features Vinod Koul
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