[PATCH 0/4] dmaengine: fsl-edma: fix eDMAv4 uart dma loop test failure

[PATCH 0/4] dmaengine: fsl-edma: fix eDMAv4 uart dma loop test failure

[Frank Li]

The commit a725990557e7d ("arm64: dts: imx93: Fix the dmas entries order")
trigger a hidden eDMAv4 hardware limitation.

Some channel require stick to odd number, some require stick to even
number.

This fixes include 3 part.
1. add limitation at eDMA driver.
2. create dt-binding header file to share define between driver and dts
3. add ODD and EVEN requirement for uart driver at dts file.

Frank Li (4):
  dmaengine: fsl-edma: fix eDMAv4 channel allocation issue
  dt-bindings: dma: fsl-edma: Add fsl-edma.h to prevent hardcoding in
    dts
  dmaengine: fsl-edma: utilize common dt-binding header file
  arm64: dts: imx93: Fix EDMA transfer failure

 arch/arm64/boot/dts/freescale/imx93.dtsi | 13 +++++++++----
 drivers/dma/fsl-edma-main.c              | 17 ++++++++++-------
 include/dt-bindings/dma/fsl-edma.h       | 21 +++++++++++++++++++++
 3 files changed, 40 insertions(+), 11 deletions(-)
 create mode 100644 include/dt-bindings/dma/fsl-edma.h

-- 
2.34.1

[PATCH 1/4] dmaengine: fsl-edma: fix eDMAv4 channel allocation issue

[Frank Li]

The eDMAv4 channel mux has a limitation where certain requests must use
even channels, while others must use odd numbers.

Add two flags (ARGS_EVEN_CH and ARGS_ODD_CH) to reflect this limitation.
The device tree source (dts) files need to be updated accordingly.

This issue was identified by the following commit:
commit a725990557e7 ("arm64: dts: imx93: Fix the dmas entries order")

Reverting channel orders triggered this problem.

Fixes: 72f5801a4e2b ("dmaengine: fsl-edma: integrate v3 support")
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
 drivers/dma/fsl-edma-main.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/dma/fsl-edma-main.c b/drivers/dma/fsl-edma-main.c
index 4635e16d7705e..3ee08f390f810 100644
--- a/drivers/dma/fsl-edma-main.c
+++ b/drivers/dma/fsl-edma-main.c
@@ -24,6 +24,8 @@
 #define ARGS_RX                         BIT(0)
 #define ARGS_REMOTE                     BIT(1)
 #define ARGS_MULTI_FIFO                 BIT(2)
+#define ARGS_EVEN_CH                    BIT(3)
+#define ARGS_ODD_CH                     BIT(4)
 
 static void fsl_edma_synchronize(struct dma_chan *chan)
 {
@@ -157,6 +159,12 @@ static struct dma_chan *fsl_edma3_xlate(struct of_phandle_args *dma_spec,
 		fsl_chan->is_remote = dma_spec->args[2] & ARGS_REMOTE;
 		fsl_chan->is_multi_fifo = dma_spec->args[2] & ARGS_MULTI_FIFO;
 
+		if ((dma_spec->args[2] & ARGS_EVEN_CH) && (i & 0x1))
+			continue;
+
+		if ((dma_spec->args[2] & ARGS_ODD_CH) && !(i & 0x1))
+			continue;
+
 		if (!b_chmux && i == dma_spec->args[0]) {
 			chan = dma_get_slave_channel(chan);
 			chan->device->privatecnt++;
-- 
2.34.1

[PATCH 2/4] dt-bindings: dma: fsl-edma: Add fsl-edma.h to prevent hardcoding in dts

[Frank Li]

Introduce a common dt-bindings header file, fsl-edma.h, shared between
the driver and dts files. This addition aims to eliminate hardcoded values
in dts files, promoting maintainability and consistency.

DTS header file not support BIT() macro yet. Directly use 2^n number.

Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
 include/dt-bindings/dma/fsl-edma.h | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)
 create mode 100644 include/dt-bindings/dma/fsl-edma.h

diff --git a/include/dt-bindings/dma/fsl-edma.h b/include/dt-bindings/dma/fsl-edma.h
new file mode 100644
index 0000000000000..fd11478cfe9cc
--- /dev/null
+++ b/include/dt-bindings/dma/fsl-edma.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
+
+#ifndef _FSL_EDMA_DT_BINDING_H_
+#define _FSL_EDMA_DT_BINDING_H_
+
+/* Receive Channel */
+#define FSL_EDMA_RX		0x1
+
+/* iMX8 audio remote DMA */
+#define FSL_EDMA_REMOTE		0x2
+
+/* FIFO is continue memory region */
+#define FSL_EDMA_MULTI_FIFO	0x4
+
+/* Channel need stick to even channel */
+#define FSL_EDMA_EVEN_CH	0x8
+
+/* Channel need stick to odd channel */
+#define FSL_EDMA_ODD_CH		0x10
+
+#endif
-- 
2.34.1

Re: [PATCH 2/4] dt-bindings: dma: fsl-edma: Add fsl-edma.h to prevent hardcoding in dts

[Rob Herring]

On Tue, 14 Nov 2023 10:48:22 -0500, Frank Li wrote:
> Introduce a common dt-bindings header file, fsl-edma.h, shared between
> the driver and dts files. This addition aims to eliminate hardcoded values
> in dts files, promoting maintainability and consistency.
> 
> DTS header file not support BIT() macro yet. Directly use 2^n number.
> 
> Signed-off-by: Frank Li <Frank.Li@nxp.com>
> ---
>  include/dt-bindings/dma/fsl-edma.h | 21 +++++++++++++++++++++
>  1 file changed, 21 insertions(+)
>  create mode 100644 include/dt-bindings/dma/fsl-edma.h
> 

Reviewed-by: Rob Herring <robh@kernel.org>

[PATCH 3/4] dmaengine: fsl-edma: utilize common dt-binding header file

[Frank Li]

Refactor the code to use the common dt-binding header file, fsl-edma.h.
Renaming ARGS* to FSL_EDMA*, ensuring no functional changes.

Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
 drivers/dma/fsl-edma-main.c | 17 ++++++-----------
 1 file changed, 6 insertions(+), 11 deletions(-)

diff --git a/drivers/dma/fsl-edma-main.c b/drivers/dma/fsl-edma-main.c
index 3ee08f390f810..f53b0ec17bcbc 100644
--- a/drivers/dma/fsl-edma-main.c
+++ b/drivers/dma/fsl-edma-main.c
@@ -9,6 +9,7 @@
  * Vybrid and Layerscape SoCs.
  */
 
+#include <dt-bindings/dma/fsl-edma.h>
 #include <linux/module.h>
 #include <linux/interrupt.h>
 #include <linux/clk.h>
@@ -21,12 +22,6 @@
 
 #include "fsl-edma-common.h"
 
-#define ARGS_RX                         BIT(0)
-#define ARGS_REMOTE                     BIT(1)
-#define ARGS_MULTI_FIFO                 BIT(2)
-#define ARGS_EVEN_CH                    BIT(3)
-#define ARGS_ODD_CH                     BIT(4)
-
 static void fsl_edma_synchronize(struct dma_chan *chan)
 {
 	struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan);
@@ -155,14 +150,14 @@ static struct dma_chan *fsl_edma3_xlate(struct of_phandle_args *dma_spec,
 		i = fsl_chan - fsl_edma->chans;
 
 		fsl_chan->priority = dma_spec->args[1];
-		fsl_chan->is_rxchan = dma_spec->args[2] & ARGS_RX;
-		fsl_chan->is_remote = dma_spec->args[2] & ARGS_REMOTE;
-		fsl_chan->is_multi_fifo = dma_spec->args[2] & ARGS_MULTI_FIFO;
+		fsl_chan->is_rxchan = dma_spec->args[2] & FSL_EDMA_RX;
+		fsl_chan->is_remote = dma_spec->args[2] & FSL_EDMA_REMOTE;
+		fsl_chan->is_multi_fifo = dma_spec->args[2] & FSL_EDMA_MULTI_FIFO;
 
-		if ((dma_spec->args[2] & ARGS_EVEN_CH) && (i & 0x1))
+		if ((dma_spec->args[2] & FSL_EDMA_EVEN_CH) && (i & 0x1))
 			continue;
 
-		if ((dma_spec->args[2] & ARGS_ODD_CH) && !(i & 0x1))
+		if ((dma_spec->args[2] & FSL_EDMA_ODD_CH) && !(i & 0x1))
 			continue;
 
 		if (!b_chmux && i == dma_spec->args[0]) {
-- 
2.34.1

[PATCH 4/4] arm64: dts: imx93: Fix EDMA transfer failure

[Frank Li]

The EDMAv4 has hardware restrictions, requiring some channels to be
allocated to ODD and others to EVEN. The previous eDMA driver did not
account for these restrictions, and it worked due to the order in dts
matching the requirements. The commit below reverts the rx/tx channel,
triggering this issue.

Adds channel requirements to the dts to instruct the driver to allocate
odd or even channels, ensuring it is not dependent on the order of rx/tx in
dts.

Fixes: a725990557e7 ("arm64: dts: imx93: Fix the dmas entries order")
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
 arch/arm64/boot/dts/freescale/imx93.dtsi | 13 +++++++++----
 1 file changed, 9 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/imx93.dtsi b/arch/arm64/boot/dts/freescale/imx93.dtsi
index ceccf47664407..6f06ebdcb2513 100644
--- a/arch/arm64/boot/dts/freescale/imx93.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx93.dtsi
@@ -4,6 +4,7 @@
  */
 
 #include <dt-bindings/clock/imx93-clock.h>
+#include <dt-bindings/dma/fsl-edma.h>
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -670,7 +671,8 @@ lpuart3: serial@42570000 {
 				interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&clk IMX93_CLK_LPUART3_GATE>;
 				clock-names = "ipg";
-				dmas = <&edma2 18 0 1>, <&edma2 17 0 0>;
+				dmas = <&edma2 18 0 (FSL_EDMA_RX | FSL_EDMA_ODD_CH)>,
+				       <&edma2 17 0 FSL_EDMA_EVEN_CH>;
 				dma-names = "rx", "tx";
 				status = "disabled";
 			};
@@ -681,7 +683,8 @@ lpuart4: serial@42580000 {
 				interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&clk IMX93_CLK_LPUART4_GATE>;
 				clock-names = "ipg";
-				dmas = <&edma2 20 0 1>, <&edma2 19 0 0>;
+				dmas = <&edma2 20 0 (FSL_EDMA_RX | FSL_EDMA_ODD_CH)>,
+				       <&edma2 19 0 FSL_EDMA_EVEN_CH>;
 				dma-names = "rx", "tx";
 				status = "disabled";
 			};
@@ -692,7 +695,8 @@ lpuart5: serial@42590000 {
 				interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&clk IMX93_CLK_LPUART5_GATE>;
 				clock-names = "ipg";
-				dmas = <&edma2 22 0 1>, <&edma2 21 0 0>;
+				dmas = <&edma2 22 0 (FSL_EDMA_RX | FSL_EDMA_ODD_CH)>,
+				       <&edma2 21 0 FSL_EDMA_EVEN_CH>;
 				dma-names = "rx", "tx";
 				status = "disabled";
 			};
@@ -703,7 +707,8 @@ lpuart6: serial@425a0000 {
 				interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&clk IMX93_CLK_LPUART6_GATE>;
 				clock-names = "ipg";
-				dmas = <&edma2 24 0 1>, <&edma2 23 0 0>;
+				dmas = <&edma2 24 0 (FSL_EDMA_RX | FSL_EDMA_ODD_CH)>,
+				       <&edma2 23 0 FSL_EDMA_EVEN_CH>;
 				dma-names = "rx", "tx";
 				status = "disabled";
 			};
-- 
2.34.1

Re: [PATCH 0/4] dmaengine: fsl-edma: fix eDMAv4 uart dma loop test failure

[Frank Li]

On Tue, Nov 14, 2023 at 10:48:20AM -0500, Frank Li wrote:
> The commit a725990557e7d ("arm64: dts: imx93: Fix the dmas entries order")
> trigger a hidden eDMAv4 hardware limitation.
> 
> Some channel require stick to odd number, some require stick to even
> number.
> 
> This fixes include 3 part.
> 1. add limitation at eDMA driver.
> 2. create dt-binding header file to share define between driver and dts
> 3. add ODD and EVEN requirement for uart driver at dts file.

@vkoul:
	Did you have chance to check this patch?

Frank	

> 
> Frank Li (4):
>   dmaengine: fsl-edma: fix eDMAv4 channel allocation issue
>   dt-bindings: dma: fsl-edma: Add fsl-edma.h to prevent hardcoding in
>     dts
>   dmaengine: fsl-edma: utilize common dt-binding header file
>   arm64: dts: imx93: Fix EDMA transfer failure
> 
>  arch/arm64/boot/dts/freescale/imx93.dtsi | 13 +++++++++----
>  drivers/dma/fsl-edma-main.c              | 17 ++++++++++-------
>  include/dt-bindings/dma/fsl-edma.h       | 21 +++++++++++++++++++++
>  3 files changed, 40 insertions(+), 11 deletions(-)
>  create mode 100644 include/dt-bindings/dma/fsl-edma.h
> 
> -- 
> 2.34.1
> 

Re: (subset) [PATCH 0/4] dmaengine: fsl-edma: fix eDMAv4 uart dma loop test failure

[Vinod Koul]

On Tue, 14 Nov 2023 10:48:20 -0500, Frank Li wrote:
> The commit a725990557e7d ("arm64: dts: imx93: Fix the dmas entries order")
> trigger a hidden eDMAv4 hardware limitation.
> 
> Some channel require stick to odd number, some require stick to even
> number.
> 
> This fixes include 3 part.
> 1. add limitation at eDMA driver.
> 2. create dt-binding header file to share define between driver and dts
> 3. add ODD and EVEN requirement for uart driver at dts file.
> 
> [...]

Applied, thanks!

[1/4] dmaengine: fsl-edma: fix eDMAv4 channel allocation issue
      commit: dc51b4442dd94ab12c146c1897bbdb40e16d5636
[2/4] dt-bindings: dma: fsl-edma: Add fsl-edma.h to prevent hardcoding in dts
      commit: 1e9b05258271b76ccc04a4b535009d2cb596506a
[3/4] dmaengine: fsl-edma: utilize common dt-binding header file
      commit: d0e217b72f9f5c5ef35e3423d393ea8093ce98ec

Best regards,
-- 
~Vinod