DMA Engine development
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From: Koichiro Den <den@valinux.co.jp>
To: Vinod Koul <vkoul@kernel.org>, Frank Li <Frank.Li@kernel.org>,
	Manivannan Sadhasivam <mani@kernel.org>
Cc: Marek Vasut <marek.vasut+renesas@mailbox.org>,
	Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>,
	dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: [PATCH v4 10/14] dmaengine: dw-edma-pcie: Add register offset match flag
Date: Fri, 10 Jul 2026 17:15:14 +0900	[thread overview]
Message-ID: <20260710081518.2394357-11-den@valinux.co.jp> (raw)
In-Reply-To: <20260710081518.2394357-1-den@valinux.co.jp>

Add a match-data flag for devices whose DMA register block starts at an
offset inside the mapped BAR. Existing Synopsys EDDA and AMD (Xilinx)
MDB/CPM6 matches keep using the BAR mapping base directly.

The offsets handled here come from static, trusted match data. Later
metadata-derived offsets are validated when the endpoint DMA metadata
path parses them at that trust boundary.

No functional change intended.

Reviewed-by: Frank Li <Frank.Li@nxp.com>
The offsets come from static match data and need no bounds check
here; metadata-derived offsets arriving with the part 3 discovery
patch are validated against the mapped BAR size at that trust
boundary.

Signed-off-by: Koichiro Den <den@valinux.co.jp>
---
Changes in v4:
  - No changes.

 drivers/dma/dw-edma/dw-edma-pcie.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/dma/dw-edma/dw-edma-pcie.c b/drivers/dma/dw-edma/dw-edma-pcie.c
index 36b18032c835..a19282c15644 100644
--- a/drivers/dma/dw-edma/dw-edma-pcie.c
+++ b/drivers/dma/dw-edma/dw-edma-pcie.c
@@ -89,6 +89,7 @@ struct dw_edma_pcie_match_data {
 };
 
 #define DW_EDMA_PCIE_F_DEVMEM_PHYS_OFF	BIT(0)
+#define DW_EDMA_PCIE_F_REG_OFFSET	BIT(1)
 
 static const struct dw_edma_pcie_data snps_edda_data = {
 	/* eDMA registers location */
@@ -464,6 +465,8 @@ static int dw_edma_pcie_probe(struct pci_dev *pdev,
 	chip->reg_base = pcim_iomap_table(pdev)[dma_data->rg.bar];
 	if (!chip->reg_base)
 		return -ENOMEM;
+	if (match->flags & DW_EDMA_PCIE_F_REG_OFFSET)
+		chip->reg_base += dma_data->rg.off;
 
 	for (i = 0; i < chip->ll_wr_cnt && !dma_data->cfg_non_ll; i++) {
 		struct dw_edma_region *ll_region = &chip->ll_region_wr[i];
-- 
2.51.0


  parent reply	other threads:[~2026-07-10  8:15 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-07-10  8:15 [PATCH v4 00/14] dmaengine: dw-edma: Prepare for PCI EP DMA (part 1/3) Koichiro Den
2026-07-10  8:15 ` [PATCH v4 01/14] dmaengine: dw-edma: Factor out HDMA interrupt setup helper Koichiro Den
2026-07-10  8:15 ` [PATCH v4 02/14] dmaengine: dw-edma: Add per-channel interrupt routing control Koichiro Den
2026-07-10  8:15 ` [PATCH v4 03/14] dmaengine: dw-edma: Add core quiesce operations Koichiro Den
2026-07-14 19:23   ` Frank Li
2026-07-10  8:15 ` [PATCH v4 04/14] dmaengine: dw-edma: Initialize IRQ data before requesting IRQs Koichiro Den
2026-07-10  8:15 ` [PATCH v4 05/14] dmaengine: dw-edma: Add partial channel ownership mode Koichiro Den
2026-07-14 19:29   ` Frank Li
2026-07-16 15:52     ` Koichiro Den
2026-07-10  8:15 ` [PATCH v4 06/14] dmaengine: dw-edma-pcie: Track non-LL mode in DMA data Koichiro Den
2026-07-10  8:15 ` [PATCH v4 07/14] dmaengine: dw-edma-pcie: Add capability match data Koichiro Den
2026-07-10  8:15 ` [PATCH v4 08/14] dmaengine: dw-edma-pcie: Rename vsec_data to dma_data Koichiro Den
2026-07-10  8:15 ` [PATCH v4 09/14] dmaengine: dw-edma-pcie: Add platform ops to match data Koichiro Den
2026-07-10  8:15 ` Koichiro Den [this message]
2026-07-10  8:15 ` [PATCH v4 11/14] dmaengine: dw-edma-pcie: Factor out descriptor block address lookup Koichiro Den
2026-07-10  8:15 ` [PATCH v4 12/14] dmaengine: dw-edma-pcie: Handle optional data blocks Koichiro Den
2026-07-10  8:15 ` [PATCH v4 13/14] dmaengine: dw-edma-pcie: Add chip flags to match data Koichiro Den
2026-07-10  8:15 ` [PATCH v4 14/14] dmaengine: dw-edma: Program endpoint function numbers Koichiro Den
2026-07-14 19:32   ` Frank Li

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