From: Koichiro Den <den@valinux.co.jp>
To: Vinod Koul <vkoul@kernel.org>, Frank Li <Frank.Li@kernel.org>,
Manivannan Sadhasivam <mani@kernel.org>
Cc: Marek Vasut <marek.vasut+renesas@mailbox.org>,
Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>,
dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: [PATCH v4 14/14] dmaengine: dw-edma: Program endpoint function numbers
Date: Fri, 10 Jul 2026 17:15:18 +0900 [thread overview]
Message-ID: <20260710081518.2394357-15-den@valinux.co.jp> (raw)
In-Reply-To: <20260710081518.2394357-1-den@valinux.co.jp>
The eDMA/HDMA transfers the driver issues carry a requester function
number in their TLPs, but nothing ever programs it: eDMA v0 leaves the
FUNC_NUM field of the channel control word zero and HDMA leaves the
per-channel func_num register at its reset value, so every transfer is
attributed to function 0. That is invisible in single-function setups,
but once the DMA block serves a non-zero endpoint function, its
requests must carry that function's number for the host to attribute
and translate them correctly.
Record the function number in the chip data (PCI_FUNC() of the probing
device for dw-edma-pcie) and program it per channel.
Endpoint-local chip instances keep func_no at 0, so transfers issued by
the endpoint-side driver remain PF0-attributed. Delegated channels are
programmed by the host-side dw-edma-pcie instance when it takes over the
channel, using that instance's PCI_FUNC().
Signed-off-by: Koichiro Den <den@valinux.co.jp>
---
Changes in v4:
- New patch in v4.
drivers/dma/dw-edma/dw-edma-core.c | 1 +
drivers/dma/dw-edma/dw-edma-core.h | 1 +
drivers/dma/dw-edma/dw-edma-pcie.c | 1 +
drivers/dma/dw-edma/dw-edma-v0-core.c | 10 +++++++++-
drivers/dma/dw-edma/dw-hdma-v0-core.c | 3 +++
drivers/dma/dw-edma/dw-hdma-v0-regs.h | 1 +
include/linux/dma/edma.h | 2 ++
7 files changed, 18 insertions(+), 1 deletion(-)
diff --git a/drivers/dma/dw-edma/dw-edma-core.c b/drivers/dma/dw-edma/dw-edma-core.c
index 0d38de4480a0..d1af44124075 100644
--- a/drivers/dma/dw-edma/dw-edma-core.c
+++ b/drivers/dma/dw-edma/dw-edma-core.c
@@ -1016,6 +1016,7 @@ static int dw_edma_channel_setup(struct dw_edma *dw, u32 wr_alloc, u32 rd_alloc)
chan = &dw->chan[i];
chan->dw = dw;
+ chan->func_no = chip->func_no;
if (i < dw->wr_ch_cnt) {
chan->id = i;
diff --git a/drivers/dma/dw-edma/dw-edma-core.h b/drivers/dma/dw-edma/dw-edma-core.h
index 8657275d2484..1cf95ab27071 100644
--- a/drivers/dma/dw-edma/dw-edma-core.h
+++ b/drivers/dma/dw-edma/dw-edma-core.h
@@ -78,6 +78,7 @@ struct dw_edma_chan {
struct dw_edma *dw;
int id;
enum dw_edma_dir dir;
+ u8 func_no;
u32 ll_max;
diff --git a/drivers/dma/dw-edma/dw-edma-pcie.c b/drivers/dma/dw-edma/dw-edma-pcie.c
index c1585c8ce11f..bb477dc0fb03 100644
--- a/drivers/dma/dw-edma/dw-edma-pcie.c
+++ b/drivers/dma/dw-edma/dw-edma-pcie.c
@@ -473,6 +473,7 @@ static int dw_edma_pcie_probe(struct pci_dev *pdev,
chip->mf = dma_data->mf;
chip->flags = match->chip_flags;
+ chip->func_no = PCI_FUNC(pdev->devfn);
chip->nr_irqs = nr_irqs;
chip->ops = match->plat_ops;
chip->cfg_non_ll = dma_data->cfg_non_ll;
diff --git a/drivers/dma/dw-edma/dw-edma-v0-core.c b/drivers/dma/dw-edma/dw-edma-v0-core.c
index 32df5d13ba8b..441fa8f67d5a 100644
--- a/drivers/dma/dw-edma/dw-edma-v0-core.c
+++ b/drivers/dma/dw-edma/dw-edma-v0-core.c
@@ -25,6 +25,8 @@ enum dw_edma_control {
DW_EDMA_V0_LLE = BIT(9),
};
+#define EDMA_V0_FUNC_NUM_MASK GENMASK(16, 12)
+
static inline struct dw_edma_v0_regs __iomem *__dw_regs(struct dw_edma *dw)
{
return dw->chip->reg_base;
@@ -159,6 +161,11 @@ static inline u32 readl_ch(struct dw_edma *dw, enum dw_edma_dir dir, u16 ch,
#define GET_CH_32(dw, dir, ch, name) \
readl_ch(dw, dir, ch, &(__dw_ch_regs(dw, dir, ch)->name))
+static u32 dw_edma_v0_func_num(struct dw_edma_chan *chan)
+{
+ return FIELD_PREP(EDMA_V0_FUNC_NUM_MASK, chan->func_no);
+}
+
/* eDMA management callbacks */
static void dw_edma_v0_core_dir_off(struct dw_edma *dw, enum dw_edma_dir dir)
{
@@ -474,7 +481,8 @@ static void dw_edma_v0_core_start(struct dw_edma_chunk *chunk, bool first)
/* Channel control */
SET_CH_32(dw, chan->dir, chan->id, ch_control1,
- (DW_EDMA_V0_CCS | DW_EDMA_V0_LLE));
+ DW_EDMA_V0_CCS | DW_EDMA_V0_LLE |
+ dw_edma_v0_func_num(chan));
/* Linked list */
/* llp is not aligned on 64bit -> keep 32bit accesses */
SET_CH_32(dw, chan->dir, chan->id, llp.lsb,
diff --git a/drivers/dma/dw-edma/dw-hdma-v0-core.c b/drivers/dma/dw-edma/dw-hdma-v0-core.c
index be22f9f811ca..ea9f18c8d707 100644
--- a/drivers/dma/dw-edma/dw-hdma-v0-core.c
+++ b/drivers/dma/dw-edma/dw-hdma-v0-core.c
@@ -375,6 +375,9 @@ static void dw_hdma_v0_core_ch_config(struct dw_edma_chan *chan)
SET_CH_32(dw, chan->dir, chan->id, msi_abort.msb, chan->msi.address_hi);
/* config MSI data */
SET_CH_32(dw, chan->dir, chan->id, msi_msgdata, chan->msi.data);
+ /* Configure the requester function number used by outbound TLPs. */
+ SET_CH_32(dw, chan->dir, chan->id, func_num,
+ FIELD_PREP(HDMA_V0_FUNC_NUM_PF_MASK, chan->func_no));
}
/* HDMA debugfs callbacks */
diff --git a/drivers/dma/dw-edma/dw-hdma-v0-regs.h b/drivers/dma/dw-edma/dw-hdma-v0-regs.h
index 7759ba9b4850..2bbcc7fabb0a 100644
--- a/drivers/dma/dw-edma/dw-hdma-v0-regs.h
+++ b/drivers/dma/dw-edma/dw-hdma-v0-regs.h
@@ -24,6 +24,7 @@
#define HDMA_V0_CONSUMER_CYCLE_BIT BIT(0)
#define HDMA_V0_DOORBELL_START BIT(0)
#define HDMA_V0_CH_STATUS_MASK GENMASK(1, 0)
+#define HDMA_V0_FUNC_NUM_PF_MASK GENMASK(7, 0)
struct dw_hdma_v0_ch_regs {
u32 ch_en; /* 0x0000 */
diff --git a/include/linux/dma/edma.h b/include/linux/dma/edma.h
index 3c33d12d1cdb..64044451d182 100644
--- a/include/linux/dma/edma.h
+++ b/include/linux/dma/edma.h
@@ -116,6 +116,7 @@ enum dw_edma_ch_irq_mode {
* @db_irq: Virtual IRQ dedicated to interrupt emulation
* @db_offset: Offset from DMA register base
* @mf: DMA register map format
+ * @func_no: PCI endpoint function number used by DMA TLPs
* @dw: struct dw_edma that is filled by dw_edma_probe()
*/
struct dw_edma_chip {
@@ -141,6 +142,7 @@ struct dw_edma_chip {
resource_size_t db_offset;
enum dw_edma_map_format mf;
+ u8 func_no;
struct dw_edma *dw;
bool cfg_non_ll;
--
2.51.0
next prev parent reply other threads:[~2026-07-10 8:15 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-10 8:15 [PATCH v4 00/14] dmaengine: dw-edma: Prepare for PCI EP DMA (part 1/3) Koichiro Den
2026-07-10 8:15 ` [PATCH v4 01/14] dmaengine: dw-edma: Factor out HDMA interrupt setup helper Koichiro Den
2026-07-10 8:15 ` [PATCH v4 02/14] dmaengine: dw-edma: Add per-channel interrupt routing control Koichiro Den
2026-07-10 8:15 ` [PATCH v4 03/14] dmaengine: dw-edma: Add core quiesce operations Koichiro Den
2026-07-14 19:23 ` Frank Li
2026-07-10 8:15 ` [PATCH v4 04/14] dmaengine: dw-edma: Initialize IRQ data before requesting IRQs Koichiro Den
2026-07-10 8:15 ` [PATCH v4 05/14] dmaengine: dw-edma: Add partial channel ownership mode Koichiro Den
2026-07-14 19:29 ` Frank Li
2026-07-16 15:52 ` Koichiro Den
2026-07-10 8:15 ` [PATCH v4 06/14] dmaengine: dw-edma-pcie: Track non-LL mode in DMA data Koichiro Den
2026-07-10 8:15 ` [PATCH v4 07/14] dmaengine: dw-edma-pcie: Add capability match data Koichiro Den
2026-07-10 8:15 ` [PATCH v4 08/14] dmaengine: dw-edma-pcie: Rename vsec_data to dma_data Koichiro Den
2026-07-10 8:15 ` [PATCH v4 09/14] dmaengine: dw-edma-pcie: Add platform ops to match data Koichiro Den
2026-07-10 8:15 ` [PATCH v4 10/14] dmaengine: dw-edma-pcie: Add register offset match flag Koichiro Den
2026-07-10 8:15 ` [PATCH v4 11/14] dmaengine: dw-edma-pcie: Factor out descriptor block address lookup Koichiro Den
2026-07-10 8:15 ` [PATCH v4 12/14] dmaengine: dw-edma-pcie: Handle optional data blocks Koichiro Den
2026-07-10 8:15 ` [PATCH v4 13/14] dmaengine: dw-edma-pcie: Add chip flags to match data Koichiro Den
2026-07-10 8:15 ` Koichiro Den [this message]
2026-07-14 19:32 ` [PATCH v4 14/14] dmaengine: dw-edma: Program endpoint function numbers Frank Li
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20260710081518.2394357-15-den@valinux.co.jp \
--to=den@valinux.co.jp \
--cc=Frank.Li@kernel.org \
--cc=dmaengine@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=mani@kernel.org \
--cc=marek.vasut+renesas@mailbox.org \
--cc=vkoul@kernel.org \
--cc=yoshihiro.shimoda.uh@renesas.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).