Re: [PATCH v5 02/14] dmaengine: dw-edma: Add per-channel interrupt routing control

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:

Pre-existing issues:
- [High] Cross-system read-modify-write (RMW) race on the shared `int_mask` register causes lost unmasks and DMA hangs. (Pre-existing)
--

--- Patch [2]: [PATCH v5 02/14] dmaengine: dw-edma: Add per-channel interrupt routing control ---
commit ce3c3f8c0117acd509b753117d45f3c2cf75e27d
Author: Koichiro Den <den@valinux.co.jp>
dmaengine: dw-edma: Add per-channel interrupt routing control

This patch adds per-channel interrupt routing control for the DesignWare
eDMA controller. It introduces a new routing mode to determine where a
channel should report completion and updates the interrupt masking and
generation logic accordingly.

> diff --git a/drivers/dma/dw-edma/dw-edma-v0-core.c b/drivers/dma/dw-edma/dw-edma-v0-core.c
> --- a/drivers/dma/dw-edma/dw-edma-v0-core.c
> +++ b/drivers/dma/dw-edma/dw-edma-v0-core.c
[ ... ]
> @@ -354,12 +360,17 @@ static void dw_edma_v0_core_ch_enable(struct dw_edma_chan *chan)
>  			break;
>  		}
>  	}
> -	/* Interrupt unmask - done, abort */
> +	/* Interrupt mask/unmask - done, abort */
>  	raw_spin_lock_irqsave(&dw->lock, flags);
>  
>  	tmp = GET_RW_32(dw, chan->dir, int_mask);
> -	tmp &= ~FIELD_PREP(EDMA_V0_DONE_INT_MASK, BIT(chan->id));
> -	tmp &= ~FIELD_PREP(EDMA_V0_ABORT_INT_MASK, BIT(chan->id));
> +	if (chan->irq_mode == DW_EDMA_CH_IRQ_REMOTE) {
> +		tmp |= FIELD_PREP(EDMA_V0_DONE_INT_MASK, BIT(chan->id));
> +		tmp |= FIELD_PREP(EDMA_V0_ABORT_INT_MASK, BIT(chan->id));
> +	} else {
> +		tmp &= ~FIELD_PREP(EDMA_V0_DONE_INT_MASK, BIT(chan->id));
> +		tmp &= ~FIELD_PREP(EDMA_V0_ABORT_INT_MASK, BIT(chan->id));
> +	}
>  	SET_RW_32(dw, chan->dir, int_mask, tmp);

[Severity: High]
This is a pre-existing issue, but does this read-modify-write sequence on the
shared int_mask register risk a race condition across the PCIe bus?

Since the PCIe Host and local endpoint drivers can independently execute
dw_edma_v0_core_ch_enable() concurrently, the local dw->lock does not
synchronize operations across the bus.

If the Host performs a read-modify-write that sets its mask bit to 1, could
this overwrite a concurrent read-modify-write by the endpoint clearing its
mask bit to 0? If the endpoint's unmask operation is reverted by the Host,
the endpoint's channel would remain masked, which appears to lead to a
lost interrupt and a DMA hang.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260717050308.2144108-1-den@valinux.co.jp?part=2