Re: [PATCH V2 2/8] dmaengine: zynqmp_dma: Free sw_desc_pool on desc_pool_v alloc failure

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:

Pre-existing issues:
- [High] The IRQ handler accesses hardware registers without checking if the device is active, violating Runtime PM guidelines.
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--- Patch [2]: [PATCH V2 2/8] dmaengine: zynqmp_dma: Free sw_desc_pool on desc_pool_v alloc failure ---
commit fa41ac69883ca2ff4e5d238f73142e53f1ec3b68
Author: Golla Nagendra <nagendra.golla@amd.com>
Subject: dmaengine: zynqmp_dma: Free sw_desc_pool on desc_pool_v alloc failure

This commit fixes a memory leak in zynqmp_dma_alloc_chan_resources() by
freeing the allocated sw_desc_pool if the subsequent desc_pool_v coherent
allocation fails. It adds a dedicated error label to ensure the software
descriptor pool is cleaned up before falling through to the runtime PM
rollback path.

> diff --git a/drivers/dma/xilinx/zynqmp_dma.c b/drivers/dma/xilinx/zynqmp_dma.c
> index 9f1e69700dd02..b7c5612806948 100644
> --- a/drivers/dma/xilinx/zynqmp_dma.c
> +++ b/drivers/dma/xilinx/zynqmp_dma.c

[ ... ]

> static irqreturn_t zynqmp_dma_irq_handler(int irq, void *data)
> {
> 	struct zynqmp_dma_chan *chan = (struct zynqmp_dma_chan *)data;
> 	u32 isr, imr, status;
> 	irqreturn_t ret = IRQ_NONE;
> 
> 	isr = readl(chan->regs + ZYNQMP_DMA_ISR);
> 	imr = readl(chan->regs + ZYNQMP_DMA_IMR);

[Severity: High]
This isn't a bug introduced by this patch, but does this interrupt handler
need to check the device's power state before accessing hardware registers?

During runtime suspend, the APB clock is disabled. If a spurious or
unexpected interrupt fires while the device is in this suspended state,
the handler executes and immediately reads ZYNQMP_DMA_ISR without calling
pm_runtime_get_if_active() to verify or resume the power state.

Could reading these registers while the clock is disabled cause a
synchronous external abort and lead to a system crash?

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Sashiko AI review · https://sashiko.dev/#/patchset/20260814045616.1661199-1-nagendra.golla@amd.com?part=2