From: "Li Youhong" <dayou5941@163.com>
To: Eugeniy.Paltsev@synopsys.com, vkoul@kernel.org
Cc: Frank.Li@kernel.org, dmaengine@vger.kernel.org,
Li Youhong <liyouhong@kylinos.cn>
Subject: [PATCH] dmaengine: dw-axi-dmac: fix cfgr_clk leak when core_clk enable fails
Date: Mon, 31 Aug 2026 17:44:38 +0800 [thread overview]
Message-ID: <20260831094438.2244538-1-dayou5941@163.com> (raw)
From: Li Youhong <liyouhong@kylinos.cn>
axi_dma_resume() enables cfgr_clk then core_clk. If enabling
core_clk fails, return without disabling cfgr_clk, leaking the
already-enabled clock. Disable cfgr_clk on that error path.
Fixes: 1fe20f1b8454 ("dmaengine: Introduce DW AXI DMAC driver")
Signed-off-by: Li Youhong <liyouhong@kylinos.cn>
---
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
index eebed2474210..6ccb3fcfa397 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
@@ -1335,8 +1335,10 @@ static int axi_dma_resume(struct axi_dma_chip *chip)
return ret;
ret = clk_prepare_enable(chip->core_clk);
- if (ret < 0)
+ if (ret < 0) {
+ clk_disable_unprepare(chip->cfgr_clk);
return ret;
+ }
axi_dma_enable(chip);
axi_dma_irq_enable(chip);
--
2.25.1
next reply other threads:[~2026-08-31 9:45 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-31 9:44 Li Youhong [this message]
2026-08-31 9:58 ` [PATCH] dmaengine: dw-axi-dmac: fix cfgr_clk leak when core_clk enable fails sashiko-bot
2026-08-31 15:07 ` Frank Li
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