Re: [PATCH] dmaengine: dw-axi-dmac: fix cfgr_clk leak when core_clk enable fails

[Frank Li <Frank.li@oss.nxp.com>]

On Mon, Aug 31, 2026 at 05:44:38PM +0800, Li Youhong wrote:
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>
> From: Li Youhong <liyouhong@kylinos.cn>
>
> axi_dma_resume() enables cfgr_clk then core_clk. If enabling
> core_clk fails, return without disabling cfgr_clk, leaking the
> already-enabled clock. Disable cfgr_clk on that error path.
>
> Fixes: 1fe20f1b8454 ("dmaengine: Introduce DW AXI DMAC driver")
> Signed-off-by: Li Youhong <liyouhong@kylinos.cn>
> ---
>  drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
> index eebed2474210..6ccb3fcfa397 100644
> --- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
> +++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
> @@ -1335,8 +1335,10 @@ static int axi_dma_resume(struct axi_dma_chip *chip)
>                 return ret;
>
>         ret = clk_prepare_enable(chip->core_clk);
> -       if (ret < 0)
> +       if (ret < 0) {
> +               clk_disable_unprepare(chip->cfgr_clk);
>                 return ret;
> +       }

Please switch to use bulk clk API.

Frank
>
>         axi_dma_enable(chip);
>         axi_dma_irq_enable(chip);
> --
> 2.25.1
>