From: Jia Wang <wangjia@ultrarisc.com>
To: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>,
Vinod Koul <vkoul@kernel.org>, Frank Li <Frank.Li@kernel.org>,
Pandith N <pandith.n@intel.com>,
Andy Shevchenko <andriy.shevchenko@linux.intel.com>,
Sia Jee Heng <jee.heng.sia@intel.com>
Cc: dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org,
Jia Wang <wangjia@ultrarisc.com>, Frank Li <Frank.Li@nxp.com>
Subject: [PATCH v3 3/4] dmaengine: dw-axi-dmac: Fix CH_CFG2 channel priority position
Date: Wed, 02 Sep 2026 17:26:13 +0800 [thread overview]
Message-ID: <20260902-dma-fix-v3-3-414c6449fbcc@ultrarisc.com> (raw)
In-Reply-To: <20260902-dma-fix-v3-0-414c6449fbcc@ultrarisc.com>
The CH_CFG2 channel priority field occupies bits 51:47 of the 64-bit
channel configuration register, corresponding to bits 19:15 of CH_CFG2_H.
The driver currently shifts the priority value by 20, programming the
wrong bits. Use bit 15 as the field position.
Fixes: 824351668a41 ("dmaengine: dw-axi-dmac: support DMAX_NUM_CHANNELS > 8")
Signed-off-by: Jia Wang <wangjia@ultrarisc.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
---
drivers/dma/dw-axi-dmac/dw-axi-dmac.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
index 67cc199e24d1..97451bb8b16a 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
@@ -327,7 +327,7 @@ enum {
#define CH_CFG2_H_TT_FC_POS 0
#define CH_CFG2_H_HS_SEL_SRC_POS 3
#define CH_CFG2_H_HS_SEL_DST_POS 4
-#define CH_CFG2_H_PRIORITY_POS 20
+#define CH_CFG2_H_PRIORITY_POS 15
/**
* DW AXI DMA channel interrupts
--
2.34.1
next prev parent reply other threads:[~2026-09-02 9:26 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-02 9:26 [PATCH v3 0/4] dmaengine: dw-axi-dmac: Fix burst encoding, LLI dump and priority Jia Wang
2026-09-02 9:26 ` [PATCH v3 1/4] dmaengine: dw-axi-dmac: Fix AXI burst length encoding Jia Wang
2026-09-02 9:39 ` sashiko-bot
2026-09-02 9:26 ` [PATCH v3 2/4] dmaengine: dw-axi-dmac: Fix LLI dump out-of-bounds access Jia Wang
2026-09-02 9:40 ` sashiko-bot
2026-09-02 9:26 ` Jia Wang [this message]
2026-09-02 9:40 ` [PATCH v3 3/4] dmaengine: dw-axi-dmac: Fix CH_CFG2 channel priority position sashiko-bot
2026-09-02 9:26 ` [PATCH v3 4/4] dmaengine: dw-axi-dmac: Use bitfield helpers for registers Jia Wang
2026-09-02 9:39 ` sashiko-bot
2026-09-02 16:08 ` Frank Li
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