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From: sashiko-bot@kernel.org
To: "Jia Wang" <wangjia@ultrarisc.com>
Cc: dmaengine@vger.kernel.org, Frank.Li@kernel.org, vkoul@kernel.org
Subject: Re: [PATCH v3 3/4] dmaengine: dw-axi-dmac: Fix CH_CFG2 channel priority position
Date: Wed, 02 Sep 2026 09:40:19 +0000	[thread overview]
Message-ID: <20260902094020.4B5FC1F000E9@smtp.kernel.org> (raw)
In-Reply-To: <20260902-dma-fix-v3-3-414c6449fbcc@ultrarisc.com>

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:

Pre-existing issues:
- [High] The shared interrupt handler unconditionally returns `IRQ_HANDLED`, defeating the kernel's spurious interrupt detection mechanism.
--

commit 24abf61259a958020ffb498a11487c8d593eb9a6
Author: Jia Wang <wangjia@ultrarisc.com>

dmaengine: dw-axi-dmac: Fix CH_CFG2 channel priority position

The CH_CFG2 channel priority field occupies bits 51:47 of the 64-bit
channel configuration register, corresponding to bits 19:15 of CH_CFG2_H.

The driver currently shifts the priority value by 20, programming the
wrong bits. Use bit 15 as the field position.

> diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
> index 67cc199e24d1f..97451bb8b16a7 100644
> --- a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
> +++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
> @@ -327,7 +327,7 @@ enum {
>  #define CH_CFG2_H_TT_FC_POS		0
>  #define CH_CFG2_H_HS_SEL_SRC_POS	3
>  #define CH_CFG2_H_HS_SEL_DST_POS	4
> -#define CH_CFG2_H_PRIORITY_POS		20
> +#define CH_CFG2_H_PRIORITY_POS		15
>  
>  /**
>   * DW AXI DMA channel interrupts

[Severity: High]
This isn't a bug introduced by this patch, but there is a pre-existing issue
in the shared interrupt handler for this driver.

Does dw_axi_dma_interrupt() unconditionally return IRQ_HANDLED even if no
channel interrupt statuses were set?

Looking at drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c:dw_axi_dma_interrupt():

static irqreturn_t dw_axi_dma_interrupt(int irq, void *dev_id)
{
	struct axi_dma_chip *chip = dev_id;
...
	/* Re-enable interrupts */
	axi_dma_irq_enable(chip);

	return IRQ_HANDLED;
}

If any other device sharing the IRQ line asserts an interrupt that it fails
to clear, returning IRQ_HANDLED here unconditionally defeats the kernel's
spurious interrupt detection mechanism. Because the IRQ line is registered
with IRQF_SHARED, this converts a localized hardware or driver failure into
a complete system freeze due to an interrupt storm.

Could this function track whether any channel interrupts were actually
processed and return IRQ_NONE if none were found?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260902-dma-fix-v3-0-414c6449fbcc@ultrarisc.com?part=3

  reply	other threads:[~2026-09-02  9:40 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-09-02  9:26 [PATCH v3 0/4] dmaengine: dw-axi-dmac: Fix burst encoding, LLI dump and priority Jia Wang
2026-09-02  9:26 ` [PATCH v3 1/4] dmaengine: dw-axi-dmac: Fix AXI burst length encoding Jia Wang
2026-09-02  9:39   ` sashiko-bot
2026-09-02  9:26 ` [PATCH v3 2/4] dmaengine: dw-axi-dmac: Fix LLI dump out-of-bounds access Jia Wang
2026-09-02  9:40   ` sashiko-bot
2026-09-02  9:26 ` [PATCH v3 3/4] dmaengine: dw-axi-dmac: Fix CH_CFG2 channel priority position Jia Wang
2026-09-02  9:40   ` sashiko-bot [this message]
2026-09-02  9:26 ` [PATCH v3 4/4] dmaengine: dw-axi-dmac: Use bitfield helpers for registers Jia Wang
2026-09-02  9:39   ` sashiko-bot
2026-09-02 16:08   ` Frank Li

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