DMA Engine development
 help / color / mirror / Atom feed
* SDXI on AMD EPYC (in relation to Nathan’s SDXI dmaengine patchset)
@ 2026-06-23 10:32 Karim Manaouil
  2026-06-23 13:10 ` Nathan Lynch
  0 siblings, 1 reply; 3+ messages in thread
From: Karim Manaouil @ 2026-06-23 10:32 UTC (permalink / raw)
  To: nathan.lynch
  Cc: shivankg, Stephen.Bates, PradeepVineshReddy.Kodamati, dmaengine,
	linux-pci

Hi Nathan and Shivank,

As Shivank already probably knows, I've been experimenting with kernel
memory offloading lately, especially in the context of THP/compaction.

I am in fact in the process of doing some experiments with Shivank's
page acceleration series [1] on Intel Sapphire Rapids with Intel DSA.
The major problem so far is that migrate_pages() is largely bottlenecked
by rmap, not copy bandwidth. However, that's a different story for now.

I have a dual-socket AMD EPYC 9004 in the lab (I pasted /proc/cpuinfo at
the end) and I wanted to see if I can get the SDXI series from Nathan [2]
to work on them, as this will open the door for me to experiment more on
AMD hardware.

I don't know if these CPUs are equipped with these accelerators or not.
lspci is showing these devices (four on each NUMA node):

# lspci | grep SDXI
06:00.1 System peripheral: Advanced Micro Devices, Inc. [AMD] SDXI
21:00.1 System peripheral: Advanced Micro Devices, Inc. [AMD] SDXI
41:00.1 System peripheral: Advanced Micro Devices, Inc. [AMD] SDXI
64:00.1 System peripheral: Advanced Micro Devices, Inc. [AMD] SDXI
81:00.1 System peripheral: Advanced Micro Devices, Inc. [AMD] SDXI
a3:00.1 System peripheral: Advanced Micro Devices, Inc. [AMD] SDXI
c1:00.1 System peripheral: Advanced Micro Devices, Inc. [AMD] SDXI
e1:00.1 System peripheral: Advanced Micro Devices, Inc. [AMD] SDXI

All of them have these PCI specs

vendor=0x1022
device=0x14dc
class=0x088000
subsystem_vendor=0x1458
subsystem_device=0x1000
BARs= 	BAR0/1 512 KiB prefetchable
	BAR2/3 512 KiB prefetchable

Class 0x088000 is:
base class    0x08  System peripheral
subclass      0x80  Other system peripheral

However, the PCI device class does not actually match the class from
Nathan's patchset [2]:

+#define PCI_CLASS_ACCELERATOR_SDXI		0x120100

+static const struct pci_device_id sdxi_id_table[] = {
+	{ PCI_DEVICE_CLASS(PCI_CLASS_ACCELERATOR_SDXI, 0xffffff) },
+	{ }
+};

So these functions appear to be exposed as generic system peripherals
(base class 0x08, subclass 0x80) rather than as SDXI processing
accelerators (base class 0x12, subclass 0x01).

Do you know whether these AMD 1022:14dc on this platform are actually
SDXI accelerators? And if so, whether the class code 0x088000 is
a firmware issue, or just the old (pre-standard) class used?

I tried to force probe these devices by also matching against 1022:14dc,
but the system resets after pcim_enable_device().

So I would like to know if these devices are actually SDXI engines, and if
so, whether Nathan's SDXI driver should bind to them at all, or whether
additional enablement/firmware is required.

Thank you

[1] https://lore.kernel.org/all/20260428155043.39251-2-shivankg@amd.com/
[2] https://lore.kernel.org/all/20260605-sdxi-base-v3-0-4d38ca2bdffe@amd.com/

# cat /proc/cpuinfo
processor       : 0
vendor_id       : AuthenticAMD
cpu family      : 25
model           : 17
model name      : AMD EPYC 9224 24-Core Processor
stepping        : 1
microcode       : 0xa101158
cpu MHz         : 1500.000
cache size      : 1024 KB
physical id     : 0
siblings        : 48
core id         : 0
cpu cores       : 24
apicid          : 0
initial apicid  : 0
fpu             : yes
fpu_exception   : yes
cpuid level     : 16
wp              : yes
flags           : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt pdpe1gb rdtscp lm constant_tsc rep_good amd_lbr_v2 nopl xtopology nonstop_tsc cpuid extd_apicid aperfmperf rapl pni pclmulqdq monitor ssse3 fma cx16 pcid sse4_1 sse4_2 x2apic movbe popcnt aes xsave avx f16c rdrand lahf_lm cmp_legacy svm extapic cr8_legacy abm sse4a misalignsse 3dnowprefetch osvw ibs skinit wdt tce topoext perfctr_core perfctr_nb bpext perfctr_llc mwaitx cpuid_fault cpb cat_l3 cdp_l3 hw_pstate ssbd mba perfmon_v2 ibrs ibpb stibp ibrs_enhanced vmmcall fsgsbase bmi1 avx2 smep bmi2 erms invpcid cqm rdt_a avx512f avx512dq rdseed adx smap avx512ifma clflushopt clwb avx512cd sha_ni avx512bw avx512vl xsaveopt xsavec xgetbv1 xsaves cqm_llc cqm_occup_llc cqm_mbm_total cqm_mbm_local user_shstk avx512_bf16 clzero irperf xsaveerptr rdpru wbnoinvd amd_ppin cppc arat npt lbrv svm_lock nrip_save tsc_scale vmcb_clean flushbyasid decodeassists pausefilter pfthreshold avic v_vmsave_vmload vgif x2avic v_spec_ctrl vnmi avx512vbmi umip pku ospke avx512_vbmi2 gfni vaes vpclmulqdq avx512_vnni avx512_bitalg avx512_vpopcntdq la57 rdpid overflow_recov succor smca fsrm flush_l1d debug_swap
bugs            : sysret_ss_attrs spectre_v1 spectre_v2 spec_store_bypass srso spectre_v2_user tsa vmscape
bogomips        : 4999.84
TLB size        : 3584 4K pages
clflush size    : 64
cache_alignment : 64
address sizes   : 52 bits physical, 57 bits virtual
power management: ts ttp tm hwpstate cpb eff_freq_ro [13] [14]

-- 
~karim

^ permalink raw reply	[flat|nested] 3+ messages in thread

* Re: SDXI on AMD EPYC (in relation to Nathan’s SDXI dmaengine patchset)
  2026-06-23 10:32 SDXI on AMD EPYC (in relation to Nathan’s SDXI dmaengine patchset) Karim Manaouil
@ 2026-06-23 13:10 ` Nathan Lynch
  2026-06-23 14:32   ` Karim Manaouil
  0 siblings, 1 reply; 3+ messages in thread
From: Nathan Lynch @ 2026-06-23 13:10 UTC (permalink / raw)
  To: Karim Manaouil
  Cc: shivankg, Stephen.Bates, PradeepVineshReddy.Kodamati, dmaengine,
	linux-pci

Karim Manaouil <kmanaouil.dev@gmail.com> writes:
>
> I have a dual-socket AMD EPYC 9004 in the lab (I pasted /proc/cpuinfo at
> the end) and I wanted to see if I can get the SDXI series from Nathan [2]
> to work on them, as this will open the door for me to experiment more on
> AMD hardware.
>
> I don't know if these CPUs are equipped with these accelerators or not.
> lspci is showing these devices (four on each NUMA node):
>
> # lspci | grep SDXI
> 06:00.1 System peripheral: Advanced Micro Devices, Inc. [AMD] SDXI
> 21:00.1 System peripheral: Advanced Micro Devices, Inc. [AMD] SDXI
> 41:00.1 System peripheral: Advanced Micro Devices, Inc. [AMD] SDXI
> 64:00.1 System peripheral: Advanced Micro Devices, Inc. [AMD] SDXI
> 81:00.1 System peripheral: Advanced Micro Devices, Inc. [AMD] SDXI
> a3:00.1 System peripheral: Advanced Micro Devices, Inc. [AMD] SDXI
> c1:00.1 System peripheral: Advanced Micro Devices, Inc. [AMD] SDXI
> e1:00.1 System peripheral: Advanced Micro Devices, Inc. [AMD] SDXI
>
> All of them have these PCI specs
>
> vendor=0x1022
> device=0x14dc
> class=0x088000
> subsystem_vendor=0x1458
> subsystem_device=0x1000
> BARs= 	BAR0/1 512 KiB prefetchable
> 	BAR2/3 512 KiB prefetchable
>
> Class 0x088000 is:
> base class    0x08  System peripheral
> subclass      0x80  Other system peripheral
>
> However, the PCI device class does not actually match the class from
> Nathan's patchset [2]:
>
> +#define PCI_CLASS_ACCELERATOR_SDXI		0x120100
>
> +static const struct pci_device_id sdxi_id_table[] = {
> +	{ PCI_DEVICE_CLASS(PCI_CLASS_ACCELERATOR_SDXI, 0xffffff) },
> +	{ }
> +};
>
> So these functions appear to be exposed as generic system peripherals
> (base class 0x08, subclass 0x80) rather than as SDXI processing
> accelerators (base class 0x12, subclass 0x01).
>
> Do you know whether these AMD 1022:14dc on this platform are actually
> SDXI accelerators?

Afraid I don't have any information about these devices. The driver
isn't intended to support them.

^ permalink raw reply	[flat|nested] 3+ messages in thread

* Re: SDXI on AMD EPYC (in relation to Nathan’s SDXI dmaengine patchset)
  2026-06-23 13:10 ` Nathan Lynch
@ 2026-06-23 14:32   ` Karim Manaouil
  0 siblings, 0 replies; 3+ messages in thread
From: Karim Manaouil @ 2026-06-23 14:32 UTC (permalink / raw)
  To: Nathan Lynch
  Cc: shivankg, Stephen.Bates, PradeepVineshReddy.Kodamati, dmaengine,
	linux-pci

On Tue, Jun 23, 2026 at 08:10:04AM -0500, Nathan Lynch wrote:
> Karim Manaouil <kmanaouil.dev@gmail.com> writes:
> >
> > I have a dual-socket AMD EPYC 9004 in the lab (I pasted /proc/cpuinfo at
> > the end) and I wanted to see if I can get the SDXI series from Nathan [2]
> > to work on them, as this will open the door for me to experiment more on
> > AMD hardware.
> >
> > I don't know if these CPUs are equipped with these accelerators or not.
> > lspci is showing these devices (four on each NUMA node):
> >
> > # lspci | grep SDXI
> > 06:00.1 System peripheral: Advanced Micro Devices, Inc. [AMD] SDXI
> > 21:00.1 System peripheral: Advanced Micro Devices, Inc. [AMD] SDXI
> > 41:00.1 System peripheral: Advanced Micro Devices, Inc. [AMD] SDXI
> > 64:00.1 System peripheral: Advanced Micro Devices, Inc. [AMD] SDXI
> > 81:00.1 System peripheral: Advanced Micro Devices, Inc. [AMD] SDXI
> > a3:00.1 System peripheral: Advanced Micro Devices, Inc. [AMD] SDXI
> > c1:00.1 System peripheral: Advanced Micro Devices, Inc. [AMD] SDXI
> > e1:00.1 System peripheral: Advanced Micro Devices, Inc. [AMD] SDXI
> >
> > All of them have these PCI specs
> >
> > vendor=0x1022
> > device=0x14dc
> > class=0x088000
> > subsystem_vendor=0x1458
> > subsystem_device=0x1000
> > BARs= 	BAR0/1 512 KiB prefetchable
> > 	BAR2/3 512 KiB prefetchable
> >
> > Class 0x088000 is:
> > base class    0x08  System peripheral
> > subclass      0x80  Other system peripheral
> >
> > However, the PCI device class does not actually match the class from
> > Nathan's patchset [2]:
> >
> > +#define PCI_CLASS_ACCELERATOR_SDXI		0x120100
> >
> > +static const struct pci_device_id sdxi_id_table[] = {
> > +	{ PCI_DEVICE_CLASS(PCI_CLASS_ACCELERATOR_SDXI, 0xffffff) },
> > +	{ }
> > +};
> >
> > So these functions appear to be exposed as generic system peripherals
> > (base class 0x08, subclass 0x80) rather than as SDXI processing
> > accelerators (base class 0x12, subclass 0x01).
> >
> > Do you know whether these AMD 1022:14dc on this platform are actually
> > SDXI accelerators?
> 
> Afraid I don't have any information about these devices. The driver
> isn't intended to support them.

Thank you for the reply, Nathan!

Is it public information which family of AMD CPUs have these
accelerators? Could you potentially share the device's PCI ID?

-- 
~karim

^ permalink raw reply	[flat|nested] 3+ messages in thread

end of thread, other threads:[~2026-06-23 14:32 UTC | newest]

Thread overview: 3+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2026-06-23 10:32 SDXI on AMD EPYC (in relation to Nathan’s SDXI dmaengine patchset) Karim Manaouil
2026-06-23 13:10 ` Nathan Lynch
2026-06-23 14:32   ` Karim Manaouil

This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox