[PATCH 0/3] dmaengine: sh: rz-dmac: add r7s72100 support

[PATCH 0/3] dmaengine: sh: rz-dmac: add r7s72100 support

[Wolfram Sang]

When activating good old Genmai board for regression testing, I found
out that not much is needed to activate the DMA controller for A1L.
Which makes sense, because the driver was initially written for this
SoC. Let it come home ;)

Patch 1 is a generic fix. The other patches are the actual enablement.
A branch with DTS additions for MMCIF can be found here:

git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux.git renesas/genmai-upstreaming

These will be upstreamed once the driver parts are in next. Adding SDHI
is still WIP because RZ/A1L usage exposes a SDHI driver bug. So much for
the value of regression testing...

Wolfram Sang (3):
  dmaengine: sh: rz-dmac: handle configs where one address is zero
  dt-bindings: dma: rz-dmac: Document RZ/A1L SoC
  dmaengine: sh: rz-dmac: add r7s72100 support

 .../bindings/dma/renesas,rz-dmac.yaml         | 27 +++++++++++++------
 drivers/dma/sh/Kconfig                        |  6 ++---
 drivers/dma/sh/rz-dmac.c                      | 27 ++++++++++---------
 3 files changed, 37 insertions(+), 23 deletions(-)

-- 
2.45.2

[PATCH 1/3] dmaengine: sh: rz-dmac: handle configs where one address is zero

[Wolfram Sang]

Configs like the ones coming from the MMC subsystem will have either
'src' or 'dst' zeroed, resulting in an unknown bus width. This will bail
out on the RZ DMA driver because of the sanity check for a valid bus
width. Reorder the code, so that the check will only be applied when the
corresponding address is non-zero.

Fixes: 5000d37042a6 ("dmaengine: sh: Add DMAC driver for RZ/G2L SoC")
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
---
 drivers/dma/sh/rz-dmac.c | 25 ++++++++++++++-----------
 1 file changed, 14 insertions(+), 11 deletions(-)

diff --git a/drivers/dma/sh/rz-dmac.c b/drivers/dma/sh/rz-dmac.c
index 65a27c5a7bce..811389fc9cb8 100644
--- a/drivers/dma/sh/rz-dmac.c
+++ b/drivers/dma/sh/rz-dmac.c
@@ -601,22 +601,25 @@ static int rz_dmac_config(struct dma_chan *chan,
 	struct rz_dmac_chan *channel = to_rz_dmac_chan(chan);
 	u32 val;
 
-	channel->src_per_address = config->src_addr;
 	channel->dst_per_address = config->dst_addr;
-
-	val = rz_dmac_ds_to_val_mapping(config->dst_addr_width);
-	if (val == CHCFG_DS_INVALID)
-		return -EINVAL;
-
 	channel->chcfg &= ~CHCFG_FILL_DDS_MASK;
-	channel->chcfg |= FIELD_PREP(CHCFG_FILL_DDS_MASK, val);
+	if (channel->dst_per_address) {
+		val = rz_dmac_ds_to_val_mapping(config->dst_addr_width);
+		if (val == CHCFG_DS_INVALID)
+			return -EINVAL;
 
-	val = rz_dmac_ds_to_val_mapping(config->src_addr_width);
-	if (val == CHCFG_DS_INVALID)
-		return -EINVAL;
+		channel->chcfg |= FIELD_PREP(CHCFG_FILL_DDS_MASK, val);
+	}
 
+	channel->src_per_address = config->src_addr;
 	channel->chcfg &= ~CHCFG_FILL_SDS_MASK;
-	channel->chcfg |= FIELD_PREP(CHCFG_FILL_SDS_MASK, val);
+	if (channel->src_per_address) {
+		val = rz_dmac_ds_to_val_mapping(config->src_addr_width);
+		if (val == CHCFG_DS_INVALID)
+			return -EINVAL;
+
+		channel->chcfg |= FIELD_PREP(CHCFG_FILL_SDS_MASK, val);
+	}
 
 	return 0;
 }
-- 
2.45.2

[PATCH 2/3] dt-bindings: dma: rz-dmac: Document RZ/A1L SoC

[Wolfram Sang]

Document the Renesas RZ/A1L DMAC block. This one does not require clocks
and resets, so update the bindings accordingly.

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
---
 .../bindings/dma/renesas,rz-dmac.yaml         | 27 +++++++++++++------
 1 file changed, 19 insertions(+), 8 deletions(-)

diff --git a/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml b/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml
index ca24cf48769f..e05aaf24eb64 100644
--- a/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml
+++ b/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml
@@ -4,18 +4,16 @@
 $id: http://devicetree.org/schemas/dma/renesas,rz-dmac.yaml#
 $schema: http://devicetree.org/meta-schemas/core.yaml#
 
-title: Renesas RZ/{G2L,G2UL,V2L} DMA Controller
+title: Renesas RZ/{A1L,G2L,G2UL,V2L} DMA Controller
 
 maintainers:
   - Biju Das <biju.das.jz@bp.renesas.com>
 
-allOf:
-  - $ref: dma-controller.yaml#
-
 properties:
   compatible:
     items:
       - enum:
+          - renesas,r7s72100-dmac # RZ/A1L
           - renesas,r9a07g043-dmac # RZ/G2UL and RZ/Five
           - renesas,r9a07g044-dmac # RZ/G2{L,LC}
           - renesas,r9a07g054-dmac # RZ/V2L
@@ -93,13 +91,26 @@ required:
   - reg
   - interrupts
   - interrupt-names
-  - clocks
-  - clock-names
   - '#dma-cells'
   - dma-channels
   - power-domains
-  - resets
-  - reset-names
+
+allOf:
+  - $ref: dma-controller.yaml#
+
+  - if:
+      not:
+        properties:
+          compatible:
+            contains:
+              enum:
+                - renesas,r7s72100-dmac
+    then:
+      required:
+        - clocks
+        - clock-names
+        - resets
+        - reset-names
 
 additionalProperties: false
 
-- 
2.45.2

[PATCH 3/3] dmaengine: sh: rz-dmac: add r7s72100 support

[Wolfram Sang]

Update descriptions and make getting resets optional.

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
---
 drivers/dma/sh/Kconfig   | 6 +++---
 drivers/dma/sh/rz-dmac.c | 2 +-
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/dma/sh/Kconfig b/drivers/dma/sh/Kconfig
index c0b2997ab7fd..2b2e8ca257f5 100644
--- a/drivers/dma/sh/Kconfig
+++ b/drivers/dma/sh/Kconfig
@@ -49,10 +49,10 @@ config RENESAS_USB_DMAC
 	  SoCs.
 
 config RZ_DMAC
-	tristate "Renesas RZ/{G2L,V2L} DMA Controller"
-	depends on ARCH_RZG2L || COMPILE_TEST
+	tristate "Renesas RZ/{A1,G2L,V2L} DMA Controller"
+	depends on ARCH_R7S72100 || ARCH_RZG2L || COMPILE_TEST
 	select RENESAS_DMA
 	select DMA_VIRTUAL_CHANNELS
 	help
 	  This driver supports the general purpose DMA controller found in the
-	  Renesas RZ/{G2L,V2L} SoC variants.
+	  Renesas RZ/{A1,G2L,V2L} SoC variants.
diff --git a/drivers/dma/sh/rz-dmac.c b/drivers/dma/sh/rz-dmac.c
index 811389fc9cb8..03f3f99f0f4a 100644
--- a/drivers/dma/sh/rz-dmac.c
+++ b/drivers/dma/sh/rz-dmac.c
@@ -893,7 +893,7 @@ static int rz_dmac_probe(struct platform_device *pdev)
 	/* Initialize the channels. */
 	INIT_LIST_HEAD(&dmac->engine.channels);
 
-	dmac->rstc = devm_reset_control_array_get_exclusive(&pdev->dev);
+	dmac->rstc = devm_reset_control_array_get_optional_exclusive(&pdev->dev);
 	if (IS_ERR(dmac->rstc))
 		return dev_err_probe(&pdev->dev, PTR_ERR(dmac->rstc),
 				     "failed to get resets\n");
-- 
2.45.2

Re: [PATCH 3/3] dmaengine: sh: rz-dmac: add r7s72100 support

[Philipp Zabel]

On Mo, 2024-09-30 at 16:59 +0200, Wolfram Sang wrote:
> Update descriptions and make getting resets optional.
> 
> Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
> ---
>  drivers/dma/sh/Kconfig   | 6 +++---
>  drivers/dma/sh/rz-dmac.c | 2 +-
>  2 files changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/dma/sh/Kconfig b/drivers/dma/sh/Kconfig
> index c0b2997ab7fd..2b2e8ca257f5 100644
> --- a/drivers/dma/sh/Kconfig
> +++ b/drivers/dma/sh/Kconfig
> @@ -49,10 +49,10 @@ config RENESAS_USB_DMAC
>  	  SoCs.
>  
>  config RZ_DMAC
> -	tristate "Renesas RZ/{G2L,V2L} DMA Controller"
> -	depends on ARCH_RZG2L || COMPILE_TEST
> +	tristate "Renesas RZ/{A1,G2L,V2L} DMA Controller"
> +	depends on ARCH_R7S72100 || ARCH_RZG2L || COMPILE_TEST
>  	select RENESAS_DMA
>  	select DMA_VIRTUAL_CHANNELS
>  	help
>  	  This driver supports the general purpose DMA controller found in the
> -	  Renesas RZ/{G2L,V2L} SoC variants.
> +	  Renesas RZ/{A1,G2L,V2L} SoC variants.
> diff --git a/drivers/dma/sh/rz-dmac.c b/drivers/dma/sh/rz-dmac.c
> index 811389fc9cb8..03f3f99f0f4a 100644
> --- a/drivers/dma/sh/rz-dmac.c
> +++ b/drivers/dma/sh/rz-dmac.c
> @@ -893,7 +893,7 @@ static int rz_dmac_probe(struct platform_device *pdev)
>  	/* Initialize the channels. */
>  	INIT_LIST_HEAD(&dmac->engine.channels);
>  
> -	dmac->rstc = devm_reset_control_array_get_exclusive(&pdev->dev);
> +	dmac->rstc = devm_reset_control_array_get_optional_exclusive(&pdev->dev);
>  	if (IS_ERR(dmac->rstc))
>  		return dev_err_probe(&pdev->dev, PTR_ERR(dmac->rstc),
>  				     "failed to get resets\n");

Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>

regards
Philipp

Re: [PATCH 2/3] dt-bindings: dma: rz-dmac: Document RZ/A1L SoC

[Geert Uytterhoeven]

Hi Wolfram,

Thanks for your patch!

On Mon, Sep 30, 2024 at 5:00 PM Wolfram Sang
<wsa+renesas@sang-engineering.com> wrote:
> Document the Renesas RZ/A1L DMAC block. This one does not require clocks

RZ/A1H

> and resets, so update the bindings accordingly.
>
> Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>

> --- a/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml
> +++ b/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml
> @@ -4,18 +4,16 @@
>  $id: http://devicetree.org/schemas/dma/renesas,rz-dmac.yaml#
>  $schema: http://devicetree.org/meta-schemas/core.yaml#
>
> -title: Renesas RZ/{G2L,G2UL,V2L} DMA Controller
> +title: Renesas RZ/{A1L,G2L,G2UL,V2L} DMA Controller

"A1H", or perhaps just "RZ-series"?

>
>  maintainers:
>    - Biju Das <biju.das.jz@bp.renesas.com>
>
> -allOf:
> -  - $ref: dma-controller.yaml#
> -
>  properties:
>    compatible:
>      items:
>        - enum:
> +          - renesas,r7s72100-dmac # RZ/A1L

RZ/A1H

The rest LGTM.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

RE: [PATCH 1/3] dmaengine: sh: rz-dmac: handle configs where one address is zero

[Biju Das]

Hi Wolfram Sang,

Thanks for the patch.

> -----Original Message-----
> From: Wolfram Sang <wsa+renesas@sang-engineering.com>
> Sent: Monday, September 30, 2024 4:00 PM
> Subject: [PATCH 1/3] dmaengine: sh: rz-dmac: handle configs where one address is zero
> 
> Configs like the ones coming from the MMC subsystem will have either 'src' or 'dst' zeroed, resulting
> in an unknown bus width. This will bail out on the RZ DMA driver because of the sanity check for a
> valid bus width. Reorder the code, so that the check will only be applied when the corresponding
> address is non-zero.
> 
> Fixes: 5000d37042a6 ("dmaengine: sh: Add DMAC driver for RZ/G2L SoC")
> Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
> ---
>  drivers/dma/sh/rz-dmac.c | 25 ++++++++++++++-----------
>  1 file changed, 14 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/dma/sh/rz-dmac.c b/drivers/dma/sh/rz-dmac.c index 65a27c5a7bce..811389fc9cb8
> 100644
> --- a/drivers/dma/sh/rz-dmac.c
> +++ b/drivers/dma/sh/rz-dmac.c
> @@ -601,22 +601,25 @@ static int rz_dmac_config(struct dma_chan *chan,
>  	struct rz_dmac_chan *channel = to_rz_dmac_chan(chan);
>  	u32 val;
> 
> -	channel->src_per_address = config->src_addr;
>  	channel->dst_per_address = config->dst_addr;
> -
> -	val = rz_dmac_ds_to_val_mapping(config->dst_addr_width);
> -	if (val == CHCFG_DS_INVALID)
> -		return -EINVAL;
> -
>  	channel->chcfg &= ~CHCFG_FILL_DDS_MASK;
> -	channel->chcfg |= FIELD_PREP(CHCFG_FILL_DDS_MASK, val);
> +	if (channel->dst_per_address) {
> +		val = rz_dmac_ds_to_val_mapping(config->dst_addr_width);
> +		if (val == CHCFG_DS_INVALID)
> +			return -EINVAL;
> 
> -	val = rz_dmac_ds_to_val_mapping(config->src_addr_width);
> -	if (val == CHCFG_DS_INVALID)
> -		return -EINVAL;
> +		channel->chcfg |= FIELD_PREP(CHCFG_FILL_DDS_MASK, val);
> +	}
> 
> +	channel->src_per_address = config->src_addr;
>  	channel->chcfg &= ~CHCFG_FILL_SDS_MASK;
> -	channel->chcfg |= FIELD_PREP(CHCFG_FILL_SDS_MASK, val);
> +	if (channel->src_per_address) {
> +		val = rz_dmac_ds_to_val_mapping(config->src_addr_width);
> +		if (val == CHCFG_DS_INVALID)
> +			return -EINVAL;
> +
> +		channel->chcfg |= FIELD_PREP(CHCFG_FILL_SDS_MASK, val);
> +	}

Now both code paths are identical, not sure may be introducing a helper
by passing channel, CHCFG_FILL_*_MASK and *_addr_width
will save some code??

Anyway, current code LGTM. So,

Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>


Cheers,
Biju

> 
>  	return 0;
>  }
> --
> 2.45.2

Re: [PATCH 1/3] dmaengine: sh: rz-dmac: handle configs where one address is zero

[Wolfram Sang]

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> Now both code paths are identical, not sure may be introducing a helper
> by passing channel, CHCFG_FILL_*_MASK and *_addr_width
> will save some code??

I had a look and I don't think so because we'd need to pass so many
parameters to the helper, that it doesn't really save anything, I'd say.

> Anyway, current code LGTM. So,
> 
> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>

Thanks!


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Re: [PATCH 2/3] dt-bindings: dma: rz-dmac: Document RZ/A1L SoC

[Wolfram Sang]

[-- Attachment #1: Type: text/plain, Size: 296 bytes --]


> > Document the Renesas RZ/A1L DMAC block. This one does not require clocks
> 
> RZ/A1H

Argh, I managed to mix it up again. Thanks!

> > -title: Renesas RZ/{G2L,G2UL,V2L} DMA Controller
> > +title: Renesas RZ/{A1L,G2L,G2UL,V2L} DMA Controller

I'd vote for your suggestion. Biju?


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Re: [PATCH 1/3] dmaengine: sh: rz-dmac: handle configs where one address is zero

[claudiu beznea]

On 30.09.2024 17:59, Wolfram Sang wrote:
> Configs like the ones coming from the MMC subsystem will have either
> 'src' or 'dst' zeroed, resulting in an unknown bus width. This will bail
> out on the RZ DMA driver because of the sanity check for a valid bus
> width. Reorder the code, so that the check will only be applied when the
> corresponding address is non-zero.
> 
> Fixes: 5000d37042a6 ("dmaengine: sh: Add DMAC driver for RZ/G2L SoC")
> Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>

Tested-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>

> ---
>  drivers/dma/sh/rz-dmac.c | 25 ++++++++++++++-----------
>  1 file changed, 14 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/dma/sh/rz-dmac.c b/drivers/dma/sh/rz-dmac.c
> index 65a27c5a7bce..811389fc9cb8 100644
> --- a/drivers/dma/sh/rz-dmac.c
> +++ b/drivers/dma/sh/rz-dmac.c
> @@ -601,22 +601,25 @@ static int rz_dmac_config(struct dma_chan *chan,
>  	struct rz_dmac_chan *channel = to_rz_dmac_chan(chan);
>  	u32 val;
>  
> -	channel->src_per_address = config->src_addr;
>  	channel->dst_per_address = config->dst_addr;
> -
> -	val = rz_dmac_ds_to_val_mapping(config->dst_addr_width);
> -	if (val == CHCFG_DS_INVALID)
> -		return -EINVAL;
> -
>  	channel->chcfg &= ~CHCFG_FILL_DDS_MASK;
> -	channel->chcfg |= FIELD_PREP(CHCFG_FILL_DDS_MASK, val);
> +	if (channel->dst_per_address) {
> +		val = rz_dmac_ds_to_val_mapping(config->dst_addr_width);
> +		if (val == CHCFG_DS_INVALID)
> +			return -EINVAL;
>  
> -	val = rz_dmac_ds_to_val_mapping(config->src_addr_width);
> -	if (val == CHCFG_DS_INVALID)
> -		return -EINVAL;
> +		channel->chcfg |= FIELD_PREP(CHCFG_FILL_DDS_MASK, val);
> +	}
>  
> +	channel->src_per_address = config->src_addr;
>  	channel->chcfg &= ~CHCFG_FILL_SDS_MASK;
> -	channel->chcfg |= FIELD_PREP(CHCFG_FILL_SDS_MASK, val);
> +	if (channel->src_per_address) {
> +		val = rz_dmac_ds_to_val_mapping(config->src_addr_width);
> +		if (val == CHCFG_DS_INVALID)
> +			return -EINVAL;
> +
> +		channel->chcfg |= FIELD_PREP(CHCFG_FILL_SDS_MASK, val);
> +	}
>  
>  	return 0;
>  }

RE: [PATCH 2/3] dt-bindings: dma: rz-dmac: Document RZ/A1L SoC

[Biju Das]

Hi Wolfram,

> -----Original Message-----
> From: Wolfram Sang <wsa+renesas@sang-engineering.com>
> Sent: Monday, September 30, 2024 8:26 PM
> Subject: Re: [PATCH 2/3] dt-bindings: dma: rz-dmac: Document RZ/A1L SoC
> 
> 
> > > Document the Renesas RZ/A1L DMAC block. This one does not require clocks
> >
> > RZ/A1H
> 
> Argh, I managed to mix it up again. Thanks!
> 
> > > -title: Renesas RZ/{G2L,G2UL,V2L} DMA Controller
> > > +title: Renesas RZ/{A1L,G2L,G2UL,V2L} DMA Controller
> 
> I'd vote for your suggestion. Biju?

This list is going to grow like RZ/A1, RZ/A2, RZ/G2L, RZ/G2LC, RZ/G2UL, RZ/V2L,
RZ/Five, RZ/G3 devices, RZ/V2H and future generation SoCs.

So maybe some thing generic should fit here.

On RZ family, majority of devices, except RZ/G1 and RZ/G2{H,M,N,E} uses this DMA.

Maybe we can mention this as "RZ DMA controller" and on commit message mention about
"RZ/G1 and RZ/G2{H,M,N,E} devices".

Cheers,
Biju

RE: [PATCH 1/3] dmaengine: sh: rz-dmac: handle configs where one address is zero

[Biju Das]

Hi Wolfram Sang,

> -----Original Message-----
> From: Wolfram Sang <wsa+renesas@sang-engineering.com>
> Sent: Monday, September 30, 2024 8:25 PM
> Subject: Re: [PATCH 1/3] dmaengine: sh: rz-dmac: handle configs where one address is zero
> 
> 
> > Now both code paths are identical, not sure may be introducing a
> > helper by passing channel, CHCFG_FILL_*_MASK and *_addr_width will
> > save some code??
> 
> I had a look and I don't think so because we'd need to pass so many parameters to the helper, that it
> doesn't really save anything, I'd say.

OK, fine by me. I just meant to avoid code duplication as it is identical blocks.

Current changes are tested with RZ/G2L on with RSPI and SSI interfaces.

So,
Tested-by: Biju Das <biju.das.jz@bp.renesas.com>

Cheers,
Biju