* [PATCH v5 0/2] CPM6 Channel Separation Support @ 2026-08-20 9:10 Devendra K Verma 2026-08-20 9:10 ` [PATCH v5 1/2] dmaengine: dw-edma: Enable Chan Separation via VSEC Devendra K Verma 2026-08-20 9:10 ` [PATCH v5 2/2] dmaengine: dw-edma: Add changes to support Channel Separation Devendra K Verma 0 siblings, 2 replies; 6+ messages in thread From: Devendra K Verma @ 2026-08-20 9:10 UTC (permalink / raw) To: mani, vkoul, frank.li, den Cc: dmaengine, linux-pci, linux-kernel, michal.simek, devverma 'Designware Cores PCI Express DM Controller - Reference Manual', section 3.2.34.3, VSEC for DEVICE INFORMATION supports the channel separation mechanisms. Basically, the HDMA IP allows the user to configure the separation between DMA channel registers and retrieve it via the VSEC capability mentioned above. In order to use the VSEC functionality following changes have been made: o Utilize the existing VSEC implementation to retrieve the channel separation and translate it to correct size. o Modify the structs and functions to calculate correct DMA channel register base using the channel, direction and channel separation selected. Devendra K Verma (2): dmaengine: dw-edma: Enable Chan Separation via VSEC dmaengine: dw-edma: Add changes to support Channel Separation drivers/dma/dw-edma/dw-edma-pcie.c | 18 +++++++++++++++ drivers/dma/dw-edma/dw-hdma-v0-core.c | 23 ++++++++++++-------- drivers/dma/dw-edma/dw-hdma-v0-debugfs.c | 17 +++++---------- drivers/dma/dw-edma/dw-hdma-v0-regs.h | 10 --------- drivers/pci/controller/dwc/pcie-designware.c | 1 + include/linux/dma/edma.h | 1 + 6 files changed, 40 insertions(+), 30 deletions(-) -- 2.43.0 ^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v5 1/2] dmaengine: dw-edma: Enable Chan Separation via VSEC 2026-08-20 9:10 [PATCH v5 0/2] CPM6 Channel Separation Support Devendra K Verma @ 2026-08-20 9:10 ` Devendra K Verma 2026-08-20 9:18 ` sashiko-bot 2026-08-20 9:10 ` [PATCH v5 2/2] dmaengine: dw-edma: Add changes to support Channel Separation Devendra K Verma 1 sibling, 1 reply; 6+ messages in thread From: Devendra K Verma @ 2026-08-20 9:10 UTC (permalink / raw) To: mani, vkoul, frank.li, den Cc: dmaengine, linux-pci, linux-kernel, michal.simek, devverma As per, 'Designware Cores PCI Express DM Controller - Reference Manual', section 3.2.34.3, VSEC for DEVICE INFORMATION supports the channel separation mechanisms. Basically, the HDMA IP allows the user to configure the separation between DMA channel registers and retrieve it via the VSEC capability mentioned above. HDMA IP supports the channel register space separation from 256B to 32KB. Default supported size is 256B. Signed-off-by: Devendra K Verma <devverma@amd.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> --- Changes in v4: o No change Changes in v3: o Reverted the trivial changes / typos. Changes in v2: o Replaced 'ch_sep_sz' with 'ch_space_sz' wherever applicable upon reviewer recommendation. o Dropped 1/3 patch of this series, after review, now the 2/3 is 1/2 of the current patch series. Changes in v1: o Modified dw_edma_get_ch_sep_sz() as per review comment. The function now supports ch_sep_sz up to 32KB. o Updated to description to reflect the supported channel separation sizes. --- drivers/dma/dw-edma/dw-edma-pcie.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/dma/dw-edma/dw-edma-pcie.c b/drivers/dma/dw-edma/dw-edma-pcie.c index 791c46e8ae4c..f287879b2cb9 100644 --- a/drivers/dma/dw-edma/dw-edma-pcie.c +++ b/drivers/dma/dw-edma/dw-edma-pcie.c @@ -33,6 +33,8 @@ #define DW_PCIE_XILINX_MDB_VSEC_ID 0x20 #define DW_PCIE_XILINX_MDB_VSEC_DMA_BAR GENMASK(10, 8) #define DW_PCIE_XILINX_MDB_VSEC_DMA_MAP GENMASK(2, 0) +/* AMD CPM6 (Xilinx) supported cap */ +#define DW_PCIE_XILINX_CPM6_VSEC_CH_SEP GENMASK(18, 16) #define DW_PCIE_XILINX_MDB_VSEC_DMA_WR_CH GENMASK(9, 0) #define DW_PCIE_XILINX_MDB_VSEC_DMA_RD_CH GENMASK(25, 16) @@ -73,6 +75,7 @@ struct dw_edma_pcie_data { u16 wr_ch_cnt; u16 rd_ch_cnt; u64 devmem_phys_off; + u32 ch_space_sz; }; static const struct dw_edma_pcie_data snps_edda_data = { @@ -189,6 +192,13 @@ static int dw_edma_pcie_irq_vector(struct device *dev, unsigned int nr) return pci_irq_vector(to_pci_dev(dev), nr); } +static u32 dw_edma_get_ch_space_sz(u32 val) +{ + if (val > 0 && val <= 7) + return 256 << val; + return 256; +} + static u64 dw_edma_pcie_address(struct device *dev, phys_addr_t cpu_addr) { struct pci_dev *pdev = to_pci_dev(dev); @@ -279,6 +289,10 @@ static void dw_edma_pcie_get_xilinx_dma_data(struct pci_dev *pdev, pdata->mf = map; pdata->rg.bar = FIELD_GET(DW_PCIE_XILINX_MDB_VSEC_DMA_BAR, val); + if (pdev->device == PCI_DEVICE_ID_XILINX_B00F) + pdata->ch_space_sz = dw_edma_get_ch_space_sz + (FIELD_GET(DW_PCIE_XILINX_CPM6_VSEC_CH_SEP, val)); + pci_read_config_dword(pdev, vsec + 0xc, &val); pdata->wr_ch_cnt = min(pdata->wr_ch_cnt, FIELD_GET(DW_PCIE_XILINX_MDB_VSEC_DMA_WR_CH, val)); -- 2.43.0 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH v5 1/2] dmaengine: dw-edma: Enable Chan Separation via VSEC 2026-08-20 9:10 ` [PATCH v5 1/2] dmaengine: dw-edma: Enable Chan Separation via VSEC Devendra K Verma @ 2026-08-20 9:18 ` sashiko-bot 0 siblings, 0 replies; 6+ messages in thread From: sashiko-bot @ 2026-08-20 9:18 UTC (permalink / raw) To: Devendra K Verma; +Cc: linux-pci, vkoul, dmaengine, Frank.Li Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider: Pre-existing issues: - [High] Failing to call pci_free_irq_vectors() in error paths after successful pci_alloc_irq_vectors() leaks IRQ resources. -- --- Patch [1]: [PATCH v5 1/2] dmaengine: dw-edma: Enable Chan Separation via VSEC --- commit 53282250df52af0d427cd82b37ad2ac609096030 Author: Devendra K Verma <devverma@amd.com> dmaengine: dw-edma: Enable Chan Separation via VSEC This commit enables channel separation mechanisms for the HDMA IP by retrieving the configuration via the DEVICE INFORMATION VSEC capability. It adds support for channel register space separation sizing. > diff --git a/drivers/dma/dw-edma/dw-edma-pcie.c b/drivers/dma/dw-edma/dw-edma-pcie.c > index 791c46e8ae4c4..f287879b2cb9e 100644 > --- a/drivers/dma/dw-edma/dw-edma-pcie.c > +++ b/drivers/dma/dw-edma/dw-edma-pcie.c [ ... ] > @@ -279,6 +289,10 @@ static void dw_edma_pcie_get_xilinx_dma_data(struct pci_dev *pdev, > pdata->mf = map; > pdata->rg.bar = FIELD_GET(DW_PCIE_XILINX_MDB_VSEC_DMA_BAR, val); > > + if (pdev->device == PCI_DEVICE_ID_XILINX_B00F) > + pdata->ch_space_sz = dw_edma_get_ch_space_sz > + (FIELD_GET(DW_PCIE_XILINX_CPM6_VSEC_CH_SEP, val)); > + > pci_read_config_dword(pdev, vsec + 0xc, &val); > pdata->wr_ch_cnt = min(pdata->wr_ch_cnt, > FIELD_GET(DW_PCIE_XILINX_MDB_VSEC_DMA_WR_CH, val)); [Severity: High] This is a pre-existing issue, but does dw_edma_pcie_probe() leak system IRQ capacity in its error handling paths? Looking at dw_edma_pcie_probe() in the same file, if pci_alloc_irq_vectors() succeeds, several subsequent error paths appear to return directly without cleaning up the allocated vectors: drivers/dma/dw-edma/dw-edma-pcie.c:dw_edma_pcie_probe() { ... /* IRQs allocation */ nr_irqs = pci_alloc_irq_vectors(pdev, 1, vsec_data->irqs, PCI_IRQ_MSI | PCI_IRQ_MSIX); ... chip->reg_base = pcim_iomap_table(pdev)[vsec_data->rg.bar]; if (!chip->reg_base) return -ENOMEM; ... /* Starting eDMA driver */ err = dw_edma_probe(chip); if (err) { pci_err(pdev, "eDMA probe failed\n"); return err; } ... } Should these failure paths explicitly call pci_free_irq_vectors() before returning to avoid leaking the IRQ resources? -- Sashiko AI review · https://sashiko.dev/#/patchset/20260820091025.683506-1-devverma@amd.com?part=1 ^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v5 2/2] dmaengine: dw-edma: Add changes to support Channel Separation 2026-08-20 9:10 [PATCH v5 0/2] CPM6 Channel Separation Support Devendra K Verma 2026-08-20 9:10 ` [PATCH v5 1/2] dmaengine: dw-edma: Enable Chan Separation via VSEC Devendra K Verma @ 2026-08-20 9:10 ` Devendra K Verma 2026-08-20 9:20 ` sashiko-bot 2026-08-20 15:22 ` Frank Li 1 sibling, 2 replies; 6+ messages in thread From: Devendra K Verma @ 2026-08-20 9:10 UTC (permalink / raw) To: mani, vkoul, frank.li, den Cc: dmaengine, linux-pci, linux-kernel, michal.simek, devverma HDMA supports configurable DMA channel register space separation which ranges from 256B to 32KB. Current implementation supports 256B as default for DMA channel register space. CPM6 supports the selection of channel register space via VSEC. The default value for channel register space for CPM6 is 512B. Updated the functions and methods to calculate the DMA channel registers base address as per the selected channel separation available as part of 'ch_space_sz'. Removed the unused function __dw_regs() and structs, namely dw_hdma_v0_ch and dw_hdma_v0_regs. Signed-off-by: Devendra K Verma <devverma@amd.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> --- Changes in v4: o No change. Changes in v3: o No change. Changes in v2: o Replace 'ch_sep_sz' with 'ch_space_sz' as per review recommendations. o As patch 1/3 of previous series dropped after review, this patch becomes 2/2 of the current series. Changes in v1: o Updated the description as per the review comment o Updated ch_sep_sz for EPC driver. --- drivers/dma/dw-edma/dw-edma-pcie.c | 4 ++++ drivers/dma/dw-edma/dw-hdma-v0-core.c | 23 ++++++++++++-------- drivers/dma/dw-edma/dw-hdma-v0-debugfs.c | 17 +++++---------- drivers/dma/dw-edma/dw-hdma-v0-regs.h | 10 --------- drivers/pci/controller/dwc/pcie-designware.c | 1 + include/linux/dma/edma.h | 1 + 6 files changed, 26 insertions(+), 30 deletions(-) diff --git a/drivers/dma/dw-edma/dw-edma-pcie.c b/drivers/dma/dw-edma/dw-edma-pcie.c index f287879b2cb9..2eb8293b87b4 100644 --- a/drivers/dma/dw-edma/dw-edma-pcie.c +++ b/drivers/dma/dw-edma/dw-edma-pcie.c @@ -114,6 +114,7 @@ static const struct dw_edma_pcie_data snps_edda_data = { .irqs = 1, .wr_ch_cnt = 2, .rd_ch_cnt = 2, + .ch_space_sz = 256, }; static const struct dw_edma_pcie_data xilinx_mdb_data = { @@ -127,6 +128,7 @@ static const struct dw_edma_pcie_data xilinx_mdb_data = { .irqs = 1, .wr_ch_cnt = 8, .rd_ch_cnt = 8, + .ch_space_sz = 256, }; static const struct dw_edma_pcie_data xilinx_cpm6_dma_data = { @@ -140,6 +142,7 @@ static const struct dw_edma_pcie_data xilinx_cpm6_dma_data = { .irqs = 1, .wr_ch_cnt = 8, .rd_ch_cnt = 8, + .ch_space_sz = 512, }; static void dw_edma_set_chan_region_offset(struct dw_edma_pcie_data *pdata, @@ -436,6 +439,7 @@ static int dw_edma_pcie_probe(struct pci_dev *pdev, chip->nr_irqs = nr_irqs; chip->ops = &dw_edma_pcie_plat_ops; chip->cfg_non_ll = non_ll; + chip->ch_space_sz = vsec_data->ch_space_sz; chip->ll_wr_cnt = vsec_data->wr_ch_cnt; chip->ll_rd_cnt = vsec_data->rd_ch_cnt; diff --git a/drivers/dma/dw-edma/dw-hdma-v0-core.c b/drivers/dma/dw-edma/dw-hdma-v0-core.c index 632abb8b481c..f8b2383b294a 100644 --- a/drivers/dma/dw-edma/dw-hdma-v0-core.c +++ b/drivers/dma/dw-edma/dw-hdma-v0-core.c @@ -23,18 +23,23 @@ enum dw_hdma_control { DW_HDMA_V0_LLE = BIT(9), }; -static inline struct dw_hdma_v0_regs __iomem *__dw_regs(struct dw_edma *dw) -{ - return dw->chip->reg_base; -} - static inline struct dw_hdma_v0_ch_regs __iomem * __dw_ch_regs(struct dw_edma *dw, enum dw_edma_dir dir, u16 ch) { - if (dir == EDMA_DIR_WRITE) - return &(__dw_regs(dw)->ch[ch].wr); - else - return &(__dw_regs(dw)->ch[ch].rd); + u32 ch_base; + + /* + * For Write, the channel register index starts at + * wr_base(ch_idx) = (2 * ch_idx) * ch_space_sz + * + * For Read channel, + * rd_base(ch_idx) = (2 * ch_idx + 1) * ch_space_sz + */ + ch_base = 2 * ch; + if (dir == EDMA_DIR_READ) + ch_base += 1; + + return dw->chip->reg_base + (ch_base * dw->chip->ch_space_sz); } #define SET_CH_32(dw, dir, ch, name, value) \ diff --git a/drivers/dma/dw-edma/dw-hdma-v0-debugfs.c b/drivers/dma/dw-edma/dw-hdma-v0-debugfs.c index dcdc57fe976c..3fa16e045a58 100644 --- a/drivers/dma/dw-edma/dw-hdma-v0-debugfs.c +++ b/drivers/dma/dw-edma/dw-hdma-v0-debugfs.c @@ -13,22 +13,17 @@ #include "dw-hdma-v0-regs.h" #include "dw-edma-core.h" -#define REGS_ADDR(dw, name) \ - ({ \ - struct dw_hdma_v0_regs __iomem *__regs = (dw)->chip->reg_base; \ - \ - (void __iomem *)&__regs->name; \ - }) - #define REGS_CH_ADDR(dw, name, _dir, _ch) \ ({ \ - struct dw_hdma_v0_ch_regs __iomem *__ch_regs; \ + struct dw_hdma_v0_ch_regs __iomem *__ch_regs; \ + off_t __off = (dw)->chip->ch_space_sz; \ \ - if (_dir == EDMA_DIR_READ) \ - __ch_regs = REGS_ADDR(dw, ch[_ch].rd); \ + if ((_dir) == EDMA_DIR_READ) \ + __off *= (2 * (_ch) + 1); \ else \ - __ch_regs = REGS_ADDR(dw, ch[_ch].wr); \ + __off *= (2 * (_ch)); \ \ + __ch_regs = ((dw)->chip->reg_base + __off); \ (void __iomem *)&__ch_regs->name; \ }) diff --git a/drivers/dma/dw-edma/dw-hdma-v0-regs.h b/drivers/dma/dw-edma/dw-hdma-v0-regs.h index 7759ba9b4850..2475b8d96133 100644 --- a/drivers/dma/dw-edma/dw-hdma-v0-regs.h +++ b/drivers/dma/dw-edma/dw-hdma-v0-regs.h @@ -84,16 +84,6 @@ struct dw_hdma_v0_ch_regs { }; } msi_abort; u32 msi_msgdata; /* 0x00a8 */ - u32 padding_2[21]; /* 0x00ac..0x00fc */ -} __packed; - -struct dw_hdma_v0_ch { - struct dw_hdma_v0_ch_regs wr; /* 0x0000 */ - struct dw_hdma_v0_ch_regs rd; /* 0x0100 */ -} __packed; - -struct dw_hdma_v0_regs { - struct dw_hdma_v0_ch ch[HDMA_V0_MAX_NR_CH]; /* 0x0000..0x0fa8 */ } __packed; struct dw_hdma_v0_lli { diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index ec4722ed9303..dfb7deaff751 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -1049,6 +1049,7 @@ static void dw_pcie_edma_init_data(struct dw_pcie *pci) pci->edma.ops = &dw_pcie_edma_ops; pci->edma.flags |= DW_EDMA_CHIP_LOCAL; + pci->edma.ch_space_sz = 256; } static int dw_pcie_edma_find_mf(struct dw_pcie *pci) diff --git a/include/linux/dma/edma.h b/include/linux/dma/edma.h index 1fafd5b0e315..182d4eeae22a 100644 --- a/include/linux/dma/edma.h +++ b/include/linux/dma/edma.h @@ -104,6 +104,7 @@ struct dw_edma_chip { struct dw_edma *dw; bool cfg_non_ll; + u32 ch_space_sz; }; /* Export to the platform drivers */ -- 2.43.0 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH v5 2/2] dmaengine: dw-edma: Add changes to support Channel Separation 2026-08-20 9:10 ` [PATCH v5 2/2] dmaengine: dw-edma: Add changes to support Channel Separation Devendra K Verma @ 2026-08-20 9:20 ` sashiko-bot 2026-08-20 15:22 ` Frank Li 1 sibling, 0 replies; 6+ messages in thread From: sashiko-bot @ 2026-08-20 9:20 UTC (permalink / raw) To: Devendra K Verma; +Cc: vkoul, Frank.Li, linux-pci, dmaengine Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider: New issues: - [High] Untrusted channel separation size from VSEC can cause out-of-bounds MMIO accesses beyond the mapped PCI BAR. Pre-existing issues: - [High] Allocated PCI IRQ vectors are leaked on multiple error paths in dw_edma_pcie_probe() due to missing cleanup. -- --- Patch [2]: [PATCH v5 2/2] dmaengine: dw-edma: Add changes to support Channel Separation --- commit a5388dc7284225085ff4d5827150b9b1002f1690 Author: Devendra K Verma <devverma@amd.com> dmaengine: dw-edma: Add changes to support Channel Separation This patch implements configurable DMA channel register space separation, ranging from 256B to 32KB, for HDMA. It updates offset calculations using ch_space_sz based on the VSEC capability for CPM6 and removes unused V0 structs. > diff --git a/drivers/dma/dw-edma/dw-edma-pcie.c b/drivers/dma/dw-edma/dw-edma-pcie.c > index f287879b2cb9e..2eb8293b87b4c 100644 > --- a/drivers/dma/dw-edma/dw-edma-pcie.c > +++ b/drivers/dma/dw-edma/dw-edma-pcie.c [ ... ] > @@ -436,6 +439,7 @@ static int dw_edma_pcie_probe(struct pci_dev *pdev, > chip->nr_irqs = nr_irqs; > chip->ops = &dw_edma_pcie_plat_ops; > chip->cfg_non_ll = non_ll; > + chip->ch_space_sz = vsec_data->ch_space_sz; [Severity: High] This is a pre-existing issue, but does dw_edma_pcie_probe() leak IRQ resources on error paths? The function successfully allocates IRQ vectors using pci_alloc_irq_vectors() earlier in the probe. However, if any subsequent initialization step fails, such as pcim_iomap_table() returning NULL: chip->reg_base = pcim_iomap_table(pdev)[vsec_data->rg.bar]; if (!chip->reg_base) return -ENOMEM; the function returns directly without calling pci_free_irq_vectors(). Could this lead to exhausting system IRQ capacity after repeated probe failures? > > chip->ll_wr_cnt = vsec_data->wr_ch_cnt; > chip->ll_rd_cnt = vsec_data->rd_ch_cnt; [ ... ] > diff --git a/drivers/dma/dw-edma/dw-hdma-v0-core.c b/drivers/dma/dw-edma/dw-hdma-v0-core.c > index 632abb8b481cf..f8b2383b294ac 100644 > --- a/drivers/dma/dw-edma/dw-hdma-v0-core.c > +++ b/drivers/dma/dw-edma/dw-hdma-v0-core.c [ ... ] > static inline struct dw_hdma_v0_ch_regs __iomem * > __dw_ch_regs(struct dw_edma *dw, enum dw_edma_dir dir, u16 ch) > { > - if (dir == EDMA_DIR_WRITE) > - return &(__dw_regs(dw)->ch[ch].wr); > - else > - return &(__dw_regs(dw)->ch[ch].rd); > + u32 ch_base; > + > + /* > + * For Write, the channel register index starts at > + * wr_base(ch_idx) = (2 * ch_idx) * ch_space_sz > + * > + * For Read channel, > + * rd_base(ch_idx) = (2 * ch_idx + 1) * ch_space_sz > + */ > + ch_base = 2 * ch; > + if (dir == EDMA_DIR_READ) > + ch_base += 1; > + > + return dw->chip->reg_base + (ch_base * dw->chip->ch_space_sz); [Severity: High] Can an untrusted channel separation size from VSEC cause out-of-bounds MMIO accesses beyond the mapped PCI BAR? If a maliciously crafted PCIe endpoint device reports a small BAR size but provides a large channel separation value via the VSEC capability, dw_edma_pcie_get_xilinx_dma_data() will extract this untrusted value to set ch_space_sz. Since the calculated offset (ch_base * dw->chip->ch_space_sz) is not explicitly bounds-checked against the actual mapped size of the BAR (such as by verifying against pci_resource_len()), could this allow the subsequent SET_CH_32() macro to dereference memory outside the mapped bounds and potentially cause a host kernel panic? > } > > #define SET_CH_32(dw, dir, ch, name, value) \ -- Sashiko AI review · https://sashiko.dev/#/patchset/20260820091025.683506-1-devverma@amd.com?part=2 ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v5 2/2] dmaengine: dw-edma: Add changes to support Channel Separation 2026-08-20 9:10 ` [PATCH v5 2/2] dmaengine: dw-edma: Add changes to support Channel Separation Devendra K Verma 2026-08-20 9:20 ` sashiko-bot @ 2026-08-20 15:22 ` Frank Li 1 sibling, 0 replies; 6+ messages in thread From: Frank Li @ 2026-08-20 15:22 UTC (permalink / raw) To: Devendra K Verma Cc: mani, vkoul, frank.li, den, dmaengine, linux-pci, linux-kernel, michal.simek On Thu, Aug 20, 2026 at 02:40:25PM +0530, Devendra K Verma wrote: > HDMA supports configurable DMA channel register space > separation which ranges from 256B to 32KB. Current implementation > supports 256B as default for DMA channel register space. > CPM6 supports the selection of channel register space via VSEC. > The default value for channel register space for CPM6 is 512B. > > Updated the functions and methods to calculate the DMA channel > registers base address as per the selected channel separation > available as part of 'ch_space_sz'. Removed the unused function > __dw_regs() and structs, namely dw_hdma_v0_ch and dw_hdma_v0_regs. > > Signed-off-by: Devendra K Verma <devverma@amd.com> > Reviewed-by: Frank Li <Frank.Li@nxp.com> > --- If only add my review-by, needn't post it new version. b4 will auto collect tags. I have to mark patch work status twices. Frank > Changes in v4: > o No change. > > Changes in v3: > o No change. > > Changes in v2: > o Replace 'ch_sep_sz' with 'ch_space_sz' as per review > recommendations. > o As patch 1/3 of previous series dropped after review, > this patch becomes 2/2 of the current series. > > Changes in v1: > o Updated the description as per the review comment > o Updated ch_sep_sz for EPC driver. > --- > drivers/dma/dw-edma/dw-edma-pcie.c | 4 ++++ > drivers/dma/dw-edma/dw-hdma-v0-core.c | 23 ++++++++++++-------- > drivers/dma/dw-edma/dw-hdma-v0-debugfs.c | 17 +++++---------- > drivers/dma/dw-edma/dw-hdma-v0-regs.h | 10 --------- > drivers/pci/controller/dwc/pcie-designware.c | 1 + > include/linux/dma/edma.h | 1 + > 6 files changed, 26 insertions(+), 30 deletions(-) > > diff --git a/drivers/dma/dw-edma/dw-edma-pcie.c b/drivers/dma/dw-edma/dw-edma-pcie.c > index f287879b2cb9..2eb8293b87b4 100644 > --- a/drivers/dma/dw-edma/dw-edma-pcie.c > +++ b/drivers/dma/dw-edma/dw-edma-pcie.c > @@ -114,6 +114,7 @@ static const struct dw_edma_pcie_data snps_edda_data = { > .irqs = 1, > .wr_ch_cnt = 2, > .rd_ch_cnt = 2, > + .ch_space_sz = 256, > }; > > static const struct dw_edma_pcie_data xilinx_mdb_data = { > @@ -127,6 +128,7 @@ static const struct dw_edma_pcie_data xilinx_mdb_data = { > .irqs = 1, > .wr_ch_cnt = 8, > .rd_ch_cnt = 8, > + .ch_space_sz = 256, > }; > > static const struct dw_edma_pcie_data xilinx_cpm6_dma_data = { > @@ -140,6 +142,7 @@ static const struct dw_edma_pcie_data xilinx_cpm6_dma_data = { > .irqs = 1, > .wr_ch_cnt = 8, > .rd_ch_cnt = 8, > + .ch_space_sz = 512, > }; > > static void dw_edma_set_chan_region_offset(struct dw_edma_pcie_data *pdata, > @@ -436,6 +439,7 @@ static int dw_edma_pcie_probe(struct pci_dev *pdev, > chip->nr_irqs = nr_irqs; > chip->ops = &dw_edma_pcie_plat_ops; > chip->cfg_non_ll = non_ll; > + chip->ch_space_sz = vsec_data->ch_space_sz; > > chip->ll_wr_cnt = vsec_data->wr_ch_cnt; > chip->ll_rd_cnt = vsec_data->rd_ch_cnt; > diff --git a/drivers/dma/dw-edma/dw-hdma-v0-core.c b/drivers/dma/dw-edma/dw-hdma-v0-core.c > index 632abb8b481c..f8b2383b294a 100644 > --- a/drivers/dma/dw-edma/dw-hdma-v0-core.c > +++ b/drivers/dma/dw-edma/dw-hdma-v0-core.c > @@ -23,18 +23,23 @@ enum dw_hdma_control { > DW_HDMA_V0_LLE = BIT(9), > }; > > -static inline struct dw_hdma_v0_regs __iomem *__dw_regs(struct dw_edma *dw) > -{ > - return dw->chip->reg_base; > -} > - > static inline struct dw_hdma_v0_ch_regs __iomem * > __dw_ch_regs(struct dw_edma *dw, enum dw_edma_dir dir, u16 ch) > { > - if (dir == EDMA_DIR_WRITE) > - return &(__dw_regs(dw)->ch[ch].wr); > - else > - return &(__dw_regs(dw)->ch[ch].rd); > + u32 ch_base; > + > + /* > + * For Write, the channel register index starts at > + * wr_base(ch_idx) = (2 * ch_idx) * ch_space_sz > + * > + * For Read channel, > + * rd_base(ch_idx) = (2 * ch_idx + 1) * ch_space_sz > + */ > + ch_base = 2 * ch; > + if (dir == EDMA_DIR_READ) > + ch_base += 1; > + > + return dw->chip->reg_base + (ch_base * dw->chip->ch_space_sz); > } > > #define SET_CH_32(dw, dir, ch, name, value) \ > diff --git a/drivers/dma/dw-edma/dw-hdma-v0-debugfs.c b/drivers/dma/dw-edma/dw-hdma-v0-debugfs.c > index dcdc57fe976c..3fa16e045a58 100644 > --- a/drivers/dma/dw-edma/dw-hdma-v0-debugfs.c > +++ b/drivers/dma/dw-edma/dw-hdma-v0-debugfs.c > @@ -13,22 +13,17 @@ > #include "dw-hdma-v0-regs.h" > #include "dw-edma-core.h" > > -#define REGS_ADDR(dw, name) \ > - ({ \ > - struct dw_hdma_v0_regs __iomem *__regs = (dw)->chip->reg_base; \ > - \ > - (void __iomem *)&__regs->name; \ > - }) > - > #define REGS_CH_ADDR(dw, name, _dir, _ch) \ > ({ \ > - struct dw_hdma_v0_ch_regs __iomem *__ch_regs; \ > + struct dw_hdma_v0_ch_regs __iomem *__ch_regs; \ > + off_t __off = (dw)->chip->ch_space_sz; \ > \ > - if (_dir == EDMA_DIR_READ) \ > - __ch_regs = REGS_ADDR(dw, ch[_ch].rd); \ > + if ((_dir) == EDMA_DIR_READ) \ > + __off *= (2 * (_ch) + 1); \ > else \ > - __ch_regs = REGS_ADDR(dw, ch[_ch].wr); \ > + __off *= (2 * (_ch)); \ > \ > + __ch_regs = ((dw)->chip->reg_base + __off); \ > (void __iomem *)&__ch_regs->name; \ > }) > > diff --git a/drivers/dma/dw-edma/dw-hdma-v0-regs.h b/drivers/dma/dw-edma/dw-hdma-v0-regs.h > index 7759ba9b4850..2475b8d96133 100644 > --- a/drivers/dma/dw-edma/dw-hdma-v0-regs.h > +++ b/drivers/dma/dw-edma/dw-hdma-v0-regs.h > @@ -84,16 +84,6 @@ struct dw_hdma_v0_ch_regs { > }; > } msi_abort; > u32 msi_msgdata; /* 0x00a8 */ > - u32 padding_2[21]; /* 0x00ac..0x00fc */ > -} __packed; > - > -struct dw_hdma_v0_ch { > - struct dw_hdma_v0_ch_regs wr; /* 0x0000 */ > - struct dw_hdma_v0_ch_regs rd; /* 0x0100 */ > -} __packed; > - > -struct dw_hdma_v0_regs { > - struct dw_hdma_v0_ch ch[HDMA_V0_MAX_NR_CH]; /* 0x0000..0x0fa8 */ > } __packed; > > struct dw_hdma_v0_lli { > diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c > index ec4722ed9303..dfb7deaff751 100644 > --- a/drivers/pci/controller/dwc/pcie-designware.c > +++ b/drivers/pci/controller/dwc/pcie-designware.c > @@ -1049,6 +1049,7 @@ static void dw_pcie_edma_init_data(struct dw_pcie *pci) > pci->edma.ops = &dw_pcie_edma_ops; > > pci->edma.flags |= DW_EDMA_CHIP_LOCAL; > + pci->edma.ch_space_sz = 256; > } > > static int dw_pcie_edma_find_mf(struct dw_pcie *pci) > diff --git a/include/linux/dma/edma.h b/include/linux/dma/edma.h > index 1fafd5b0e315..182d4eeae22a 100644 > --- a/include/linux/dma/edma.h > +++ b/include/linux/dma/edma.h > @@ -104,6 +104,7 @@ struct dw_edma_chip { > > struct dw_edma *dw; > bool cfg_non_ll; > + u32 ch_space_sz; > }; > > /* Export to the platform drivers */ > -- > 2.43.0 > ^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2026-08-20 15:22 UTC | newest] Thread overview: 6+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2026-08-20 9:10 [PATCH v5 0/2] CPM6 Channel Separation Support Devendra K Verma 2026-08-20 9:10 ` [PATCH v5 1/2] dmaengine: dw-edma: Enable Chan Separation via VSEC Devendra K Verma 2026-08-20 9:18 ` sashiko-bot 2026-08-20 9:10 ` [PATCH v5 2/2] dmaengine: dw-edma: Add changes to support Channel Separation Devendra K Verma 2026-08-20 9:20 ` sashiko-bot 2026-08-20 15:22 ` Frank Li
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