* [PATCH v2] dmaengine: dw-axi-dmac: convert to clk bulk APIs
@ 2026-09-01 1:39 Li Youhong
2026-09-01 1:51 ` sashiko-bot
2026-09-01 19:16 ` Frank Li
0 siblings, 2 replies; 3+ messages in thread
From: Li Youhong @ 2026-09-01 1:39 UTC (permalink / raw)
To: Eugeniy.Paltsev, vkoul; +Cc: Frank.Li, dmaengine, Li Youhong, Frank Li
From: Li Youhong <liyouhong@kylinos.cn>
axi_dma_resume() enables cfgr_clk then core_clk. If enabling
core_clk fails, return without disabling cfgr_clk, leaking the
already-enabled clock.
Switch both clocks to the clk bulk helpers so prepare/enable
failures roll back automatically, and update probe/remove/
suspend/resume accordingly.
Fixes: 1fe20f1b8454 ("dmaengine: Introduce DW AXI DMAC driver")
Suggested-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Li Youhong <liyouhong@kylinos.cn>
---
v2:
- Convert to clk bulk APIs
- Use a static const clk table with ARRAY_SIZE/memcpy
v1: link: https://lore.kernel.org/all/20260831094438.2244538-1-dayou5941@163.com/
---
.../dma/dw-axi-dmac/dw-axi-dmac-platform.c | 23 ++++++-------------
drivers/dma/dw-axi-dmac/dw-axi-dmac.h | 8 +++++--
2 files changed, 13 insertions(+), 18 deletions(-)
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
index eebed2474210..3a957af0e089 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
@@ -1320,8 +1320,7 @@ static int axi_dma_suspend(struct axi_dma_chip *chip)
axi_dma_irq_disable(chip);
axi_dma_disable(chip);
- clk_disable_unprepare(chip->core_clk);
- clk_disable_unprepare(chip->cfgr_clk);
+ clk_bulk_disable_unprepare(ARRAY_SIZE(chip->clks), chip->clks);
return 0;
}
@@ -1330,11 +1329,7 @@ static int axi_dma_resume(struct axi_dma_chip *chip)
{
int ret;
- ret = clk_prepare_enable(chip->cfgr_clk);
- if (ret < 0)
- return ret;
-
- ret = clk_prepare_enable(chip->core_clk);
+ ret = clk_bulk_prepare_enable(ARRAY_SIZE(chip->clks), chip->clks);
if (ret < 0)
return ret;
@@ -1524,13 +1519,10 @@ static int dw_probe(struct platform_device *pdev)
chip->dw->hdata->use_cfg2 = !!(flags & AXI_DMA_FLAG_USE_CFG2);
- chip->core_clk = devm_clk_get(chip->dev, "core-clk");
- if (IS_ERR(chip->core_clk))
- return PTR_ERR(chip->core_clk);
-
- chip->cfgr_clk = devm_clk_get(chip->dev, "cfgr-clk");
- if (IS_ERR(chip->cfgr_clk))
- return PTR_ERR(chip->cfgr_clk);
+ memcpy(chip->clks, dw_axi_dmac_clks, sizeof(chip->clks));
+ ret = devm_clk_bulk_get(chip->dev, ARRAY_SIZE(chip->clks), chip->clks);
+ if (ret)
+ return ret;
ret = parse_device_properties(chip);
if (ret)
@@ -1642,8 +1634,7 @@ static void dw_remove(struct platform_device *pdev)
u32 i;
/* Enable clk before accessing to registers */
- clk_prepare_enable(chip->cfgr_clk);
- clk_prepare_enable(chip->core_clk);
+ clk_bulk_prepare_enable(ARRAY_SIZE(chip->clks), chip->clks);
axi_dma_irq_disable(chip);
for (i = 0; i < dw->hdata->nr_channels; i++) {
axi_chan_disable(&chip->dw->chan[i]);
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
index 67cc199e24d1..fb11b525727e 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
@@ -22,6 +22,11 @@
#define DMAC_MAX_MASTERS 2
#define DMAC_MAX_BLK_SIZE 0x200000
+static const struct clk_bulk_data dw_axi_dmac_clks[] = {
+ { .id = "cfgr-clk", },
+ { .id = "core-clk", },
+};
+
struct dw_axi_dma_hcfg {
u32 nr_channels;
u32 nr_masters;
@@ -69,8 +74,7 @@ struct axi_dma_chip {
int irq[DMAC_MAX_CHANNELS];
void __iomem *regs;
void __iomem *apb_regs;
- struct clk *core_clk;
- struct clk *cfgr_clk;
+ struct clk_bulk_data clks[ARRAY_SIZE(dw_axi_dmac_clks)];
struct dw_axi_dma *dw;
};
--
2.25.1
^ permalink raw reply related [flat|nested] 3+ messages in thread* Re: [PATCH v2] dmaengine: dw-axi-dmac: convert to clk bulk APIs
2026-09-01 1:39 [PATCH v2] dmaengine: dw-axi-dmac: convert to clk bulk APIs Li Youhong
@ 2026-09-01 1:51 ` sashiko-bot
2026-09-01 19:16 ` Frank Li
1 sibling, 0 replies; 3+ messages in thread
From: sashiko-bot @ 2026-09-01 1:51 UTC (permalink / raw)
To: Li Youhong; +Cc: dmaengine, Frank.Li, vkoul
Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider:
Pre-existing issues:
- [High] Unchecked return value of `clk_bulk_prepare_enable()` in `dw_remove()` risks synchronous external abort (bus fault).
- [High] Hardware dismantling and tasklet termination in `dw_remove` race with devres-managed DMA engine unregistration.
- [High] Out-of-bounds array write when parsing device tree interrupts in `axi_req_irqs`.
--
commit d3c59d86966d2cb3f7687638252b5fce4a07a2b0
Author: Li Youhong <liyouhong@kylinos.cn>
dmaengine: dw-axi-dmac: convert to clk bulk APIs
This patch switches the core and configuration clocks in the dw-axi-dmac
driver to use the clock bulk helpers. This ensures that prepare and enable
failures are automatically rolled back, preventing clock leaks.
> diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
> index eebed2474210d..3a957af0e089d 100644
> --- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
> +++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
> @@ -1524,13 +1519,10 @@ static int dw_probe(struct platform_device *pdev)
>
> chip->dw->hdata->use_cfg2 = !!(flags & AXI_DMA_FLAG_USE_CFG2);
>
> - chip->core_clk = devm_clk_get(chip->dev, "core-clk");
> - if (IS_ERR(chip->core_clk))
> - return PTR_ERR(chip->core_clk);
> -
> - chip->cfgr_clk = devm_clk_get(chip->dev, "cfgr-clk");
> - if (IS_ERR(chip->cfgr_clk))
> - return PTR_ERR(chip->cfgr_clk);
> + memcpy(chip->clks, dw_axi_dmac_clks, sizeof(chip->clks));
> + ret = devm_clk_bulk_get(chip->dev, ARRAY_SIZE(chip->clks), chip->clks);
> + if (ret)
> + return ret;
>
> ret = parse_device_properties(chip);
> if (ret)
[Severity: High]
This is a pre-existing issue not introduced by this patch, but while
looking at device initialization triggered from dw_probe(), is there
a bounds checking issue in axi_req_irqs() when parsing the device tree?
In axi_req_irqs(), the code reads:
int irq_count = platform_irq_count(pdev);
for (int i = 0; i < irq_count; i++) {
chip->irq[i] = platform_get_irq(pdev, i);
}
If a malformed device tree provides more than DMAC_MAX_CHANNELS (32)
interrupts, will this loop write past the bounds of the fixed-size
chip->irq[32] array and overwrite subsequent critical fields like regs
or clks?
[ ... ]
> @@ -1642,8 +1634,7 @@ static void dw_remove(struct platform_device *pdev)
> u32 i;
>
> /* Enable clk before accessing to registers */
> - clk_prepare_enable(chip->cfgr_clk);
> - clk_prepare_enable(chip->core_clk);
> + clk_bulk_prepare_enable(ARRAY_SIZE(chip->clks), chip->clks);
> axi_dma_irq_disable(chip);
[Severity: High]
This isn't a bug introduced by this patch, but since we are modifying the
clock enablement here, does it make sense to check the return value of
clk_bulk_prepare_enable()?
If the clock controller fails to re-enable the clocks during a sysfs device
unbind, this code will proceed to call axi_dma_irq_disable() and access
hardware MMIO registers on an unclocked peripheral. Can this lead to a
synchronous external abort and kernel panic?
[Severity: High]
This is another pre-existing issue in dw_remove(), but is it safe to
manually tear down the tasklets and channels further down in this function?
Down in dw_remove(), we have:
list_for_each_entry_safe(chan, _chan, &dw->dma.channels,
vc.chan.device_node) {
list_del(&chan->vc.chan.device_node);
tasklet_kill(&chan->vc.task);
}
Since devres is used to unregister the DMA engine via
dma_async_device_unregister(), does prematurely deleting the channels from
dw->dma.channels bypass the subsystem protections? If a client driver is
still actively holding DMA channels during unbind, can this allow clients
to schedule dead tasklets or access freed resources while the DMA engine is
still publicly registered?
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260901013916.194253-1-dayou5941@163.com?part=1
^ permalink raw reply [flat|nested] 3+ messages in thread* Re: [PATCH v2] dmaengine: dw-axi-dmac: convert to clk bulk APIs
2026-09-01 1:39 [PATCH v2] dmaengine: dw-axi-dmac: convert to clk bulk APIs Li Youhong
2026-09-01 1:51 ` sashiko-bot
@ 2026-09-01 19:16 ` Frank Li
1 sibling, 0 replies; 3+ messages in thread
From: Frank Li @ 2026-09-01 19:16 UTC (permalink / raw)
To: Li Youhong
Cc: Eugeniy.Paltsev, vkoul, Frank.Li, dmaengine, Li Youhong, Frank Li
On Tue, Sep 01, 2026 at 09:39:16AM +0800, Li Youhong wrote:
> From: Li Youhong <liyouhong@kylinos.cn>
>
> axi_dma_resume() enables cfgr_clk then core_clk. If enabling
> core_clk fails, return without disabling cfgr_clk, leaking the
> already-enabled clock.
>
> Switch both clocks to the clk bulk helpers so prepare/enable
> failures roll back automatically, and update probe/remove/
> suspend/resume accordingly.
>
> Fixes: 1fe20f1b8454 ("dmaengine: Introduce DW AXI DMAC driver")
> Suggested-by: Frank Li <Frank.Li@nxp.com>
> Signed-off-by: Li Youhong <liyouhong@kylinos.cn>
> ---
> v2:
> - Convert to clk bulk APIs
> - Use a static const clk table with ARRAY_SIZE/memcpy
> v1: link: https://lore.kernel.org/all/20260831094438.2244538-1-dayou5941@163.com/
>
> ---
> .../dma/dw-axi-dmac/dw-axi-dmac-platform.c | 23 ++++++-------------
> drivers/dma/dw-axi-dmac/dw-axi-dmac.h | 8 +++++--
> 2 files changed, 13 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
> index eebed2474210..3a957af0e089 100644
> --- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
> +++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
> @@ -1320,8 +1320,7 @@ static int axi_dma_suspend(struct axi_dma_chip *chip)
> axi_dma_irq_disable(chip);
> axi_dma_disable(chip);
>
> - clk_disable_unprepare(chip->core_clk);
> - clk_disable_unprepare(chip->cfgr_clk);
> + clk_bulk_disable_unprepare(ARRAY_SIZE(chip->clks), chip->clks);
>
> return 0;
> }
> @@ -1330,11 +1329,7 @@ static int axi_dma_resume(struct axi_dma_chip *chip)
> {
> int ret;
>
> - ret = clk_prepare_enable(chip->cfgr_clk);
> - if (ret < 0)
> - return ret;
> -
> - ret = clk_prepare_enable(chip->core_clk);
> + ret = clk_bulk_prepare_enable(ARRAY_SIZE(chip->clks), chip->clks);
> if (ret < 0)
> return ret;
>
> @@ -1524,13 +1519,10 @@ static int dw_probe(struct platform_device *pdev)
>
> chip->dw->hdata->use_cfg2 = !!(flags & AXI_DMA_FLAG_USE_CFG2);
>
> - chip->core_clk = devm_clk_get(chip->dev, "core-clk");
> - if (IS_ERR(chip->core_clk))
> - return PTR_ERR(chip->core_clk);
> -
> - chip->cfgr_clk = devm_clk_get(chip->dev, "cfgr-clk");
> - if (IS_ERR(chip->cfgr_clk))
> - return PTR_ERR(chip->cfgr_clk);
> + memcpy(chip->clks, dw_axi_dmac_clks, sizeof(chip->clks));
> + ret = devm_clk_bulk_get(chip->dev, ARRAY_SIZE(chip->clks), chip->clks);
> + if (ret)
> + return ret;
>
> ret = parse_device_properties(chip);
> if (ret)
> @@ -1642,8 +1634,7 @@ static void dw_remove(struct platform_device *pdev)
> u32 i;
>
> /* Enable clk before accessing to registers */
> - clk_prepare_enable(chip->cfgr_clk);
> - clk_prepare_enable(chip->core_clk);
> + clk_bulk_prepare_enable(ARRAY_SIZE(chip->clks), chip->clks);
> axi_dma_irq_disable(chip);
> for (i = 0; i < dw->hdata->nr_channels; i++) {
> axi_chan_disable(&chip->dw->chan[i]);
> diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
> index 67cc199e24d1..fb11b525727e 100644
> --- a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
> +++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
> @@ -22,6 +22,11 @@
> #define DMAC_MAX_MASTERS 2
> #define DMAC_MAX_BLK_SIZE 0x200000
>
> +static const struct clk_bulk_data dw_axi_dmac_clks[] = {
> + { .id = "cfgr-clk", },
> + { .id = "core-clk", },
> +};
> +
Avoid define varible in header file, in case header file included more
than once. I know you want to use marco ARRAY_SIZE().
#define DW_AXI_DMA_MAX_CLKS 2
chip->clks[0].id = "cfgr-clk";
chip->clks[1].id = "core-clk";
> struct dw_axi_dma_hcfg {
> u32 nr_channels;
> u32 nr_masters;
> @@ -69,8 +74,7 @@ struct axi_dma_chip {
> int irq[DMAC_MAX_CHANNELS];
> void __iomem *regs;
> void __iomem *apb_regs;
> - struct clk *core_clk;
> - struct clk *cfgr_clk;
> + struct clk_bulk_data clks[ARRAY_SIZE(dw_axi_dmac_clks)];
> struct dw_axi_dma *dw;
> };
>
> --
> 2.25.1
>
^ permalink raw reply [flat|nested] 3+ messages in thread
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2026-09-01 1:51 ` sashiko-bot
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