* [13/14] MIPS: JZ4780: DTS: Update DMA node to match driver changes
From: Paul Cercueil @ 2018-07-03 12:32 UTC (permalink / raw)
To: Vinod Koul, Rob Herring, Mark Rutland, Ralf Baechle, Paul Burton,
James Hogan, Zubair Lutfullah Kakakhel
Cc: Mathieu Malaterre, Daniel Silsby, dmaengine, devicetree,
linux-kernel, linux-mips, Paul Cercueil
The driver now requires two memory resources to be supplied, the first
one for the channel-specific registers, the second one for the
controller-specific registers.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
---
arch/mips/boot/dts/ingenic/jz4780.dtsi | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/mips/boot/dts/ingenic/jz4780.dtsi b/arch/mips/boot/dts/ingenic/jz4780.dtsi
index aa4e8f75ff5d..ad3b1f827cf5 100644
--- a/arch/mips/boot/dts/ingenic/jz4780.dtsi
+++ b/arch/mips/boot/dts/ingenic/jz4780.dtsi
@@ -247,7 +247,8 @@
dma: dma@13420000 {
compatible = "ingenic,jz4780-dma";
- reg = <0x13420000 0x10000>;
+ reg = <0x13420000 0x400
+ 0x13421000 0x40>;
#dma-cells = <2>;
interrupt-parent = <&intc>;
^ permalink raw reply related
* [14/14] MIPS: JZ4770: DTS: Add DMA nodes
From: Paul Cercueil @ 2018-07-03 12:32 UTC (permalink / raw)
To: Vinod Koul, Rob Herring, Mark Rutland, Ralf Baechle, Paul Burton,
James Hogan, Zubair Lutfullah Kakakhel
Cc: Mathieu Malaterre, Daniel Silsby, dmaengine, devicetree,
linux-kernel, linux-mips, Paul Cercueil
Add the two devicetree nodes for the two DMA cores of the JZ4770 SoC,
disabled by default, as currently there are no clients for the DMA
driver (until the MMC driver and/or others get a devicetree node).
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
---
arch/mips/boot/dts/ingenic/jz4770.dtsi | 30 ++++++++++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/arch/mips/boot/dts/ingenic/jz4770.dtsi b/arch/mips/boot/dts/ingenic/jz4770.dtsi
index 7c2804f3f5f1..fda17beeb08b 100644
--- a/arch/mips/boot/dts/ingenic/jz4770.dtsi
+++ b/arch/mips/boot/dts/ingenic/jz4770.dtsi
@@ -196,6 +196,36 @@
status = "disabled";
};
+ dmac0: jz4770-dma@13420000 {
+ compatible = "ingenic,jz4770-dma";
+ reg = <0x13420000 0xC0
+ 0x13420300 0x20>;
+
+ #dma-cells = <1>;
+
+ clocks = <&cgu JZ4770_CLK_DMA>;
+ interrupt-parent = <&intc>;
+ interrupts = <24>;
+
+ /* Disable dmac0 until we have something that uses it */
+ status = "disabled";
+ };
+
+ dmac1: jz4770-dma@13420100 {
+ compatible = "ingenic,jz4770-dma";
+ reg = <0x13420100 0xC0
+ 0x13420400 0x20>;
+
+ #dma-cells = <1>;
+
+ clocks = <&cgu JZ4770_CLK_DMA>;
+ interrupt-parent = <&intc>;
+ interrupts = <23>;
+
+ /* Disable dmac1 until we have something that uses it */
+ status = "disabled";
+ };
+
uhc: uhc@13430000 {
compatible = "generic-ohci";
reg = <0x13430000 0x1000>;
^ permalink raw reply related
* [v7,1/2] dmaengine: fsl-edma: extract common fsl-edma code (no changes in behavior intended)
From: Angelo Dureghello @ 2018-07-03 13:39 UTC (permalink / raw)
To: Vinod; +Cc: dmaengine, linux-m68k
Hi Vinod,
On Tue, Jul 03, 2018 at 06:00:14PM +0530, Vinod wrote:
> On 03-07-18, 12:37, Angelo Dureghello wrote:
> > This patch adds a new fsl-edma-common module to allow new
> > mcf-edma module code to use most of the fsl-edma code.
> >
> > Due to some differences between ColdFire edma (64 channels) and
> > fsl-edma (32 channels), as register set offsets and some other
> > points as the different interrupt organization and other minor
> > things, a common module can collect most of the code for both
> > 32 and 64 channel edma module versions.
>
> ??
>
> You didn't see my email https://marc.info/?l=dmaengine&m=153060940829531&w=2
>
Ops, missed it. No prob, new patch follow with the 2 fixes.
Regards,
Angelo
> --
> ~Vinod
> --
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^ permalink raw reply
* dmaengine: fsl-edma-common: fix semantic check errors
From: Angelo Dureghello @ 2018-07-03 14:06 UTC (permalink / raw)
To: vinod.koul; +Cc: dmaengine, Angelo Dureghello
This patch fixes 'different address space' errors.
Signed-off-by: Angelo Dureghello <angelo@sysam.it>
---
drivers/dma/fsl-edma-common.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/dma/fsl-edma-common.c b/drivers/dma/fsl-edma-common.c
index 17d677bd11f9..72e52c1b5527 100644
--- a/drivers/dma/fsl-edma-common.c
+++ b/drivers/dma/fsl-edma-common.c
@@ -228,7 +228,7 @@ static void fsl_edma_set_tcd_regs(struct fsl_edma_chan *fsl_chan,
struct fsl_edma_hw_tcd *tcd)
{
struct fsl_edma_engine *edma = fsl_chan->edma;
- struct fsl_edma_hw_tcd *mtcd = edma->regs.tcd
+ struct fsl_edma_hw_tcd __iomem *mtcd = edma->regs.tcd
+ fsl_chan->vchan.chan.chan_id;
/*
^ permalink raw reply related
* [02/14] dmaengine: dma-jz4780: Separate chan/ctrl registers
From: Paul Burton @ 2018-07-03 16:53 UTC (permalink / raw)
To: Paul Cercueil
Cc: Vinod Koul, Rob Herring, Mark Rutland, Ralf Baechle, James Hogan,
Zubair Lutfullah Kakakhel, Mathieu Malaterre, Daniel Silsby,
dmaengine, devicetree, linux-kernel, linux-mips
Hi Paul,
On Tue, Jul 03, 2018 at 02:32:02PM +0200, Paul Cercueil wrote:
> @@ -804,9 +818,19 @@ static int jz4780_dma_probe(struct platform_device *pdev)
> return -EINVAL;
> }
>
> - jzdma->base = devm_ioremap_resource(dev, res);
> - if (IS_ERR(jzdma->base))
> - return PTR_ERR(jzdma->base);
> + jzdma->chn_base = devm_ioremap_resource(dev, res);
> + if (IS_ERR(jzdma->chn_base))
> + return PTR_ERR(jzdma->chn_base);
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
> + if (!res) {
> + dev_err(dev, "failed to get I/O memory\n");
> + return -EINVAL;
> + }
> +
> + jzdma->ctrl_base = devm_ioremap_resource(dev, res);
> + if (IS_ERR(jzdma->ctrl_base))
> + return PTR_ERR(jzdma->ctrl_base);
Could we have this failure case fall back to the existing behaviour
where we only have a single resource covering all the registers? That
would avoid breaking bisection between this patch & the one that updates
the JZ4780 DT.
For example:
#define JZ4780_DMA_CTRL_OFFSET 0x1000
res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
if (res) {
jzdma->ctrl_base = devm_ioremap_resource(dev, res);
if (IS_ERR(jzdma->ctrl_base))
return PTR_ERR(jzdma->ctrl_base);
} else {
jzdma->ctrl_base = jzdma->chn_base + JZ4780_DMA_CTRL_OFFSET;
}
Then you could remove the fallback after patch 13, to end up with the
same code you have now but without breaking bisection.
Most correct might be to move patch 13 to right after this one, so that
the JZ4780-specific fallback can be removed before adding support for
any of the other SoCs.
Thanks,
Paul
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^ permalink raw reply
* [v1] dmaengine: imx-sdma: add structure description to eliminate build warning with 'W=1'
From: Robin Gong @ 2018-07-03 17:49 UTC (permalink / raw)
To: vkoul, dan.j.williams; +Cc: dmaengine, linux-kernel, linux-imx
Some member description or colons miss cause build warning with 'W=1'
as below:
drivers/dma/imx-sdma.c:326: warning: Function parameter or member 'vd' not described in 'sdma_desc'
drivers/dma/imx-sdma.c:326: warning: Function parameter or member 'num_bd' not described in 'sdma_desc'
drivers/dma/imx-sdma.c:326: warning: Function parameter or member 'bd_phys' not described in 'sdma_desc'
drivers/dma/imx-sdma.c:326: warning: Function parameter or member 'buf_tail' not described in 'sdma_desc'
drivers/dma/imx-sdma.c:326: warning: Function parameter or member 'buf_ptail' not described in 'sdma_desc'
drivers/dma/imx-sdma.c:326: warning: Function parameter or member 'period_len' not described in 'sdma_desc'
drivers/dma/imx-sdma.c:326: warning: Function parameter or member 'chn_real_count' not described in 'sdma_desc'
drivers/dma/imx-sdma.c:326: warning: Function parameter or member 'chn_count' not described in 'sdma_desc
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
Reported-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
---
drivers/dma/imx-sdma.c | 85 +++++++++++++++++++++++++++++++++-----------------
1 file changed, 57 insertions(+), 28 deletions(-)
diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c
index 3de3281..5c810c1 100644
--- a/drivers/dma/imx-sdma.c
+++ b/drivers/dma/imx-sdma.c
@@ -202,9 +202,9 @@ struct sdma_buffer_descriptor {
/**
* struct sdma_channel_control - Channel control Block
*
- * @current_bd_ptr current buffer descriptor processed
- * @base_bd_ptr first element of buffer descriptor array
- * @unused padding. The SDMA engine expects an array of 128 byte
+ * @current_bd_ptr: current buffer descriptor processed
+ * @base_bd_ptr: first element of buffer descriptor array
+ * @unused: padding. The SDMA engine expects an array of 128 byte
* control blocks
*/
struct sdma_channel_control {
@@ -217,10 +217,13 @@ struct sdma_channel_control {
* struct sdma_state_registers - SDMA context for a channel
*
* @pc: program counter
+ * @unused1: unused
* @t: test bit: status of arithmetic & test instruction
* @rpc: return program counter
+ * @unused0: unused
* @sf: source fault while loading data
* @spc: loop start program counter
+ * @unused2: unused
* @df: destination fault while storing data
* @epc: loop end program counter
* @lm: loop mode
@@ -258,6 +261,14 @@ struct sdma_state_registers {
* @dsa: dedicated core source address register
* @ds: dedicated core status register
* @dd: dedicated core data register
+ * @scratch0: 1st word of dedicated ram for context switch
+ * @scratch1: 2nd word of dedicated ram for context switch
+ * @scratch2: 3rd word of dedicated ram for context switch
+ * @scratch3: 4th word of dedicated ram for context switch
+ * @scratch4: 5th word of dedicated ram for context switch
+ * @scratch5: 6th word of dedicated ram for context switch
+ * @scratch6: 7th word of dedicated ram for context switch
+ * @scratch7: 8th word of dedicated ram for context switch
*/
struct sdma_context_data {
struct sdma_state_registers channel_state;
@@ -291,15 +302,16 @@ struct sdma_engine;
/**
* struct sdma_desc - descriptor structor for one transfer
- * @vd descriptor for virt dma
- * @num_bd max NUM_BD. number of descriptors currently handling
- * @buf_tail ID of the buffer that was processed
- * @buf_ptail ID of the previous buffer that was processed
- * @period_len period length, used in cyclic.
- * @chn_real_count the real count updated from bd->mode.count
- * @chn_count the transfer count set
- * @sdmac sdma_channel pointer
- * @bd pointer of allocate bd
+ * @vd: descriptor for virt dma
+ * @num_bd: max NUM_BD. number of descriptors currently handling
+ * @bd_phys: physical address of bd
+ * @buf_tail: ID of the buffer that was processed
+ * @buf_ptail: ID of the previous buffer that was processed
+ * @period_len: period length, used in cyclic.
+ * @chn_real_count: the real count updated from bd->mode.count
+ * @chn_count: the transfer count set
+ * @sdmac: sdma_channel pointer
+ * @bd: pointer of allocate bd
*/
struct sdma_desc {
struct virt_dma_desc vd;
@@ -317,13 +329,30 @@ struct sdma_desc {
/**
* struct sdma_channel - housekeeping for a SDMA channel
*
- * @sdma pointer to the SDMA engine for this channel
- * @channel the channel number, matches dmaengine chan_id + 1
- * @direction transfer type. Needed for setting SDMA script
- * @peripheral_type Peripheral type. Needed for setting SDMA script
- * @event_id0 aka dma request line
- * @event_id1 for channels that use 2 events
- * @word_size peripheral access size
+ * @vc: virt_dma base structure
+ * @desc: sdma description including vd and other special member
+ * @sdma: pointer to the SDMA engine for this channel
+ * @channel: the channel number, matches dmaengine chan_id + 1
+ * @direction: transfer type. Needed for setting SDMA script
+ * @peripheral_type: Peripheral type. Needed for setting SDMA script
+ * @event_id0: aka dma request line
+ * @event_id1: for channels that use 2 events
+ * @word_size: peripheral access size
+ * @pc_from_device: script address for those device_2_memory
+ * @pc_to_device: script address for those memory_2_device
+ * @device_to_device: script address for those device_2_device
+ * @flags: loop mode or not
+ * @per_address: peripheral source or destination address in common case
+ * destination address in p_2_p case
+ * @per_address2: peripheral source address in p_2_p case
+ * @event_mask: event mask used in p_2_p script
+ * @watermark_level: value for gReg[7], some script will extend it from
+ * basic watermark such as p_2_p
+ * @shp_addr: value for gReg[6]
+ * @per_addr: value for gReg[2]
+ * @status: status of dma channel
+ * @data: specific sdma interface structure
+ * @bd_pool: dma_pool for bd
*/
struct sdma_channel {
struct virt_dma_chan vc;
@@ -359,15 +388,15 @@ struct sdma_channel {
/**
* struct sdma_firmware_header - Layout of the firmware image
*
- * @magic "SDMA"
- * @version_major increased whenever layout of struct sdma_script_start_addrs
- * changes.
- * @version_minor firmware minor version (for binary compatible changes)
- * @script_addrs_start offset of struct sdma_script_start_addrs in this image
- * @num_script_addrs Number of script addresses in this image
- * @ram_code_start offset of SDMA ram image in this firmware image
- * @ram_code_size size of SDMA ram image
- * @script_addrs Stores the start address of the SDMA scripts
+ * @magic: "SDMA"
+ * @version_major: increased whenever layout of struct
+ * sdma_script_start_addrs changes.
+ * @version_minor: firmware minor version (for binary compatible changes)
+ * @script_addrs_start: offset of struct sdma_script_start_addrs in this image
+ * @num_script_addrs: Number of script addresses in this image
+ * @ram_code_start: offset of SDMA ram image in this firmware image
+ * @ram_code_size: size of SDMA ram image
+ * @script_addrs: Stores the start address of the SDMA scripts
* (in SDMA memory space)
*/
struct sdma_firmware_header {
^ permalink raw reply related
* [1/3] dt-bindings: k3dma: add optional property dma_min_chan
From: Rob Herring @ 2018-07-03 18:54 UTC (permalink / raw)
To: Guodong Xu
Cc: vkoul, mark.rutland, dan.j.williams, liyu65, suzhuangluan,
xuhongtao8, zhongkaihua, xuezhiliang, xupeng7, sunliang10,
fengbaopeng, dmaengine, devicetree, linux-kernel
On Fri, Jun 22, 2018 at 11:24:14AM +0800, Guodong Xu wrote:
> From: Li Yu <liyu65@hisilicon.com>
>
> Add optional property dma_min_chan for k3dma.
>
> Signed-off-by: Li Yu <liyu65@hisilicon.com>
> ---
> Documentation/devicetree/bindings/dma/k3dma.txt | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/dma/k3dma.txt b/Documentation/devicetree/bindings/dma/k3dma.txt
> index 4945aeac4dc4..2fa1370c3173 100644
> --- a/Documentation/devicetree/bindings/dma/k3dma.txt
> +++ b/Documentation/devicetree/bindings/dma/k3dma.txt
> @@ -12,6 +12,11 @@ Required properties:
> have specific request line
> - clocks: clock required
>
> +Optional properties:
> +- dma_min_chan: the minimum number of DMA channel which begin to use
> + the default value is 0, but in some platform is
> + configured 1, like hi3660 platform
Can't this be implied by the compatible?
If not, needs vendor prefix and don't use '_' in property names.
Rob
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^ permalink raw reply
* dma: ste_dma40: Remove VLA usage
From: Arnd Bergmann @ 2018-07-03 19:43 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Linus Walleij, Kees Cook, Linux Kernel Mailing List, Vinod Koul,
dmaengine, Dan Williams, Linux ARM
On Mon, Jul 2, 2018 at 5:28 PM, Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> On Mon, Jul 2, 2018 at 4:22 PM Linus Walleij <linus.walleij@linaro.org> wrote:
>> On Fri, Jun 29, 2018 at 11:22 PM Arnd Bergmann <arnd@arndb.de> wrote:
>>
>> > - Nobody uses this driver in practice, as the hardware platform
>> > was a dead end
>>
>> Depends what you mean with dead end.
>>
>> The hardware was deployed in a few million handsets from Samsung
>> and Sony.
>>
>> Some have been picked up as targets for PostmarketOS:
>> https://wiki.postmarketos.org/wiki/Samsung_Galaxy_S_Advance_(samsung-i9070)
>> https://wiki.postmarketos.org/wiki/Samsung_Galaxy_SIII_mini_(samsung-i8190)
>>
>> So it is no more dead end than anything else discontinued, and it
>> has a living community who want it suppored by the mainline
>> kernel if possible.
I meant that when ST-Ericsson imploded, STMicroelectronics inherited the
SoC family but never did any follow-up chips. We only really ever supported the
original U8500 but not the later models (which have partial support), and that
is very unlikely to change, so all the devices that can run this
driver are already
known. This is only relevant because the dynamic allocation size depends on
the chip model.
> Mixup with SuperH-based ST40?
No, but I wouldn't be surprised to find an ST40 inside the D40 engine ;-)
Arnd
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^ permalink raw reply
* [v2] dmaengine: rcar-dmac: convert to SPDX identifiers
From: Kuninori Morimoto @ 2018-07-04 0:34 UTC (permalink / raw)
To: Vinod
Cc: Geert Uytterhoeven, Dan Williams, Magnus Damm, Linux-Renesas,
Laurent Pinchart, Kieran Bingham, Geert Uytterhoeven, dmaengine,
Hiroki Negishi
From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
This patch is using C++ comment style for SPDX line only,
because driver author want it.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
---
I posted this because I don't know which style was OK.
Please pick-up best side patch
v1 -> v2
- used // for SPDX line only
drivers/dma/sh/rcar-dmac.c | 5 +----
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/drivers/dma/sh/rcar-dmac.c b/drivers/dma/sh/rcar-dmac.c
index 79d14af..ebd160d 100644
--- a/drivers/dma/sh/rcar-dmac.c
+++ b/drivers/dma/sh/rcar-dmac.c
@@ -1,13 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0
/*
* Renesas R-Car Gen2 DMA Controller Driver
*
* Copyright (C) 2014 Renesas Electronics Inc.
*
* Author: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
- *
- * This is free software; you can redistribute it and/or modify
- * it under the terms of version 2 of the GNU General Public License as
- * published by the Free Software Foundation.
*/
#include <linux/delay.h>
^ permalink raw reply related
* [1/3] dt-bindings: k3dma: add optional property dma_min_chan
From: Guodong Xu @ 2018-07-04 1:14 UTC (permalink / raw)
To: Rob Herring
Cc: vkoul, Mark Rutland, dan.j.williams, liyu65, Suzhuangluan,
xuhongtao (A), zhongkaihua, Xuezhiliang, xupeng (Q), sunliang10,
Fengbaopeng (kevin, Kirin Solution Dept), dmaengine, devicetree,
linux-kernel
On Wed, Jul 4, 2018 at 2:54 AM Rob Herring <robh@kernel.org> wrote:
>
> On Fri, Jun 22, 2018 at 11:24:14AM +0800, Guodong Xu wrote:
> > From: Li Yu <liyu65@hisilicon.com>
> >
> > Add optional property dma_min_chan for k3dma.
> >
> > Signed-off-by: Li Yu <liyu65@hisilicon.com>
> > ---
> > Documentation/devicetree/bindings/dma/k3dma.txt | 6 ++++++
> > 1 file changed, 6 insertions(+)
> >
> > diff --git a/t b/Documentation/devicetree/bindings/dma/k3dma.txt
> > index 4945aeac4dc4..2fa1370c3173 100644
> > --- a/Documentation/devicetree/bindings/dma/k3dma.txt
> > +++ b/Documentation/devicetree/bindings/dma/k3dma.txt
> > @@ -12,6 +12,11 @@ Required properties:
> > have specific request line
> > - clocks: clock required
> >
> > +Optional properties:
> > +- dma_min_chan: the minimum number of DMA channel which begin to use
> > + the default value is 0, but in some platform is
> > + configured 1, like hi3660 platform
>
> Can't this be implied by the compatible?
>
No. "hisilicon,k3-dma-1.0" can work with series of hisilicon kirin
SoC. And each has different reservation of channels for on-chip
coprocessors.
> If not, needs vendor prefix and don't use '_' in property names.
>
Sure, thanks. Will change that when design new property. As Vinod
suggested, it makes sense to change this to a mask.
-Guodong
> Rob
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^ permalink raw reply
* dmaengine: fsl-edma-common: Add missing MODULE_LICENSE
From: Vinod Koul @ 2018-07-04 5:01 UTC (permalink / raw)
To: dmaengine; +Cc: angelo, Vinod Koul
Commit 9bfdea6db982: ("dmaengine: fsl-edma: extract common fsl-edma
code") introduced a common module from FSL routines but missed adding
MODULE_LICENSE tag resulting in warning:
WARNING: modpost: missing MODULE_LICENSE() in drivers/dma/fsl-edma-common.o
Fixes: 9bfdea6db982: ("dmaengine: fsl-edma: extract common fsl-edma code")
Reported-by: Stephen Rothwell <sfr@canb.auug.org.au>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
---
drivers/dma/fsl-edma-common.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/dma/fsl-edma-common.c b/drivers/dma/fsl-edma-common.c
index 17d677bd11f9..fd4333995a0e 100644
--- a/drivers/dma/fsl-edma-common.c
+++ b/drivers/dma/fsl-edma-common.c
@@ -668,3 +668,5 @@ void fsl_edma_setup_regs(struct fsl_edma_engine *edma)
edma->regs.tcd = edma->membase + EDMA_TCD;
}
EXPORT_SYMBOL_GPL(fsl_edma_setup_regs);
+
+MODULE_LICENSE("GPL v2");
^ permalink raw reply related
* dmaengine: fsl-edma-common: Add missing MODULE_LICENSE
From: Angelo Dureghello @ 2018-07-04 6:31 UTC (permalink / raw)
To: Vinod Koul; +Cc: dmaengine
Reviewed-by: Angelo Dureghello <angelo@sysam.it>
Many thanks,
Angelo
On Wed, Jul 04, 2018 at 10:31:59AM +0530, Vinod Koul wrote:
> Commit 9bfdea6db982: ("dmaengine: fsl-edma: extract common fsl-edma
> code") introduced a common module from FSL routines but missed adding
> MODULE_LICENSE tag resulting in warning:
>
> WARNING: modpost: missing MODULE_LICENSE() in drivers/dma/fsl-edma-common.o
>
> Fixes: 9bfdea6db982: ("dmaengine: fsl-edma: extract common fsl-edma code")
> Reported-by: Stephen Rothwell <sfr@canb.auug.org.au>
> Signed-off-by: Vinod Koul <vkoul@kernel.org>
> ---
> drivers/dma/fsl-edma-common.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/dma/fsl-edma-common.c b/drivers/dma/fsl-edma-common.c
> index 17d677bd11f9..fd4333995a0e 100644
> --- a/drivers/dma/fsl-edma-common.c
> +++ b/drivers/dma/fsl-edma-common.c
> @@ -668,3 +668,5 @@ void fsl_edma_setup_regs(struct fsl_edma_engine *edma)
> edma->regs.tcd = edma->membase + EDMA_TCD;
> }
> EXPORT_SYMBOL_GPL(fsl_edma_setup_regs);
> +
> +MODULE_LICENSE("GPL v2");
> --
> 2.14.4
>
> --
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^ permalink raw reply
* dma: add support for reporting pause and resume separately
From: Vinod Koul @ 2018-07-04 7:00 UTC (permalink / raw)
To: Marek Szyprowski, Mark Brown, Lars-Peter Clausen
Cc: dmaengine, alsa-devel, linux-kernel, Dan Williams,
Bartlomiej Zolnierkiewicz
Hi Marek,
On 02-07-18, 15:08, Marek Szyprowski wrote:
> 'cmd_pause' DMA channel capability means that respective DMA engine
> supports both pausing and resuming given DMA channel. However, in some
> cases it is important to know if DMA channel can be paused without the
> need to resume it. This is a typical requirement for proper residue
> reading on transfer timeout in UART drivers. There are also some DMA
> engines with limited hardware, which doesn't really support resuming.
Am curious given that your hardware does not support resume, what was motivation
for adding pause?
> Reporting pause and resume capabilities separately allows UART drivers to
> properly check for the really required capabilities and operate in DMA
> mode also in systems with limited DMA hardware. On the other hand drivers,
> which rely on full channel suspend/resume support, should now check for
> both 'pause' and 'resume' features.
>
> Existing clients of dma_get_slave_caps() have been checked and the only
> driver which rely on proper channel resuming is soc-generic-dmaengine-pcm
> driver, which has been updated to check the newly added capability.
> Existing 'cmd_pause' now only indicates that DMA engine support pausing
> given DMA channel.
The change looks fine to me. I was hoping that serial would also check
this..
Mark, Lars you okay with this?
>
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> ---
> This patch is a follow-up of the Vinod's advise from the following
> discussion:
> https://www.spinics.net/lists/linux-samsung-soc/msg63166.html
> ---
> drivers/dma/dmaengine.c | 8 ++------
> include/linux/dmaengine.h | 5 ++++-
> sound/soc/soc-generic-dmaengine-pcm.c | 2 +-
> 3 files changed, 7 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/dma/dmaengine.c b/drivers/dma/dmaengine.c
> index 08ba8473a284..84ac38dbdb65 100644
> --- a/drivers/dma/dmaengine.c
> +++ b/drivers/dma/dmaengine.c
> @@ -500,12 +500,8 @@ int dma_get_slave_caps(struct dma_chan *chan, struct dma_slave_caps *caps)
> caps->max_burst = device->max_burst;
> caps->residue_granularity = device->residue_granularity;
> caps->descriptor_reuse = device->descriptor_reuse;
> -
> - /*
> - * Some devices implement only pause (e.g. to get residuum) but no
> - * resume. However cmd_pause is advertised as pause AND resume.
> - */
> - caps->cmd_pause = !!(device->device_pause && device->device_resume);
> + caps->cmd_pause = !!device->device_pause;
> + caps->cmd_resume = !!device->device_resume;
> caps->cmd_terminate = !!device->device_terminate_all;
>
> return 0;
> diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h
> index 861be5cab1df..c8c3a7a93802 100644
> --- a/include/linux/dmaengine.h
> +++ b/include/linux/dmaengine.h
> @@ -415,7 +415,9 @@ enum dma_residue_granularity {
> * each type, the dma controller should set BIT(<TYPE>) and same
> * should be checked by controller as well
> * @max_burst: max burst capability per-transfer
> - * @cmd_pause: true, if pause and thereby resume is supported
> + * @cmd_pause: true, if pause is supported (i.e. for reading residue or
> + * for resume later)
> + * @cmd_resume: true, if resume is supported
> * @cmd_terminate: true, if terminate cmd is supported
> * @residue_granularity: granularity of the reported transfer residue
> * @descriptor_reuse: if a descriptor can be reused by client and
> @@ -427,6 +429,7 @@ struct dma_slave_caps {
> u32 directions;
> u32 max_burst;
> bool cmd_pause;
> + bool cmd_resume;
> bool cmd_terminate;
> enum dma_residue_granularity residue_granularity;
> bool descriptor_reuse;
> diff --git a/sound/soc/soc-generic-dmaengine-pcm.c b/sound/soc/soc-generic-dmaengine-pcm.c
> index 56a541b9ff9e..76c46d793843 100644
> --- a/sound/soc/soc-generic-dmaengine-pcm.c
> +++ b/sound/soc/soc-generic-dmaengine-pcm.c
> @@ -156,7 +156,7 @@ static int dmaengine_pcm_set_runtime_hwparams(struct snd_pcm_substream *substrea
>
> ret = dma_get_slave_caps(chan, &dma_caps);
> if (ret == 0) {
> - if (dma_caps.cmd_pause)
> + if (dma_caps.cmd_pause && dma_caps.cmd_resume)
> hw.info |= SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME;
> if (dma_caps.residue_granularity <= DMA_RESIDUE_GRANULARITY_SEGMENT)
> hw.info |= SNDRV_PCM_INFO_BATCH;
> --
> 2.17.1
>
> --
> To unsubscribe from this list: send the line "unsubscribe dmaengine" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* [v2] dmaengine: rcar-dmac: convert to SPDX identifiers
From: Geert Uytterhoeven @ 2018-07-04 7:20 UTC (permalink / raw)
To: Kuninori Morimoto
Cc: vkoul, Dan Williams, Magnus Damm, Linux-Renesas, Laurent Pinchart,
Kieran Bingham, Geert Uytterhoeven, dmaengine, hiroki.negishi.bx
On Wed, Jul 4, 2018 at 2:34 AM Kuninori Morimoto
<kuninori.morimoto.gx@renesas.com> wrote:
> From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
>
> This patch is using C++ comment style for SPDX line only,
> because driver author want it.
>
> Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
> August 21 - Release of renesas-drivers-2018-08-21-v4.18 (TBC) or
> Release of renesas-drivers-2018-08-21-v4.19-rc1 (TBC)
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
^ permalink raw reply
* [-next] dmaengine: fsl-edma: fix the error return code in mcf_edma_probe()
From: weiyongjun (A) @ 2018-07-04 8:21 UTC (permalink / raw)
To: Vinod Koul, Dan Williams, Angelo Dureghello
Cc: Wei Yongjun, dmaengine, kernel-janitors
The error return code PTR_ERR(pdata) is always 0 since pdata is
NULL in this error handling case.
Fixes: 5c1355ad87a2 ("dmaengine: fsl-edma: add ColdFire mcf5441x edma support")
Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com>
---
drivers/dma/mcf-edma.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
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diff --git a/drivers/dma/mcf-edma.c b/drivers/dma/mcf-edma.c
index 31e5317..787b7b6 100644
--- a/drivers/dma/mcf-edma.c
+++ b/drivers/dma/mcf-edma.c
@@ -175,7 +175,7 @@ static int mcf_edma_probe(struct platform_device *pdev)
pdata = dev_get_platdata(&pdev->dev);
if (!pdata)
- return PTR_ERR(pdata);
+ return -EINVAL;
chans = pdata->dma_channels;
len = sizeof(*mcf_edma) + sizeof(*mcf_chan) * chans;
^ permalink raw reply related
* [-next] dmaengine: fsl-edma: fix the error return code in mcf_edma_probe()
From: Angelo Dureghello @ 2018-07-04 9:04 UTC (permalink / raw)
To: Wei Yongjun; +Cc: Vinod Koul, Dan Williams, dmaengine, kernel-janitors
Reviewed-by: Angelo Dureghello <angelo@sysam.it>
Thanks for the fix.
On Wed, Jul 04, 2018 at 08:21:51AM +0000, Wei Yongjun wrote:
> The error return code PTR_ERR(pdata) is always 0 since pdata is
> NULL in this error handling case.
>
> Fixes: 5c1355ad87a2 ("dmaengine: fsl-edma: add ColdFire mcf5441x edma support")
> Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com>
> ---
> drivers/dma/mcf-edma.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/dma/mcf-edma.c b/drivers/dma/mcf-edma.c
> index 31e5317..787b7b6 100644
> --- a/drivers/dma/mcf-edma.c
> +++ b/drivers/dma/mcf-edma.c
> @@ -175,7 +175,7 @@ static int mcf_edma_probe(struct platform_device *pdev)
>
> pdata = dev_get_platdata(&pdev->dev);
> if (!pdata)
> - return PTR_ERR(pdata);
> + return -EINVAL;
>
> chans = pdata->dma_channels;
> len = sizeof(*mcf_edma) + sizeof(*mcf_chan) * chans;
>
> --
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^ permalink raw reply
* [v2] dmaengine: imx-sdma: add missing structure description
From: Robin Gong @ 2018-07-04 10:06 UTC (permalink / raw)
To: vkoul, dan.j.williams; +Cc: dmaengine, linux-kernel, linux-imx
Some member description or colons missing cause build warning with
'W=1' as below:
drivers/dma/imx-sdma.c:326: warning: Function parameter or member 'vd' not described in 'sdma_desc'
drivers/dma/imx-sdma.c:326: warning: Function parameter or member 'num_bd' not described in 'sdma_desc'
drivers/dma/imx-sdma.c:326: warning: Function parameter or member 'bd_phys' not described in 'sdma_desc'
drivers/dma/imx-sdma.c:326: warning: Function parameter or member 'buf_tail' not described in 'sdma_desc'
drivers/dma/imx-sdma.c:326: warning: Function parameter or member 'buf_ptail' not described in 'sdma_desc'
drivers/dma/imx-sdma.c:326: warning: Function parameter or member 'period_len' not described in 'sdma_desc'
drivers/dma/imx-sdma.c:326: warning: Function parameter or member 'chn_real_count' not described in 'sdma_desc'
drivers/dma/imx-sdma.c:326: warning: Function parameter or member 'chn_count' not described in 'sdma_desc
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
Reported-by: Vinod Koul <vkoul@kernel.org>
---
drivers/dma/imx-sdma.c | 85 +++++++++++++++++++++++++++++++++-----------------
1 file changed, 57 insertions(+), 28 deletions(-)
diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c
index 3de3281..c24baf9 100644
--- a/drivers/dma/imx-sdma.c
+++ b/drivers/dma/imx-sdma.c
@@ -202,9 +202,9 @@ struct sdma_buffer_descriptor {
/**
* struct sdma_channel_control - Channel control Block
*
- * @current_bd_ptr current buffer descriptor processed
- * @base_bd_ptr first element of buffer descriptor array
- * @unused padding. The SDMA engine expects an array of 128 byte
+ * @current_bd_ptr: current buffer descriptor processed
+ * @base_bd_ptr: first element of buffer descriptor array
+ * @unused: padding. The SDMA engine expects an array of 128 byte
* control blocks
*/
struct sdma_channel_control {
@@ -217,10 +217,13 @@ struct sdma_channel_control {
* struct sdma_state_registers - SDMA context for a channel
*
* @pc: program counter
+ * @unused1: unused
* @t: test bit: status of arithmetic & test instruction
* @rpc: return program counter
+ * @unused0: unused
* @sf: source fault while loading data
* @spc: loop start program counter
+ * @unused2: unused
* @df: destination fault while storing data
* @epc: loop end program counter
* @lm: loop mode
@@ -258,6 +261,14 @@ struct sdma_state_registers {
* @dsa: dedicated core source address register
* @ds: dedicated core status register
* @dd: dedicated core data register
+ * @scratch0: 1st word of dedicated ram for context switch
+ * @scratch1: 2nd word of dedicated ram for context switch
+ * @scratch2: 3rd word of dedicated ram for context switch
+ * @scratch3: 4th word of dedicated ram for context switch
+ * @scratch4: 5th word of dedicated ram for context switch
+ * @scratch5: 6th word of dedicated ram for context switch
+ * @scratch6: 7th word of dedicated ram for context switch
+ * @scratch7: 8th word of dedicated ram for context switch
*/
struct sdma_context_data {
struct sdma_state_registers channel_state;
@@ -291,15 +302,16 @@ struct sdma_engine;
/**
* struct sdma_desc - descriptor structor for one transfer
- * @vd descriptor for virt dma
- * @num_bd max NUM_BD. number of descriptors currently handling
- * @buf_tail ID of the buffer that was processed
- * @buf_ptail ID of the previous buffer that was processed
- * @period_len period length, used in cyclic.
- * @chn_real_count the real count updated from bd->mode.count
- * @chn_count the transfer count set
- * @sdmac sdma_channel pointer
- * @bd pointer of allocate bd
+ * @vd: descriptor for virt dma
+ * @num_bd: number of descriptors currently handling
+ * @bd_phys: physical address of bd
+ * @buf_tail: ID of the buffer that was processed
+ * @buf_ptail: ID of the previous buffer that was processed
+ * @period_len: period length, used in cyclic.
+ * @chn_real_count: the real count updated from bd->mode.count
+ * @chn_count: the transfer count set
+ * @sdmac: sdma_channel pointer
+ * @bd: pointer of allocate bd
*/
struct sdma_desc {
struct virt_dma_desc vd;
@@ -317,13 +329,30 @@ struct sdma_desc {
/**
* struct sdma_channel - housekeeping for a SDMA channel
*
- * @sdma pointer to the SDMA engine for this channel
- * @channel the channel number, matches dmaengine chan_id + 1
- * @direction transfer type. Needed for setting SDMA script
- * @peripheral_type Peripheral type. Needed for setting SDMA script
- * @event_id0 aka dma request line
- * @event_id1 for channels that use 2 events
- * @word_size peripheral access size
+ * @vc: virt_dma base structure
+ * @desc: sdma description including vd and other special member
+ * @sdma: pointer to the SDMA engine for this channel
+ * @channel: the channel number, matches dmaengine chan_id + 1
+ * @direction: transfer type. Needed for setting SDMA script
+ * @peripheral_type: Peripheral type. Needed for setting SDMA script
+ * @event_id0: aka dma request line
+ * @event_id1: for channels that use 2 events
+ * @word_size: peripheral access size
+ * @pc_from_device: script address for those device_2_memory
+ * @pc_to_device: script address for those memory_2_device
+ * @device_to_device: script address for those device_2_device
+ * @flags: loop mode or not
+ * @per_address: peripheral source or destination address in common case
+ * destination address in p_2_p case
+ * @per_address2: peripheral source address in p_2_p case
+ * @event_mask: event mask used in p_2_p script
+ * @watermark_level: value for gReg[7], some script will extend it from
+ * basic watermark such as p_2_p
+ * @shp_addr: value for gReg[6]
+ * @per_addr: value for gReg[2]
+ * @status: status of dma channel
+ * @data: specific sdma interface structure
+ * @bd_pool: dma_pool for bd
*/
struct sdma_channel {
struct virt_dma_chan vc;
@@ -359,15 +388,15 @@ struct sdma_channel {
/**
* struct sdma_firmware_header - Layout of the firmware image
*
- * @magic "SDMA"
- * @version_major increased whenever layout of struct sdma_script_start_addrs
- * changes.
- * @version_minor firmware minor version (for binary compatible changes)
- * @script_addrs_start offset of struct sdma_script_start_addrs in this image
- * @num_script_addrs Number of script addresses in this image
- * @ram_code_start offset of SDMA ram image in this firmware image
- * @ram_code_size size of SDMA ram image
- * @script_addrs Stores the start address of the SDMA scripts
+ * @magic: "SDMA"
+ * @version_major: increased whenever layout of struct
+ * sdma_script_start_addrs changes.
+ * @version_minor: firmware minor version (for binary compatible changes)
+ * @script_addrs_start: offset of struct sdma_script_start_addrs in this image
+ * @num_script_addrs: Number of script addresses in this image
+ * @ram_code_start: offset of SDMA ram image in this firmware image
+ * @ram_code_size: size of SDMA ram image
+ * @script_addrs: Stores the start address of the SDMA scripts
* (in SDMA memory space)
*/
struct sdma_firmware_header {
^ permalink raw reply related
* dma: add support for reporting pause and resume separately
From: Andy Shevchenko @ 2018-07-04 10:38 UTC (permalink / raw)
To: Vinod
Cc: Marek Szyprowski, Mark Brown, Lars-Peter Clausen, dmaengine,
ALSA Development Mailing List, Linux Kernel Mailing List,
Dan Williams, Bartlomiej Zolnierkiewicz
On Wed, Jul 4, 2018 at 10:00 AM, Vinod <vkoul@kernel.org> wrote:
> Hi Marek,
>
> On 02-07-18, 15:08, Marek Szyprowski wrote:
>> 'cmd_pause' DMA channel capability means that respective DMA engine
>> supports both pausing and resuming given DMA channel. However, in some
>> cases it is important to know if DMA channel can be paused without the
>> need to resume it. This is a typical requirement for proper residue
>> reading on transfer timeout in UART drivers. There are also some DMA
>> engines with limited hardware, which doesn't really support resuming.
>
> Am curious given that your hardware does not support resume, what was motivation
> for adding pause?
>
>> Reporting pause and resume capabilities separately allows UART drivers to
>> properly check for the really required capabilities and operate in DMA
>> mode also in systems with limited DMA hardware. On the other hand drivers,
>> which rely on full channel suspend/resume support, should now check for
>> both 'pause' and 'resume' features.
>>
>> Existing clients of dma_get_slave_caps() have been checked and the only
>> driver which rely on proper channel resuming is soc-generic-dmaengine-pcm
>> driver, which has been updated to check the newly added capability.
>> Existing 'cmd_pause' now only indicates that DMA engine support pausing
>> given DMA channel.
>
> The change looks fine to me. I was hoping that serial would also check
> this..
AFAIU serial does not need to resume.
^ permalink raw reply
* [PATCHv2,1/2] firmware: add request_firmware_nowait_nowarn function
From: Sebastian Reichel @ 2018-07-04 16:04 UTC (permalink / raw)
To: Greg Kroah-Hartman, Kees Cook, Hans de Goede
Cc: andresx7, torvalds, Luis R. Rodriguez, Dan Williams, Vinod Koul,
dmaengine, linux-kernel, Rafał Miłecki, kernel,
Sebastian Reichel
So far we got only one function for loading firmware asynchronously:
request_firmware_nowait. This adds another method for loading async
firmware without generating a warning when the firmware file is missing.
This is useful for devices, which also work without a firmware (i.e.
by using ROM firmware).
This is based on previous work from Rafał Miłecki <rafal@milecki.pl>.
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk>
---
drivers/base/firmware_loader/main.c | 40 ++++++++++++++++++++++++-----
include/linux/firmware.h | 12 +++++++++
2 files changed, 45 insertions(+), 7 deletions(-)
diff --git a/drivers/base/firmware_loader/main.c b/drivers/base/firmware_loader/main.c
index 0943e7065e0e..ede1a90e075e 100644
--- a/drivers/base/firmware_loader/main.c
+++ b/drivers/base/firmware_loader/main.c
@@ -774,7 +774,7 @@ static void request_firmware_work_func(struct work_struct *work)
_request_firmware(&fw, fw_work->name, fw_work->device, NULL, 0,
fw_work->opt_flags);
fw_work->cont(fw, fw_work->context);
- put_device(fw_work->device); /* taken in request_firmware_nowait() */
+ put_device(fw_work->device); /* taken in __request_firmware_nowait() */
module_put(fw_work->module);
kfree_const(fw_work->name);
@@ -782,8 +782,9 @@ static void request_firmware_work_func(struct work_struct *work)
}
/**
- * request_firmware_nowait() - asynchronous version of request_firmware
+ * __request_firmware_nowait() - asynchronous version of request_firmware
* @module: module requesting the firmware
+ * @opt_flags: flags that control firmware loading process, see FW_OPT_*
* @uevent: sends uevent to copy the firmware image if this flag
* is non-zero else the firmware copy must be done manually.
* @name: name of firmware file
@@ -804,13 +805,14 @@ static void request_firmware_work_func(struct work_struct *work)
*
* - can't sleep at all if @gfp is GFP_ATOMIC.
**/
-int
-request_firmware_nowait(
- struct module *module, bool uevent,
+static int
+__request_firmware_nowait(
+ struct module *module, unsigned int opt_flags,
const char *name, struct device *device, gfp_t gfp, void *context,
void (*cont)(const struct firmware *fw, void *context))
{
struct firmware_work *fw_work;
+ bool uevent = !!(opt_flags & FW_OPT_UEVENT);
fw_work = kzalloc(sizeof(struct firmware_work), gfp);
if (!fw_work)
@@ -825,8 +827,7 @@ request_firmware_nowait(
fw_work->device = device;
fw_work->context = context;
fw_work->cont = cont;
- fw_work->opt_flags = FW_OPT_NOWAIT |
- (uevent ? FW_OPT_UEVENT : FW_OPT_USERHELPER);
+ fw_work->opt_flags = FW_OPT_NOWAIT | opt_flags;
if (!uevent && fw_cache_is_setup(device, name)) {
kfree_const(fw_work->name);
@@ -845,8 +846,33 @@ request_firmware_nowait(
schedule_work(&fw_work->work);
return 0;
}
+
+int request_firmware_nowait(struct module *module, bool uevent,
+ const char *name, struct device *device, gfp_t gfp,
+ void *context,
+ void (*cont)(const struct firmware *fw, void *context))
+{
+ unsigned int opt_flags = (uevent ? FW_OPT_UEVENT : FW_OPT_USERHELPER);
+
+ return __request_firmware_nowait(module, opt_flags, name, device, gfp,
+ context, cont);
+}
EXPORT_SYMBOL(request_firmware_nowait);
+int request_firmware_nowait_nowarn(struct module *module, bool uevent,
+ const char *name, struct device *dev,
+ gfp_t gfp, void *context,
+ void (*cont)(const struct firmware *fw,
+ void *context))
+{
+ unsigned int opt_flags = (uevent ? FW_OPT_UEVENT : FW_OPT_USERHELPER);
+ opt_flags |= FW_OPT_NO_WARN;
+
+ return __request_firmware_nowait(module, opt_flags, name, dev, gfp,
+ context, cont);
+}
+EXPORT_SYMBOL(request_firmware_nowait_nowarn);
+
#ifdef CONFIG_PM_SLEEP
static ASYNC_DOMAIN_EXCLUSIVE(fw_cache_domain);
diff --git a/include/linux/firmware.h b/include/linux/firmware.h
index 2dd566c91d44..a6d0bc8273a4 100644
--- a/include/linux/firmware.h
+++ b/include/linux/firmware.h
@@ -48,6 +48,10 @@ int request_firmware_nowait(
struct module *module, bool uevent,
const char *name, struct device *device, gfp_t gfp, void *context,
void (*cont)(const struct firmware *fw, void *context));
+int request_firmware_nowait_nowarn(
+ struct module *module, bool uevent,
+ const char *name, struct device *device, gfp_t gfp, void *context,
+ void (*cont)(const struct firmware *fw, void *context));
int request_firmware_direct(const struct firmware **fw, const char *name,
struct device *device);
int request_firmware_into_buf(const struct firmware **firmware_p,
@@ -77,6 +81,14 @@ static inline int request_firmware_nowait(
return -EINVAL;
}
+static inline int request_firmware_nowait_nowarn(
+ struct module *module, bool uevent,
+ const char *name, struct device *device, gfp_t gfp, void *context,
+ void (*cont)(const struct firmware *fw, void *context))
+{
+ return -EINVAL;
+}
+
static inline void release_firmware(const struct firmware *fw)
{
}
^ permalink raw reply related
* [PATCHv2,2/2] dmaengine: imx-sdma: request firmware with FW_OPT_NO_WARN
From: Sebastian Reichel @ 2018-07-04 16:05 UTC (permalink / raw)
To: Greg Kroah-Hartman, Kees Cook, Hans de Goede
Cc: andresx7, torvalds, Luis R. Rodriguez, Dan Williams, Vinod Koul,
dmaengine, linux-kernel, Rafał Miłecki, kernel,
Sebastian Reichel
Request firmware with FW_OPT_NO_WARN. The driver works without the
firmware by using the one supplied in ROM. There is already an info
message, that informs about this.
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk>
---
drivers/dma/imx-sdma.c | 10 +++-------
1 file changed, 3 insertions(+), 7 deletions(-)
diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c
index f077992635c2..68f7e5a2092f 100644
--- a/drivers/dma/imx-sdma.c
+++ b/drivers/dma/imx-sdma.c
@@ -1599,13 +1599,9 @@ static int sdma_event_remap(struct sdma_engine *sdma)
static int sdma_get_firmware(struct sdma_engine *sdma,
const char *fw_name)
{
- int ret;
-
- ret = request_firmware_nowait(THIS_MODULE,
- FW_ACTION_HOTPLUG, fw_name, sdma->dev,
- GFP_KERNEL, sdma, sdma_load_firmware);
-
- return ret;
+ return request_firmware_nowait_nowarn(THIS_MODULE, FW_ACTION_HOTPLUG,
+ fw_name, sdma->dev, GFP_KERNEL,
+ sdma, sdma_load_firmware);
}
static int sdma_init(struct sdma_engine *sdma)
^ permalink raw reply related
* [01/14] dmaengine: dma-jz4780: Avoid hardcoding number of channels
From: PrasannaKumar Muralidharan @ 2018-07-04 16:28 UTC (permalink / raw)
To: Paul Cercueil
Cc: Vinod Koul, Rob Herring, Mark Rutland, Ralf Baechle, Paul Burton,
James Hogan, Zubair Lutfullah Kakakhel, Mathieu Malaterre,
Daniel Silsby, dmaengine,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list, Linux-MIPS
Hi Paul,
On 3 July 2018 at 18:02, Paul Cercueil <paul@crapouillou.net> wrote:
> As part of the work to support various other Ingenic JZ47xx SoC versions,
> which don't feature the same number of DMA channels per core, we now
> deduce the number of DMA channels available from the devicetree
> compatible string.
>
> Signed-off-by: Paul Cercueil <paul@crapouillou.net>
> ---
> drivers/dma/dma-jz4780.c | 53 +++++++++++++++++++++++++++++-----------
> 1 file changed, 39 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/dma/dma-jz4780.c b/drivers/dma/dma-jz4780.c
> index 85820a2d69d4..b40f491f0367 100644
> --- a/drivers/dma/dma-jz4780.c
> +++ b/drivers/dma/dma-jz4780.c
> @@ -16,6 +16,7 @@
> #include <linux/interrupt.h>
> #include <linux/module.h>
> #include <linux/of.h>
> +#include <linux/of_device.h>
> #include <linux/of_dma.h>
> #include <linux/platform_device.h>
> #include <linux/slab.h>
> @@ -23,8 +24,6 @@
> #include "dmaengine.h"
> #include "virt-dma.h"
>
> -#define JZ_DMA_NR_CHANNELS 32
> -
> /* Global registers. */
> #define JZ_DMA_REG_DMAC 0x1000
> #define JZ_DMA_REG_DIRQP 0x1004
> @@ -135,14 +134,20 @@ struct jz4780_dma_chan {
> unsigned int curr_hwdesc;
> };
>
> +enum jz_version {
> + ID_JZ4780,
> +};
> +
> struct jz4780_dma_dev {
> struct dma_device dma_device;
> void __iomem *base;
> struct clk *clk;
> unsigned int irq;
> + unsigned int nb_channels;
> + enum jz_version version;
>
> uint32_t chan_reserved;
> - struct jz4780_dma_chan chan[JZ_DMA_NR_CHANNELS];
> + struct jz4780_dma_chan chan[];
Looks like a variable length array in struct. I think there is some
effort to remove the usage of VLA. Can you revisit this? I may be
wrong, please feel free to correct.
> };
>
> struct jz4780_dma_filter_data {
> @@ -648,7 +653,7 @@ static irqreturn_t jz4780_dma_irq_handler(int irq, void *data)
>
> pending = jz4780_dma_readl(jzdma, JZ_DMA_REG_DIRQP);
>
> - for (i = 0; i < JZ_DMA_NR_CHANNELS; i++) {
> + for (i = 0; i < jzdma->nb_channels; i++) {
> if (!(pending & (1<<i)))
> continue;
>
> @@ -728,7 +733,7 @@ static struct dma_chan *jz4780_of_dma_xlate(struct of_phandle_args *dma_spec,
> data.channel = dma_spec->args[1];
>
> if (data.channel > -1) {
> - if (data.channel >= JZ_DMA_NR_CHANNELS) {
> + if (data.channel >= jzdma->nb_channels) {
> dev_err(jzdma->dma_device.dev,
> "device requested non-existent channel %u\n",
> data.channel);
> @@ -752,19 +757,45 @@ static struct dma_chan *jz4780_of_dma_xlate(struct of_phandle_args *dma_spec,
> }
> }
>
> +static const unsigned int jz4780_dma_nb_channels[] = {
> + [ID_JZ4780] = 32,
> +};
> +
> +static const struct of_device_id jz4780_dma_dt_match[] = {
> + { .compatible = "ingenic,jz4780-dma", .data = (void *)ID_JZ4780 },
> + {},
> +};
> +MODULE_DEVICE_TABLE(of, jz4780_dma_dt_match);
> +
> static int jz4780_dma_probe(struct platform_device *pdev)
> {
> struct device *dev = &pdev->dev;
> + const struct of_device_id *of_id = of_match_device(
> + jz4780_dma_dt_match, dev);
> struct jz4780_dma_dev *jzdma;
> struct jz4780_dma_chan *jzchan;
> struct dma_device *dd;
> struct resource *res;
> + enum jz_version version;
> + unsigned int nb_channels;
> int i, ret;
>
> - jzdma = devm_kzalloc(dev, sizeof(*jzdma), GFP_KERNEL);
> + if (of_id)
> + version = (enum jz_version)of_id->data;
> + else
> + version = ID_JZ4780; /* Default when not probed from DT */
> +
> + nb_channels = jz4780_dma_nb_channels[version];
> +
> + jzdma = devm_kzalloc(dev, sizeof(*jzdma)
> + + sizeof(*jzdma->chan) * nb_channels,
> + GFP_KERNEL);
> if (!jzdma)
> return -ENOMEM;
>
> + jzdma->nb_channels = nb_channels;
> + jzdma->version = version;
> +
> platform_set_drvdata(pdev, jzdma);
>
> res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> @@ -839,7 +870,7 @@ static int jz4780_dma_probe(struct platform_device *pdev)
>
> INIT_LIST_HEAD(&dd->channels);
>
> - for (i = 0; i < JZ_DMA_NR_CHANNELS; i++) {
> + for (i = 0; i < jzdma->nb_channels; i++) {
> jzchan = &jzdma->chan[i];
> jzchan->id = i;
>
> @@ -884,19 +915,13 @@ static int jz4780_dma_remove(struct platform_device *pdev)
>
> free_irq(jzdma->irq, jzdma);
>
> - for (i = 0; i < JZ_DMA_NR_CHANNELS; i++)
> + for (i = 0; i < jzdma->nb_channels; i++)
> tasklet_kill(&jzdma->chan[i].vchan.task);
>
> dma_async_device_unregister(&jzdma->dma_device);
> return 0;
> }
>
> -static const struct of_device_id jz4780_dma_dt_match[] = {
> - { .compatible = "ingenic,jz4780-dma", .data = NULL },
> - {},
> -};
> -MODULE_DEVICE_TABLE(of, jz4780_dma_dt_match);
> -
> static struct platform_driver jz4780_dma_driver = {
> .probe = jz4780_dma_probe,
> .remove = jz4780_dma_remove,
> --
> 2.18.0
>
>
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^ permalink raw reply
* [02/14] dmaengine: dma-jz4780: Separate chan/ctrl registers
From: PrasannaKumar Muralidharan @ 2018-07-04 16:35 UTC (permalink / raw)
To: Paul Cercueil
Cc: Vinod Koul, Rob Herring, Mark Rutland, Ralf Baechle, Paul Burton,
James Hogan, Zubair Lutfullah Kakakhel, Mathieu Malaterre,
Daniel Silsby, dmaengine,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list, Linux-MIPS
Paul,
On 3 July 2018 at 18:02, Paul Cercueil <paul@crapouillou.net> wrote:
> The register area of the JZ4780 DMA core can be split into different
> sections for different purposes:
>
> * one set of registers is used to perform actions at the DMA core level,
> that will generally affect all channels;
>
> * one set of registers per DMA channel, to perform actions at the DMA
> channel level, that will only affect the channel in question.
>
> The problem rises when trying to support new versions of the JZ47xx
> Ingenic SoC. For instance, the JZ4770 has two DMA cores, each one
> with six DMA channels, and the register sets are interleaved:
> <DMA0 chan regs> <DMA1 chan regs> <DMA0 ctrl regs> <DMA1 ctrl regs>
>
> By using one memory resource for the channel-specific registers and
> one memory resource for the core-specific registers, we can support
> the JZ4770, by initializing the driver once per DMA core with different
> addresses.
As per my understanding device tree should be modified only when
hardware changes. This looks the other way around. It must be possible
to achieve what you are trying to do in this patch without changing
the device tree.
> Signed-off-by: Paul Cercueil <paul@crapouillou.net>
> ---
> .../devicetree/bindings/dma/jz4780-dma.txt | 6 +-
> drivers/dma/dma-jz4780.c | 106 +++++++++++-------
> 2 files changed, 69 insertions(+), 43 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/dma/jz4780-dma.txt b/Documentation/devicetree/bindings/dma/jz4780-dma.txt
> index f25feee62b15..f9b1864f5b77 100644
> --- a/Documentation/devicetree/bindings/dma/jz4780-dma.txt
> +++ b/Documentation/devicetree/bindings/dma/jz4780-dma.txt
> @@ -3,7 +3,8 @@
> Required properties:
>
> - compatible: Should be "ingenic,jz4780-dma"
> -- reg: Should contain the DMA controller registers location and length.
> +- reg: Should contain the DMA channel registers location and length, followed
> + by the DMA controller registers location and length.
> - interrupts: Should contain the interrupt specifier of the DMA controller.
> - interrupt-parent: Should be the phandle of the interrupt controller that
> - clocks: Should contain a clock specifier for the JZ4780 PDMA clock.
> @@ -22,7 +23,8 @@ Example:
>
> dma: dma@13420000 {
> compatible = "ingenic,jz4780-dma";
> - reg = <0x13420000 0x10000>;
> + reg = <0x13420000 0x400
> + 0x13421000 0x40>;
>
> interrupt-parent = <&intc>;
> interrupts = <10>;
> diff --git a/drivers/dma/dma-jz4780.c b/drivers/dma/dma-jz4780.c
> index b40f491f0367..4d234caf5d62 100644
> --- a/drivers/dma/dma-jz4780.c
> +++ b/drivers/dma/dma-jz4780.c
> @@ -25,26 +25,26 @@
> #include "virt-dma.h"
>
> /* Global registers. */
> -#define JZ_DMA_REG_DMAC 0x1000
> -#define JZ_DMA_REG_DIRQP 0x1004
> -#define JZ_DMA_REG_DDR 0x1008
> -#define JZ_DMA_REG_DDRS 0x100c
> -#define JZ_DMA_REG_DMACP 0x101c
> -#define JZ_DMA_REG_DSIRQP 0x1020
> -#define JZ_DMA_REG_DSIRQM 0x1024
> -#define JZ_DMA_REG_DCIRQP 0x1028
> -#define JZ_DMA_REG_DCIRQM 0x102c
> +#define JZ_DMA_REG_DMAC 0x00
> +#define JZ_DMA_REG_DIRQP 0x04
> +#define JZ_DMA_REG_DDR 0x08
> +#define JZ_DMA_REG_DDRS 0x0c
> +#define JZ_DMA_REG_DMACP 0x1c
> +#define JZ_DMA_REG_DSIRQP 0x20
> +#define JZ_DMA_REG_DSIRQM 0x24
> +#define JZ_DMA_REG_DCIRQP 0x28
> +#define JZ_DMA_REG_DCIRQM 0x2c
>
> /* Per-channel registers. */
> #define JZ_DMA_REG_CHAN(n) (n * 0x20)
> -#define JZ_DMA_REG_DSA(n) (0x00 + JZ_DMA_REG_CHAN(n))
> -#define JZ_DMA_REG_DTA(n) (0x04 + JZ_DMA_REG_CHAN(n))
> -#define JZ_DMA_REG_DTC(n) (0x08 + JZ_DMA_REG_CHAN(n))
> -#define JZ_DMA_REG_DRT(n) (0x0c + JZ_DMA_REG_CHAN(n))
> -#define JZ_DMA_REG_DCS(n) (0x10 + JZ_DMA_REG_CHAN(n))
> -#define JZ_DMA_REG_DCM(n) (0x14 + JZ_DMA_REG_CHAN(n))
> -#define JZ_DMA_REG_DDA(n) (0x18 + JZ_DMA_REG_CHAN(n))
> -#define JZ_DMA_REG_DSD(n) (0x1c + JZ_DMA_REG_CHAN(n))
> +#define JZ_DMA_REG_DSA 0x00
> +#define JZ_DMA_REG_DTA 0x04
> +#define JZ_DMA_REG_DTC 0x08
> +#define JZ_DMA_REG_DRT 0x0c
> +#define JZ_DMA_REG_DCS 0x10
> +#define JZ_DMA_REG_DCM 0x14
> +#define JZ_DMA_REG_DDA 0x18
> +#define JZ_DMA_REG_DSD 0x1c
>
> #define JZ_DMA_DMAC_DMAE BIT(0)
> #define JZ_DMA_DMAC_AR BIT(2)
> @@ -140,7 +140,8 @@ enum jz_version {
>
> struct jz4780_dma_dev {
> struct dma_device dma_device;
> - void __iomem *base;
> + void __iomem *chn_base;
> + void __iomem *ctrl_base;
> struct clk *clk;
> unsigned int irq;
> unsigned int nb_channels;
> @@ -174,16 +175,28 @@ static inline struct jz4780_dma_dev *jz4780_dma_chan_parent(
> dma_device);
> }
>
> -static inline uint32_t jz4780_dma_readl(struct jz4780_dma_dev *jzdma,
> +static inline uint32_t jz4780_dma_chn_readl(struct jz4780_dma_dev *jzdma,
> + unsigned int chn, unsigned int reg)
> +{
> + return readl(jzdma->chn_base + reg + JZ_DMA_REG_CHAN(chn));
> +}
> +
> +static inline void jz4780_dma_chn_writel(struct jz4780_dma_dev *jzdma,
> + unsigned int chn, unsigned int reg, uint32_t val)
> +{
> + writel(val, jzdma->chn_base + reg + JZ_DMA_REG_CHAN(chn));
> +}
> +
> +static inline uint32_t jz4780_dma_ctrl_readl(struct jz4780_dma_dev *jzdma,
> unsigned int reg)
> {
> - return readl(jzdma->base + reg);
> + return readl(jzdma->ctrl_base + reg);
> }
>
> -static inline void jz4780_dma_writel(struct jz4780_dma_dev *jzdma,
> +static inline void jz4780_dma_ctrl_writel(struct jz4780_dma_dev *jzdma,
> unsigned int reg, uint32_t val)
> {
> - writel(val, jzdma->base + reg);
> + writel(val, jzdma->ctrl_base + reg);
> }
>
> static struct jz4780_dma_desc *jz4780_dma_desc_alloc(
> @@ -478,17 +491,18 @@ static void jz4780_dma_begin(struct jz4780_dma_chan *jzchan)
> }
>
> /* Use 8-word descriptors. */
> - jz4780_dma_writel(jzdma, JZ_DMA_REG_DCS(jzchan->id), JZ_DMA_DCS_DES8);
> + jz4780_dma_chn_writel(jzdma, jzchan->id,
> + JZ_DMA_REG_DCS, JZ_DMA_DCS_DES8);
>
> /* Write descriptor address and initiate descriptor fetch. */
> desc_phys = jzchan->desc->desc_phys +
> (jzchan->curr_hwdesc * sizeof(*jzchan->desc->desc));
> - jz4780_dma_writel(jzdma, JZ_DMA_REG_DDA(jzchan->id), desc_phys);
> - jz4780_dma_writel(jzdma, JZ_DMA_REG_DDRS, BIT(jzchan->id));
> + jz4780_dma_chn_writel(jzdma, jzchan->id, JZ_DMA_REG_DDA, desc_phys);
> + jz4780_dma_ctrl_writel(jzdma, JZ_DMA_REG_DDRS, BIT(jzchan->id));
>
> /* Enable the channel. */
> - jz4780_dma_writel(jzdma, JZ_DMA_REG_DCS(jzchan->id),
> - JZ_DMA_DCS_DES8 | JZ_DMA_DCS_CTE);
> + jz4780_dma_chn_writel(jzdma, jzchan->id, JZ_DMA_REG_DCS,
> + JZ_DMA_DCS_DES8 | JZ_DMA_DCS_CTE);
> }
>
> static void jz4780_dma_issue_pending(struct dma_chan *chan)
> @@ -514,7 +528,7 @@ static int jz4780_dma_terminate_all(struct dma_chan *chan)
> spin_lock_irqsave(&jzchan->vchan.lock, flags);
>
> /* Clear the DMA status and stop the transfer. */
> - jz4780_dma_writel(jzdma, JZ_DMA_REG_DCS(jzchan->id), 0);
> + jz4780_dma_chn_writel(jzdma, jzchan->id, JZ_DMA_REG_DCS, 0);
> if (jzchan->desc) {
> vchan_terminate_vdesc(&jzchan->desc->vdesc);
> jzchan->desc = NULL;
> @@ -563,8 +577,8 @@ static size_t jz4780_dma_desc_residue(struct jz4780_dma_chan *jzchan,
> residue += desc->desc[i].dtc << jzchan->transfer_shift;
>
> if (next_sg != 0) {
> - count = jz4780_dma_readl(jzdma,
> - JZ_DMA_REG_DTC(jzchan->id));
> + count = jz4780_dma_chn_readl(jzdma, jzchan->id,
> + JZ_DMA_REG_DTC);
> residue += count << jzchan->transfer_shift;
> }
>
> @@ -611,8 +625,8 @@ static void jz4780_dma_chan_irq(struct jz4780_dma_dev *jzdma,
>
> spin_lock(&jzchan->vchan.lock);
>
> - dcs = jz4780_dma_readl(jzdma, JZ_DMA_REG_DCS(jzchan->id));
> - jz4780_dma_writel(jzdma, JZ_DMA_REG_DCS(jzchan->id), 0);
> + dcs = jz4780_dma_chn_readl(jzdma, jzchan->id, JZ_DMA_REG_DCS);
> + jz4780_dma_chn_writel(jzdma, jzchan->id, JZ_DMA_REG_DCS, 0);
>
> if (dcs & JZ_DMA_DCS_AR) {
> dev_warn(&jzchan->vchan.chan.dev->device,
> @@ -651,7 +665,7 @@ static irqreturn_t jz4780_dma_irq_handler(int irq, void *data)
> uint32_t pending, dmac;
> int i;
>
> - pending = jz4780_dma_readl(jzdma, JZ_DMA_REG_DIRQP);
> + pending = jz4780_dma_ctrl_readl(jzdma, JZ_DMA_REG_DIRQP);
>
> for (i = 0; i < jzdma->nb_channels; i++) {
> if (!(pending & (1<<i)))
> @@ -661,12 +675,12 @@ static irqreturn_t jz4780_dma_irq_handler(int irq, void *data)
> }
>
> /* Clear halt and address error status of all channels. */
> - dmac = jz4780_dma_readl(jzdma, JZ_DMA_REG_DMAC);
> + dmac = jz4780_dma_ctrl_readl(jzdma, JZ_DMA_REG_DMAC);
> dmac &= ~(JZ_DMA_DMAC_HLT | JZ_DMA_DMAC_AR);
> - jz4780_dma_writel(jzdma, JZ_DMA_REG_DMAC, dmac);
> + jz4780_dma_ctrl_writel(jzdma, JZ_DMA_REG_DMAC, dmac);
>
> /* Clear interrupt pending status. */
> - jz4780_dma_writel(jzdma, JZ_DMA_REG_DIRQP, 0);
> + jz4780_dma_ctrl_writel(jzdma, JZ_DMA_REG_DIRQP, 0);
>
> return IRQ_HANDLED;
> }
> @@ -804,9 +818,19 @@ static int jz4780_dma_probe(struct platform_device *pdev)
> return -EINVAL;
> }
>
> - jzdma->base = devm_ioremap_resource(dev, res);
> - if (IS_ERR(jzdma->base))
> - return PTR_ERR(jzdma->base);
> + jzdma->chn_base = devm_ioremap_resource(dev, res);
> + if (IS_ERR(jzdma->chn_base))
> + return PTR_ERR(jzdma->chn_base);
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
> + if (!res) {
> + dev_err(dev, "failed to get I/O memory\n");
> + return -EINVAL;
> + }
> +
> + jzdma->ctrl_base = devm_ioremap_resource(dev, res);
> + if (IS_ERR(jzdma->ctrl_base))
> + return PTR_ERR(jzdma->ctrl_base);
>
> ret = platform_get_irq(pdev, 0);
> if (ret < 0) {
> @@ -864,9 +888,9 @@ static int jz4780_dma_probe(struct platform_device *pdev)
> * Also set the FMSC bit - it increases MSC performance, so it makes
> * little sense not to enable it.
> */
> - jz4780_dma_writel(jzdma, JZ_DMA_REG_DMAC,
> + jz4780_dma_ctrl_writel(jzdma, JZ_DMA_REG_DMAC,
> JZ_DMA_DMAC_DMAE | JZ_DMA_DMAC_FMSC);
> - jz4780_dma_writel(jzdma, JZ_DMA_REG_DMACP, 0);
> + jz4780_dma_ctrl_writel(jzdma, JZ_DMA_REG_DMACP, 0);
>
> INIT_LIST_HEAD(&dd->channels);
>
> --
> 2.18.0
>
>
Regards,
PrasannaKumar
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* [03/14] dmaengine: dma-jz4780: Use 4-word descriptors
From: PrasannaKumar Muralidharan @ 2018-07-04 16:40 UTC (permalink / raw)
To: Paul Cercueil
Cc: Vinod Koul, Rob Herring, Mark Rutland, Ralf Baechle, Paul Burton,
James Hogan, Zubair Lutfullah Kakakhel, Mathieu Malaterre,
Daniel Silsby, dmaengine,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list, Linux-MIPS
Hi Paul,
On 3 July 2018 at 18:02, Paul Cercueil <paul@crapouillou.net> wrote:
> The only information we use in the 8-word version of the hardware DMA
> descriptor that is not present in the 4-word version is the transfer
> type, aka. the ID of the source or recipient device.
>
> Since the transfer type will never change for a DMA channel in use,
> we can just set it once for all in the corresponding DMA register
> before starting any transfer.
>
> This has several benefits:
>
> * the driver will handle twice as many hardware DMA descriptors;
>
> * the driver is closer to support the JZ4740, which only supports 4-word
> hardware DMA descriptors;
>
> * the JZ4770 SoC needs the transfer type to be set in the corresponding
> DMA register anyway, even if 8-word descriptors are in use.
>
> Signed-off-by: Paul Cercueil <paul@crapouillou.net>
> ---
> drivers/dma/dma-jz4780.c | 21 +++++++++------------
> 1 file changed, 9 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/dma/dma-jz4780.c b/drivers/dma/dma-jz4780.c
> index 4d234caf5d62..cd2cd70fd843 100644
> --- a/drivers/dma/dma-jz4780.c
> +++ b/drivers/dma/dma-jz4780.c
> @@ -93,17 +93,12 @@
> * @dtc: transfer count (number of blocks of the transfer size specified in DCM
> * to transfer) in the low 24 bits, offset of the next descriptor from the
> * descriptor base address in the upper 8 bits.
> - * @sd: target/source stride difference (in stride transfer mode).
> - * @drt: request type
> */
> struct jz4780_dma_hwdesc {
> uint32_t dcm;
> uint32_t dsa;
> uint32_t dta;
> uint32_t dtc;
> - uint32_t sd;
> - uint32_t drt;
> - uint32_t reserved[2];
> };
>
> /* Size of allocations for hardware descriptor blocks. */
> @@ -280,7 +275,6 @@ static int jz4780_dma_setup_hwdesc(struct jz4780_dma_chan *jzchan,
> desc->dcm = JZ_DMA_DCM_SAI;
> desc->dsa = addr;
> desc->dta = config->dst_addr;
> - desc->drt = jzchan->transfer_type;
>
> width = config->dst_addr_width;
> maxburst = config->dst_maxburst;
> @@ -288,7 +282,6 @@ static int jz4780_dma_setup_hwdesc(struct jz4780_dma_chan *jzchan,
> desc->dcm = JZ_DMA_DCM_DAI;
> desc->dsa = config->src_addr;
> desc->dta = addr;
> - desc->drt = jzchan->transfer_type;
>
> width = config->src_addr_width;
> maxburst = config->src_maxburst;
> @@ -433,9 +426,10 @@ static struct dma_async_tx_descriptor *jz4780_dma_prep_dma_memcpy(
> tsz = jz4780_dma_transfer_size(dest | src | len,
> &jzchan->transfer_shift);
>
> + jzchan->transfer_type = JZ_DMA_DRT_AUTO;
> +
> desc->desc[0].dsa = src;
> desc->desc[0].dta = dest;
> - desc->desc[0].drt = JZ_DMA_DRT_AUTO;
> desc->desc[0].dcm = JZ_DMA_DCM_TIE | JZ_DMA_DCM_SAI | JZ_DMA_DCM_DAI |
> tsz << JZ_DMA_DCM_TSZ_SHIFT |
> JZ_DMA_WIDTH_32_BIT << JZ_DMA_DCM_SP_SHIFT |
> @@ -490,9 +484,12 @@ static void jz4780_dma_begin(struct jz4780_dma_chan *jzchan)
> (jzchan->curr_hwdesc + 1) % jzchan->desc->count;
> }
>
> - /* Use 8-word descriptors. */
> - jz4780_dma_chn_writel(jzdma, jzchan->id,
> - JZ_DMA_REG_DCS, JZ_DMA_DCS_DES8);
> + /* Use 4-word descriptors. */
> + jz4780_dma_chn_writel(jzdma, jzchan->id, JZ_DMA_REG_DCS, 0);
> +
> + /* Set transfer type. */
> + jz4780_dma_chn_writel(jzdma, jzchan->id, JZ_DMA_REG_DRT,
> + jzchan->transfer_type);
>
> /* Write descriptor address and initiate descriptor fetch. */
> desc_phys = jzchan->desc->desc_phys +
> @@ -502,7 +499,7 @@ static void jz4780_dma_begin(struct jz4780_dma_chan *jzchan)
>
> /* Enable the channel. */
> jz4780_dma_chn_writel(jzdma, jzchan->id, JZ_DMA_REG_DCS,
> - JZ_DMA_DCS_DES8 | JZ_DMA_DCS_CTE);
> + JZ_DMA_DCS_CTE);
> }
>
> static void jz4780_dma_issue_pending(struct dma_chan *chan)
> --
> 2.18.0
>
>
Patch looks good to me.
Reviewed-by: PrasannaKumar Muralidharan <prasannatsmkumar@gmail.com>
Regards,
PrasannaKumar
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* [05/14] dmaengine: dma-jz4780: Add support for the JZ4740 SoC
From: PrasannaKumar Muralidharan @ 2018-07-04 16:52 UTC (permalink / raw)
To: Paul Cercueil
Cc: Vinod Koul, Rob Herring, Mark Rutland, Ralf Baechle, Paul Burton,
James Hogan, Zubair Lutfullah Kakakhel, Mathieu Malaterre,
Daniel Silsby, dmaengine,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list, Linux-MIPS
On 3 July 2018 at 18:02, Paul Cercueil <paul@crapouillou.net> wrote:
> The JZ4740 SoC has a single DMA core starring six DMA channels.
>
> Signed-off-by: Paul Cercueil <paul@crapouillou.net>
> ---
> Documentation/devicetree/bindings/dma/jz4780-dma.txt | 1 +
> drivers/dma/Kconfig | 2 +-
> drivers/dma/dma-jz4780.c | 4 ++++
> 3 files changed, 6 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/dma/jz4780-dma.txt b/Documentation/devicetree/bindings/dma/jz4780-dma.txt
> index 0fd0759053be..d7ca3f925fdf 100644
> --- a/Documentation/devicetree/bindings/dma/jz4780-dma.txt
> +++ b/Documentation/devicetree/bindings/dma/jz4780-dma.txt
> @@ -5,6 +5,7 @@ Required properties:
> - compatible: Should be one of:
> * ingenic,jz4780-dma
> * ingenic,jz4770-dma
> + * ingenic,jz4740-dma
> - reg: Should contain the DMA channel registers location and length, followed
> by the DMA controller registers location and length.
> - interrupts: Should contain the interrupt specifier of the DMA controller.
> diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
> index 48d25dccedb7..a935d15ec581 100644
> --- a/drivers/dma/Kconfig
> +++ b/drivers/dma/Kconfig
> @@ -143,7 +143,7 @@ config DMA_JZ4740
>
> config DMA_JZ4780
> tristate "JZ4780 DMA support"
> - depends on MACH_JZ4780 || MACH_JZ4770 || COMPILE_TEST
> + depends on MACH_INGENIC || COMPILE_TEST
> select DMA_ENGINE
> select DMA_VIRTUAL_CHANNELS
> help
> diff --git a/drivers/dma/dma-jz4780.c b/drivers/dma/dma-jz4780.c
> index 7b8b2dcd119e..ccadbe61dde7 100644
> --- a/drivers/dma/dma-jz4780.c
> +++ b/drivers/dma/dma-jz4780.c
> @@ -133,6 +133,7 @@ struct jz4780_dma_chan {
> };
>
> enum jz_version {
> + ID_JZ4740,
> ID_JZ4770,
> ID_JZ4780,
> };
> @@ -247,6 +248,7 @@ static void jz4780_dma_desc_free(struct virt_dma_desc *vdesc)
> }
>
> static const unsigned int jz4780_dma_ord_max[] = {
> + [ID_JZ4740] = 5,
> [ID_JZ4770] = 6,
> [ID_JZ4780] = 7,
> };
> @@ -801,11 +803,13 @@ static struct dma_chan *jz4780_of_dma_xlate(struct of_phandle_args *dma_spec,
> }
>
> static const unsigned int jz4780_dma_nb_channels[] = {
> + [ID_JZ4740] = 6,
> [ID_JZ4770] = 6,
> [ID_JZ4780] = 32,
> };
>
> static const struct of_device_id jz4780_dma_dt_match[] = {
> + { .compatible = "ingenic,jz4740-dma", .data = (void *)ID_JZ4740 },
> { .compatible = "ingenic,jz4770-dma", .data = (void *)ID_JZ4770 },
> { .compatible = "ingenic,jz4780-dma", .data = (void *)ID_JZ4780 },
> {},
> --
> 2.18.0
>
>
Patch looks good to me.
Reviewed-by: PrasannaKumar Muralidharan <prasannatsmkumar@gmail.com>/
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* [06/14] dmaengine: dma-jz4780: Add support for the JZ4725B SoC
From: PrasannaKumar Muralidharan @ 2018-07-04 16:55 UTC (permalink / raw)
To: Paul Cercueil
Cc: Vinod Koul, Rob Herring, Mark Rutland, Ralf Baechle, Paul Burton,
James Hogan, Zubair Lutfullah Kakakhel, Mathieu Malaterre,
Daniel Silsby, dmaengine,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list, Linux-MIPS
On 3 July 2018 at 18:02, Paul Cercueil <paul@crapouillou.net> wrote:
> The JZ4725B has one DMA core starring six DMA channels.
> As for the JZ4770, each DMA channel's clock can be enabled with
> a register write, the difference here being that once started, it
> is not possible to turn it off.
>
> Signed-off-by: Paul Cercueil <paul@crapouillou.net>
> ---
> Documentation/devicetree/bindings/dma/jz4780-dma.txt | 1 +
> drivers/dma/dma-jz4780.c | 6 ++++++
> 2 files changed, 7 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/dma/jz4780-dma.txt b/Documentation/devicetree/bindings/dma/jz4780-dma.txt
> index d7ca3f925fdf..5d302b488e88 100644
> --- a/Documentation/devicetree/bindings/dma/jz4780-dma.txt
> +++ b/Documentation/devicetree/bindings/dma/jz4780-dma.txt
> @@ -5,6 +5,7 @@ Required properties:
> - compatible: Should be one of:
> * ingenic,jz4780-dma
> * ingenic,jz4770-dma
> + * ingenic,jz4725b-dma
> * ingenic,jz4740-dma
> - reg: Should contain the DMA channel registers location and length, followed
> by the DMA controller registers location and length.
> diff --git a/drivers/dma/dma-jz4780.c b/drivers/dma/dma-jz4780.c
> index ccadbe61dde7..922e4031e70e 100644
> --- a/drivers/dma/dma-jz4780.c
> +++ b/drivers/dma/dma-jz4780.c
> @@ -134,6 +134,7 @@ struct jz4780_dma_chan {
>
> enum jz_version {
> ID_JZ4740,
> + ID_JZ4725B,
> ID_JZ4770,
> ID_JZ4780,
> };
> @@ -204,6 +205,8 @@ static inline void jz4780_dma_chan_enable(struct jz4780_dma_dev *jzdma,
> {
> if (jzdma->version == ID_JZ4770)
> jz4780_dma_ctrl_writel(jzdma, JZ_DMA_REG_DCKES, BIT(chn));
> + else if (jzdma->version == ID_JZ4725B)
> + jz4780_dma_ctrl_writel(jzdma, JZ_DMA_REG_DCKE, BIT(chn));
> }
>
> static inline void jz4780_dma_chan_disable(struct jz4780_dma_dev *jzdma,
> @@ -249,6 +252,7 @@ static void jz4780_dma_desc_free(struct virt_dma_desc *vdesc)
>
> static const unsigned int jz4780_dma_ord_max[] = {
> [ID_JZ4740] = 5,
> + [ID_JZ4725B] = 5,
> [ID_JZ4770] = 6,
> [ID_JZ4780] = 7,
> };
> @@ -804,12 +808,14 @@ static struct dma_chan *jz4780_of_dma_xlate(struct of_phandle_args *dma_spec,
>
> static const unsigned int jz4780_dma_nb_channels[] = {
> [ID_JZ4740] = 6,
> + [ID_JZ4725B] = 6,
> [ID_JZ4770] = 6,
> [ID_JZ4780] = 32,
> };
>
> static const struct of_device_id jz4780_dma_dt_match[] = {
> { .compatible = "ingenic,jz4740-dma", .data = (void *)ID_JZ4740 },
> + { .compatible = "ingenic,jz4725b-dma", .data = (void *)ID_JZ4725B },
> { .compatible = "ingenic,jz4770-dma", .data = (void *)ID_JZ4770 },
> { .compatible = "ingenic,jz4780-dma", .data = (void *)ID_JZ4780 },
> {},
> --
> 2.18.0
>
>
Reviewed-by: PrasannaKumar Muralidharan <prasannatsmkumar@gmail.com>
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