* [RFC,2/6] dma: Add Synopsys eDMA IP version 0 support
From: Eugeniy Paltsev @ 2018-12-12 13:39 UTC (permalink / raw)
To: dmaengine@vger.kernel.org, linux-pci@vger.kernel.org,
gustavo.pimentel@synopsys.com
Cc: vkoul@kernel.org, andriy.shevchenko@linux.intel.com, Joao Pinto,
Alexey Brodkin
Hi Gustavo,
On Wed, 2018-12-12 at 12:13 +0100, Gustavo Pimentel wrote:
> Add support for the eDMA IP version 0 driver for both register maps (legacy
> and unroll).
[snip]
> diff --git a/drivers/dma/dw-edma/dw-edma-v0-core.c b/drivers/dma/dw-edma/dw-edma-v0-core.c
> new file mode 100644
> index 0000000..cc362b0
> --- /dev/null
> +++ b/drivers/dma/dw-edma/dw-edma-v0-core.c
> @@ -0,0 +1,346 @@
> +// SPDX-License-Identifier: GPL-2.0
> +// Copyright (c) 2018 Synopsys, Inc. and/or its affiliates.
> +// Synopsys DesignWare eDMA v0 core
> +
> +#include "dw-edma-core.h"
> +#include "dw-edma-v0-core.h"
> +#include "dw-edma-v0-regs.h"
> +#include "dw-edma-v0-debugfs.h"
> +
> +#define QWORD_HI(value) ((value & 0xFFFFFFFF00000000llu) >> 32)
Use upper_32_bits() macros.
> +#define QWORD_LO(value) (value & 0x00000000FFFFFFFFllu)
Use lower_32_bits() macros.
> +enum dw_edma_control {
> + DW_EDMA_CB = BIT(0),
> + DW_EDMA_TCB = BIT(1),
> + DW_EDMA_LLP = BIT(2),
> + DW_EDMA_LIE = BIT(3),
> + DW_EDMA_RIE = BIT(4),
[snip]
> + viewport_sel = (ch & 0x00000007ul);
[snip]
> +void dw_edma_v0_core_off(struct dw_edma *dw)
> +{
> + SET_BOTH(dw, int_mask, 0x00FF00FFul);
> + SET_BOTH(dw, int_clear, 0x00FF00FFul);
> + SET_BOTH(dw, engine_en, 0x00000000ul);
> +}
[snip]
> + num_ch &= 0x0000000Ful;
> + } else {
> + num_ch &= 0x000F0000ul;
I guess it's better to name this magic numbers via defines.
[snip]
> +
> +bool dw_edma_v0_core_status_done_int(struct dw_edma_chan *chan)
> +{
> + struct dw_edma *dw = chan->chip->dw;
> + u32 tmp;
> +
> + tmp = GET_RW(dw, chan->dir, int_status);
> + tmp &= BIT(chan->id);
> +
> + return tmp ? true : false;
return !!tmp;
> +}
> +
> +bool dw_edma_v0_core_status_abort_int(struct dw_edma_chan *chan)
> +{
> + struct dw_edma *dw = chan->chip->dw;
> + u32 tmp;
> +
> + tmp = GET_RW(dw, chan->dir, int_status);
> + tmp &= BIT(chan->id + 16);
> +
> + return tmp ? true : false;
ditto.
--
Eugeniy Paltsev
^ permalink raw reply
* [RFC,4/6] dma: Add Synopsys eDMA IP PCIe glue-logic
From: Andy Shevchenko @ 2018-12-12 13:25 UTC (permalink / raw)
To: Gustavo Pimentel
Cc: linux-pci, dmaengine, Vinod Koul, Eugeniy Paltsev,
Lorenzo Pieralisi, Joao Pinto
On Wed, Dec 12, 2018 at 12:13:24PM +0100, Gustavo Pimentel wrote:
> Synopsys eDMA IP is normally distributed along with Synopsys PCIe
> EndPoint IP (depends of the use and licensing agreement).
>
> This IP requires some basic configurations, such as:
> - eDMA registers BAR
> - eDMA registers offset
> - eDMA linked list BAR
> - eDMA linked list offset
> - eDMA linked list size
> - eDMA version
> - eDMA mode
>
> As a working example, PCIe glue-logic will attach to a Synopsys PCIe
> EndPoint IP prototype kit (Vendor ID = 0x16c3, Device ID = 0xedda),
> which has built-in an eDMA IP with this default configuration:
> - eDMA registers BAR = 0
> - eDMA registers offset = 0x1000 (4 Kbytes)
> - eDMA linked list BAR = 2
> - eDMA linked list offset = 0x0 (0 Kbytes)
> - eDMA linked list size = 0x20000 (128 Kbytes)
> - eDMA version = 0
> - eDMA mode = EDMA_MODE_UNROLL
>
> This driver can be compile as built-in or external module in kernel.
>
> To enable this driver just select DW_EDMA_PCIE option in kernel
> configuration, however it requires and selects automatically DW_EDMA
> option too.
It seems this driver somehow written as a copy-paste of existing pieces w/o good reasons to do such.
> +enum dw_edma_pcie_bar {
> + BAR_0,
> + BAR_1,
> + BAR_2,
> + BAR_3,
> + BAR_4,
> + BAR_5
> +};
Why do you need this at all?
> +static const struct dw_edma_pcie_data snps_edda_data = {
> + // eDMA registers location
> + .regs_bar = BAR_0,
> + .regs_off = 0x1000, // 4 KBytes
> + // eDMA memory linked list location
> + .ll_bar = BAR_2,
> + .ll_off = 0, // 0 KBytes
> + .ll_sz = 0x20000, // 128 KBytes
> + // Other
> + .version = 0,
> + .mode = EDMA_MODE_UNROLL,
> +};
Huh? Isn't this
> +
> +static int dw_edma_pcie_probe(struct pci_dev *pdev,
> + const struct pci_device_id *pid)
> +{
> + const struct dw_edma_pcie_data *pdata = (void *)pid->driver_data;
> + struct device *dev = &pdev->dev;
> + struct dw_edma_chip *chip;
> + struct dw_edma *dw;
> + void __iomem *reg;
> + int err, irq = -1;
> + u32 addr_hi, addr_lo;
> + u16 flags;
> + u8 cap_off;
> +
> + if (!pdata) {
> + dev_err(dev, "%s missing data struture\n",
> + pci_name(pdev));
> + return -EFAULT;
> + }
> +
> + err = pcim_enable_device(pdev);
> + if (err) {
> + dev_err(dev, "%s enabling device failed\n",
> + pci_name(pdev));
> + return err;
> + }
> +
> + err = pcim_iomap_regions(pdev, 1 << pdata->regs_bar, pci_name(pdev));
> + if (err) {
> + dev_err(dev, "%s eDMA register BAR I/O memory remapping failed\n",
> + pci_name(pdev));
> + return err;
> + }
> +
> + err = pcim_iomap_regions(pdev, 1 << pdata->ll_bar, pci_name(pdev));
> + if (err) {
> + dev_err(dev, "%s eDMA linked list BAR I/O remapping failed\n",
> + pci_name(pdev));
> + return err;
> + }
This could be done in one call.
> +
> + pci_set_master(pdev);
> +
> + err = pci_try_set_mwi(pdev);
> + if (err) {
> + dev_err(dev, "%s DMA memory write invalidate\n",
> + pci_name(pdev));
> + return err;
> + }
Are you sure you need this?
> +
> + err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
> + if (err) {
> + dev_err(dev, "%s DMA mask set failed\n",
> + pci_name(pdev));
> + return err;
> + }
> +
> + err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
> + if (err) {
> + dev_err(dev, "%s consistent DMA mask set failed\n",
> + pci_name(pdev));
> + return err;
> + }
> +
> + chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
> + if (!chip)
> + return -ENOMEM;
> +
> + dw = devm_kzalloc(&pdev->dev, sizeof(*dw), GFP_KERNEL);
> + if (!dw)
> + return -ENOMEM;
> +
> + irq = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI | PCI_IRQ_MSIX);
> + if (irq < 0) {
> + dev_err(dev, "%s failed to alloc IRQ vector\n",
> + pci_name(pdev));
> + return -EPERM;
> + }
> +
> + chip->dw = dw;
> + chip->dev = dev;
> + chip->id = pdev->devfn;
> + chip->irq = pdev->irq;
> +
> + dw->regs = pcim_iomap_table(pdev)[pdata->regs_bar];
> + dw->regs += pdata->regs_off;
> +
> + dw->va_ll = pcim_iomap_table(pdev)[pdata->ll_bar];
> + dw->va_ll += pdata->ll_off;
> + dw->pa_ll = pdev->resource[pdata->ll_bar].start;
> + dw->pa_ll += pdata->ll_off;
> + dw->ll_sz = pdata->ll_sz;
> +
> + dw->msi_addr = 0;
> + dw->msi_data = 0;
> +
> + dw->version = pdata->version;
> + dw->mode = pdata->mode;
> +
> + dev_info(dev, "Version:\t%u\n", dw->version);
> +
> + dev_info(dev, "Mode:\t%s\n",
> + dw->mode == EDMA_MODE_LEGACY ? "Legacy" : "Unroll");
> +
> + dev_info(dev, "Registers:\tBAR=%u, off=0x%.16llx B, addr=0x%.8lx\n",
> + pdata->regs_bar, pdata->regs_off,
> + (unsigned long) dw->regs);
Oh, no, don't do casting when printing something. In only rare cases it's needed, not here.
> +
> + dev_info(dev,
> + "L. List:\tBAR=%u, off=0x%.16llx B, sz=0x%.8x B, vaddr=0x%.8lx, paddr=0x%.8lx",
> + pdata->ll_bar, pdata->ll_off, pdata->ll_sz,
> + (unsigned long) dw->va_ll,
> + (unsigned long) dw->pa_ll);
This is noise, either remove or move to dbg level.
> + if (pdev->msi_cap && pdev->msi_enabled) {
> + cap_off = pdev->msi_cap + PCI_MSI_FLAGS;
> + pci_read_config_word(pdev, cap_off, &flags);
> + if (flags & PCI_MSI_FLAGS_ENABLE) {
> + cap_off = pdev->msi_cap + PCI_MSI_ADDRESS_LO;
> + pci_read_config_dword(pdev, cap_off, &addr_lo);
> +
> + if (flags & PCI_MSI_FLAGS_64BIT) {
> + cap_off = pdev->msi_cap + PCI_MSI_ADDRESS_HI;
> + pci_read_config_dword(pdev, cap_off, &addr_hi);
> + cap_off = pdev->msi_cap + PCI_MSI_DATA_64;
> + } else {
> + addr_hi = 0;
> + cap_off = pdev->msi_cap + PCI_MSI_DATA_32;
> + }
> +
> + dw->msi_addr = addr_hi;
> + dw->msi_addr <<= 32;
> + dw->msi_addr |= addr_lo;
> +
> + pci_read_config_dword(pdev, cap_off, &(dw->msi_data));
> + dw->msi_data &= 0xffff;
> +
> + dev_info(dev,
> + "MSI:\t\taddr=0x%.16llx, data=0x%.8x, nr=%d\n",
> + dw->msi_addr, dw->msi_data, pdev->irq);
> + }
> + }
> +
> + if (pdev->msix_cap && pdev->msix_enabled) {
> + u32 offset;
> + u8 bir;
> +
> + cap_off = pdev->msix_cap + PCI_MSIX_FLAGS;
> + pci_read_config_word(pdev, cap_off, &flags);
> +
> + if (flags & PCI_MSIX_FLAGS_ENABLE) {
> + cap_off = pdev->msix_cap + PCI_MSIX_TABLE;
> + pci_read_config_dword(pdev, cap_off, &offset);
> +
> + bir = offset & PCI_MSIX_TABLE_BIR;
> + offset &= PCI_MSIX_TABLE_OFFSET;
> +
> + reg = pcim_iomap_table(pdev)[bir];
> + reg += offset;
> +
> + addr_lo = readl(reg + PCI_MSIX_ENTRY_LOWER_ADDR);
> + addr_hi = readl(reg + PCI_MSIX_ENTRY_UPPER_ADDR);
> + dw->msi_addr = addr_hi;
> + dw->msi_addr <<= 32;
> + dw->msi_addr |= addr_lo;
> +
> + dw->msi_data = readl(reg + PCI_MSIX_ENTRY_DATA);
> +
> + dev_info(dev,
> + "MSI-X:\taddr=0x%.16llx, data=0x%.8x, nr=%d\n",
> + dw->msi_addr, dw->msi_data, pdev->irq);
> + }
> + }
What is this? Why?
> +
> + if (!pdev->msi_enabled && !pdev->msix_enabled) {
There is a helper from PCI core for this.
> + dev_err(dev, "%s enable interrupt failed\n",
> + pci_name(pdev));
> + return -EPERM;
> + }
> +
> + err = dw_edma_probe(chip);
> + if (err) {
> + dev_err(dev, "%s eDMA probe failed\n",
> + pci_name(pdev));
> + return err;
> + }
> +
> + pci_set_drvdata(pdev, chip);
> +
> + dev_info(dev, "DesignWare eDMA PCIe driver loaded completely\n");
> +
> + return 0;
> +}
> +
> +static void dw_edma_pcie_remove(struct pci_dev *pdev)
> +{
> + struct dw_edma_chip *chip = pci_get_drvdata(pdev);
> + struct device *dev = &pdev->dev;
> + int err;
> +
> + err = dw_edma_remove(chip);
> + if (err) {
> + dev_warn(dev, "%s can't remove device properly: %d\n",
> + pci_name(pdev), err);
dev_warn + dev_name ?! Have you tried to see what would be the output?
> + }
> +
> + pci_free_irq_vectors(pdev);
> +
> + dev_info(dev, "DesignWare eDMA PCIe driver unloaded completely\n");
> +}
> +
> +#ifdef CONFIG_PM_SLEEP
You can use __maybe_unused instead of this.
> +#endif /* CONFIG_PM_SLEEP */
^ permalink raw reply
* [RFC,6/6] pci: pci_ids: Add Synopsys device id 0xedda
From: Gustavo Pimentel @ 2018-12-12 11:13 UTC (permalink / raw)
To: linux-pci, dmaengine
Cc: Gustavo Pimentel, Kishon Vijay Abraham I, Bjorn Helgaas,
Lorenzo Pieralisi, Joao Pinto
Create and add Synopsys device id (0xedda) to pci id list, since this id
is now being use on two different drivers (pci_endpoint_test.ko and
dw-edma-pcie.ko).
Signed-off-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
Cc: Kishon Vijay Abraham I <kishon@ti.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Joao Pinto <jpinto@synopsys.com>
---
drivers/dma/dw-edma/dw-edma-pcie.c | 2 +-
drivers/misc/pci_endpoint_test.c | 2 +-
include/linux/pci_ids.h | 1 +
3 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/dma/dw-edma/dw-edma-pcie.c b/drivers/dma/dw-edma/dw-edma-pcie.c
index f29a861..50e0db4 100644
--- a/drivers/dma/dw-edma/dw-edma-pcie.c
+++ b/drivers/dma/dw-edma/dw-edma-pcie.c
@@ -280,7 +280,7 @@ static const struct dev_pm_ops dw_edma_pcie_dev_pm_ops = {
};
static const struct pci_device_id dw_edma_pcie_id_table[] = {
- { PCI_DEVICE_DATA(SYNOPSYS, 0xedda, &snps_edda_data) },
+ { PCI_DEVICE_DATA(SYNOPSYS, EDDA, &snps_edda_data) },
{ }
};
MODULE_DEVICE_TABLE(pci, dw_edma_pcie_id_table);
diff --git a/drivers/misc/pci_endpoint_test.c b/drivers/misc/pci_endpoint_test.c
index 896e2df..d27efe838 100644
--- a/drivers/misc/pci_endpoint_test.c
+++ b/drivers/misc/pci_endpoint_test.c
@@ -788,7 +788,7 @@ static void pci_endpoint_test_remove(struct pci_dev *pdev)
static const struct pci_device_id pci_endpoint_test_tbl[] = {
{ PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_DRA74x) },
{ PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_DRA72x) },
- { PCI_DEVICE(PCI_VENDOR_ID_SYNOPSYS, 0xedda) },
+ { PCI_DEVICE_DATA(SYNOPSYS, EDDA, NULL) },
{ }
};
MODULE_DEVICE_TABLE(pci, pci_endpoint_test_tbl);
diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
index 69f0abe..57f17dd 100644
--- a/include/linux/pci_ids.h
+++ b/include/linux/pci_ids.h
@@ -2358,6 +2358,7 @@
#define PCI_DEVICE_ID_CENATEK_IDE 0x0001
#define PCI_VENDOR_ID_SYNOPSYS 0x16c3
+#define PCI_DEVICE_ID_SYNOPSYS_EDDA 0xedda
#define PCI_VENDOR_ID_VITESSE 0x1725
#define PCI_DEVICE_ID_VITESSE_VSC7174 0x7174
^ permalink raw reply related
* [RFC,5/6] MAINTAINERS: Add Synopsys eDMA IP driver maintainer
From: Gustavo Pimentel @ 2018-12-12 11:13 UTC (permalink / raw)
To: linux-pci, dmaengine
Cc: Gustavo Pimentel, Vinod Koul, Eugeniy Paltsev, Joao Pinto
Add Synopsys eDMA IP driver maintainer.
This driver aims to support Synopsys eDMA IP and is normally distributed
along with Synopsys PCIe EndPoint IP (depends of the use and licensing
agreement).
Signed-off-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
Cc: Vinod Koul <vkoul@kernel.org>
Cc: Eugeniy Paltsev <paltsev@synopsys.com>
Cc: Joao Pinto <jpinto@synopsys.com>
---
MAINTAINERS | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index f485597..bdbfc14 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -4256,6 +4256,13 @@ L: linux-mtd@lists.infradead.org
S: Supported
F: drivers/mtd/nand/raw/denali*
+DESIGNWARE EDMA CORE IP DRIVER
+M: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
+L: dmaengine@vger.kernel.org
+S: Maintained
+F: drivers/dma/dw-edma/
+F: include/linux/dma/edma.h
+
DESIGNWARE USB2 DRD IP DRIVER
M: Minas Harutyunyan <hminas@synopsys.com>
L: linux-usb@vger.kernel.org
^ permalink raw reply related
* [RFC,4/6] dma: Add Synopsys eDMA IP PCIe glue-logic
From: Gustavo Pimentel @ 2018-12-12 11:13 UTC (permalink / raw)
To: linux-pci, dmaengine
Cc: Gustavo Pimentel, Vinod Koul, Eugeniy Paltsev, Lorenzo Pieralisi,
Andy Shevchenko, Joao Pinto
Synopsys eDMA IP is normally distributed along with Synopsys PCIe
EndPoint IP (depends of the use and licensing agreement).
This IP requires some basic configurations, such as:
- eDMA registers BAR
- eDMA registers offset
- eDMA linked list BAR
- eDMA linked list offset
- eDMA linked list size
- eDMA version
- eDMA mode
As a working example, PCIe glue-logic will attach to a Synopsys PCIe
EndPoint IP prototype kit (Vendor ID = 0x16c3, Device ID = 0xedda),
which has built-in an eDMA IP with this default configuration:
- eDMA registers BAR = 0
- eDMA registers offset = 0x1000 (4 Kbytes)
- eDMA linked list BAR = 2
- eDMA linked list offset = 0x0 (0 Kbytes)
- eDMA linked list size = 0x20000 (128 Kbytes)
- eDMA version = 0
- eDMA mode = EDMA_MODE_UNROLL
This driver can be compile as built-in or external module in kernel.
To enable this driver just select DW_EDMA_PCIE option in kernel
configuration, however it requires and selects automatically DW_EDMA
option too.
Signed-off-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
Cc: Vinod Koul <vkoul@kernel.org>
Cc: Eugeniy Paltsev <paltsev@synopsys.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: Joao Pinto <jpinto@synopsys.com>
---
drivers/dma/dw-edma/Kconfig | 9 ++
drivers/dma/dw-edma/Makefile | 1 +
drivers/dma/dw-edma/dw-edma-pcie.c | 302 +++++++++++++++++++++++++++++++++++++
3 files changed, 312 insertions(+)
create mode 100644 drivers/dma/dw-edma/dw-edma-pcie.c
diff --git a/drivers/dma/dw-edma/Kconfig b/drivers/dma/dw-edma/Kconfig
index 3016bed..c0838ce 100644
--- a/drivers/dma/dw-edma/Kconfig
+++ b/drivers/dma/dw-edma/Kconfig
@@ -7,3 +7,12 @@ config DW_EDMA
help
Support the Synopsys DesignWare eDMA controller, normally
implemented on endpoints SoCs.
+
+config DW_EDMA_PCIE
+ tristate "Synopsys DesignWare eDMA PCIe driver"
+ depends on PCI && PCI_MSI
+ select DW_EDMA
+ help
+ Provides a glue-logic between the Synopsys DesignWare
+ eDMA controller and an endpoint PCIe device. This also serves
+ as a reference design to whom desires to use this IP.
diff --git a/drivers/dma/dw-edma/Makefile b/drivers/dma/dw-edma/Makefile
index 0c53033..8d45c0d 100644
--- a/drivers/dma/dw-edma/Makefile
+++ b/drivers/dma/dw-edma/Makefile
@@ -4,3 +4,4 @@ obj-$(CONFIG_DW_EDMA) += dw-edma.o
dw-edma-$(CONFIG_DEBUG_FS) := dw-edma-v0-debugfs.o
dw-edma-objs := dw-edma-core.o \
dw-edma-v0-core.o $(dw-edma-y)
+obj-$(CONFIG_DW_EDMA_PCIE) += dw-edma-pcie.o
diff --git a/drivers/dma/dw-edma/dw-edma-pcie.c b/drivers/dma/dw-edma/dw-edma-pcie.c
new file mode 100644
index 0000000..f29a861
--- /dev/null
+++ b/drivers/dma/dw-edma/dw-edma-pcie.c
@@ -0,0 +1,302 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018 Synopsys, Inc. and/or its affiliates.
+// Synopsys DesignWare eDMA PCIe driver
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/pci.h>
+#include <linux/device.h>
+#include <linux/dma/edma.h>
+
+#include "dw-edma-core.h"
+
+#define DRV_PCIE_NAME "dw-edma-pcie"
+
+enum dw_edma_pcie_bar {
+ BAR_0,
+ BAR_1,
+ BAR_2,
+ BAR_3,
+ BAR_4,
+ BAR_5
+};
+
+struct dw_edma_pcie_data {
+ enum dw_edma_pcie_bar regs_bar;
+ u64 regs_off;
+ enum dw_edma_pcie_bar ll_bar;
+ u64 ll_off;
+ size_t ll_sz;
+ u32 version;
+ enum dw_edma_mode mode;
+};
+
+static const struct dw_edma_pcie_data snps_edda_data = {
+ // eDMA registers location
+ .regs_bar = BAR_0,
+ .regs_off = 0x1000, // 4 KBytes
+ // eDMA memory linked list location
+ .ll_bar = BAR_2,
+ .ll_off = 0, // 0 KBytes
+ .ll_sz = 0x20000, // 128 KBytes
+ // Other
+ .version = 0,
+ .mode = EDMA_MODE_UNROLL,
+};
+
+static int dw_edma_pcie_probe(struct pci_dev *pdev,
+ const struct pci_device_id *pid)
+{
+ const struct dw_edma_pcie_data *pdata = (void *)pid->driver_data;
+ struct device *dev = &pdev->dev;
+ struct dw_edma_chip *chip;
+ struct dw_edma *dw;
+ void __iomem *reg;
+ int err, irq = -1;
+ u32 addr_hi, addr_lo;
+ u16 flags;
+ u8 cap_off;
+
+ if (!pdata) {
+ dev_err(dev, "%s missing data struture\n",
+ pci_name(pdev));
+ return -EFAULT;
+ }
+
+ err = pcim_enable_device(pdev);
+ if (err) {
+ dev_err(dev, "%s enabling device failed\n",
+ pci_name(pdev));
+ return err;
+ }
+
+ err = pcim_iomap_regions(pdev, 1 << pdata->regs_bar, pci_name(pdev));
+ if (err) {
+ dev_err(dev, "%s eDMA register BAR I/O memory remapping failed\n",
+ pci_name(pdev));
+ return err;
+ }
+
+ err = pcim_iomap_regions(pdev, 1 << pdata->ll_bar, pci_name(pdev));
+ if (err) {
+ dev_err(dev, "%s eDMA linked list BAR I/O remapping failed\n",
+ pci_name(pdev));
+ return err;
+ }
+
+ pci_set_master(pdev);
+
+ err = pci_try_set_mwi(pdev);
+ if (err) {
+ dev_err(dev, "%s DMA memory write invalidate\n",
+ pci_name(pdev));
+ return err;
+ }
+
+ err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
+ if (err) {
+ dev_err(dev, "%s DMA mask set failed\n",
+ pci_name(pdev));
+ return err;
+ }
+
+ err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
+ if (err) {
+ dev_err(dev, "%s consistent DMA mask set failed\n",
+ pci_name(pdev));
+ return err;
+ }
+
+ chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
+ if (!chip)
+ return -ENOMEM;
+
+ dw = devm_kzalloc(&pdev->dev, sizeof(*dw), GFP_KERNEL);
+ if (!dw)
+ return -ENOMEM;
+
+ irq = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI | PCI_IRQ_MSIX);
+ if (irq < 0) {
+ dev_err(dev, "%s failed to alloc IRQ vector\n",
+ pci_name(pdev));
+ return -EPERM;
+ }
+
+ chip->dw = dw;
+ chip->dev = dev;
+ chip->id = pdev->devfn;
+ chip->irq = pdev->irq;
+
+ dw->regs = pcim_iomap_table(pdev)[pdata->regs_bar];
+ dw->regs += pdata->regs_off;
+
+ dw->va_ll = pcim_iomap_table(pdev)[pdata->ll_bar];
+ dw->va_ll += pdata->ll_off;
+ dw->pa_ll = pdev->resource[pdata->ll_bar].start;
+ dw->pa_ll += pdata->ll_off;
+ dw->ll_sz = pdata->ll_sz;
+
+ dw->msi_addr = 0;
+ dw->msi_data = 0;
+
+ dw->version = pdata->version;
+ dw->mode = pdata->mode;
+
+ dev_info(dev, "Version:\t%u\n", dw->version);
+
+ dev_info(dev, "Mode:\t%s\n",
+ dw->mode == EDMA_MODE_LEGACY ? "Legacy" : "Unroll");
+
+ dev_info(dev, "Registers:\tBAR=%u, off=0x%.16llx B, addr=0x%.8lx\n",
+ pdata->regs_bar, pdata->regs_off,
+ (unsigned long) dw->regs);
+
+ dev_info(dev,
+ "L. List:\tBAR=%u, off=0x%.16llx B, sz=0x%.8x B, vaddr=0x%.8lx, paddr=0x%.8lx",
+ pdata->ll_bar, pdata->ll_off, pdata->ll_sz,
+ (unsigned long) dw->va_ll,
+ (unsigned long) dw->pa_ll);
+
+ if (pdev->msi_cap && pdev->msi_enabled) {
+ cap_off = pdev->msi_cap + PCI_MSI_FLAGS;
+ pci_read_config_word(pdev, cap_off, &flags);
+ if (flags & PCI_MSI_FLAGS_ENABLE) {
+ cap_off = pdev->msi_cap + PCI_MSI_ADDRESS_LO;
+ pci_read_config_dword(pdev, cap_off, &addr_lo);
+
+ if (flags & PCI_MSI_FLAGS_64BIT) {
+ cap_off = pdev->msi_cap + PCI_MSI_ADDRESS_HI;
+ pci_read_config_dword(pdev, cap_off, &addr_hi);
+ cap_off = pdev->msi_cap + PCI_MSI_DATA_64;
+ } else {
+ addr_hi = 0;
+ cap_off = pdev->msi_cap + PCI_MSI_DATA_32;
+ }
+
+ dw->msi_addr = addr_hi;
+ dw->msi_addr <<= 32;
+ dw->msi_addr |= addr_lo;
+
+ pci_read_config_dword(pdev, cap_off, &(dw->msi_data));
+ dw->msi_data &= 0xffff;
+
+ dev_info(dev,
+ "MSI:\t\taddr=0x%.16llx, data=0x%.8x, nr=%d\n",
+ dw->msi_addr, dw->msi_data, pdev->irq);
+ }
+ }
+
+ if (pdev->msix_cap && pdev->msix_enabled) {
+ u32 offset;
+ u8 bir;
+
+ cap_off = pdev->msix_cap + PCI_MSIX_FLAGS;
+ pci_read_config_word(pdev, cap_off, &flags);
+
+ if (flags & PCI_MSIX_FLAGS_ENABLE) {
+ cap_off = pdev->msix_cap + PCI_MSIX_TABLE;
+ pci_read_config_dword(pdev, cap_off, &offset);
+
+ bir = offset & PCI_MSIX_TABLE_BIR;
+ offset &= PCI_MSIX_TABLE_OFFSET;
+
+ reg = pcim_iomap_table(pdev)[bir];
+ reg += offset;
+
+ addr_lo = readl(reg + PCI_MSIX_ENTRY_LOWER_ADDR);
+ addr_hi = readl(reg + PCI_MSIX_ENTRY_UPPER_ADDR);
+ dw->msi_addr = addr_hi;
+ dw->msi_addr <<= 32;
+ dw->msi_addr |= addr_lo;
+
+ dw->msi_data = readl(reg + PCI_MSIX_ENTRY_DATA);
+
+ dev_info(dev,
+ "MSI-X:\taddr=0x%.16llx, data=0x%.8x, nr=%d\n",
+ dw->msi_addr, dw->msi_data, pdev->irq);
+ }
+ }
+
+ if (!pdev->msi_enabled && !pdev->msix_enabled) {
+ dev_err(dev, "%s enable interrupt failed\n",
+ pci_name(pdev));
+ return -EPERM;
+ }
+
+ err = dw_edma_probe(chip);
+ if (err) {
+ dev_err(dev, "%s eDMA probe failed\n",
+ pci_name(pdev));
+ return err;
+ }
+
+ pci_set_drvdata(pdev, chip);
+
+ dev_info(dev, "DesignWare eDMA PCIe driver loaded completely\n");
+
+ return 0;
+}
+
+static void dw_edma_pcie_remove(struct pci_dev *pdev)
+{
+ struct dw_edma_chip *chip = pci_get_drvdata(pdev);
+ struct device *dev = &pdev->dev;
+ int err;
+
+ err = dw_edma_remove(chip);
+ if (err) {
+ dev_warn(dev, "%s can't remove device properly: %d\n",
+ pci_name(pdev), err);
+ }
+
+ pci_free_irq_vectors(pdev);
+
+ dev_info(dev, "DesignWare eDMA PCIe driver unloaded completely\n");
+}
+
+#ifdef CONFIG_PM_SLEEP
+
+static int dw_edma_pcie_suspend_late(struct device *dev)
+{
+ struct pci_dev *pci = to_pci_dev(dev);
+ struct dw_edma_chip *chip = pci_get_drvdata(pci);
+
+ return dw_edma_disable(chip);
+};
+
+static int dw_edma_pcie_resume_early(struct device *dev)
+{
+ struct pci_dev *pci = to_pci_dev(dev);
+ struct dw_edma_chip *chip = pci_get_drvdata(pci);
+
+ return dw_edma_enable(chip);
+};
+
+#endif /* CONFIG_PM_SLEEP */
+
+static const struct dev_pm_ops dw_edma_pcie_dev_pm_ops = {
+ SET_LATE_SYSTEM_SLEEP_PM_OPS(dw_edma_pcie_suspend_late,
+ dw_edma_pcie_resume_early)
+};
+
+static const struct pci_device_id dw_edma_pcie_id_table[] = {
+ { PCI_DEVICE_DATA(SYNOPSYS, 0xedda, &snps_edda_data) },
+ { }
+};
+MODULE_DEVICE_TABLE(pci, dw_edma_pcie_id_table);
+
+static struct pci_driver dw_edma_pcie_driver = {
+ .name = DRV_PCIE_NAME,
+ .id_table = dw_edma_pcie_id_table,
+ .probe = dw_edma_pcie_probe,
+ .remove = dw_edma_pcie_remove,
+ .driver = {
+ .pm = &dw_edma_pcie_dev_pm_ops,
+ },
+};
+
+module_pci_driver(dw_edma_pcie_driver);
+
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("Synopsys DesignWare eDMA PCIe driver");
+MODULE_AUTHOR("Gustavo Pimentel <gustavo.pimentel@synopsys.com>");
^ permalink raw reply related
* [RFC,3/6] dma: Add Synopsys eDMA IP version 0 debugfs support
From: Gustavo Pimentel @ 2018-12-12 11:13 UTC (permalink / raw)
To: linux-pci, dmaengine
Cc: Gustavo Pimentel, Vinod Koul, Eugeniy Paltsev, Andy Shevchenko,
Joao Pinto
Add Synopsys eDMA IP version 0 debugfs support to assist any debug
in the future.
Creates a file system structure composed by folders and files that mimic
the IP register map (this files are read only) to ease any debug.
To enable this feature is necessary to select DEBUG_FS option on kernel
configuration.
Small output example:
(eDMA IP version 0, unroll, 1 write + 1 read channels)
% mount -t debugfs none /sys/kernel/debug/
% tree /sys/kernel/debug/dw-edma/
dw-edma/
├── mode
├── wr_ch_count
├── rd_ch_count
└── registers
├── ctrl_data_arb_prior
├── ctrl
├── write
│ ├── engine_en
│ ├── doorbell
│ ├── ch_arb_weight_low
│ ├── ch_arb_weight_high
│ ├── int_status
│ ├── int_mask
│ ├── int_clear
│ ├── err_status
│ ├── done_imwr_low
│ ├── done_imwr_high
│ ├── abort_imwr_low
│ ├── abort_imwr_high
│ ├── ch01_imwr_data
│ ├── ch23_imwr_data
│ ├── ch45_imwr_data
│ ├── ch67_imwr_data
│ ├── linked_list_err_en
│ ├── engine_chgroup
│ ├── engine_hshake_cnt_low
│ ├── engine_hshake_cnt_high
│ ├── ch0_pwr_en
│ ├── ch1_pwr_en
│ ├── ch2_pwr_en
│ ├── ch3_pwr_en
│ ├── ch4_pwr_en
│ ├── ch5_pwr_en
│ ├── ch6_pwr_en
│ ├── ch7_pwr_en
│ └── channel:0
│ ├── ch_control1
│ ├── ch_control2
│ ├── transfer_size
│ ├── sar_low
│ ├── sar_high
│ ├── dar_high
│ ├── llp_low
│ └── llp_high
└── read
├── engine_en
├── doorbell
├── ch_arb_weight_low
├── ch_arb_weight_high
├── int_status
├── int_mask
├── int_clear
├── err_status_low
├── err_status_high
├── done_imwr_low
├── done_imwr_high
├── abort_imwr_low
├── abort_imwr_high
├── ch01_imwr_data
├── ch23_imwr_data
├── ch45_imwr_data
├── ch67_imwr_data
├── linked_list_err_en
├── engine_chgroup
├── engine_hshake_cnt_low
├── engine_hshake_cnt_high
├── ch0_pwr_en
├── ch1_pwr_en
├── ch2_pwr_en
├── ch3_pwr_en
├── ch4_pwr_en
├── ch5_pwr_en
├── ch6_pwr_en
├── ch7_pwr_en
└── channel:0
├── ch_control1
├── ch_control2
├── transfer_size
├── sar_low
├── sar_high
├── dar_high
├── llp_low
└── llp_high
Signed-off-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
Cc: Vinod Koul <vkoul@kernel.org>
Cc: Eugeniy Paltsev <paltsev@synopsys.com>
Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: Joao Pinto <jpinto@synopsys.com>
---
drivers/dma/dw-edma/Makefile | 3 +-
drivers/dma/dw-edma/dw-edma-v0-core.c | 3 +-
drivers/dma/dw-edma/dw-edma-v0-debugfs.c | 359 +++++++++++++++++++++++++++++++
drivers/dma/dw-edma/dw-edma-v0-debugfs.h | 21 ++
4 files changed, 384 insertions(+), 2 deletions(-)
create mode 100644 drivers/dma/dw-edma/dw-edma-v0-debugfs.c
create mode 100644 drivers/dma/dw-edma/dw-edma-v0-debugfs.h
diff --git a/drivers/dma/dw-edma/Makefile b/drivers/dma/dw-edma/Makefile
index 01c7c63..0c53033 100644
--- a/drivers/dma/dw-edma/Makefile
+++ b/drivers/dma/dw-edma/Makefile
@@ -1,5 +1,6 @@
# SPDX-License-Identifier: GPL-2.0
obj-$(CONFIG_DW_EDMA) += dw-edma.o
+dw-edma-$(CONFIG_DEBUG_FS) := dw-edma-v0-debugfs.o
dw-edma-objs := dw-edma-core.o \
- dw-edma-v0-core.o
+ dw-edma-v0-core.o $(dw-edma-y)
diff --git a/drivers/dma/dw-edma/dw-edma-v0-core.c b/drivers/dma/dw-edma/dw-edma-v0-core.c
index cc362b0..945eddd 100644
--- a/drivers/dma/dw-edma/dw-edma-v0-core.c
+++ b/drivers/dma/dw-edma/dw-edma-v0-core.c
@@ -338,9 +338,10 @@ int dw_edma_v0_core_device_config(struct dma_chan *dchan)
// eDMA debug fs callbacks
int dw_edma_v0_core_debugfs_on(struct dw_edma_chip *chip)
{
- return 0;
+ return dw_edma_v0_debugfs_on(chip);
}
void dw_edma_v0_core_debugfs_off(void)
{
+ dw_edma_v0_debugfs_off();
}
diff --git a/drivers/dma/dw-edma/dw-edma-v0-debugfs.c b/drivers/dma/dw-edma/dw-edma-v0-debugfs.c
new file mode 100644
index 0000000..2d16911
--- /dev/null
+++ b/drivers/dma/dw-edma/dw-edma-v0-debugfs.c
@@ -0,0 +1,359 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018 Synopsys, Inc. and/or its affiliates.
+// Synopsys DesignWare eDMA v0 core
+
+#include <linux/debugfs.h>
+
+#include "dw-edma-v0-debugfs.h"
+#include "dw-edma-v0-regs.h"
+#include "dw-edma-core.h"
+
+#define DRV_V0_CORE_NAME "dw-edma-v0-core"
+
+#define RD_PERM 0444
+
+#define REGS_ADDR(name) \
+ (&(regs->name))
+#define REGISTER(name) \
+ { #name, REGS_ADDR(name) }
+
+#define WR_REGISTER(name) \
+ { #name, REGS_ADDR(wr_##name) }
+#define RD_REGISTER(name) \
+ { #name, REGS_ADDR(rd_##name) }
+
+#define WR_REGISTER_LEGACY(name) \
+ { #name, REGS_ADDR(type.legacy.wr_##name) }
+#define RD_REGISTER_LEGACY(name) \
+ { #name, REGS_ADDR(type.legacy.rd_##name) }
+
+#define WR_REGISTER_UNROLL(name) \
+ { #name, REGS_ADDR(type.unroll.wr_##name) }
+#define RD_REGISTER_UNROLL(name) \
+ { #name, REGS_ADDR(type.unroll.rd_##name) }
+
+#define WRITE_STR "write"
+#define READ_STR "read"
+#define CHANNEL_STR "channel"
+#define REGISTERS_STR "registers"
+
+static struct dentry *base_dir;
+static struct dw_edma *dw;
+static struct dw_edma_v0_regs *regs;
+
+static struct {
+ void *start;
+ void *end;
+} lim[2][EDMA_V0_MAX_NR_CH];
+
+struct debugfs_entries {
+ char name[24];
+ void __iomem *reg;
+};
+
+static int dw_edma_debugfs_u32_get(void *data, u64 *val)
+{
+ if (dw->mode == EDMA_MODE_LEGACY &&
+ data >= (void *)®s->type.legacy.ch) {
+ void *ptr = (void *)&(regs->type.legacy.ch);
+ u32 viewport_sel = 0;
+ unsigned long flags;
+ u16 ch;
+
+ for (ch = 0; ch < dw->wr_ch_count; ch++)
+ if (lim[0][ch].start >= data && data < lim[0][ch].end) {
+ ptr += (data - lim[0][ch].start);
+ goto legacy_sel_wr;
+ }
+
+ for (ch = 0; ch < dw->rd_ch_count; ch++)
+ if (lim[1][ch].start >= data && data < lim[1][ch].end) {
+ ptr += (data - lim[1][ch].start);
+ goto legacy_sel_rd;
+ }
+
+ return 0;
+legacy_sel_rd:
+ viewport_sel = BIT(31);
+legacy_sel_wr:
+ viewport_sel |= (ch & 0x00000007ul);
+
+ raw_spin_lock_irqsave(&dw->lock, flags);
+ *val = readl((u32 *) ptr);
+ raw_spin_unlock_irqrestore(&dw->lock, flags);
+ } else {
+ *val = readl((u32 *)data);
+ }
+
+ return 0;
+}
+DEFINE_DEBUGFS_ATTRIBUTE(fops_x32, dw_edma_debugfs_u32_get, NULL, "0x%08llx\n");
+
+static int dw_edma_debugfs_create_x32(const struct debugfs_entries entries[],
+ int nr_entries, struct dentry *dir)
+{
+ struct dentry *entry;
+ int i;
+
+ for (i = 0; i < nr_entries; i++) {
+ entry = debugfs_create_file_unsafe(entries[i].name, RD_PERM,
+ dir, entries[i].reg,
+ &fops_x32);
+ if (!entry)
+ return -EPERM;
+ }
+
+ return 0;
+}
+
+static int dw_edma_debugfs_regs_ch(struct dw_edma_v0_ch_regs *regs,
+ struct dentry *dir)
+{
+ int nr_entries;
+ const struct debugfs_entries debugfs_regs[] = {
+ REGISTER(ch_control1),
+ REGISTER(ch_control2),
+ REGISTER(transfer_size),
+ REGISTER(sar_low),
+ REGISTER(sar_high),
+ REGISTER(dar_low),
+ REGISTER(dar_high),
+ REGISTER(llp_low),
+ REGISTER(llp_high),
+ };
+
+ nr_entries = sizeof(debugfs_regs) / sizeof(struct debugfs_entries);
+ return dw_edma_debugfs_create_x32(debugfs_regs, nr_entries, dir);
+}
+
+static int dw_edma_debugfs_regs_wr(struct dentry *dir)
+{
+ struct dentry *regs_dir, *ch_dir;
+ int nr_entries, i, err;
+ char name[16];
+ const struct debugfs_entries debugfs_regs[] = {
+ // eDMA global registers
+ WR_REGISTER(engine_en),
+ WR_REGISTER(doorbell),
+ WR_REGISTER(ch_arb_weight_low),
+ WR_REGISTER(ch_arb_weight_high),
+ // eDMA interrupts registers
+ WR_REGISTER(int_status),
+ WR_REGISTER(int_mask),
+ WR_REGISTER(int_clear),
+ WR_REGISTER(err_status),
+ WR_REGISTER(done_imwr_low),
+ WR_REGISTER(done_imwr_high),
+ WR_REGISTER(abort_imwr_low),
+ WR_REGISTER(abort_imwr_high),
+ WR_REGISTER(ch01_imwr_data),
+ WR_REGISTER(ch23_imwr_data),
+ WR_REGISTER(ch45_imwr_data),
+ WR_REGISTER(ch67_imwr_data),
+ WR_REGISTER(linked_list_err_en),
+ };
+ const struct debugfs_entries debugfs_unroll_regs[] = {
+ // eDMA channel context grouping
+ WR_REGISTER_UNROLL(engine_chgroup),
+ WR_REGISTER_UNROLL(engine_hshake_cnt_low),
+ WR_REGISTER_UNROLL(engine_hshake_cnt_high),
+ WR_REGISTER_UNROLL(ch0_pwr_en),
+ WR_REGISTER_UNROLL(ch1_pwr_en),
+ WR_REGISTER_UNROLL(ch2_pwr_en),
+ WR_REGISTER_UNROLL(ch3_pwr_en),
+ WR_REGISTER_UNROLL(ch4_pwr_en),
+ WR_REGISTER_UNROLL(ch5_pwr_en),
+ WR_REGISTER_UNROLL(ch6_pwr_en),
+ WR_REGISTER_UNROLL(ch7_pwr_en),
+ };
+
+ regs_dir = debugfs_create_dir(WRITE_STR, dir);
+ if (!regs_dir)
+ return -EPERM;
+
+ nr_entries = sizeof(debugfs_regs) / sizeof(struct debugfs_entries);
+ err = dw_edma_debugfs_create_x32(debugfs_regs, nr_entries, regs_dir);
+ if (err)
+ return err;
+
+ if (dw->mode == EDMA_MODE_UNROLL) {
+ nr_entries = sizeof(debugfs_unroll_regs) /
+ sizeof(struct debugfs_entries);
+ err = dw_edma_debugfs_create_x32(debugfs_unroll_regs,
+ nr_entries, regs_dir);
+ if (err)
+ return err;
+ }
+
+ for (i = 0; i < dw->wr_ch_count; i++) {
+ snprintf(name, sizeof(name), "%s:%d", CHANNEL_STR, i);
+
+ ch_dir = debugfs_create_dir(name, regs_dir);
+ if (!ch_dir)
+ return -EPERM;
+
+ err = dw_edma_debugfs_regs_ch(&(regs->type.unroll.ch[i].wr),
+ ch_dir);
+ if (err)
+ return err;
+
+ lim[0][i].start = ®s->type.unroll.ch[i].wr;
+ lim[0][i].end = ®s->type.unroll.ch[i].padding_1[0];
+ }
+
+ return 0;
+}
+
+static int dw_edma_debugfs_regs_rd(struct dentry *dir)
+{
+ struct dentry *regs_dir, *ch_dir;
+ int nr_entries, i, err;
+ char name[16];
+ const struct debugfs_entries debugfs_regs[] = {
+ // eDMA global registers
+ RD_REGISTER(engine_en),
+ RD_REGISTER(doorbell),
+ RD_REGISTER(ch_arb_weight_low),
+ RD_REGISTER(ch_arb_weight_high),
+ // eDMA interrupts registers
+ RD_REGISTER(int_status),
+ RD_REGISTER(int_mask),
+ RD_REGISTER(int_clear),
+ RD_REGISTER(err_status_low),
+ RD_REGISTER(err_status_high),
+ RD_REGISTER(linked_list_err_en),
+ RD_REGISTER(done_imwr_low),
+ RD_REGISTER(done_imwr_high),
+ RD_REGISTER(abort_imwr_low),
+ RD_REGISTER(abort_imwr_high),
+ RD_REGISTER(ch01_imwr_data),
+ RD_REGISTER(ch23_imwr_data),
+ RD_REGISTER(ch45_imwr_data),
+ RD_REGISTER(ch67_imwr_data),
+ };
+ const struct debugfs_entries debugfs_unroll_regs[] = {
+ // eDMA channel context grouping
+ RD_REGISTER_UNROLL(engine_chgroup),
+ RD_REGISTER_UNROLL(engine_hshake_cnt_low),
+ RD_REGISTER_UNROLL(engine_hshake_cnt_high),
+ RD_REGISTER_UNROLL(ch0_pwr_en),
+ RD_REGISTER_UNROLL(ch1_pwr_en),
+ RD_REGISTER_UNROLL(ch2_pwr_en),
+ RD_REGISTER_UNROLL(ch3_pwr_en),
+ RD_REGISTER_UNROLL(ch4_pwr_en),
+ RD_REGISTER_UNROLL(ch5_pwr_en),
+ RD_REGISTER_UNROLL(ch6_pwr_en),
+ RD_REGISTER_UNROLL(ch7_pwr_en),
+ };
+
+ regs_dir = debugfs_create_dir(READ_STR, dir);
+ if (!regs_dir)
+ return -EPERM;
+
+ nr_entries = sizeof(debugfs_regs) / sizeof(struct debugfs_entries);
+ err = dw_edma_debugfs_create_x32(debugfs_regs, nr_entries, regs_dir);
+ if (err)
+ return err;
+
+ if (dw->mode == EDMA_MODE_UNROLL) {
+ nr_entries = sizeof(debugfs_unroll_regs) /
+ sizeof(struct debugfs_entries);
+ err = dw_edma_debugfs_create_x32(debugfs_unroll_regs,
+ nr_entries, regs_dir);
+ if (err)
+ return err;
+ }
+
+ for (i = 0; i < dw->rd_ch_count; i++) {
+ snprintf(name, sizeof(name), "%s:%d", CHANNEL_STR, i);
+
+ ch_dir = debugfs_create_dir(name, regs_dir);
+ if (!ch_dir)
+ return -EPERM;
+
+ err = dw_edma_debugfs_regs_ch(&(regs->type.unroll.ch[i].rd),
+ ch_dir);
+ if (err)
+ return err;
+
+ lim[1][i].start = ®s->type.unroll.ch[i].rd;
+ lim[1][i].end = ®s->type.unroll.ch[i].padding_2[0];
+ }
+
+ return 0;
+}
+
+static int dw_edma_debugfs_regs(void)
+{
+ struct dentry *regs_dir;
+ int nr_entries, err;
+ const struct debugfs_entries debugfs_regs[] = {
+ REGISTER(ctrl_data_arb_prior),
+ REGISTER(ctrl),
+ };
+
+ regs_dir = debugfs_create_dir(REGISTERS_STR, base_dir);
+ if (!regs_dir)
+ return -EPERM;
+
+ nr_entries = sizeof(debugfs_regs) / sizeof(struct debugfs_entries);
+ err = dw_edma_debugfs_create_x32(debugfs_regs, nr_entries, regs_dir);
+ if (err)
+ return err;
+
+ err = dw_edma_debugfs_regs_wr(regs_dir);
+ if (err)
+ return err;
+
+ err = dw_edma_debugfs_regs_rd(regs_dir);
+ if (err)
+ return err;
+
+ return 0;
+}
+
+int dw_edma_v0_debugfs_on(struct dw_edma_chip *chip)
+{
+ struct dentry *entry;
+ int err;
+
+ dw = chip->dw;
+ if (!dw)
+ return -EPERM;
+
+ regs = (struct dw_edma_v0_regs *) dw->regs;
+ if (!regs)
+ return -EPERM;
+
+ base_dir = debugfs_create_dir(DRV_NAME, 0);
+ if (!base_dir)
+ return -EPERM;
+
+ entry = debugfs_create_u32("version", RD_PERM, base_dir,
+ &(dw->version));
+ if (!entry)
+ return -EPERM;
+
+ entry = debugfs_create_u32("mode", RD_PERM, base_dir,
+ &(dw->mode));
+ if (!entry)
+ return -EPERM;
+
+ entry = debugfs_create_u16("wr_ch_count", RD_PERM, base_dir,
+ &(dw->wr_ch_count));
+ if (!entry)
+ return -EPERM;
+
+ entry = debugfs_create_u16("rd_ch_count", RD_PERM, base_dir,
+ &(dw->rd_ch_count));
+ if (!entry)
+ return -EPERM;
+
+ err = dw_edma_debugfs_regs();
+ return err;
+}
+
+void dw_edma_v0_debugfs_off(void)
+{
+ debugfs_remove_recursive(base_dir);
+}
diff --git a/drivers/dma/dw-edma/dw-edma-v0-debugfs.h b/drivers/dma/dw-edma/dw-edma-v0-debugfs.h
new file mode 100644
index 0000000..702e454
--- /dev/null
+++ b/drivers/dma/dw-edma/dw-edma-v0-debugfs.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+// Copyright (c) 2018 Synopsys, Inc. and/or its affiliates.
+// Synopsys DesignWare eDMA v0 core
+
+#ifndef _DW_EDMA_V0_DEBUG_FS_H
+#define _DW_EDMA_V0_DEBUG_FS_H
+
+#include <linux/dma/edma.h>
+
+#ifdef CONFIG_DEBUG_FS
+int dw_edma_v0_debugfs_on(struct dw_edma_chip *chip);
+void dw_edma_v0_debugfs_off(void);
+#else
+static inline int dw_edma_v0_debugfs_on(struct dw_edma_chip *chip);
+{
+ return 0;
+}
+static inline void dw_edma_v0_debugfs_off(void);
+#endif /* CONFIG_DEBUG_FS */
+
+#endif /* _DW_EDMA_V0_DEBUG_FS_H */
^ permalink raw reply related
* [RFC,2/6] dma: Add Synopsys eDMA IP version 0 support
From: Gustavo Pimentel @ 2018-12-12 11:13 UTC (permalink / raw)
To: linux-pci, dmaengine
Cc: Gustavo Pimentel, Vinod Koul, Eugeniy Paltsev, Andy Shevchenko,
Joao Pinto
Add support for the eDMA IP version 0 driver for both register maps (legacy
and unroll).
The legacy register mapping was the initial implementation, which consisted
in having all registers belonging to channels multiplexed, which could be
change anytime (which could led a race-condition) by view port register
(access to only one channel available each time).
This register mapping is not very effective and efficient in a multithread
environment, which has led to the development of unroll registers mapping,
which consists of having all channels registers accessible any time by
spreading all channels registers by an offset between them.
This version supports a maximum of 16 independent channels (8 write +
8 read), which can run simultaneously.
Implements a scatter-gather transfer through a linked list, where the size
of linked list depends on the allocated memory divided equally among all
channels.
Each linked list descriptor can transfer from 1 byte to 4 Gbytes and is
alignmented to DWORD.
Both SAR (Source Address Register) and DAR (Destination Address Register)
are alignmented to byte.
Signed-off-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
Cc: Vinod Koul <vkoul@kernel.org>
Cc: Eugeniy Paltsev <paltsev@synopsys.com>
Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: Joao Pinto <jpinto@synopsys.com>
---
drivers/dma/dw-edma/Makefile | 3 +-
drivers/dma/dw-edma/dw-edma-core.c | 20 ++
drivers/dma/dw-edma/dw-edma-v0-core.c | 346 ++++++++++++++++++++++++++++++++++
drivers/dma/dw-edma/dw-edma-v0-core.h | 24 +++
drivers/dma/dw-edma/dw-edma-v0-regs.h | 143 ++++++++++++++
5 files changed, 535 insertions(+), 1 deletion(-)
create mode 100644 drivers/dma/dw-edma/dw-edma-v0-core.c
create mode 100644 drivers/dma/dw-edma/dw-edma-v0-core.h
create mode 100644 drivers/dma/dw-edma/dw-edma-v0-regs.h
diff --git a/drivers/dma/dw-edma/Makefile b/drivers/dma/dw-edma/Makefile
index 3224010..01c7c63 100644
--- a/drivers/dma/dw-edma/Makefile
+++ b/drivers/dma/dw-edma/Makefile
@@ -1,4 +1,5 @@
# SPDX-License-Identifier: GPL-2.0
obj-$(CONFIG_DW_EDMA) += dw-edma.o
-dw-edma-objs := dw-edma-core.o
+dw-edma-objs := dw-edma-core.o \
+ dw-edma-v0-core.o
diff --git a/drivers/dma/dw-edma/dw-edma-core.c b/drivers/dma/dw-edma/dw-edma-core.c
index b4c2982..c08125a 100644
--- a/drivers/dma/dw-edma/dw-edma-core.c
+++ b/drivers/dma/dw-edma/dw-edma-core.c
@@ -12,6 +12,7 @@
#include <linux/dma/edma.h>
#include "dw-edma-core.h"
+#include "dw-edma-v0-core.h"
#include "../dmaengine.h"
#include "../virt-dma.h"
@@ -26,6 +27,22 @@
SET(dw->rd_edma, name, value); \
} while (0)
+static const struct dw_edma_core_ops dw_edma_v0_core_ops = {
+ // eDMA management callbacks
+ .off = dw_edma_v0_core_off,
+ .ch_count = dw_edma_v0_core_ch_count,
+ .ch_status = dw_edma_v0_core_ch_status,
+ .clear_done_int = dw_edma_v0_core_clear_done_int,
+ .clear_abort_int = dw_edma_v0_core_clear_abort_int,
+ .status_done_int = dw_edma_v0_core_status_done_int,
+ .status_abort_int = dw_edma_v0_core_status_abort_int,
+ .start = dw_edma_v0_core_start,
+ .device_config = dw_edma_v0_core_device_config,
+ // eDMA debug fs callbacks
+ .debugfs_on = dw_edma_v0_core_debugfs_on,
+ .debugfs_off = dw_edma_v0_core_debugfs_off,
+};
+
static inline
struct device *dchan2dev(struct dma_chan *dchan)
{
@@ -740,6 +757,9 @@ int dw_edma_probe(struct dw_edma_chip *chip)
raw_spin_lock_init(&dw->lock);
switch (dw->version) {
+ case 0:
+ dw->ops = ops = &dw_edma_v0_core_ops;
+ break;
default:
dev_err(chip->dev, ": unsupported version\n");
return -EPERM;
diff --git a/drivers/dma/dw-edma/dw-edma-v0-core.c b/drivers/dma/dw-edma/dw-edma-v0-core.c
new file mode 100644
index 0000000..cc362b0
--- /dev/null
+++ b/drivers/dma/dw-edma/dw-edma-v0-core.c
@@ -0,0 +1,346 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018 Synopsys, Inc. and/or its affiliates.
+// Synopsys DesignWare eDMA v0 core
+
+#include "dw-edma-core.h"
+#include "dw-edma-v0-core.h"
+#include "dw-edma-v0-regs.h"
+#include "dw-edma-v0-debugfs.h"
+
+#define QWORD_HI(value) ((value & 0xFFFFFFFF00000000llu) >> 32)
+#define QWORD_LO(value) (value & 0x00000000FFFFFFFFllu)
+
+enum dw_edma_control {
+ DW_EDMA_CB = BIT(0),
+ DW_EDMA_TCB = BIT(1),
+ DW_EDMA_LLP = BIT(2),
+ DW_EDMA_LIE = BIT(3),
+ DW_EDMA_RIE = BIT(4),
+ DW_EDMA_CCS = BIT(8),
+ DW_EDMA_LLE = BIT(9),
+};
+
+static inline struct dw_edma_v0_regs __iomem *__dw_regs(struct dw_edma *dw)
+{
+ return dw->regs;
+}
+#define SET(dw, name, value) \
+ writel(value, &(__dw_regs(dw)->name))
+
+#define GET(dw, name) \
+ readl(&(__dw_regs(dw)->name))
+
+#define SET_RW(dw, dir, name, value) \
+ do { \
+ if (dir == EDMA_DIR_WRITE) \
+ SET(dw, wr_##name, value); \
+ else \
+ SET(dw, rd_##name, value); \
+ } while (0)
+
+#define GET_RW(dw, dir, name) \
+ (dir == EDMA_DIR_WRITE \
+ ? GET(dw, wr_##name) \
+ : GET(dw, rd_##name))
+
+#define SET_BOTH(dw, name, value) \
+ do { \
+ SET(dw, wr_##name, value); \
+ SET(dw, rd_##name, value); \
+ } while (0)
+
+static inline struct dw_edma_v0_ch_regs __iomem *
+__dw_ch_regs(struct dw_edma *dw, enum dw_edma_dir dir, u16 ch)
+{
+ if (dw->mode == EDMA_MODE_LEGACY)
+ return &(__dw_regs(dw)->type.legacy.ch);
+
+ if (dir == EDMA_DIR_WRITE)
+ return &__dw_regs(dw)->type.unroll.ch[ch].wr;
+
+ return &__dw_regs(dw)->type.unroll.ch[ch].rd;
+}
+
+static inline void writel_ch(struct dw_edma *dw, enum dw_edma_dir dir, u16 ch,
+ u32 value, void __iomem *addr)
+{
+ if (dw->mode == EDMA_MODE_LEGACY) {
+ u32 viewport_sel;
+ unsigned long flags;
+
+ raw_spin_lock_irqsave(&dw->lock, flags);
+
+ viewport_sel = (ch & 0x00000007ul);
+ if (dir == EDMA_DIR_READ)
+ viewport_sel |= BIT(31);
+
+ writel(viewport_sel,
+ &(__dw_regs(dw)->type.legacy.viewport_sel));
+ writel(value, addr);
+
+ raw_spin_unlock_irqrestore(&dw->lock, flags);
+ } else {
+ writel(value, addr);
+ }
+}
+
+static inline u32 readl_ch(struct dw_edma *dw, enum dw_edma_dir dir, u16 ch,
+ const void __iomem *addr)
+{
+ u32 value;
+
+ if (dw->mode == EDMA_MODE_LEGACY) {
+ u32 viewport_sel;
+ unsigned long flags;
+
+ raw_spin_lock_irqsave(&dw->lock, flags);
+
+ viewport_sel = (ch & 0x00000007ul);
+ if (dir == EDMA_DIR_READ)
+ viewport_sel |= BIT(31);
+
+ writel(viewport_sel,
+ &(__dw_regs(dw)->type.legacy.viewport_sel));
+ value = readl(addr);
+
+ raw_spin_unlock_irqrestore(&dw->lock, flags);
+ } else {
+ value = readl(addr);
+ }
+
+ return value;
+}
+#define SET_CH(dw, dir, ch, name, value) \
+ writel_ch(dw, dir, ch, value, &(__dw_ch_regs(dw, dir, ch)->name))
+
+#define GET_CH(dw, dir, ch, name) \
+ readl_ch(dw, dir, ch, &(__dw_ch_regs(dw, dir, ch)->name))
+
+#define SET_LL(ll, value) \
+ writel(value, ll)
+
+// eDMA management callbacks
+void dw_edma_v0_core_off(struct dw_edma *dw)
+{
+ SET_BOTH(dw, int_mask, 0x00FF00FFul);
+ SET_BOTH(dw, int_clear, 0x00FF00FFul);
+ SET_BOTH(dw, engine_en, 0x00000000ul);
+}
+
+u16 dw_edma_v0_core_ch_count(struct dw_edma *dw, enum dw_edma_dir dir)
+{
+ u32 num_ch = GET(dw, ctrl);
+
+ if (dir == EDMA_DIR_WRITE) {
+ num_ch &= 0x0000000Ful;
+ } else {
+ num_ch &= 0x000F0000ul;
+ num_ch >>= 16;
+ }
+
+ if (num_ch > EDMA_V0_MAX_NR_CH)
+ num_ch = EDMA_V0_MAX_NR_CH;
+
+ return (u16)num_ch;
+}
+
+enum dma_status dw_edma_v0_core_ch_status(struct dw_edma_chan *chan)
+{
+ struct dw_edma *dw = chan->chip->dw;
+ u32 tmp = GET_CH(dw, chan->dir, chan->id, ch_control1);
+
+ tmp &= 0x00000060ul;
+ tmp >>= 5;
+ if (tmp == 1)
+ return DMA_IN_PROGRESS;
+ else if (tmp == 3)
+ return DMA_COMPLETE;
+ else
+ return DMA_ERROR;
+}
+
+void dw_edma_v0_core_clear_done_int(struct dw_edma_chan *chan)
+{
+ struct dw_edma *dw = chan->chip->dw;
+
+ SET_RW(dw, chan->dir, int_clear, BIT(chan->id));
+}
+
+void dw_edma_v0_core_clear_abort_int(struct dw_edma_chan *chan)
+{
+ struct dw_edma *dw = chan->chip->dw;
+
+ SET_RW(dw, chan->dir, int_clear, BIT(chan->id + 16));
+}
+
+bool dw_edma_v0_core_status_done_int(struct dw_edma_chan *chan)
+{
+ struct dw_edma *dw = chan->chip->dw;
+ u32 tmp;
+
+ tmp = GET_RW(dw, chan->dir, int_status);
+ tmp &= BIT(chan->id);
+
+ return tmp ? true : false;
+}
+
+bool dw_edma_v0_core_status_abort_int(struct dw_edma_chan *chan)
+{
+ struct dw_edma *dw = chan->chip->dw;
+ u32 tmp;
+
+ tmp = GET_RW(dw, chan->dir, int_status);
+ tmp &= BIT(chan->id + 16);
+
+ return tmp ? true : false;
+}
+
+static void dw_edma_v0_core_write_chunk(struct dw_edma_chunk *chunk)
+{
+ struct dw_edma_burst *child;
+ struct dw_edma_v0_lli *lli;
+ struct dw_edma_v0_llp *llp;
+ u32 control = 0, i = 0, j;
+ u64 sar, dar, addr;
+
+ lli = (struct dw_edma_v0_lli *) chunk->v_addr;
+
+ if (chunk->cb)
+ control = DW_EDMA_CB;
+
+ j = atomic_read(&chunk->bursts_alloc);
+ list_for_each_entry(child, &chunk->burst->list, list) {
+ j--;
+ if (!j)
+ control |= (DW_EDMA_LIE | DW_EDMA_RIE);
+
+ // Channel control
+ SET_LL(&(lli[i].control), control);
+ // Transfer size
+ SET_LL(&(lli[i].transfer_size), child->sz);
+ // SAR - low, high
+ sar = cpu_to_le64(child->sar);
+ SET_LL(&(lli[i].sar_low), QWORD_LO(sar));
+ SET_LL(&(lli[i].sar_high), QWORD_HI(sar));
+ // DAR - low, high
+ dar = cpu_to_le64(child->dar);
+ SET_LL(&(lli[i].dar_low), QWORD_LO(dar));
+ SET_LL(&(lli[i].dar_high), QWORD_HI(dar));
+
+ i++;
+ }
+
+ llp = (struct dw_edma_v0_llp *) &(lli[i]);
+ control = DW_EDMA_LLP | DW_EDMA_TCB;
+ if (!chunk->cb)
+ control |= DW_EDMA_CB;
+
+ // Channel control
+ SET_LL(&(llp->control), control);
+ // Linked list - low, high
+ addr = cpu_to_le64(chunk->p_addr);
+ SET_LL(&(llp->llp_low), QWORD_LO(addr));
+ SET_LL(&(llp->llp_high), QWORD_HI(addr));
+}
+
+void dw_edma_v0_core_start(struct dw_edma_chunk *chunk, bool first)
+{
+ struct dw_edma_chan *chan = chunk->chan;
+ struct dw_edma *dw = chan->chip->dw;
+ u32 mask;
+ u64 llp;
+
+ dw_edma_v0_core_write_chunk(chunk);
+
+ if (first) {
+ // Enable engine
+ SET_RW(dw, chan->dir, engine_en, 0x00000001ul);
+ // Interrupt unmask - done, abort
+ mask = GET_RW(dw, chan->dir, int_mask);
+ mask &= ~(BIT(chan->id + 16) | BIT(chan->id));
+ SET_RW(dw, chan->dir, int_mask, mask);
+ // Linked list error
+ SET_RW(dw, chan->dir, linked_list_err_en, BIT(chan->id));
+ // Channel control
+ SET_CH(dw, chan->dir, chan->id, ch_control1,
+ DW_EDMA_CCS | DW_EDMA_LLE);
+ // Linked list - low, high
+ llp = cpu_to_le64(chunk->p_addr);
+ SET_CH(dw, chan->dir, chan->id, llp_low, QWORD_LO(llp));
+ SET_CH(dw, chan->dir, chan->id, llp_high, QWORD_HI(llp));
+ }
+ // Doorbell
+ SET_RW(dw, chan->dir, doorbell, chan->id & 0x00000007ul);
+}
+
+int dw_edma_v0_core_device_config(struct dma_chan *dchan)
+{
+ struct dw_edma_chan *chan = dchan2dw_edma_chan(dchan);
+ struct dw_edma *dw = chan->chip->dw;
+ u32 tmp;
+
+ // MSI done addr - low, high
+ SET_RW(dw, chan->dir, done_imwr_low, QWORD_LO(chan->msi_done_addr));
+ SET_RW(dw, chan->dir, done_imwr_high, QWORD_HI(chan->msi_done_addr));
+ // MSI abort addr - low, high
+ SET_RW(dw, chan->dir, abort_imwr_low, QWORD_LO(chan->msi_abort_addr));
+ SET_RW(dw, chan->dir, abort_imwr_high, QWORD_HI(chan->msi_abort_addr));
+ // MSI data - low, high
+ switch (chan->id) {
+ case 0:
+ case 1:
+ tmp = GET_RW(dw, chan->dir, ch01_imwr_data);
+ break;
+ case 2:
+ case 3:
+ tmp = GET_RW(dw, chan->dir, ch23_imwr_data);
+ break;
+ case 4:
+ case 5:
+ tmp = GET_RW(dw, chan->dir, ch45_imwr_data);
+ break;
+ case 6:
+ case 7:
+ tmp = GET_RW(dw, chan->dir, ch67_imwr_data);
+ break;
+ }
+
+ if (chan->id & 0x00000001ul) {
+ tmp &= 0x00FFu;
+ tmp |= ((u32)chan->msi_data << 16);
+ } else {
+ tmp &= 0xFF00u;
+ tmp |= chan->msi_data;
+ }
+
+ switch (chan->id) {
+ case 0:
+ case 1:
+ SET_RW(dw, chan->dir, ch01_imwr_data, tmp);
+ break;
+ case 2:
+ case 3:
+ SET_RW(dw, chan->dir, ch23_imwr_data, tmp);
+ break;
+ case 4:
+ case 5:
+ SET_RW(dw, chan->dir, ch45_imwr_data, tmp);
+ break;
+ case 6:
+ case 7:
+ SET_RW(dw, chan->dir, ch67_imwr_data, tmp);
+ break;
+ }
+
+ return 0;
+}
+
+// eDMA debug fs callbacks
+int dw_edma_v0_core_debugfs_on(struct dw_edma_chip *chip)
+{
+ return 0;
+}
+
+void dw_edma_v0_core_debugfs_off(void)
+{
+}
diff --git a/drivers/dma/dw-edma/dw-edma-v0-core.h b/drivers/dma/dw-edma/dw-edma-v0-core.h
new file mode 100644
index 0000000..e698e27
--- /dev/null
+++ b/drivers/dma/dw-edma/dw-edma-v0-core.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+//Copyright (c) 2018 Synopsys, Inc. and/or its affiliates.
+//Synopsys DesignWare eDMA v0 core
+
+#ifndef _DW_EDMA_V0_CORE_H
+#define _DW_EDMA_V0_CORE_H
+
+#include <linux/dma/edma.h>
+
+// eDMA management callbacks
+void dw_edma_v0_core_off(struct dw_edma *chan);
+u16 dw_edma_v0_core_ch_count(struct dw_edma *chan, enum dw_edma_dir dir);
+enum dma_status dw_edma_v0_core_ch_status(struct dw_edma_chan *chan);
+void dw_edma_v0_core_clear_done_int(struct dw_edma_chan *chan);
+void dw_edma_v0_core_clear_abort_int(struct dw_edma_chan *chan);
+bool dw_edma_v0_core_status_done_int(struct dw_edma_chan *chan);
+bool dw_edma_v0_core_status_abort_int(struct dw_edma_chan *chan);
+void dw_edma_v0_core_start(struct dw_edma_chunk *chunk, bool first);
+int dw_edma_v0_core_device_config(struct dma_chan *dchan);
+// eDMA debug fs callbacks
+int dw_edma_v0_core_debugfs_on(struct dw_edma_chip *chip);
+void dw_edma_v0_core_debugfs_off(void);
+
+#endif /* _DW_EDMA_V0_CORE_H */
diff --git a/drivers/dma/dw-edma/dw-edma-v0-regs.h b/drivers/dma/dw-edma/dw-edma-v0-regs.h
new file mode 100644
index 0000000..564b2e0
--- /dev/null
+++ b/drivers/dma/dw-edma/dw-edma-v0-regs.h
@@ -0,0 +1,143 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+// Copyright (c) 2018 Synopsys, Inc. and/or its affiliates.
+// Synopsys DesignWare eDMA v0 core
+
+#ifndef _DW_EDMA_V0_REGS_H
+#define _DW_EDMA_V0_REGS_H
+
+#include <linux/dmaengine.h>
+
+#define EDMA_V0_MAX_NR_CH 8
+
+struct dw_edma_v0_ch_regs {
+ u32 ch_control1; // B + 0x000
+ u32 ch_control2; // B + 0x004
+ u32 transfer_size; // B + 0x008
+ u32 sar_low; // B + 0x00c
+ u32 sar_high; // B + 0x010
+ u32 dar_low; // B + 0x014
+ u32 dar_high; // B + 0x018
+ u32 llp_low; // B + 0x01c
+ u32 llp_high; // B + 0x020
+};
+
+struct dw_edma_v0_ch {
+ struct dw_edma_v0_ch_regs wr; // B + 0x200
+ u32 padding_1[55]; // B + [0x224..0x2fc]
+ struct dw_edma_v0_ch_regs rd; // B + 0x300
+ u32 padding_2[55]; // B + [0x224..0x2fc]
+};
+
+struct dw_edma_v0_unroll {
+ u32 padding_1; // B + 0x0f8
+ u32 wr_engine_chgroup; // B + 0x100
+ u32 rd_engine_chgroup; // B + 0x104
+ u32 wr_engine_hshake_cnt_low; // B + 0x108
+ u32 wr_engine_hshake_cnt_high; // B + 0x10c
+ u32 padding_2[2]; // B + [0x110..0x114]
+ u32 rd_engine_hshake_cnt_low; // B + 0x118
+ u32 rd_engine_hshake_cnt_high; // B + 0x11c
+ u32 padding_3[2]; // B + [0x120..0x124]
+ u32 wr_ch0_pwr_en; // B + 0x128
+ u32 wr_ch1_pwr_en; // B + 0x12c
+ u32 wr_ch2_pwr_en; // B + 0x130
+ u32 wr_ch3_pwr_en; // B + 0x134
+ u32 wr_ch4_pwr_en; // B + 0x138
+ u32 wr_ch5_pwr_en; // B + 0x13c
+ u32 wr_ch6_pwr_en; // B + 0x140
+ u32 wr_ch7_pwr_en; // B + 0x144
+ u32 padding_4[8]; // B + [0x148..0x164]
+ u32 rd_ch0_pwr_en; // B + 0x168
+ u32 rd_ch1_pwr_en; // B + 0x16c
+ u32 rd_ch2_pwr_en; // B + 0x170
+ u32 rd_ch3_pwr_en; // B + 0x174
+ u32 rd_ch4_pwr_en; // B + 0x178
+ u32 rd_ch5_pwr_en; // B + 0x18c
+ u32 rd_ch6_pwr_en; // B + 0x180
+ u32 rd_ch7_pwr_en; // B + 0x184
+ u32 padding_5[30]; // B + [0x188..0x1fc]
+ struct dw_edma_v0_ch ch[EDMA_V0_MAX_NR_CH]; // B + i*0x400
+};
+
+struct dw_edma_v0_legacy {
+ u32 viewport_sel; // B + 0x0f8
+ struct dw_edma_v0_ch_regs ch; // B + [0x100..0x120]
+};
+
+struct dw_edma_v0_regs {
+ // eDMA global registers
+ u32 ctrl_data_arb_prior; // B + 0x000
+ u32 padding_1; // B + 0x004
+ u32 ctrl; // B + 0x008
+ u32 wr_engine_en; // B + 0x00c
+ u32 wr_doorbell; // B + 0x010
+ u32 padding_2; // B + 0x014
+ u32 wr_ch_arb_weight_low; // B + 0x018
+ u32 wr_ch_arb_weight_high; // B + 0x01c
+ u32 padding_3[3]; // B + [0x020..0x028]
+ u32 rd_engine_en; // B + 0x02c
+ u32 rd_doorbell; // B + 0x030
+ u32 padding_4; // B + 0x034
+ u32 rd_ch_arb_weight_low; // B + 0x038
+ u32 rd_ch_arb_weight_high; // B + 0x03c
+ u32 padding_5[3]; // B + [0x040..0x048]
+ // eDMA interrupts registers
+ u32 wr_int_status; // B + 0x04c
+ u32 padding_6; // B + 0x050
+ u32 wr_int_mask; // B + 0x054
+ u32 wr_int_clear; // B + 0x058
+ u32 wr_err_status; // B + 0x05c
+ u32 wr_done_imwr_low; // B + 0x060
+ u32 wr_done_imwr_high; // B + 0x064
+ u32 wr_abort_imwr_low; // B + 0x068
+ u32 wr_abort_imwr_high; // B + 0x06c
+ u32 wr_ch01_imwr_data; // B + 0x070
+ u32 wr_ch23_imwr_data; // B + 0x074
+ u32 wr_ch45_imwr_data; // B + 0x078
+ u32 wr_ch67_imwr_data; // B + 0x07c
+ u32 padding_7[4]; // B + [0x080..0x08c]
+ u32 wr_linked_list_err_en; // B + 0x090
+ u32 padding_8[3]; // B + [0x094..0x09c]
+ u32 rd_int_status; // B + 0x0a0
+ u32 padding_9; // B + 0x0a4
+ u32 rd_int_mask; // B + 0x0a8
+ u32 rd_int_clear; // B + 0x0ac
+ u32 padding_10; // B + 0x0b0
+ u32 rd_err_status_low; // B + 0x0b4
+ u32 rd_err_status_high; // B + 0x0b8
+ u32 padding_11[2]; // B + [0x0bc..0x0c0]
+ u32 rd_linked_list_err_en; // B + 0x0c4
+ u32 padding_12; // B + 0x0c8
+ u32 rd_done_imwr_low; // B + 0x0cc
+ u32 rd_done_imwr_high; // B + 0x0d0
+ u32 rd_abort_imwr_low; // B + 0x0d4
+ u32 rd_abort_imwr_high; // B + 0x0d8
+ u32 rd_ch01_imwr_data; // B + 0x0dc
+ u32 rd_ch23_imwr_data; // B + 0x0e0
+ u32 rd_ch45_imwr_data; // B + 0x0e4
+ u32 rd_ch67_imwr_data; // B + 0x0e8
+ u32 padding_13[4]; // B + [0x0ec..0x0f8]
+ // eDMA channel context grouping
+ union Type {
+ struct dw_edma_v0_legacy legacy; // B + [0x0f8..0x120]
+ struct dw_edma_v0_unroll unroll; // B + [0x0f8..0x1120]
+ } type;
+};
+
+struct dw_edma_v0_lli {
+ u32 control;
+ u32 transfer_size;
+ u32 sar_low;
+ u32 sar_high;
+ u32 dar_low;
+ u32 dar_high;
+};
+
+struct dw_edma_v0_llp {
+ u32 control;
+ u32 reserved;
+ u32 llp_low;
+ u32 llp_high;
+};
+
+#endif /* _DW_EDMA_V0_REGS_H */
^ permalink raw reply related
* [RFC,1/6] dma: Add Synopsys eDMA IP core driver
From: Gustavo Pimentel @ 2018-12-12 11:13 UTC (permalink / raw)
To: linux-pci, dmaengine
Cc: Gustavo Pimentel, Vinod Koul, Eugeniy Paltsev, Andy Shevchenko,
Joao Pinto
Add Synopsys eDMA IP core driver to kernel.
This core driver, initializes and configures the eDMA IP using vma-helpers
functions and dma-engine subsystem.
Also creates an abstration layer through callbacks allowing different
registers mappings in the future, organized in to versions.
This driver can be compile as built-in or external module in kernel.
To enable this driver just select DW_EDMA option in kernel configuration,
however it requires and selects automatically DMA_ENGINE and
DMA_VIRTUAL_CHANNELS option too.
Signed-off-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
Cc: Vinod Koul <vkoul@kernel.org>
Cc: Eugeniy Paltsev <paltsev@synopsys.com>
Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: Joao Pinto <jpinto@synopsys.com>
---
drivers/dma/Kconfig | 2 +
drivers/dma/Makefile | 1 +
drivers/dma/dw-edma/Kconfig | 9 +
drivers/dma/dw-edma/Makefile | 4 +
drivers/dma/dw-edma/dw-edma-core.c | 925 +++++++++++++++++++++++++++++++++++++
drivers/dma/dw-edma/dw-edma-core.h | 145 ++++++
include/linux/dma/edma.h | 42 ++
7 files changed, 1128 insertions(+)
create mode 100644 drivers/dma/dw-edma/Kconfig
create mode 100644 drivers/dma/dw-edma/Makefile
create mode 100644 drivers/dma/dw-edma/dw-edma-core.c
create mode 100644 drivers/dma/dw-edma/dw-edma-core.h
create mode 100644 include/linux/dma/edma.h
diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index de511db..40517f8 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -640,6 +640,8 @@ source "drivers/dma/qcom/Kconfig"
source "drivers/dma/dw/Kconfig"
+source "drivers/dma/dw-edma/Kconfig"
+
source "drivers/dma/hsu/Kconfig"
source "drivers/dma/sh/Kconfig"
diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
index 7fcc4d8..3ebfab0 100644
--- a/drivers/dma/Makefile
+++ b/drivers/dma/Makefile
@@ -29,6 +29,7 @@ obj-$(CONFIG_DMA_SUN4I) += sun4i-dma.o
obj-$(CONFIG_DMA_SUN6I) += sun6i-dma.o
obj-$(CONFIG_DW_AXI_DMAC) += dw-axi-dmac/
obj-$(CONFIG_DW_DMAC_CORE) += dw/
+obj-$(CONFIG_DW_EDMA) += dw-edma/
obj-$(CONFIG_EP93XX_DMA) += ep93xx_dma.o
obj-$(CONFIG_FSL_DMA) += fsldma.o
obj-$(CONFIG_FSL_EDMA) += fsl-edma.o fsl-edma-common.o
diff --git a/drivers/dma/dw-edma/Kconfig b/drivers/dma/dw-edma/Kconfig
new file mode 100644
index 0000000..3016bed
--- /dev/null
+++ b/drivers/dma/dw-edma/Kconfig
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0
+
+config DW_EDMA
+ tristate "Synopsys DesignWare eDMA controller driver"
+ select DMA_ENGINE
+ select DMA_VIRTUAL_CHANNELS
+ help
+ Support the Synopsys DesignWare eDMA controller, normally
+ implemented on endpoints SoCs.
diff --git a/drivers/dma/dw-edma/Makefile b/drivers/dma/dw-edma/Makefile
new file mode 100644
index 0000000..3224010
--- /dev/null
+++ b/drivers/dma/dw-edma/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0
+
+obj-$(CONFIG_DW_EDMA) += dw-edma.o
+dw-edma-objs := dw-edma-core.o
diff --git a/drivers/dma/dw-edma/dw-edma-core.c b/drivers/dma/dw-edma/dw-edma-core.c
new file mode 100644
index 0000000..b4c2982
--- /dev/null
+++ b/drivers/dma/dw-edma/dw-edma-core.c
@@ -0,0 +1,925 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018 Synopsys, Inc. and/or its affiliates.
+// Synopsys DesignWare eDMA core driver
+
+#include <linux/module.h>
+#include <linux/device.h>
+#include <linux/kernel.h>
+#include <linux/pm_runtime.h>
+#include <linux/dmaengine.h>
+#include <linux/err.h>
+#include <linux/interrupt.h>
+#include <linux/dma/edma.h>
+
+#include "dw-edma-core.h"
+#include "../dmaengine.h"
+#include "../virt-dma.h"
+
+#define DRV_CORE_NAME "dw-edma-core"
+
+#define SET(reg, name, val) \
+ reg.name = val
+
+#define SET_BOTH_CH(name, value) \
+ do { \
+ SET(dw->wr_edma, name, value); \
+ SET(dw->rd_edma, name, value); \
+ } while (0)
+
+static inline
+struct device *dchan2dev(struct dma_chan *dchan)
+{
+ return &dchan->dev->device;
+}
+
+static inline
+struct device *chan2dev(struct dw_edma_chan *chan)
+{
+ return &chan->vc.chan.dev->device;
+}
+
+static inline
+const struct dw_edma_core_ops *chan2ops(struct dw_edma_chan *chan)
+{
+ return chan->chip->dw->ops;
+}
+
+static inline
+struct dw_edma_desc *vd2dw_edma_desc(struct virt_dma_desc *vd)
+{
+ return container_of(vd, struct dw_edma_desc, vd);
+}
+
+static struct dw_edma_burst *dw_edma_alloc_burst(struct dw_edma_chunk *chunk)
+{
+ struct dw_edma_chan *chan = chunk->chan;
+ struct dw_edma_burst *burst;
+
+ burst = kzalloc(sizeof(struct dw_edma_burst), GFP_NOWAIT);
+ if (unlikely(!burst)) {
+ dev_err(chan2dev(chan), ": fail to alloc new burst\n");
+ return NULL;
+ }
+
+ INIT_LIST_HEAD(&burst->list);
+ burst->sar = 0;
+ burst->dar = 0;
+ burst->sz = 0;
+
+ if (chunk->burst) {
+ atomic_inc(&chunk->bursts_alloc);
+ dev_dbg(chan2dev(chan), ": alloc new burst element (%d)\n",
+ atomic_read(&chunk->bursts_alloc));
+ list_add_tail(&burst->list, &chunk->burst->list);
+ } else {
+ atomic_set(&chunk->bursts_alloc, 0);
+ chunk->burst = burst;
+ dev_dbg(chan2dev(chan), ": alloc new burst head\n");
+ }
+
+ return burst;
+}
+
+static struct dw_edma_chunk *dw_edma_alloc_chunk(struct dw_edma_desc *desc)
+{
+ struct dw_edma_chan *chan = desc->chan;
+ struct dw_edma *dw = chan->chip->dw;
+ struct dw_edma_chunk *chunk;
+
+ chunk = kzalloc(sizeof(struct dw_edma_chunk), GFP_NOWAIT);
+ if (unlikely(!chunk)) {
+ dev_err(chan2dev(chan), ": fail to alloc new chunk\n");
+ return NULL;
+ }
+
+ INIT_LIST_HEAD(&chunk->list);
+ chunk->chan = chan;
+ chunk->cb = !(atomic_read(&desc->chunks_alloc) % 2);
+ chunk->sz = 0;
+ chunk->p_addr = (dma_addr_t) (dw->pa_ll + chan->ll_off);
+ chunk->v_addr = (dma_addr_t) (dw->va_ll + chan->ll_off);
+
+ if (desc->chunk) {
+ atomic_inc(&desc->chunks_alloc);
+ dev_dbg(chan2dev(chan), ": alloc new chunk element (%d)\n",
+ atomic_read(&desc->chunks_alloc));
+ list_add_tail(&chunk->list, &desc->chunk->list);
+ dw_edma_alloc_burst(chunk);
+ } else {
+ chunk->burst = NULL;
+ atomic_set(&desc->chunks_alloc, 0);
+ desc->chunk = chunk;
+ dev_dbg(chan2dev(chan), ": alloc new chunk head\n");
+ }
+
+ return chunk;
+}
+
+static struct dw_edma_desc *dw_edma_alloc_desc(struct dw_edma_chan *chan)
+{
+ struct dw_edma_desc *desc;
+
+ dev_dbg(chan2dev(chan), ": alloc new descriptor\n");
+
+ desc = kzalloc(sizeof(struct dw_edma_desc), GFP_NOWAIT);
+ if (unlikely(!desc)) {
+ dev_err(chan2dev(chan), ": fail to alloc new descriptor\n");
+ return NULL;
+ }
+
+ desc->chan = chan;
+ desc->alloc_sz = 0;
+ desc->xfer_sz = 0;
+ desc->chunk = NULL;
+ dw_edma_alloc_chunk(desc);
+
+ return desc;
+}
+
+static void dw_edma_free_burst(struct dw_edma_chunk *chunk)
+{
+ struct dw_edma_burst *child, *_next;
+
+ if (!chunk->burst)
+ return;
+
+ // Remove all the list elements
+ list_for_each_entry_safe(child, _next, &chunk->burst->list, list) {
+ list_del(&child->list);
+ kfree(child);
+ atomic_dec(&chunk->bursts_alloc);
+ }
+
+ // Remove the list head
+ kfree(child);
+ chunk->burst = NULL;
+}
+
+static void dw_edma_free_chunk(struct dw_edma_desc *desc)
+{
+ struct dw_edma_chan *chan = desc->chan;
+ struct dw_edma_chunk *child, *_next;
+
+ if (!desc->chunk)
+ return;
+
+ // Remove all the list elements
+ list_for_each_entry_safe(child, _next, &desc->chunk->list, list) {
+ dw_edma_free_burst(child);
+ if (atomic_read(&child->bursts_alloc))
+ dev_dbg(chan2dev(chan),
+ ": %d bursts still allocated\n",
+ atomic_read(&child->bursts_alloc));
+ list_del(&child->list);
+ kfree(child);
+ atomic_dec(&desc->chunks_alloc);
+ }
+
+ // Remove the list head
+ kfree(child);
+ desc->chunk = NULL;
+}
+
+static void dw_edma_free_desc(struct dw_edma_desc *desc)
+{
+ struct dw_edma_chan *chan = desc->chan;
+
+ dw_edma_free_chunk(desc);
+ if (atomic_read(&desc->chunks_alloc))
+ dev_dbg(chan2dev(chan),
+ ": %d chunks still allocated\n",
+ atomic_read(&desc->chunks_alloc));
+}
+
+static void vchan_free_desc(struct virt_dma_desc *vdesc)
+{
+ dw_edma_free_desc(vd2dw_edma_desc(vdesc));
+}
+
+static void start_transfer(struct dw_edma_chan *chan)
+{
+ struct virt_dma_desc *vd;
+ struct dw_edma_desc *desc;
+ struct dw_edma_chunk *child, *_next;
+ const struct dw_edma_core_ops *ops = chan2ops(chan);
+
+ vd = vchan_next_desc(&chan->vc);
+ if (!vd)
+ return;
+
+ desc = vd2dw_edma_desc(vd);
+ if (!desc)
+ return;
+
+ list_for_each_entry_safe(child, _next, &desc->chunk->list, list) {
+ ops->start(child, !desc->xfer_sz);
+ desc->xfer_sz += child->sz;
+ dev_dbg(chan2dev(chan),
+ ": transfer of %u bytes started\n", child->sz);
+
+ dw_edma_free_burst(child);
+ if (atomic_read(&child->bursts_alloc))
+ dev_dbg(chan2dev(chan),
+ ": %d bursts still allocated\n",
+ atomic_read(&child->bursts_alloc));
+ list_del(&child->list);
+ kfree(child);
+ atomic_dec(&desc->chunks_alloc);
+
+ return;
+ }
+}
+
+static int dw_edma_device_config(struct dma_chan *dchan,
+ struct dma_slave_config *config)
+{
+ struct dw_edma_chan *chan = dchan2dw_edma_chan(dchan);
+ const struct dw_edma_core_ops *ops = chan2ops(chan);
+ enum dma_transfer_direction dir;
+ unsigned long flags;
+ int err = 0;
+
+ spin_lock_irqsave(&chan->vc.lock, flags);
+
+ if (!config) {
+ err = -EINVAL;
+ goto err_config;
+ }
+
+ if (chan->configured) {
+ dev_err(chan2dev(chan), ": channel already configured\n");
+ err = -EPERM;
+ goto err_config;
+ }
+
+ dir = config->direction;
+ if (dir == DMA_DEV_TO_MEM && chan->dir == EDMA_DIR_WRITE) {
+ dev_info(chan2dev(chan),
+ ": direction DMA_DEV_TO_MEM (EDMA_DIR_WRITE)\n");
+ chan->p_addr = config->src_addr;
+ } else if (dir == DMA_MEM_TO_DEV && chan->dir == EDMA_DIR_READ) {
+ dev_info(chan2dev(chan),
+ ": direction DMA_MEM_TO_DEV (EDMA_DIR_READ)\n");
+ chan->p_addr = config->dst_addr;
+ } else {
+ dev_err(chan2dev(chan), ": invalid direction\n");
+ err = -EINVAL;
+ goto err_config;
+ }
+
+ dev_info(chan2dev(chan),
+ ": src_addr(physical) = 0x%.16x\n", config->src_addr);
+ dev_info(chan2dev(chan),
+ ": dst_addr(physical) = 0x%.16x\n", config->dst_addr);
+
+ err = ops->device_config(dchan);
+ if (!err) {
+ chan->configured = true;
+ dev_dbg(chan2dev(chan), ": channel configured\n");
+ }
+
+err_config:
+ spin_unlock_irqrestore(&chan->vc.lock, flags);
+ return err;
+}
+
+static int dw_edma_device_pause(struct dma_chan *dchan)
+{
+ struct dw_edma_chan *chan = dchan2dw_edma_chan(dchan);
+ unsigned long flags;
+ int err = 0;
+
+ spin_lock_irqsave(&chan->vc.lock, flags);
+
+ if (!chan->configured) {
+ dev_err(dchan2dev(dchan), ": channel not configured\n");
+ err = -EPERM;
+ goto err_pause;
+ }
+
+ switch (chan->status) {
+ case EDMA_ST_IDLE:
+ dev_err(dchan2dev(dchan), ": channel is idle\n");
+ err = -EPERM;
+ goto err_pause;
+ case EDMA_ST_PAUSE:
+ dev_err(dchan2dev(dchan), ": channel is already paused\n");
+ err = -EPERM;
+ goto err_pause;
+ case EDMA_ST_BUSY:
+ // Only acceptable state
+ break;
+ default:
+ dev_err(dchan2dev(dchan), ": invalid status state\n");
+ err = -EINVAL;
+ goto err_pause;
+ }
+
+ switch (chan->request) {
+ case EDMA_REQ_NONE:
+ chan->request = EDMA_REQ_PAUSE;
+ dev_dbg(dchan2dev(dchan), ": pause requested\n");
+ break;
+ case EDMA_REQ_STOP:
+ dev_err(dchan2dev(dchan),
+ ": there is already an ongoing request to stop, any pause request is overridden\n");
+ err = -EPERM;
+ break;
+ case EDMA_REQ_PAUSE:
+ dev_err(dchan2dev(dchan),
+ ": there is already an ongoing request to pause\n");
+ err = -EBUSY;
+ break;
+ default:
+ dev_err(dchan2dev(dchan), ": invalid request state\n");
+ err = -EINVAL;
+ break;
+ }
+
+err_pause:
+ spin_unlock_irqrestore(&chan->vc.lock, flags);
+ return err;
+}
+
+static int dw_edma_device_resume(struct dma_chan *dchan)
+{
+ struct dw_edma_chan *chan = dchan2dw_edma_chan(dchan);
+ unsigned long flags;
+ int err = 0;
+
+ spin_lock_irqsave(&chan->vc.lock, flags);
+
+ if (!chan->configured) {
+ dev_err(dchan2dev(dchan), ": channel not configured\n");
+ err = -EPERM;
+ goto err_resume;
+ }
+
+ switch (chan->status) {
+ case EDMA_ST_IDLE:
+ dev_err(dchan2dev(dchan), ": channel is idle\n");
+ err = -EPERM;
+ goto err_resume;
+ case EDMA_ST_PAUSE:
+ // Only acceptable state
+ break;
+ case EDMA_ST_BUSY:
+ dev_err(dchan2dev(dchan), ": channel is not paused\n");
+ err = -EPERM;
+ goto err_resume;
+ default:
+ dev_err(dchan2dev(dchan), ": invalid status state\n");
+ err = -EINVAL;
+ goto err_resume;
+ }
+
+ switch (chan->request) {
+ case EDMA_REQ_NONE:
+ chan->status = EDMA_ST_BUSY;
+ dev_dbg(dchan2dev(dchan), ": transfer resumed\n");
+ start_transfer(chan);
+ break;
+ case EDMA_REQ_STOP:
+ dev_err(dchan2dev(dchan),
+ ": there is already an ongoing request to stop, any resume request is overridden\n");
+ err = -EPERM;
+ break;
+ case EDMA_REQ_PAUSE:
+ dev_err(dchan2dev(dchan),
+ ": there is an ongoing request to pause, this request will be aborted\n");
+ chan->request = EDMA_REQ_NONE;
+ err = -EPERM;
+ break;
+ default:
+ dev_err(dchan2dev(dchan), ": invalid request state\n");
+ err = -EINVAL;
+ break;
+ }
+
+err_resume:
+ spin_unlock_irqrestore(&chan->vc.lock, flags);
+ return err;
+}
+
+static int dw_edma_device_terminate_all(struct dma_chan *dchan)
+{
+ struct dw_edma_chan *chan = dchan2dw_edma_chan(dchan);
+ unsigned long flags;
+ int err = 0;
+ LIST_HEAD(head);
+
+ spin_lock_irqsave(&chan->vc.lock, flags);
+
+ if (!chan->configured) {
+ dev_err(dchan2dev(dchan), ": channel not configured\n");
+ err = -EPERM;
+ goto err_terminate;
+ }
+
+ switch (chan->status) {
+ case EDMA_ST_IDLE:
+ dev_err(dchan2dev(dchan), ": channel is idle\n");
+ err = -EPERM;
+ goto err_terminate;
+ case EDMA_ST_PAUSE:
+ dev_dbg(dchan2dev(dchan),
+ ": channel is paused, stopping immediately\n");
+ vchan_get_all_descriptors(&chan->vc, &head);
+ vchan_dma_desc_free_list(&chan->vc, &head);
+ chan->status = EDMA_ST_IDLE;
+ goto err_terminate;
+ case EDMA_ST_BUSY:
+ // Only acceptable state
+ break;
+ default:
+ dev_err(dchan2dev(dchan), ": invalid status state\n");
+ err = -EINVAL;
+ goto err_terminate;
+ }
+
+ switch (chan->request) {
+ case EDMA_REQ_NONE:
+ chan->request = EDMA_REQ_STOP;
+ dev_dbg(dchan2dev(dchan), ": termination requested\n");
+ break;
+ case EDMA_REQ_STOP:
+ dev_dbg(dchan2dev(dchan),
+ ": there is already an ongoing request to stop\n");
+ err = -EBUSY;
+ break;
+ case EDMA_REQ_PAUSE:
+ dev_dbg(dchan2dev(dchan),
+ ": there is an ongoing request to pause, this request overridden by stop request\n");
+ chan->request = EDMA_REQ_STOP;
+ err = -EPERM;
+ break;
+ default:
+ dev_err(dchan2dev(dchan), ": invalid request state\n");
+ err = -EINVAL;
+ break;
+ }
+
+err_terminate:
+ spin_unlock_irqrestore(&chan->vc.lock, flags);
+ return err;
+}
+
+static void dw_edma_device_issue_pending(struct dma_chan *dchan)
+{
+ struct dw_edma_chan *chan = dchan2dw_edma_chan(dchan);
+ unsigned long flags;
+
+ spin_lock_irqsave(&chan->vc.lock, flags);
+
+ if (chan->configured && chan->request == EDMA_REQ_NONE &&
+ chan->status == EDMA_ST_IDLE && vchan_issue_pending(&chan->vc)) {
+ dev_dbg(dchan2dev(dchan), ": transfer issued\n");
+ chan->status = EDMA_ST_BUSY;
+ start_transfer(chan);
+ }
+
+ spin_unlock_irqrestore(&chan->vc.lock, flags);
+}
+
+static enum dma_status
+dw_edma_device_tx_status(struct dma_chan *dchan, dma_cookie_t cookie,
+ struct dma_tx_state *txstate)
+{
+ struct dw_edma_chan *chan = dchan2dw_edma_chan(dchan);
+ const struct dw_edma_core_ops *ops = chan2ops(chan);
+ unsigned long flags;
+ enum dma_status ret;
+
+ spin_lock_irqsave(&chan->vc.lock, flags);
+
+ ret = ops->ch_status(chan);
+ if (ret == DMA_ERROR) {
+ goto ret_status;
+ } else if (ret == DMA_IN_PROGRESS) {
+ chan->status = EDMA_ST_BUSY;
+ goto ret_status;
+ } else {
+ // DMA_COMPLETE
+ if (chan->status == EDMA_ST_PAUSE)
+ ret = DMA_PAUSED;
+ else if (chan->status == EDMA_ST_BUSY)
+ ret = DMA_IN_PROGRESS;
+ else
+ ret = DMA_COMPLETE;
+ }
+
+ret_status:
+ spin_unlock_irqrestore(&chan->vc.lock, flags);
+ dma_set_residue(txstate, 0);
+
+ return ret;
+}
+
+static struct dma_async_tx_descriptor *
+dw_edma_device_prep_slave_sg(struct dma_chan *dchan, struct scatterlist *sgl,
+ unsigned int sg_len, enum dma_transfer_direction direction,
+ unsigned long flags, void *context)
+{
+ struct dw_edma_chan *chan = dchan2dw_edma_chan(dchan);
+ struct dw_edma_desc *desc;
+ struct dw_edma_chunk *chunk;
+ struct dw_edma_burst *burst;
+ struct scatterlist *sg;
+ dma_addr_t dev_addr = chan->p_addr;
+ int i;
+
+ if (sg_len < 1) {
+ dev_err(chan2dev(chan), ": invalid sg length %u\n", sg_len);
+ return NULL;
+ }
+
+ if (direction == DMA_DEV_TO_MEM && chan->dir == EDMA_DIR_WRITE) {
+ dev_dbg(chan2dev(chan), ": prepare operation (WRITE)\n");
+ } else if (direction == DMA_MEM_TO_DEV && chan->dir == EDMA_DIR_READ) {
+ dev_dbg(chan2dev(chan), ": prepare operation (READ)\n");
+ } else {
+ dev_err(chan2dev(chan), ": invalid direction\n");
+ return NULL;
+ }
+
+ if (!chan->configured) {
+ dev_err(dchan2dev(dchan), ": channel not configured\n");
+ return NULL;
+ }
+ if (chan->status == EDMA_ST_BUSY) {
+ dev_err(chan2dev(chan), ": channel is busy or paused\n");
+ return NULL;
+ }
+
+ desc = dw_edma_alloc_desc(chan);
+ if (unlikely(!desc))
+ return NULL;
+
+ chunk = dw_edma_alloc_chunk(desc);
+ if (unlikely(!chunk))
+ goto err_alloc;
+
+ for_each_sg(sgl, sg, sg_len, i) {
+ if (atomic_read(&chunk->bursts_alloc) == chan->ll_max) {
+ chunk = dw_edma_alloc_chunk(desc);
+ if (unlikely(!chunk))
+ goto err_alloc;
+ }
+
+ burst = dw_edma_alloc_burst(chunk);
+
+ if (unlikely(!burst))
+ goto err_alloc;
+
+ if (direction == DMA_MEM_TO_DEV) {
+ burst->sar = sg_dma_address(sg);
+ burst->dar = dev_addr;
+ } else {
+ burst->sar = dev_addr;
+ burst->dar = sg_dma_address(sg);
+ }
+
+ burst->sz = sg_dma_len(sg);
+ chunk->sz += burst->sz;
+ desc->alloc_sz += burst->sz;
+ dev_addr += burst->sz;
+
+ dev_dbg(chan2dev(chan),
+ "lli %u/%u, sar=0x%.16llx, dar=0x%.16llx, size=%u bytes\n",
+ i + 1, sg_len,
+ burst->sar, burst->dar,
+ burst->sz);
+ }
+
+ return vchan_tx_prep(&chan->vc, &desc->vd, flags);
+
+err_alloc:
+ dw_edma_free_desc(desc);
+ return NULL;
+}
+
+static void dw_edma_done_interrupt(struct dw_edma_chan *chan)
+{
+ struct dw_edma *dw = chan->chip->dw;
+ const struct dw_edma_core_ops *ops = dw->ops;
+ struct virt_dma_desc *vd;
+ struct dw_edma_desc *desc;
+ unsigned long flags;
+
+ ops->clear_done_int(chan);
+ dev_dbg(chan2dev(chan), ": clear done interrupt\n");
+
+ spin_lock_irqsave(&chan->vc.lock, flags);
+ vd = vchan_next_desc(&chan->vc);
+ switch (chan->request) {
+ case EDMA_REQ_NONE:
+ desc = vd2dw_edma_desc(vd);
+ if (atomic_read(&desc->chunks_alloc)) {
+ dev_dbg(chan2dev(chan), ": sub-transfer complete\n");
+ chan->status = EDMA_ST_BUSY;
+ dev_dbg(chan2dev(chan),
+ ": transferred %u bytes\n", desc->xfer_sz);
+ start_transfer(chan);
+ } else {
+ list_del(&vd->node);
+ vchan_cookie_complete(vd);
+ chan->status = EDMA_ST_IDLE;
+ dev_dbg(chan2dev(chan), ": transfer complete\n");
+ }
+ break;
+ case EDMA_REQ_STOP:
+ list_del(&vd->node);
+ vchan_cookie_complete(vd);
+ chan->request = EDMA_REQ_NONE;
+ chan->status = EDMA_ST_IDLE;
+ dev_dbg(chan2dev(chan), ": transfer stop\n");
+ break;
+ case EDMA_REQ_PAUSE:
+ chan->request = EDMA_REQ_NONE;
+ chan->status = EDMA_ST_PAUSE;
+ break;
+ default:
+ dev_err(chan2dev(chan), ": invalid status state\n");
+ break;
+ }
+ spin_unlock_irqrestore(&chan->vc.lock, flags);
+}
+
+static void dw_edma_abort_interrupt(struct dw_edma_chan *chan)
+{
+ struct dw_edma *dw = chan->chip->dw;
+ const struct dw_edma_core_ops *ops = dw->ops;
+ struct virt_dma_desc *vd;
+ unsigned long flags;
+
+ ops->clear_abort_int(chan);
+ dev_dbg(chan2dev(chan), ": clear abort interrupt\n");
+
+ spin_lock_irqsave(&chan->vc.lock, flags);
+ vd = vchan_next_desc(&chan->vc);
+ list_del(&vd->node);
+ vchan_cookie_complete(vd);
+ chan->request = EDMA_REQ_NONE;
+ chan->status = EDMA_ST_IDLE;
+
+ spin_unlock_irqrestore(&chan->vc.lock, flags);
+}
+
+static irqreturn_t dw_edma_interrupt(int irq, void *data)
+{
+ struct dw_edma_chip *chip = data;
+ struct dw_edma *dw = chip->dw;
+ const struct dw_edma_core_ops *ops = dw->ops;
+ struct dw_edma_chan *chan;
+ u32 i;
+
+ // Poll, clear and process every chanel interrupt status
+ for (i = 0; i < (dw->wr_ch_count + dw->rd_ch_count); i++) {
+ chan = &dw->chan[i];
+
+ if (ops->status_done_int(chan))
+ dw_edma_done_interrupt(chan);
+
+ if (ops->status_abort_int(chan))
+ dw_edma_abort_interrupt(chan);
+ }
+
+ return IRQ_HANDLED;
+}
+
+static int dw_edma_alloc_chan_resources(struct dma_chan *dchan)
+{
+ struct dw_edma_chan *chan = dchan2dw_edma_chan(dchan);
+
+ if (chan->status != EDMA_ST_IDLE) {
+ dev_err(chan2dev(chan), ": channel is busy\n");
+ return -EBUSY;
+ }
+
+ dev_dbg(dchan2dev(dchan), ": allocated\n");
+
+ pm_runtime_get(chan->chip->dev);
+
+ return 0;
+}
+
+static void dw_edma_free_chan_resources(struct dma_chan *dchan)
+{
+ struct dw_edma_chan *chan = dchan2dw_edma_chan(dchan);
+ unsigned long timeout = jiffies + msecs_to_jiffies(5000);
+ int ret;
+
+ if (chan->status != EDMA_ST_IDLE)
+ dev_err(chan2dev(chan), ": channel is busy\n");
+
+ do {
+ ret = dw_edma_device_terminate_all(dchan);
+ if (!ret)
+ break;
+
+ if (time_after_eq(jiffies, timeout)) {
+ dev_err(chan2dev(chan), ": timeout\n");
+ return;
+ }
+
+ cpu_relax();
+ } while (1);
+
+ dev_dbg(dchan2dev(dchan), ": freed\n");
+
+ pm_runtime_put(chan->chip->dev);
+}
+
+int dw_edma_probe(struct dw_edma_chip *chip)
+{
+ struct dw_edma *dw = chip->dw;
+ const struct dw_edma_core_ops *ops;
+ size_t ll_chunk = dw->ll_sz;
+ int i, j, err;
+
+ raw_spin_lock_init(&dw->lock);
+
+ switch (dw->version) {
+ default:
+ dev_err(chip->dev, ": unsupported version\n");
+ return -EPERM;
+ }
+
+ pm_runtime_get_sync(chip->dev);
+
+ dw->wr_ch_count = ops->ch_count(dw, WRITE);
+ if (!dw->wr_ch_count) {
+ dev_err(chip->dev, ": invalid number of write channels(0)\n");
+ return -EINVAL;
+ }
+
+ dw->rd_ch_count = ops->ch_count(dw, READ);
+ if (!dw->rd_ch_count) {
+ dev_err(chip->dev, ": invalid number of read channels(0)\n");
+ return -EINVAL;
+ }
+
+ dev_info(chip->dev, "Channels:\twrite=%d, read=%d\n",
+ dw->wr_ch_count, dw->rd_ch_count);
+
+ dw->chan = devm_kcalloc(chip->dev, dw->wr_ch_count + dw->rd_ch_count,
+ sizeof(*dw->chan), GFP_KERNEL);
+ if (!dw->chan)
+ return -ENOMEM;
+
+ ll_chunk /= roundup_pow_of_two(dw->wr_ch_count + dw->rd_ch_count);
+
+ // Disable eDMA, only to establish the ideal initial conditions
+ ops->off(dw);
+
+ snprintf(dw->name, sizeof(dw->name), "%s:%d", DRV_CORE_NAME, chip->id);
+
+ err = devm_request_irq(chip->dev, chip->irq, dw_edma_interrupt,
+ IRQF_SHARED, dw->name, chip);
+ if (err)
+ return err;
+
+ INIT_LIST_HEAD(&dw->wr_edma.channels);
+ for (i = 0; i < dw->wr_ch_count; i++) {
+ struct dw_edma_chan *chan = &dw->chan[i];
+
+ chan->chip = chip;
+ chan->id = i;
+ chan->dir = EDMA_DIR_WRITE;
+ chan->configured = false;
+ chan->request = EDMA_REQ_NONE;
+ chan->status = EDMA_ST_IDLE;
+
+ chan->ll_off = (ll_chunk * i);
+ chan->ll_max = (ll_chunk / 24) - 1;
+
+ chan->msi_done_addr = dw->msi_addr;
+ chan->msi_abort_addr = dw->msi_addr;
+ chan->msi_data = dw->msi_data;
+
+ chan->vc.desc_free = vchan_free_desc;
+ vchan_init(&chan->vc, &dw->wr_edma);
+ }
+ dma_cap_set(DMA_SLAVE, dw->wr_edma.cap_mask);
+ dw->wr_edma.directions = BIT(DMA_MEM_TO_DEV);
+ dw->wr_edma.chancnt = dw->wr_ch_count;
+
+ INIT_LIST_HEAD(&dw->rd_edma.channels);
+ for (j = 0; j < dw->rd_ch_count; j++, i++) {
+ struct dw_edma_chan *chan = &dw->chan[i];
+
+ chan->chip = chip;
+ chan->id = j;
+ chan->dir = EDMA_DIR_READ;
+ chan->request = EDMA_REQ_NONE;
+ chan->status = EDMA_ST_IDLE;
+
+ chan->ll_off = (ll_chunk * i);
+ chan->ll_max = (ll_chunk / 24) - 1;
+
+ chan->msi_done_addr = dw->msi_addr;
+ chan->msi_abort_addr = dw->msi_addr;
+ chan->msi_data = dw->msi_data;
+
+ chan->vc.desc_free = vchan_free_desc;
+ vchan_init(&chan->vc, &dw->rd_edma);
+ }
+ dma_cap_set(DMA_SLAVE, dw->rd_edma.cap_mask);
+ dw->rd_edma.directions = BIT(DMA_DEV_TO_MEM);
+ dw->rd_edma.chancnt = dw->rd_ch_count;
+
+ // Set DMA capabilities
+ SET_BOTH_CH(src_addr_widths, BIT(DMA_SLAVE_BUSWIDTH_4_BYTES));
+ SET_BOTH_CH(dst_addr_widths, BIT(DMA_SLAVE_BUSWIDTH_4_BYTES));
+ SET_BOTH_CH(residue_granularity, DMA_RESIDUE_GRANULARITY_DESCRIPTOR);
+
+ SET_BOTH_CH(dev, chip->dev);
+
+ SET_BOTH_CH(device_alloc_chan_resources, dw_edma_alloc_chan_resources);
+ SET_BOTH_CH(device_free_chan_resources, dw_edma_free_chan_resources);
+
+ SET_BOTH_CH(device_config, dw_edma_device_config);
+ SET_BOTH_CH(device_pause, dw_edma_device_pause);
+ SET_BOTH_CH(device_resume, dw_edma_device_resume);
+ SET_BOTH_CH(device_terminate_all, dw_edma_device_terminate_all);
+ SET_BOTH_CH(device_issue_pending, dw_edma_device_issue_pending);
+ SET_BOTH_CH(device_tx_status, dw_edma_device_tx_status);
+ SET_BOTH_CH(device_prep_slave_sg, dw_edma_device_prep_slave_sg);
+
+ // Power management
+ pm_runtime_enable(chip->dev);
+
+ // Register DMA device
+ err = dma_async_device_register(&dw->wr_edma);
+ if (err)
+ goto err_pm_disable;
+
+ err = dma_async_device_register(&dw->rd_edma);
+ if (err)
+ goto err_pm_disable;
+
+ // Turn debugfs on
+ err = ops->debugfs_on(chip);
+ if (err) {
+ dev_err(chip->dev, ": unable to create debugfs structure\n");
+ goto err_pm_disable;
+ }
+
+ dev_info(chip->dev,
+ "DesignWare eDMA controller driver loaded completely\n");
+
+ return 0;
+
+err_pm_disable:
+ pm_runtime_disable(chip->dev);
+
+ return err;
+}
+EXPORT_SYMBOL_GPL(dw_edma_probe);
+
+int dw_edma_remove(struct dw_edma_chip *chip)
+{
+ struct dw_edma *dw = chip->dw;
+ const struct dw_edma_core_ops *ops = dw->ops;
+ struct dw_edma_chan *chan, *_chan;
+
+ // Disable eDMA
+ if (ops)
+ ops->off(dw);
+
+ // Free irq
+ devm_free_irq(chip->dev, chip->irq, chip);
+
+ // Power management
+ pm_runtime_disable(chip->dev);
+
+ list_for_each_entry_safe(chan, _chan, &dw->wr_edma.channels,
+ vc.chan.device_node) {
+ list_del(&chan->vc.chan.device_node);
+ tasklet_kill(&chan->vc.task);
+ }
+
+ list_for_each_entry_safe(chan, _chan, &dw->rd_edma.channels,
+ vc.chan.device_node) {
+ list_del(&chan->vc.chan.device_node);
+ tasklet_kill(&chan->vc.task);
+ }
+
+ // Deregister eDMA device
+ dma_async_device_unregister(&dw->wr_edma);
+ dma_async_device_unregister(&dw->rd_edma);
+
+ // Turn debugfs off
+ if (ops)
+ ops->debugfs_off();
+
+ dev_info(chip->dev,
+ ": DesignWare eDMA controller driver unloaded complete\n");
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(dw_edma_remove);
+
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("Synopsys DesignWare eDMA controller core driver");
+MODULE_AUTHOR("Gustavo Pimentel <gustavo.pimentel@synopsys.com>");
diff --git a/drivers/dma/dw-edma/dw-edma-core.h b/drivers/dma/dw-edma/dw-edma-core.h
new file mode 100644
index 0000000..1d11a65
--- /dev/null
+++ b/drivers/dma/dw-edma/dw-edma-core.h
@@ -0,0 +1,145 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+// Copyright (c) 2018 Synopsys, Inc. and/or its affiliates.
+// Synopsys DesignWare eDMA core driver
+
+#ifndef _DW_EDMA_CORE_H
+#define _DW_EDMA_CORE_H
+
+#include <linux/dma/edma.h>
+
+#include "../virt-dma.h"
+
+#define DRV_NAME "dw-edma"
+
+enum dw_edma_dir {
+ EDMA_DIR_WRITE = 0,
+ EDMA_DIR_READ
+};
+
+enum dw_edma_mode {
+ EDMA_MODE_LEGACY = 0,
+ EDMA_MODE_UNROLL
+};
+
+enum dw_edma_request {
+ EDMA_REQ_NONE = 0,
+ EDMA_REQ_STOP,
+ EDMA_REQ_PAUSE
+};
+
+enum dw_edma_status {
+ EDMA_ST_IDLE = 0,
+ EDMA_ST_PAUSE,
+ EDMA_ST_BUSY
+};
+
+struct dw_edma_chan;
+struct dw_edma_chunk;
+
+struct dw_edma_core_ops {
+ // eDMA management callbacks
+ void (*off)(struct dw_edma *dw);
+ u16 (*ch_count)(struct dw_edma *dw, enum dw_edma_dir dir);
+ enum dma_status (*ch_status)(struct dw_edma_chan *chan);
+ void (*clear_done_int)(struct dw_edma_chan *chan);
+ void (*clear_abort_int)(struct dw_edma_chan *chan);
+ bool (*status_done_int)(struct dw_edma_chan *chan);
+ bool (*status_abort_int)(struct dw_edma_chan *chan);
+ void (*start)(struct dw_edma_chunk *chunk, bool first);
+ int (*device_config)(struct dma_chan *dchan);
+ // eDMA debug fs callbacks
+ int (*debugfs_on)(struct dw_edma_chip *chip);
+ void (*debugfs_off)(void);
+};
+
+struct dw_edma_burst {
+ struct list_head list;
+ u64 sar;
+ u64 dar;
+ u32 sz;
+};
+
+struct dw_edma_chunk {
+ struct list_head list;
+ struct dw_edma_chan *chan;
+ struct dw_edma_burst *burst;
+
+ atomic_t bursts_alloc;
+
+ bool cb;
+ u32 sz;
+
+ dma_addr_t p_addr; // Linked list
+ dma_addr_t v_addr; // Linked list
+};
+
+struct dw_edma_desc {
+ struct virt_dma_desc vd;
+ struct dw_edma_chan *chan;
+ struct dw_edma_chunk *chunk;
+
+ atomic_t chunks_alloc;
+
+ u32 alloc_sz;
+ u32 xfer_sz;
+};
+
+struct dw_edma_chan {
+ struct virt_dma_chan vc;
+ struct dw_edma_chip *chip;
+ int id;
+ enum dw_edma_dir dir;
+
+ u64 ll_off;
+ u32 ll_max;
+
+ u64 msi_done_addr;
+ u64 msi_abort_addr;
+ u32 msi_data;
+
+ enum dw_edma_request request;
+ enum dw_edma_status status;
+ bool configured;
+
+ dma_addr_t p_addr; // Data
+};
+
+struct dw_edma {
+ char name[20];
+
+ struct dma_device wr_edma;
+ u16 wr_ch_count;
+ struct dma_device rd_edma;
+ u16 rd_ch_count;
+
+ void __iomem *regs;
+
+ void __iomem *va_ll;
+ resource_size_t pa_ll;
+ size_t ll_sz;
+
+ u64 msi_addr;
+ u32 msi_data;
+
+ u32 version;
+ enum dw_edma_mode mode;
+
+ struct dw_edma_chan *chan;
+ const struct dw_edma_core_ops *ops;
+
+ raw_spinlock_t lock; // Only for legacy type
+};
+
+static inline
+struct dw_edma_chan *vc2dw_edma_chan(struct virt_dma_chan *vc)
+{
+ return container_of(vc, struct dw_edma_chan, vc);
+}
+
+static inline
+struct dw_edma_chan *dchan2dw_edma_chan(struct dma_chan *dchan)
+{
+ return vc2dw_edma_chan(to_virt_chan(dchan));
+}
+
+#endif /* _DW_EDMA_CORE_H */
diff --git a/include/linux/dma/edma.h b/include/linux/dma/edma.h
new file mode 100644
index 0000000..5e62523
--- /dev/null
+++ b/include/linux/dma/edma.h
@@ -0,0 +1,42 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+// Copyright (c) 2018 Synopsys, Inc. and/or its affiliates.
+// Synopsys DesignWare eDMA core driver
+
+#ifndef _DW_EDMA_H
+#define _DW_EDMA_H
+
+#include <linux/device.h>
+#include <linux/dmaengine.h>
+
+struct dw_edma;
+
+/**
+ * struct dw_edma_chip - representation of DesignWare eDMA controller hardware
+ * @dev: struct device of the eDMA controller
+ * @id: instance ID
+ * @irq: irq line
+ * @dw: struct dw_edma that is filed by dw_edma_probe()
+ */
+struct dw_edma_chip {
+ struct device *dev;
+ int id;
+ int irq;
+ struct dw_edma *dw;
+};
+
+/* Export to the platform drivers */
+#if IS_ENABLED(CONFIG_DW_EDMA)
+int dw_edma_probe(struct dw_edma_chip *chip);
+int dw_edma_remove(struct dw_edma_chip *chip);
+#else
+static inline int dw_edma_probe(struct dw_edma_chip *chip)
+{
+ return -ENODEV;
+}
+static inline int dw_edma_remove(struct dw_edma_chip *chip)
+{
+ return 0;
+}
+#endif /* CONFIG_DW_EDMA */
+
+#endif /* _DW_EDMA_H */
^ permalink raw reply related
* [1/6] driver core: Introduce device_iommu_mapped() function
From: Joerg Roedel @ 2018-12-12 11:07 UTC (permalink / raw)
To: Greg Kroah-Hartman
Cc: Joerg Roedel, iommu, Russell Currey, Sam Bobroff, oohall,
Benjamin Herrenschmidt, Paul Mackerras, Michael Ellerman,
Lorenzo Pieralisi, Hanjun Guo, Sudeep Holla, Dan Williams,
Vinod Koul, Mathias Nyman, linux-kernel, linux-acpi, dmaengine,
linux-usb
On Wed, Dec 12, 2018 at 12:04:35PM +0100, Greg Kroah-Hartman wrote:
> On Tue, Dec 11, 2018 at 02:43:38PM +0100, Joerg Roedel wrote:
> > Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
> > Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
>
> No need to have a cc: line if I have already acked it :)
Right, I'll remove it, sorry for the noise.
Regards,
Joerg
^ permalink raw reply
* [1/6] driver core: Introduce device_iommu_mapped() function
From: Greg Kroah-Hartman @ 2018-12-12 11:04 UTC (permalink / raw)
To: Joerg Roedel
Cc: iommu, Russell Currey, Sam Bobroff, oohall,
Benjamin Herrenschmidt, Paul Mackerras, Michael Ellerman,
Lorenzo Pieralisi, Hanjun Guo, Sudeep Holla, Dan Williams,
Vinod Koul, jroedel, Mathias Nyman, linux-kernel, linux-acpi,
dmaengine, linux-usb
On Tue, Dec 11, 2018 at 02:43:38PM +0100, Joerg Roedel wrote:
> From: Joerg Roedel <jroedel@suse.de>
>
> Some places in the kernel check the iommu_group pointer in
> 'struct device' in order to find ot whether a device is
> mapped by an IOMMU.
>
> This is not good way to make this check, as the pointer will
> be moved to 'struct dev_iommu_data'. This way to make the
> check is also not very readable.
>
> Introduce an explicit function to perform this check.
>
> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
> Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
No need to have a cc: line if I have already acked it :)
thanks,
greg k-h
^ permalink raw reply
* [v5,1/2] dmaengine: 8250_mtk_dma: add Mediatek uart DMA support
From: Sean Wang @ 2018-12-11 23:12 UTC (permalink / raw)
To: long.cheng
Cc: vkoul, robh+dt, mark.rutland, ryder.lee, Matthias Brugger,
dan.j.williams, gregkh, jslaby,
Sean Wang (王志亘), dmaengine, devicetree,
linux-arm-kernel, linux-mediatek, linux-kernel, linux-serial,
srv_heupstream, yingjoe.chen, YT Shen
Sorry for that I didn't have a full review at one time in the earlier version
On Mon, Dec 10, 2018 at 9:37 PM Long Cheng
<long.cheng@mediatek.com> wrote:
>
> In DMA engine framework, add 8250 mtk dma to support it.
It looks like there are still many rooms to improve the description,
especially it's a totally new driver.
>
> Signed-off-by: Long Cheng <long.cheng@mediatek.com>
> ---
> drivers/dma/mediatek/8250_mtk_dma.c | 830 +++++++++++++++++++++++++++++++++++
> drivers/dma/mediatek/Kconfig | 11 +
> drivers/dma/mediatek/Makefile | 1 +
> 3 files changed, 842 insertions(+)
> create mode 100644 drivers/dma/mediatek/8250_mtk_dma.c
>
> diff --git a/drivers/dma/mediatek/8250_mtk_dma.c b/drivers/dma/mediatek/8250_mtk_dma.c
> new file mode 100644
> index 0000000..f79d180
> --- /dev/null
> +++ b/drivers/dma/mediatek/8250_mtk_dma.c
> @@ -0,0 +1,830 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Mediatek 8250 DMA driver.
MediaTek
> + *
> + * Copyright (c) 2018 MediaTek Inc.
> + * Author: Long Cheng <long.cheng@mediatek.com>
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/dmaengine.h>
> +#include <linux/dma-mapping.h>
> +#include <linux/err.h>
> +#include <linux/init.h>
> +#include <linux/interrupt.h>
> +#include <linux/list.h>
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/of_dma.h>
> +#include <linux/of_device.h>
> +#include <linux/platform_device.h>
> +#include <linux/slab.h>
> +#include <linux/spinlock.h>
> +#include <linux/pm_runtime.h>
> +#include <linux/iopoll.h>
> +
> +#include "../virt-dma.h"
> +
> +#define MTK_APDMA_DEFAULT_REQUESTS 127
> +#define MTK_APDMA_CHANNELS (CONFIG_SERIAL_8250_NR_UARTS * 2)
> +
> +#define VFF_EN_B BIT(0)
> +#define VFF_STOP_B BIT(0)
> +#define VFF_FLUSH_B BIT(0)
> +#define VFF_4G_SUPPORT_B BIT(0)
> +#define VFF_RX_INT_EN0_B BIT(0) /*rx valid size >= vff thre*/
> +#define VFF_RX_INT_EN1_B BIT(1)
> +#define VFF_TX_INT_EN_B BIT(0) /*tx left size >= vff thre*/
> +#define VFF_WARM_RST_B BIT(0)
> +#define VFF_RX_INT_FLAG_CLR_B (BIT(0) | BIT(1))
> +#define VFF_TX_INT_FLAG_CLR_B 0
> +#define VFF_STOP_CLR_B 0
> +#define VFF_FLUSH_CLR_B 0
> +#define VFF_INT_EN_CLR_B 0
> +#define VFF_4G_SUPPORT_CLR_B 0
> +
> +/* interrupt trigger level for tx */
> +#define VFF_TX_THRE(n) ((n) * 7 / 8)
> +/* interrupt trigger level for rx */
> +#define VFF_RX_THRE(n) ((n) * 3 / 4)
> +
> +#define MTK_DMA_RING_SIZE 0xffffU
> +/* invert this bit when wrap ring head again*/
> +#define MTK_DMA_RING_WRAP 0x10000U
> +
> +#define VFF_INT_FLAG 0x00
> +#define VFF_INT_EN 0x04
> +#define VFF_EN 0x08
> +#define VFF_RST 0x0c
> +#define VFF_STOP 0x10
> +#define VFF_FLUSH 0x14
> +#define VFF_ADDR 0x1c
> +#define VFF_LEN 0x24
> +#define VFF_THRE 0x28
> +#define VFF_WPT 0x2c
> +#define VFF_RPT 0x30
> +/*TX: the buffer size HW can read. RX: the buffer size SW can read.*/
> +#define VFF_VALID_SIZE 0x3c
> +/*TX: the buffer size SW can write. RX: the buffer size HW can write.*/
> +#define VFF_LEFT_SIZE 0x40
> +#define VFF_DEBUG_STATUS 0x50
> +#define VFF_4G_SUPPORT 0x54
> +
> +struct mtk_dmadev {
> + struct dma_device ddev;
> + void __iomem *mem_base[MTK_APDMA_CHANNELS];
> + spinlock_t lock; /* dma dev lock */
> + struct tasklet_struct task;
we can drop tasklet and instead allows descriptors to be handled as
fast as possible.
similar suggestions have been made in the other dmaengine [1] and mtk-hsdma.c
[1] https://lkml.org/lkml/2018/11/11/146
> + struct list_head pending;
> + struct clk *clk;
> + unsigned int dma_requests;
> + bool support_33bits;
> + unsigned int dma_irq[MTK_APDMA_CHANNELS];
> + struct mtk_chan *ch[MTK_APDMA_CHANNELS];
> +};
> +
> +struct mtk_chan {
> + struct virt_dma_chan vc;
> + struct list_head node;
> + struct dma_slave_config cfg;
> + void __iomem *base;
> + struct mtk_dma_desc *desc;
> +
> + bool stop;
> + bool requested;
> +
> + unsigned int rx_status;
> +};
> +
> +struct mtk_dma_sg {
> + dma_addr_t addr;
> + unsigned int en; /* number of elements (24-bit) */
> + unsigned int fn; /* number of frames (16-bit) */
> +};
> +
> +struct mtk_dma_desc {
> + struct virt_dma_desc vd;
> + enum dma_transfer_direction dir;
> +
> + unsigned int sglen;
> + struct mtk_dma_sg sg[0];
> +
> + unsigned int len;
> +};
> +
> +static inline struct mtk_dmadev *to_mtk_dma_dev(struct dma_device *d)
> +{
> + return container_of(d, struct mtk_dmadev, ddev);
> +}
> +
> +static inline struct mtk_chan *to_mtk_dma_chan(struct dma_chan *c)
> +{
> + return container_of(c, struct mtk_chan, vc.chan);
> +}
> +
> +static inline struct mtk_dma_desc *to_mtk_dma_desc
> + (struct dma_async_tx_descriptor *t)
> +{
> + return container_of(t, struct mtk_dma_desc, vd.tx);
> +}
> +
> +static void mtk_dma_chan_write(struct mtk_chan *c,
> + unsigned int reg, unsigned int val)
> +{
> + writel(val, c->base + reg);
> +}
> +
> +static unsigned int mtk_dma_chan_read(struct mtk_chan *c, unsigned int reg)
> +{
> + return readl(c->base + reg);
> +}
> +
> +static void mtk_dma_desc_free(struct virt_dma_desc *vd)
> +{
> + struct dma_chan *chan = vd->tx.chan;
> + struct mtk_chan *c = to_mtk_dma_chan(chan);
> +
> + kfree(c->desc);
> + c->desc = NULL;
> +}
> +
> +static void mtk_dma_tx_flush(struct dma_chan *chan)
> +{
If the user is only one, let's span the content into where the user is.
> + struct mtk_chan *c = to_mtk_dma_chan(chan);
> +
> + if (mtk_dma_chan_read(c, VFF_FLUSH) == 0U)
> + mtk_dma_chan_write(c, VFF_FLUSH, VFF_FLUSH_B);
> +}
> +
> +static void mtk_dma_tx_write(struct dma_chan *chan)
> +{
If the user is only one, let's span the content into where the user is.
> + struct mtk_chan *c = to_mtk_dma_chan(chan);
> + unsigned int txcount = c->desc->len;
> + unsigned int len, send, left, wpt, wrap;
> +
> + len = mtk_dma_chan_read(c, VFF_LEN);
> +
> + while ((left = mtk_dma_chan_read(c, VFF_LEFT_SIZE)) > 0U) {
> + if (c->desc->len == 0U)
merge the condition back into the condition in while
> + break;
> + send = min_t(unsigned int, left, c->desc->len);
> + wpt = mtk_dma_chan_read(c, VFF_WPT);
> + wrap = wpt & MTK_DMA_RING_WRAP ? 0U : MTK_DMA_RING_WRAP;
> +
> + if ((wpt & (len - 1U)) + send < len)
> + mtk_dma_chan_write(c, VFF_WPT, wpt + send);
> + else
> + mtk_dma_chan_write(c, VFF_WPT,
> + ((wpt + send) & (len - 1U))
> + | wrap);
> +
> + c->desc->len -= send;
->len can be renamed to ->avail_len to say it's variable during the work
> + }
> +
> + if (txcount != c->desc->len) {
> + mtk_dma_chan_write(c, VFF_INT_EN, VFF_TX_INT_EN_B);
> + mtk_dma_tx_flush(chan);
> + }
> +}
> +
> +static void mtk_dma_start_tx(struct mtk_chan *c)
> +{
> + if (mtk_dma_chan_read(c, VFF_LEFT_SIZE) == 0U)
> + mtk_dma_chan_write(c, VFF_INT_EN, VFF_TX_INT_EN_B);
> + else
> + mtk_dma_tx_write(&c->vc.chan);
> +
> + c->stop = false;
> +}
> +
> +static void mtk_dma_get_rx_size(struct mtk_chan *c)
> +{
If the user is only one, let's span the content into where the user is.
> + unsigned int rx_size = mtk_dma_chan_read(c, VFF_LEN);
> + unsigned int rdptr, wrptr, wrreg, rdreg, count;
too much variable seems a little lousy, two variables are enough
unsigned int rd, wr;
> +
> + rdreg = mtk_dma_chan_read(c, VFF_RPT);
> + wrreg = mtk_dma_chan_read(c, VFF_WPT);
> + rdptr = rdreg & MTK_DMA_RING_SIZE;
> + wrptr = wrreg & MTK_DMA_RING_SIZE;
rd = mtk_dma_chan_read(c, VFF_RPT) & MTK_DMA_RING_SIZE;
wr = mtk_dma_chan_read(c, VFF_WPT) & MTK_DMA_RING_SIZE
> + count = ((rdreg ^ wrreg) & MTK_DMA_RING_WRAP) ?
> + (wrptr + rx_size - rdptr) : (wrptr - rdptr);
> +
> + c->rx_status = count;
drop the variable count and have a direct assignment
> +
> + mtk_dma_chan_write(c, VFF_RPT, wrreg);
> +}
> +
> +static void mtk_dma_start_rx(struct mtk_chan *c)
> +{
> + struct dma_chan *chan = &c->vc.chan;
> + struct mtk_dmadev *mtkd = to_mtk_dma_dev(chan->device);
> + struct mtk_dma_desc *d = c->desc;
> +
> + if (mtk_dma_chan_read(c, VFF_VALID_SIZE) == 0U)
> + return;
> +
> + if (d && vchan_next_desc(&c->vc)) {
> + mtk_dma_get_rx_size(c);
> + list_del(&d->vd.node);
> + vchan_cookie_complete(&d->vd);
> + } else {
> + spin_lock(&mtkd->lock);
> + if (list_empty(&mtkd->pending))
> + list_add_tail(&c->node, &mtkd->pending);
> + spin_unlock(&mtkd->lock);
> + tasklet_schedule(&mtkd->task);
> + }
> +}
> +
> +static void mtk_dma_reset(struct mtk_chan *c)
> +{
If the user is only one, let's span the content into where the user is.
> + struct mtk_dmadev *mtkd = to_mtk_dma_dev(c->vc.chan.device);
> + u32 status;
> + int ret;
> +
> + mtk_dma_chan_write(c, VFF_ADDR, 0);
> + mtk_dma_chan_write(c, VFF_THRE, 0);
> + mtk_dma_chan_write(c, VFF_LEN, 0);
> + mtk_dma_chan_write(c, VFF_RST, VFF_WARM_RST_B);
> +
> + ret = readx_poll_timeout(readl,
> + c->base + VFF_EN,
> + status, status == 0, 10, 100);
> + if (ret) {
> + dev_err(c->vc.chan.device->dev,
> + "dma reset: fail, timeout\n");
> + return;
> + }
> +
> + if (c->cfg.direction == DMA_DEV_TO_MEM)
> + mtk_dma_chan_write(c, VFF_RPT, 0);
> + else if (c->cfg.direction == DMA_MEM_TO_DEV)
> + mtk_dma_chan_write(c, VFF_WPT, 0);
using switch and case statement
> +
> + if (mtkd->support_33bits)
> + mtk_dma_chan_write(c, VFF_4G_SUPPORT, VFF_4G_SUPPORT_CLR_B);
> +}
> +
> +static void mtk_dma_stop(struct mtk_chan *c)
If the user is only one, let's span the content into where the user is.
> +{
> + u32 status;
> + int ret;
> +
> + mtk_dma_chan_write(c, VFF_FLUSH, VFF_FLUSH_CLR_B);
> + /* Wait for flush */
> + ret = readx_poll_timeout(readl,
> + c->base + VFF_FLUSH,
> + status,
> + (status & VFF_FLUSH_B) != VFF_FLUSH_B,
> + 10, 100);
> + if (ret)
> + dev_err(c->vc.chan.device->dev,
> + "dma stop: polling FLUSH fail, DEBUG=0x%x\n",
> + mtk_dma_chan_read(c, VFF_DEBUG_STATUS));
> +
> + /*set stop as 1 -> wait until en is 0 -> set stop as 0*/
> + mtk_dma_chan_write(c, VFF_STOP, VFF_STOP_B);
> + ret = readx_poll_timeout(readl,
> + c->base + VFF_EN,
> + status, status == 0, 10, 100);
> + if (ret)
> + dev_err(c->vc.chan.device->dev,
> + "dma stop: polling VFF_EN fail, DEBUG=0x%x\n",
> + mtk_dma_chan_read(c, VFF_DEBUG_STATUS));
> +
> + mtk_dma_chan_write(c, VFF_STOP, VFF_STOP_CLR_B);
> + mtk_dma_chan_write(c, VFF_INT_EN, VFF_INT_EN_CLR_B);
> +
> + if (c->cfg.direction == DMA_DEV_TO_MEM)
> + mtk_dma_chan_write(c, VFF_INT_FLAG, VFF_RX_INT_FLAG_CLR_B);
> + else
> + mtk_dma_chan_write(c, VFF_INT_FLAG, VFF_TX_INT_FLAG_CLR_B);
using switch and case statement
> +
> + c->stop = true;
> +}
> +
> +/*
> + * This callback schedules all pending channels. We could be more
> + * clever here by postponing allocation of the real DMA channels to
> + * this point, and freeing them when our virtual channel becomes idle.
> + *
> + * We would then need to deal with 'all channels in-use'
> + */
> +static void mtk_dma_sched(unsigned long data)
> +{
As at the initial be said, try to make descriptors submit as fast as
possible without involving in a tasklet. The same improvement had been
done at mtk-hsdma.c so you could have a reference to it first if you
have no much idea of how to begin to improve.
> + struct mtk_dmadev *mtkd = (struct mtk_dmadev *)data;
> + struct virt_dma_desc *vd;
> + struct mtk_chan *c;
> + unsigned long flags;
> + LIST_HEAD(head);
> +
> + spin_lock_irq(&mtkd->lock);
> + list_splice_tail_init(&mtkd->pending, &head);
> + spin_unlock_irq(&mtkd->lock);
> +
> + if (!list_empty(&head)) {
> + c = list_first_entry(&head, struct mtk_chan, node);
> +
> + spin_lock_irqsave(&c->vc.lock, flags);
> + if (c->cfg.direction == DMA_DEV_TO_MEM) {
> + list_del_init(&c->node);
> + mtk_dma_start_rx(c);
> + } else if (c->cfg.direction == DMA_MEM_TO_DEV) {
> + vd = vchan_next_desc(&c->vc);
> + c->desc = to_mtk_dma_desc(&vd->tx);
> + list_del_init(&c->node);
> + mtk_dma_start_tx(c);
> + }
> + spin_unlock_irqrestore(&c->vc.lock, flags);
> + }
> +}
> +
> +static int mtk_dma_alloc_chan_resources(struct dma_chan *chan)
> +{
> + struct mtk_dmadev *mtkd = to_mtk_dma_dev(chan->device);
> + struct mtk_chan *c = to_mtk_dma_chan(chan);
> + int ret = -EBUSY;
> +
> + pm_runtime_get_sync(mtkd->ddev.dev);
> +
> + if (!mtkd->ch[chan->chan_id]) {
> + c->base = mtkd->mem_base[chan->chan_id]
mtkd->mem_base is unnecessary, we can directly decide c->base in the
driver probe stage
> + mtkd->ch[chan->chan_id] = c;
mtkd->ch is also unnecessary, the core always pass struct dma_chan
*chan to each callback function
> + ret = 1;
ret be 1 seems be wrong
> + }
> + c->requested = false;
> + mtk_dma_reset(c);
> +
> + return ret;
> +}
> +
> +static void mtk_dma_free_chan_resources(struct dma_chan *chan)
> +{
> + struct mtk_dmadev *mtkd = to_mtk_dma_dev(chan->device);
> + struct mtk_chan *c = to_mtk_dma_chan(chan);
> +
> + if (c->requested) {
> + c->requested = false;
> + free_irq(mtkd->dma_irq[chan->chan_id], chan);
it makes not consistent because there are not request_irq present at
mtk_dma_alloc_chan_resources. but I'd prefer a devm_request_irq is
being done
as the driver got probe.
> + }
> +
> + tasklet_kill(&mtkd->task);
> + tasklet_kill(&c->vc.task);
> +
> + c->base = NULL;
> + mtkd->ch[chan->chan_id] = NULL;
> + vchan_free_chan_resources(&c->vc);
> +
> + pm_runtime_put_sync(mtkd->ddev.dev);
> +}
> +
> +static enum dma_status mtk_dma_tx_status(struct dma_chan *chan,
> + dma_cookie_t cookie,
> + struct dma_tx_state *txstate)
> +{
> + struct mtk_chan *c = to_mtk_dma_chan(chan);
> + enum dma_status ret;
> + unsigned long flags;
> +
> + if (!txstate)
> + return DMA_ERROR;
> +
> + ret = dma_cookie_status(chan, cookie, txstate);
> + spin_lock_irqsave(&c->vc.lock, flags);
> + if (ret == DMA_IN_PROGRESS) {
> + c->rx_status = mtk_dma_chan_read(c, VFF_RPT)
> + & MTK_DMA_RING_SIZE;
> + dma_set_residue(txstate, c->rx_status);
> + } else if (ret == DMA_COMPLETE && c->cfg.direction == DMA_DEV_TO_MEM) {
> + dma_set_residue(txstate, c->rx_status);
> + } else {
> + dma_set_residue(txstate, 0);
> + }
> + spin_unlock_irqrestore(&c->vc.lock, flags);
> +
> + return ret;
> +}
> +
> +static struct dma_async_tx_descriptor *mtk_dma_prep_slave_sg
> + (struct dma_chan *chan, struct scatterlist *sgl,
> + unsigned int sglen, enum dma_transfer_direction dir,
> + unsigned long tx_flags, void *context)
> +{
> + struct mtk_chan *c = to_mtk_dma_chan(chan);
> + struct scatterlist *sgent;
> + struct mtk_dma_desc *d;
> + struct mtk_dma_sg *sg;
> + unsigned int size, i, j, en;
> +
> + en = 1;
> +
> + if ((dir != DMA_DEV_TO_MEM) &&
> + (dir != DMA_MEM_TO_DEV)) {
> + dev_err(chan->device->dev, "bad direction\n");
> + return NULL;
> + }
> +
> + /* Now allocate and setup the descriptor. */
> + d = kzalloc(sizeof(*d) + sglen * sizeof(d->sg[0]), GFP_ATOMIC);
> + if (!d)
> + return NULL;
> +
> + d->dir = dir;
> +
> + j = 0;
> + for_each_sg(sgl, sgent, sglen, i) {
> + d->sg[j].addr = sg_dma_address(sgent);
> + d->sg[j].en = en;
> + d->sg[j].fn = sg_dma_len(sgent) / en;
> + j++;
> + }
> +
> + d->sglen = j;
> +
> + if (dir == DMA_MEM_TO_DEV) {
> + for (size = i = 0; i < d->sglen; i++) {
> + sg = &d->sg[i];
> + size += sg->en * sg->fn;
> + }
> + d->len = size;
> + }
> +
The driver always only handles data move for the single contiguous
area, but it seems the callback must provide the scatter-gather
function to the dmaegine. otherwise, why is the callback be called
device_prep_slave_sg?
> + return vchan_tx_prep(&c->vc, &d->vd, tx_flags);
> +}
> +
> +static void mtk_dma_issue_pending(struct dma_chan *chan)
> +{
> + struct mtk_chan *c = to_mtk_dma_chan(chan);
> + struct virt_dma_desc *vd;
> + struct mtk_dmadev *mtkd;
> + unsigned long flags;
> +
> + spin_lock_irqsave(&c->vc.lock, flags);
> + if (c->cfg.direction == DMA_DEV_TO_MEM) {
> + mtkd = to_mtk_dma_dev(chan->device);
mtkd can be dropped as it seems no users
> + if (vchan_issue_pending(&c->vc) && !c->desc) {
> + vd = vchan_next_desc(&c->vc);
> + c->desc = to_mtk_dma_desc(&vd->tx);
> + }
> + } else if (c->cfg.direction == DMA_MEM_TO_DEV) {
> + if (vchan_issue_pending(&c->vc) && !c->desc) {
> + vd = vchan_next_desc(&c->vc);
> + c->desc = to_mtk_dma_desc(&vd->tx);
> + mtk_dma_start_tx(c);
> + }
> + }
> + spin_unlock_irqrestore(&c->vc.lock, flags);
> +}
> +
> +static irqreturn_t mtk_dma_rx_interrupt(int irq, void *dev_id)
> +{
> + struct dma_chan *chan = (struct dma_chan *)dev_id;
> + struct mtk_chan *c = to_mtk_dma_chan(chan);
> + unsigned long flags;
> +
> + spin_lock_irqsave(&c->vc.lock, flags);
> + mtk_dma_chan_write(c, VFF_INT_FLAG, VFF_RX_INT_FLAG_CLR_B);
> +
> + mtk_dma_start_rx(c);
> +
> + spin_unlock_irqrestore(&c->vc.lock, flags);
> +
> + return IRQ_HANDLED;
> +}
> +
> +static irqreturn_t mtk_dma_tx_interrupt(int irq, void *dev_id)
> +{
> + struct dma_chan *chan = (struct dma_chan *)dev_id;
> + struct mtk_dmadev *mtkd = to_mtk_dma_dev(chan->device);
> + struct mtk_chan *c = to_mtk_dma_chan(chan);
> + struct mtk_dma_desc *d = c->desc;
> + unsigned long flags;
> +
> + spin_lock_irqsave(&c->vc.lock, flags);
> + if (d->len != 0U) {
> + list_add_tail(&c->node, &mtkd->pending);
> + tasklet_schedule(&mtkd->task);
> + } else {
> + list_del(&d->vd.node);
> + vchan_cookie_complete(&d->vd);
> + }
> + spin_unlock_irqrestore(&c->vc.lock, flags);
> +
> + mtk_dma_chan_write(c, VFF_INT_FLAG, VFF_TX_INT_FLAG_CLR_B);
> +
> + return IRQ_HANDLED;
> +}
> +
> +static int mtk_dma_slave_config(struct dma_chan *chan,
> + struct dma_slave_config *cfg)
> +{
> + struct mtk_chan *c = to_mtk_dma_chan(chan);
> + struct mtk_dmadev *mtkd = to_mtk_dma_dev(c->vc.chan.device);
> + int ret;
> +
> + c->cfg = *cfg;
> +
> + if (cfg->direction == DMA_DEV_TO_MEM) {
> + unsigned int rx_len = cfg->src_addr_width * 1024;
it seems you should use cfg->src_port_window_size as the comments explains
* @src_port_window_size: The length of the register area in words the data need
* to be accessed on the device side. It is only used for devices which is using
* an area instead of a single register to receive the data. Typically the DMA
* loops in this area in order to transfer the data.
* @dst_port_window_size: same as src_port_window_size but for the destination
* port.
> +
> + mtk_dma_chan_write(c, VFF_ADDR, cfg->src_addr);
> + mtk_dma_chan_write(c, VFF_LEN, rx_len);
> + mtk_dma_chan_write(c, VFF_THRE, VFF_RX_THRE(rx_len));
> + mtk_dma_chan_write(c,
> + VFF_INT_EN, VFF_RX_INT_EN0_B
> + | VFF_RX_INT_EN1_B);
> + mtk_dma_chan_write(c, VFF_INT_FLAG, VFF_RX_INT_FLAG_CLR_B);
> + mtk_dma_chan_write(c, VFF_EN, VFF_EN_B);
I'd prefer to move those channel interrupt enablement to
.device_alloc_chan_resources
and related disablement to .device_free_chan_resources
> +
> + if (!c->requested) {
> + c->requested = true;
> + ret = request_irq(mtkd->dma_irq[chan->chan_id],
> + mtk_dma_rx_interrupt,
> + IRQF_TRIGGER_NONE,
> + KBUILD_MODNAME, chan);
ISR registration usually happens as the driver got probe, it can give
the system more flexibility to manage such IRQ affinity on the fly.
> + if (ret < 0) {
> + dev_err(chan->device->dev, "Can't request rx dma IRQ\n");
> + return -EINVAL;
> + }
> + }
> + } else if (cfg->direction == DMA_MEM_TO_DEV) {
> + unsigned int tx_len = cfg->dst_addr_width * 1024;
Ditto as above, it seems you should use cfg->dst_port_window_size
> +
> + mtk_dma_chan_write(c, VFF_ADDR, cfg->dst_addr);
> + mtk_dma_chan_write(c, VFF_LEN, tx_len);
> + mtk_dma_chan_write(c, VFF_THRE, VFF_TX_THRE(tx_len));
> + mtk_dma_chan_write(c, VFF_INT_FLAG, VFF_TX_INT_FLAG_CLR_B);
> + mtk_dma_chan_write(c, VFF_EN, VFF_EN_B);
ditto, I'd prefer to move those channel interrupt enablement to
.device_alloc_chan_resources and related disablement to
.device_free_chan_resources
> +
> + if (!c->requested) {
> + c->requested = true;
> + ret = request_irq(mtkd->dma_irq[chan->chan_id],
> + mtk_dma_tx_interrupt,
> + IRQF_TRIGGER_NONE,
> + KBUILD_MODNAME, chan);
ditto, we can request ISR with devm_request_irq in the driver got
probe and trim the c->request member
> + if (ret < 0) {
> + dev_err(chan->device->dev, "Can't request tx dma IRQ\n");
> + return -EINVAL;
> + }
> + }
> + }
> +
> + if (mtkd->support_33bits)
> + mtk_dma_chan_write(c, VFF_4G_SUPPORT, VFF_4G_SUPPORT_B);
> +
> + if (mtk_dma_chan_read(c, VFF_EN) != VFF_EN_B) {
> + dev_err(chan->device->dev,
> + "config dma dir[%d] fail\n", cfg->direction);
> + return -EINVAL;
> + }
> +
> + return 0;
> +}
> +
> +static int mtk_dma_terminate_all(struct dma_chan *chan)
> +{
> + struct mtk_chan *c = to_mtk_dma_chan(chan);
> + unsigned long flags;
> +
> + spin_lock_irqsave(&c->vc.lock, flags);
> + list_del_init(&c->node);
> + mtk_dma_stop(c);
> + spin_unlock_irqrestore(&c->vc.lock, flags);
> +
> + return 0;
> +}
> +
> +static int mtk_dma_device_pause(struct dma_chan *chan)
> +{
> + /* just for check caps pass */
> + return -EINVAL;
always return error code seems not the client driver wants us to do.
maybe if the hardware doesn't support pause, we can make a software
pause, that waits until all active descriptors in hardware done, then
disable interrupt and then stop handling the following vd in the
vchan.
> +}
> +
> +static int mtk_dma_device_resume(struct dma_chan *chan)
> +{
> + /* just for check caps pass */
> + return -EINVAL;
similar to the above
> +}
> +
> +static void mtk_dma_free(struct mtk_dmadev *mtkd)
> +{
> + tasklet_kill(&mtkd->task);
> + while (list_empty(&mtkd->ddev.channels) == 0) {
!list_empty(&mtkd->ddev.channels)
> + struct mtk_chan *c = list_first_entry(&mtkd->ddev.channels,
> + struct mtk_chan, vc.chan.device_node);
> +
> + list_del(&c->vc.chan.device_node);
> + tasklet_kill(&c->vc.task);
> + devm_kfree(mtkd->ddev.dev, c);
no need to call devm_kfree, the core would help do this
> + }
> +}
> +
> +static const struct of_device_id mtk_uart_dma_match[] = {
> + { .compatible = "mediatek,mt6577-uart-dma", },
> + { /* sentinel */ },
> +};
> +MODULE_DEVICE_TABLE(of, mtk_uart_dma_match);
> +
> +static int mtk_apdma_probe(struct platform_device *pdev)
> +{
> + struct mtk_dmadev *mtkd;
> + struct resource *res;
> + struct mtk_chan *c;
> + unsigned int i;
> + int rc;
> +
> + mtkd = devm_kzalloc(&pdev->dev, sizeof(*mtkd), GFP_KERNEL);
> + if (!mtkd)
> + return -ENOMEM;
> +
> + for (i = 0; i < MTK_APDMA_CHANNELS; i++) {
> + res = platform_get_resource(pdev, IORESOURCE_MEM, i);
> + if (!res)
> + return -ENODEV;
> + mtkd->mem_base[i] = devm_ioremap_resource(&pdev->dev, res);
> + if (IS_ERR(mtkd->mem_base[i]))
> + return PTR_ERR(mtkd->mem_base[i]);
> + }
> +
> + for (i = 0; i < MTK_APDMA_CHANNELS; i++) {
> + mtkd->dma_irq[i] = platform_get_irq(pdev, i);
> + if ((int)mtkd->dma_irq[i] < 0) {
> + dev_err(&pdev->dev, "failed to get IRQ[%d]\n", i);
> + return -EINVAL;
> + }
> + }
> +
> + mtkd->clk = devm_clk_get(&pdev->dev, NULL);
> + if (IS_ERR(mtkd->clk)) {
> + dev_err(&pdev->dev, "No clock specified\n");
> + return PTR_ERR(mtkd->clk);
> + }
> +
> + if (of_property_read_bool(pdev->dev.of_node, "dma-33bits")) {
> + dev_info(&pdev->dev, "Support dma 33bits\n");
> + mtkd->support_33bits = true;
> + }
> +
> + if (mtkd->support_33bits)
> + rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(33));
> + else
> + rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32 |
mtkd->support_33bits));
> + if (rc)
> + return rc;
> +
> + dma_cap_set(DMA_SLAVE, mtkd->ddev.cap_mask);
> + mtkd->ddev.device_alloc_chan_resources = mtk_dma_alloc_chan_resources;
> + mtkd->ddev.device_free_chan_resources = mtk_dma_free_chan_resources;
> + mtkd->ddev.device_tx_status = mtk_dma_tx_status;
> + mtkd->ddev.device_issue_pending = mtk_dma_issue_pending;
> + mtkd->ddev.device_prep_slave_sg = mtk_dma_prep_slave_sg;
> + mtkd->ddev.device_config = mtk_dma_slave_config;
> + mtkd->ddev.device_pause = mtk_dma_device_pause;
> + mtkd->ddev.device_resume = mtk_dma_device_resume;
> + mtkd->ddev.device_terminate_all = mtk_dma_terminate_all;
> + mtkd->ddev.src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE);
> + mtkd->ddev.dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE);
> + mtkd->ddev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
> + mtkd->ddev.residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT;
> + mtkd->ddev.dev = &pdev->dev;
> + INIT_LIST_HEAD(&mtkd->ddev.channels);
> + INIT_LIST_HEAD(&mtkd->pending);
> +
> + spin_lock_init(&mtkd->lock);
> + tasklet_init(&mtkd->task, mtk_dma_sched, (unsigned long)mtkd);
> +
> + mtkd->dma_requests = MTK_APDMA_DEFAULT_REQUESTS;
> + if (of_property_read_u32(pdev->dev.of_node,
> + "dma-requests", &mtkd->dma_requests)) {
> + dev_info(&pdev->dev,
> + "Missing dma-requests property, using %u.\n",
> + MTK_APDMA_DEFAULT_REQUESTS);
> + }
> +
> + for (i = 0; i < MTK_APDMA_CHANNELS; i++) {
> + c = devm_kzalloc(mtkd->ddev.dev, sizeof(*c), GFP_KERNEL);
> + if (!c)
> + goto err_no_dma;
> +
> + c->vc.desc_free = mtk_dma_desc_free;
> + vchan_init(&c->vc, &mtkd->ddev);
> + INIT_LIST_HEAD(&c->node);
> + }
> +
> + pm_runtime_enable(&pdev->dev);
> + pm_runtime_set_active(&pdev->dev);
> +
> + rc = dma_async_device_register(&mtkd->ddev);
> + if (rc)
> + goto rpm_disable;
> +
> + platform_set_drvdata(pdev, mtkd);
> +
> + if (pdev->dev.of_node) {
> + /* Device-tree DMA controller registration */
> + rc = of_dma_controller_register(pdev->dev.of_node,
> + of_dma_xlate_by_chan_id,
> + mtkd);
> + if (rc)
> + goto dma_remove;
> + }
> +
> + return rc;
> +
> +dma_remove:
> + dma_async_device_unregister(&mtkd->ddev);
> +rpm_disable:
> + pm_runtime_disable(&pdev->dev);
> +err_no_dma:
> + mtk_dma_free(mtkd);
> + return rc;
> +}
> +
> +static int mtk_apdma_remove(struct platform_device *pdev)
> +{
> + struct mtk_dmadev *mtkd = platform_get_drvdata(pdev);
> +
> + if (pdev->dev.of_node)
> + of_dma_controller_free(pdev->dev.of_node);
> +
> + pm_runtime_disable(&pdev->dev);
> + pm_runtime_put_noidle(&pdev->dev);
> +
> + dma_async_device_unregister(&mtkd->ddev);
> +
> + mtk_dma_free(mtkd);
> +
> + return 0;
> +}
> +
> +#ifdef CONFIG_PM_SLEEP
> +static int mtk_dma_suspend(struct device *dev)
> +{
> + struct mtk_dmadev *mtkd = dev_get_drvdata(dev);
> +
> + if (!pm_runtime_suspended(dev))
> + clk_disable_unprepare(mtkd->clk);
> +
> + return 0;
> +}
> +
> +static int mtk_dma_resume(struct device *dev)
> +{
> + int ret;
> + struct mtk_dmadev *mtkd = dev_get_drvdata(dev);
> +
> + if (!pm_runtime_suspended(dev)) {
> + ret = clk_prepare_enable(mtkd->clk);
> + if (ret)
> + return ret;
> + }
> +
> + return 0;
> +}
> +#endif /* CONFIG_PM_SLEEP */
> +
> +#ifdef CONFIG_PM
> +static int mtk_dma_runtime_suspend(struct device *dev)
> +{
> + struct mtk_dmadev *mtkd = dev_get_drvdata(dev);
> +
> + clk_disable_unprepare(mtkd->clk);
> +
> + return 0;
> +}
> +
> +static int mtk_dma_runtime_resume(struct device *dev)
> +{
> + int ret;
> + struct mtk_dmadev *mtkd = dev_get_drvdata(dev);
> +
> + ret = clk_prepare_enable(mtkd->clk);
> + if (ret)
> + return ret;
> +
> + return 0;
> +}
> +#endif /* CONFIG_PM */
> +
> +static const struct dev_pm_ops mtk_dma_pm_ops = {
> + SET_SYSTEM_SLEEP_PM_OPS(mtk_dma_suspend, mtk_dma_resume)
> + SET_RUNTIME_PM_OPS(mtk_dma_runtime_suspend,
> + mtk_dma_runtime_resume, NULL)
> +};
> +
> +static struct platform_driver mtk_dma_driver = {
mtk_dma is much general and all functions and structures in the driver
should be all consistent. I'd prefer to have all naming starts with
mtk_uart_apdma.
> + .probe = mtk_apdma_probe,
such as
mtk_uart_apdma_probe
> + .remove = mtk_apdma_remove,
mtk_uart_apdma_remove
> + .driver = {
> + .name = KBUILD_MODNAME,
> + .pm = &mtk_dma_pm_ops,
mtk_uart_apdma_pm_ops
> + .of_match_table = of_match_ptr(mtk_uart_dma_match),
mtk_uart_apdma_match
> + },
> +};
> +
> +module_platform_driver(mtk_dma_driver);
mtk_uart_apdma_driver
> +
> +MODULE_DESCRIPTION("MediaTek UART APDMA Controller Driver");
> +MODULE_AUTHOR("Long Cheng <long.cheng@mediatek.com>");
> +MODULE_LICENSE("GPL v2");
> +
> diff --git a/drivers/dma/mediatek/Kconfig b/drivers/dma/mediatek/Kconfig
> index 27bac0b..d399624 100644
> --- a/drivers/dma/mediatek/Kconfig
> +++ b/drivers/dma/mediatek/Kconfig
> @@ -1,4 +1,15 @@
>
> +config DMA_MTK_UART
MTK_UART_APDMA to align the other drivers
> + tristate "MediaTek SoCs APDMA support for UART"
> + depends on OF && SERIAL_8250_MT6577
> + select DMA_ENGINE
> + select DMA_VIRTUAL_CHANNELS
> + help
> + Support for the UART DMA engine found on MediaTek MTK SoCs.
> + when 8250 mtk uart is enabled, and if you want to using DMA,
8250 mtk uart should be changed to SERIAL_8250_MT6577 to be more intuitive
> + you can enable the config. the DMA engine just only be used
> + with MediaTek Socs.
SoCs
> +
> config MTK_HSDMA
> tristate "MediaTek High-Speed DMA controller support"
> depends on ARCH_MEDIATEK || COMPILE_TEST
> diff --git a/drivers/dma/mediatek/Makefile b/drivers/dma/mediatek/Makefile
> index 6e778f8..2f2efd9 100644
> --- a/drivers/dma/mediatek/Makefile
> +++ b/drivers/dma/mediatek/Makefile
> @@ -1 +1,2 @@
> +obj-$(CONFIG_DMA_MTK_UART) += 8250_mtk_dma.o
obj-$(CONFIG_MTK_UART_APDMA) += mtk-uart-apdma.o
to align the other dirvers
> obj-$(CONFIG_MTK_HSDMA) += mtk-hsdma.o
> --
> 1.7.9.5
>
^ permalink raw reply
* [1/6] driver core: Introduce device_iommu_mapped() function
From: Joerg Roedel @ 2018-12-11 15:18 UTC (permalink / raw)
To: Sergei Shtylyov
Cc: iommu, Russell Currey, Sam Bobroff, oohall,
Benjamin Herrenschmidt, Paul Mackerras, Michael Ellerman,
Lorenzo Pieralisi, Hanjun Guo, Sudeep Holla, Dan Williams,
Vinod Koul, jroedel, Mathias Nyman, Greg Kroah-Hartman,
linux-kernel, linux-acpi, dmaengine, linux-usb
On Tue, Dec 11, 2018 at 05:59:33PM +0300, Sergei Shtylyov wrote:
> > +static inline bool device_iommu_mapped(struct device *dev)
> > +{
> > + return (dev->iommu_group != NULL);
>
> You know that parens are unnecessary here, right? :-)
Yes, I know, but it feels incomplete to me without them :-)
Joerg
^ permalink raw reply
* [1/6] driver core: Introduce device_iommu_mapped() function
From: Sergei Shtylyov @ 2018-12-11 14:59 UTC (permalink / raw)
To: Joerg Roedel, iommu
Cc: Russell Currey, Sam Bobroff, oohall, Benjamin Herrenschmidt,
Paul Mackerras, Michael Ellerman, Lorenzo Pieralisi, Hanjun Guo,
Sudeep Holla, Dan Williams, Vinod Koul, jroedel, Mathias Nyman,
Greg Kroah-Hartman, linux-kernel, linux-acpi, dmaengine,
linux-usb
Hello!
On 12/11/2018 04:43 PM, Joerg Roedel wrote:
> From: Joerg Roedel <jroedel@suse.de>
>
> Some places in the kernel check the iommu_group pointer in
> 'struct device' in order to find ot whether a device is
> mapped by an IOMMU.
>
> This is not good way to make this check, as the pointer will
> be moved to 'struct dev_iommu_data'. This way to make the
> check is also not very readable.
>
> Introduce an explicit function to perform this check.
>
> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
> Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
> Acked-by: Robin Murphy <robin.murphy@arm.com>
> Signed-off-by: Joerg Roedel <jroedel@suse.de>
> ---
> include/linux/device.h | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
> diff --git a/include/linux/device.h b/include/linux/device.h
> index 1b25c7a43f4c..6cb4640b6160 100644
> --- a/include/linux/device.h
> +++ b/include/linux/device.h
> @@ -1058,6 +1058,16 @@ static inline struct device *kobj_to_dev(struct kobject *kobj)
> return container_of(kobj, struct device, kobj);
> }
>
> +/**
> + * device_iommu_mapped - Returns true when the device DMA is translated
> + * by an IOMMU
> + * @dev: Device to perform the check on
> + */
> +static inline bool device_iommu_mapped(struct device *dev)
> +{
> + return (dev->iommu_group != NULL);
You know that parens are unnecessary here, right? :-)
> +}
> +
> /* Get the wakeup routines, which depend on struct device */
> #include <linux/pm_wakeup.h>
>
MBR, Sergei
^ permalink raw reply
* [6/6] dmaengine: sh: rcar-dmac: Use device_iommu_mapped()
From: Joerg Roedel @ 2018-12-11 13:43 UTC (permalink / raw)
To: iommu
Cc: Russell Currey, Sam Bobroff, oohall, Benjamin Herrenschmidt,
Paul Mackerras, Michael Ellerman, Lorenzo Pieralisi, Hanjun Guo,
Sudeep Holla, Dan Williams, Vinod Koul, Joerg Roedel, jroedel,
Mathias Nyman, Greg Kroah-Hartman, linux-kernel, linux-acpi,
dmaengine, linux-usb
From: Joerg Roedel <jroedel@suse.de>
Use Use device_iommu_mapped() to check if the device is
already mapped by an IOMMU.
Acked-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Joerg Roedel <jroedel@suse.de>
---
drivers/dma/sh/rcar-dmac.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/dma/sh/rcar-dmac.c b/drivers/dma/sh/rcar-dmac.c
index 74fa2b1a6a86..2b4f25698169 100644
--- a/drivers/dma/sh/rcar-dmac.c
+++ b/drivers/dma/sh/rcar-dmac.c
@@ -1809,7 +1809,7 @@ static int rcar_dmac_probe(struct platform_device *pdev)
* level we can't disable it selectively, so ignore channel 0 for now if
* the device is part of an IOMMU group.
*/
- if (pdev->dev.iommu_group) {
+ if (device_iommu_mapped(&pdev->dev)) {
dmac->n_channels--;
channels_offset = 1;
}
^ permalink raw reply related
* [5/6] xhci: Use device_iommu_mapped()
From: Joerg Roedel @ 2018-12-11 13:43 UTC (permalink / raw)
To: iommu
Cc: Russell Currey, Sam Bobroff, oohall, Benjamin Herrenschmidt,
Paul Mackerras, Michael Ellerman, Lorenzo Pieralisi, Hanjun Guo,
Sudeep Holla, Dan Williams, Vinod Koul, Joerg Roedel, jroedel,
Mathias Nyman, Greg Kroah-Hartman, linux-kernel, linux-acpi,
dmaengine, linux-usb
From: Joerg Roedel <jroedel@suse.de>
Replace the dev->iommu_group check with a proper function
call that better reprensents its purpose.
Cc: Mathias Nyman <mathias.nyman@intel.com>
Acked-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Joerg Roedel <jroedel@suse.de>
---
drivers/usb/host/xhci.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c
index dae3be1b9c8f..8eacd2ed412b 100644
--- a/drivers/usb/host/xhci.c
+++ b/drivers/usb/host/xhci.c
@@ -244,7 +244,7 @@ static void xhci_zero_64b_regs(struct xhci_hcd *xhci)
* an iommu. Doing anything when there is no iommu is definitely
* unsafe...
*/
- if (!(xhci->quirks & XHCI_ZERO_64B_REGS) || !dev->iommu_group)
+ if (!(xhci->quirks & XHCI_ZERO_64B_REGS) || !device_iommu_mapped(dev))
return;
xhci_info(xhci, "Zeroing 64bit base registers, expecting fault\n");
^ permalink raw reply related
* [4/6] powerpc/iommu: Use device_iommu_mapped()
From: Joerg Roedel @ 2018-12-11 13:43 UTC (permalink / raw)
To: iommu
Cc: Russell Currey, Sam Bobroff, oohall, Benjamin Herrenschmidt,
Paul Mackerras, Michael Ellerman, Lorenzo Pieralisi, Hanjun Guo,
Sudeep Holla, Dan Williams, Vinod Koul, Joerg Roedel, jroedel,
Mathias Nyman, Greg Kroah-Hartman, linux-kernel, linux-acpi,
dmaengine, linux-usb
From: Joerg Roedel <jroedel@suse.de>
Use the new function to replace the open-coded iommu check.
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Russell Currey <ruscur@russell.cc>
Cc: Sam Bobroff <sbobroff@linux.ibm.com>
Acked-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Joerg Roedel <jroedel@suse.de>
---
arch/powerpc/kernel/eeh.c | 2 +-
arch/powerpc/kernel/iommu.c | 6 +++---
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/kernel/eeh.c b/arch/powerpc/kernel/eeh.c
index 6cae6b56ffd6..23fe62f11486 100644
--- a/arch/powerpc/kernel/eeh.c
+++ b/arch/powerpc/kernel/eeh.c
@@ -1472,7 +1472,7 @@ static int dev_has_iommu_table(struct device *dev, void *data)
if (!dev)
return 0;
- if (dev->iommu_group) {
+ if (device_iommu_mapped(dev)) {
*ppdev = pdev;
return 1;
}
diff --git a/arch/powerpc/kernel/iommu.c b/arch/powerpc/kernel/iommu.c
index f0dc680e659a..48d58d1dcac2 100644
--- a/arch/powerpc/kernel/iommu.c
+++ b/arch/powerpc/kernel/iommu.c
@@ -1086,7 +1086,7 @@ int iommu_add_device(struct device *dev)
if (!device_is_registered(dev))
return -ENOENT;
- if (dev->iommu_group) {
+ if (device_iommu_mapped(dev)) {
pr_debug("%s: Skipping device %s with iommu group %d\n",
__func__, dev_name(dev),
iommu_group_id(dev->iommu_group));
@@ -1129,7 +1129,7 @@ void iommu_del_device(struct device *dev)
* and we needn't detach them from the associated
* IOMMU groups
*/
- if (!dev->iommu_group) {
+ if (!device_iommu_mapped(dev)) {
pr_debug("iommu_tce: skipping device %s with no tbl\n",
dev_name(dev));
return;
@@ -1148,7 +1148,7 @@ static int tce_iommu_bus_notifier(struct notifier_block *nb,
case BUS_NOTIFY_ADD_DEVICE:
return iommu_add_device(dev);
case BUS_NOTIFY_DEL_DEVICE:
- if (dev->iommu_group)
+ if (device_iommu_mapped(dev))
iommu_del_device(dev);
return 0;
default:
^ permalink raw reply related
* [3/6] ACPI/IORT: Use device_iommu_mapped()
From: Joerg Roedel @ 2018-12-11 13:43 UTC (permalink / raw)
To: iommu
Cc: Russell Currey, Sam Bobroff, oohall, Benjamin Herrenschmidt,
Paul Mackerras, Michael Ellerman, Lorenzo Pieralisi, Hanjun Guo,
Sudeep Holla, Dan Williams, Vinod Koul, Joerg Roedel, jroedel,
Mathias Nyman, Greg Kroah-Hartman, linux-kernel, linux-acpi,
dmaengine, linux-usb
From: Joerg Roedel <jroedel@suse.de>
Replace the iommu-check with a proper and readable function
call.
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Joerg Roedel <jroedel@suse.de>
---
drivers/acpi/arm64/iort.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/acpi/arm64/iort.c b/drivers/acpi/arm64/iort.c
index 70f4e80b9246..0125c8eb9e81 100644
--- a/drivers/acpi/arm64/iort.c
+++ b/drivers/acpi/arm64/iort.c
@@ -805,7 +805,7 @@ static inline int iort_add_device_replay(const struct iommu_ops *ops,
{
int err = 0;
- if (ops->add_device && dev->bus && !dev->iommu_group)
+ if (ops->add_device && dev->bus && !device_iommu_mapped(dev))
err = ops->add_device(dev);
return err;
^ permalink raw reply related
* [2/6] iommu/of: Use device_iommu_mapped()
From: Joerg Roedel @ 2018-12-11 13:43 UTC (permalink / raw)
To: iommu
Cc: Russell Currey, Sam Bobroff, oohall, Benjamin Herrenschmidt,
Paul Mackerras, Michael Ellerman, Lorenzo Pieralisi, Hanjun Guo,
Sudeep Holla, Dan Williams, Vinod Koul, Joerg Roedel, jroedel,
Mathias Nyman, Greg Kroah-Hartman, linux-kernel, linux-acpi,
dmaengine, linux-usb
From: Joerg Roedel <jroedel@suse.de>
Use Use device_iommu_mapped() to check if the device is
already mapped by an IOMMU.
Acked-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Joerg Roedel <jroedel@suse.de>
---
drivers/iommu/of_iommu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/iommu/of_iommu.c b/drivers/iommu/of_iommu.c
index c5dd63072529..bfcf139503f0 100644
--- a/drivers/iommu/of_iommu.c
+++ b/drivers/iommu/of_iommu.c
@@ -220,7 +220,7 @@ const struct iommu_ops *of_iommu_configure(struct device *dev,
* If we have reason to believe the IOMMU driver missed the initial
* add_device callback for dev, replay it to get things in order.
*/
- if (ops && ops->add_device && dev->bus && !dev->iommu_group)
+ if (ops && ops->add_device && dev->bus && !device_iommu_mapped(dev))
err = ops->add_device(dev);
/* Ignore all other errors apart from EPROBE_DEFER */
^ permalink raw reply related
* [1/6] driver core: Introduce device_iommu_mapped() function
From: Joerg Roedel @ 2018-12-11 13:43 UTC (permalink / raw)
To: iommu
Cc: Russell Currey, Sam Bobroff, oohall, Benjamin Herrenschmidt,
Paul Mackerras, Michael Ellerman, Lorenzo Pieralisi, Hanjun Guo,
Sudeep Holla, Dan Williams, Vinod Koul, Joerg Roedel, jroedel,
Mathias Nyman, Greg Kroah-Hartman, linux-kernel, linux-acpi,
dmaengine, linux-usb
From: Joerg Roedel <jroedel@suse.de>
Some places in the kernel check the iommu_group pointer in
'struct device' in order to find ot whether a device is
mapped by an IOMMU.
This is not good way to make this check, as the pointer will
be moved to 'struct dev_iommu_data'. This way to make the
check is also not very readable.
Introduce an explicit function to perform this check.
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Acked-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Joerg Roedel <jroedel@suse.de>
---
include/linux/device.h | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/include/linux/device.h b/include/linux/device.h
index 1b25c7a43f4c..6cb4640b6160 100644
--- a/include/linux/device.h
+++ b/include/linux/device.h
@@ -1058,6 +1058,16 @@ static inline struct device *kobj_to_dev(struct kobject *kobj)
return container_of(kobj, struct device, kobj);
}
+/**
+ * device_iommu_mapped - Returns true when the device DMA is translated
+ * by an IOMMU
+ * @dev: Device to perform the check on
+ */
+static inline bool device_iommu_mapped(struct device *dev)
+{
+ return (dev->iommu_group != NULL);
+}
+
/* Get the wakeup routines, which depend on struct device */
#include <linux/pm_wakeup.h>
^ permalink raw reply related
* [v5,2/2] arm: dts: mt2712: add uart APDMA to device tree
From: Long Cheng @ 2018-12-11 5:37 UTC (permalink / raw)
To: Vinod Koul, Rob Herring, Mark Rutland, Ryder Lee
Cc: Matthias Brugger, Dan Williams, Greg Kroah-Hartman, Jiri Slaby,
Sean Wang, Sean Wang, dmaengine, devicetree, linux-arm-kernel,
linux-mediatek, linux-kernel, linux-serial, srv_heupstream,
Yingjoe Chen, YT Shen, Long Cheng
1. add uart APDMA controller device node
2. add uart 0/1/2/3/4/5 DMA function
Signed-off-by: Long Cheng <long.cheng@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 50 +++++++++++++++++++++++++++++
1 file changed, 50 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
index 976d92a..a59728b 100644
--- a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
@@ -300,6 +300,9 @@
interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_LOW>;
clocks = <&baud_clk>, <&sys_clk>;
clock-names = "baud", "bus";
+ dmas = <&apdma 10
+ &apdma 11>;
+ dma-names = "tx", "rx";
status = "disabled";
};
@@ -378,6 +381,38 @@
status = "disabled";
};
+ apdma: dma-controller@11000400 {
+ compatible = "mediatek,mt2712-uart-dma",
+ "mediatek,mt6577-uart-dma";
+ reg = <0 0x11000400 0 0x80>,
+ <0 0x11000480 0 0x80>,
+ <0 0x11000500 0 0x80>,
+ <0 0x11000580 0 0x80>,
+ <0 0x11000600 0 0x80>,
+ <0 0x11000680 0 0x80>,
+ <0 0x11000700 0 0x80>,
+ <0 0x11000780 0 0x80>,
+ <0 0x11000800 0 0x80>,
+ <0 0x11000880 0 0x80>,
+ <0 0x11000900 0 0x80>,
+ <0 0x11000980 0 0x80>;
+ interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 105 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 107 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 108 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 109 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 111 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 113 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 114 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&pericfg CLK_PERI_AP_DMA>;
+ clock-names = "apdma";
+ #dma-cells = <1>;
+ };
+
uart0: serial@11002000 {
compatible = "mediatek,mt2712-uart",
"mediatek,mt6577-uart";
@@ -385,6 +420,9 @@
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
clocks = <&baud_clk>, <&sys_clk>;
clock-names = "baud", "bus";
+ dmas = <&apdma 0
+ &apdma 1>;
+ dma-names = "tx", "rx";
status = "disabled";
};
@@ -395,6 +433,9 @@
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
clocks = <&baud_clk>, <&sys_clk>;
clock-names = "baud", "bus";
+ dmas = <&apdma 2
+ &apdma 3>;
+ dma-names = "tx", "rx";
status = "disabled";
};
@@ -405,6 +446,9 @@
interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
clocks = <&baud_clk>, <&sys_clk>;
clock-names = "baud", "bus";
+ dmas = <&apdma 4
+ &apdma 5>;
+ dma-names = "tx", "rx";
status = "disabled";
};
@@ -415,6 +459,9 @@
interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>;
clocks = <&baud_clk>, <&sys_clk>;
clock-names = "baud", "bus";
+ dmas = <&apdma 6
+ &apdma 7>;
+ dma-names = "tx", "rx";
status = "disabled";
};
@@ -629,6 +676,9 @@
interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_LOW>;
clocks = <&baud_clk>, <&sys_clk>;
clock-names = "baud", "bus";
+ dmas = <&apdma 8
+ &apdma 9>;
+ dma-names = "tx", "rx";
status = "disabled";
};
^ permalink raw reply related
* [v5,1/2] dmaengine: 8250_mtk_dma: add Mediatek uart DMA support
From: Long Cheng @ 2018-12-11 5:37 UTC (permalink / raw)
To: Vinod Koul, Rob Herring, Mark Rutland, Ryder Lee
Cc: Matthias Brugger, Dan Williams, Greg Kroah-Hartman, Jiri Slaby,
Sean Wang, Sean Wang, dmaengine, devicetree, linux-arm-kernel,
linux-mediatek, linux-kernel, linux-serial, srv_heupstream,
Yingjoe Chen, YT Shen, Long Cheng
In DMA engine framework, add 8250 mtk dma to support it.
Signed-off-by: Long Cheng <long.cheng@mediatek.com>
---
drivers/dma/mediatek/8250_mtk_dma.c | 830 +++++++++++++++++++++++++++++++++++
drivers/dma/mediatek/Kconfig | 11 +
drivers/dma/mediatek/Makefile | 1 +
3 files changed, 842 insertions(+)
create mode 100644 drivers/dma/mediatek/8250_mtk_dma.c
diff --git a/drivers/dma/mediatek/8250_mtk_dma.c b/drivers/dma/mediatek/8250_mtk_dma.c
new file mode 100644
index 0000000..f79d180
--- /dev/null
+++ b/drivers/dma/mediatek/8250_mtk_dma.c
@@ -0,0 +1,830 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Mediatek 8250 DMA driver.
+ *
+ * Copyright (c) 2018 MediaTek Inc.
+ * Author: Long Cheng <long.cheng@mediatek.com>
+ */
+
+#include <linux/clk.h>
+#include <linux/dmaengine.h>
+#include <linux/dma-mapping.h>
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/list.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of_dma.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/spinlock.h>
+#include <linux/pm_runtime.h>
+#include <linux/iopoll.h>
+
+#include "../virt-dma.h"
+
+#define MTK_APDMA_DEFAULT_REQUESTS 127
+#define MTK_APDMA_CHANNELS (CONFIG_SERIAL_8250_NR_UARTS * 2)
+
+#define VFF_EN_B BIT(0)
+#define VFF_STOP_B BIT(0)
+#define VFF_FLUSH_B BIT(0)
+#define VFF_4G_SUPPORT_B BIT(0)
+#define VFF_RX_INT_EN0_B BIT(0) /*rx valid size >= vff thre*/
+#define VFF_RX_INT_EN1_B BIT(1)
+#define VFF_TX_INT_EN_B BIT(0) /*tx left size >= vff thre*/
+#define VFF_WARM_RST_B BIT(0)
+#define VFF_RX_INT_FLAG_CLR_B (BIT(0) | BIT(1))
+#define VFF_TX_INT_FLAG_CLR_B 0
+#define VFF_STOP_CLR_B 0
+#define VFF_FLUSH_CLR_B 0
+#define VFF_INT_EN_CLR_B 0
+#define VFF_4G_SUPPORT_CLR_B 0
+
+/* interrupt trigger level for tx */
+#define VFF_TX_THRE(n) ((n) * 7 / 8)
+/* interrupt trigger level for rx */
+#define VFF_RX_THRE(n) ((n) * 3 / 4)
+
+#define MTK_DMA_RING_SIZE 0xffffU
+/* invert this bit when wrap ring head again*/
+#define MTK_DMA_RING_WRAP 0x10000U
+
+#define VFF_INT_FLAG 0x00
+#define VFF_INT_EN 0x04
+#define VFF_EN 0x08
+#define VFF_RST 0x0c
+#define VFF_STOP 0x10
+#define VFF_FLUSH 0x14
+#define VFF_ADDR 0x1c
+#define VFF_LEN 0x24
+#define VFF_THRE 0x28
+#define VFF_WPT 0x2c
+#define VFF_RPT 0x30
+/*TX: the buffer size HW can read. RX: the buffer size SW can read.*/
+#define VFF_VALID_SIZE 0x3c
+/*TX: the buffer size SW can write. RX: the buffer size HW can write.*/
+#define VFF_LEFT_SIZE 0x40
+#define VFF_DEBUG_STATUS 0x50
+#define VFF_4G_SUPPORT 0x54
+
+struct mtk_dmadev {
+ struct dma_device ddev;
+ void __iomem *mem_base[MTK_APDMA_CHANNELS];
+ spinlock_t lock; /* dma dev lock */
+ struct tasklet_struct task;
+ struct list_head pending;
+ struct clk *clk;
+ unsigned int dma_requests;
+ bool support_33bits;
+ unsigned int dma_irq[MTK_APDMA_CHANNELS];
+ struct mtk_chan *ch[MTK_APDMA_CHANNELS];
+};
+
+struct mtk_chan {
+ struct virt_dma_chan vc;
+ struct list_head node;
+ struct dma_slave_config cfg;
+ void __iomem *base;
+ struct mtk_dma_desc *desc;
+
+ bool stop;
+ bool requested;
+
+ unsigned int rx_status;
+};
+
+struct mtk_dma_sg {
+ dma_addr_t addr;
+ unsigned int en; /* number of elements (24-bit) */
+ unsigned int fn; /* number of frames (16-bit) */
+};
+
+struct mtk_dma_desc {
+ struct virt_dma_desc vd;
+ enum dma_transfer_direction dir;
+
+ unsigned int sglen;
+ struct mtk_dma_sg sg[0];
+
+ unsigned int len;
+};
+
+static inline struct mtk_dmadev *to_mtk_dma_dev(struct dma_device *d)
+{
+ return container_of(d, struct mtk_dmadev, ddev);
+}
+
+static inline struct mtk_chan *to_mtk_dma_chan(struct dma_chan *c)
+{
+ return container_of(c, struct mtk_chan, vc.chan);
+}
+
+static inline struct mtk_dma_desc *to_mtk_dma_desc
+ (struct dma_async_tx_descriptor *t)
+{
+ return container_of(t, struct mtk_dma_desc, vd.tx);
+}
+
+static void mtk_dma_chan_write(struct mtk_chan *c,
+ unsigned int reg, unsigned int val)
+{
+ writel(val, c->base + reg);
+}
+
+static unsigned int mtk_dma_chan_read(struct mtk_chan *c, unsigned int reg)
+{
+ return readl(c->base + reg);
+}
+
+static void mtk_dma_desc_free(struct virt_dma_desc *vd)
+{
+ struct dma_chan *chan = vd->tx.chan;
+ struct mtk_chan *c = to_mtk_dma_chan(chan);
+
+ kfree(c->desc);
+ c->desc = NULL;
+}
+
+static void mtk_dma_tx_flush(struct dma_chan *chan)
+{
+ struct mtk_chan *c = to_mtk_dma_chan(chan);
+
+ if (mtk_dma_chan_read(c, VFF_FLUSH) == 0U)
+ mtk_dma_chan_write(c, VFF_FLUSH, VFF_FLUSH_B);
+}
+
+static void mtk_dma_tx_write(struct dma_chan *chan)
+{
+ struct mtk_chan *c = to_mtk_dma_chan(chan);
+ unsigned int txcount = c->desc->len;
+ unsigned int len, send, left, wpt, wrap;
+
+ len = mtk_dma_chan_read(c, VFF_LEN);
+
+ while ((left = mtk_dma_chan_read(c, VFF_LEFT_SIZE)) > 0U) {
+ if (c->desc->len == 0U)
+ break;
+ send = min_t(unsigned int, left, c->desc->len);
+ wpt = mtk_dma_chan_read(c, VFF_WPT);
+ wrap = wpt & MTK_DMA_RING_WRAP ? 0U : MTK_DMA_RING_WRAP;
+
+ if ((wpt & (len - 1U)) + send < len)
+ mtk_dma_chan_write(c, VFF_WPT, wpt + send);
+ else
+ mtk_dma_chan_write(c, VFF_WPT,
+ ((wpt + send) & (len - 1U))
+ | wrap);
+
+ c->desc->len -= send;
+ }
+
+ if (txcount != c->desc->len) {
+ mtk_dma_chan_write(c, VFF_INT_EN, VFF_TX_INT_EN_B);
+ mtk_dma_tx_flush(chan);
+ }
+}
+
+static void mtk_dma_start_tx(struct mtk_chan *c)
+{
+ if (mtk_dma_chan_read(c, VFF_LEFT_SIZE) == 0U)
+ mtk_dma_chan_write(c, VFF_INT_EN, VFF_TX_INT_EN_B);
+ else
+ mtk_dma_tx_write(&c->vc.chan);
+
+ c->stop = false;
+}
+
+static void mtk_dma_get_rx_size(struct mtk_chan *c)
+{
+ unsigned int rx_size = mtk_dma_chan_read(c, VFF_LEN);
+ unsigned int rdptr, wrptr, wrreg, rdreg, count;
+
+ rdreg = mtk_dma_chan_read(c, VFF_RPT);
+ wrreg = mtk_dma_chan_read(c, VFF_WPT);
+ rdptr = rdreg & MTK_DMA_RING_SIZE;
+ wrptr = wrreg & MTK_DMA_RING_SIZE;
+ count = ((rdreg ^ wrreg) & MTK_DMA_RING_WRAP) ?
+ (wrptr + rx_size - rdptr) : (wrptr - rdptr);
+
+ c->rx_status = count;
+
+ mtk_dma_chan_write(c, VFF_RPT, wrreg);
+}
+
+static void mtk_dma_start_rx(struct mtk_chan *c)
+{
+ struct dma_chan *chan = &c->vc.chan;
+ struct mtk_dmadev *mtkd = to_mtk_dma_dev(chan->device);
+ struct mtk_dma_desc *d = c->desc;
+
+ if (mtk_dma_chan_read(c, VFF_VALID_SIZE) == 0U)
+ return;
+
+ if (d && vchan_next_desc(&c->vc)) {
+ mtk_dma_get_rx_size(c);
+ list_del(&d->vd.node);
+ vchan_cookie_complete(&d->vd);
+ } else {
+ spin_lock(&mtkd->lock);
+ if (list_empty(&mtkd->pending))
+ list_add_tail(&c->node, &mtkd->pending);
+ spin_unlock(&mtkd->lock);
+ tasklet_schedule(&mtkd->task);
+ }
+}
+
+static void mtk_dma_reset(struct mtk_chan *c)
+{
+ struct mtk_dmadev *mtkd = to_mtk_dma_dev(c->vc.chan.device);
+ u32 status;
+ int ret;
+
+ mtk_dma_chan_write(c, VFF_ADDR, 0);
+ mtk_dma_chan_write(c, VFF_THRE, 0);
+ mtk_dma_chan_write(c, VFF_LEN, 0);
+ mtk_dma_chan_write(c, VFF_RST, VFF_WARM_RST_B);
+
+ ret = readx_poll_timeout(readl,
+ c->base + VFF_EN,
+ status, status == 0, 10, 100);
+ if (ret) {
+ dev_err(c->vc.chan.device->dev,
+ "dma reset: fail, timeout\n");
+ return;
+ }
+
+ if (c->cfg.direction == DMA_DEV_TO_MEM)
+ mtk_dma_chan_write(c, VFF_RPT, 0);
+ else if (c->cfg.direction == DMA_MEM_TO_DEV)
+ mtk_dma_chan_write(c, VFF_WPT, 0);
+
+ if (mtkd->support_33bits)
+ mtk_dma_chan_write(c, VFF_4G_SUPPORT, VFF_4G_SUPPORT_CLR_B);
+}
+
+static void mtk_dma_stop(struct mtk_chan *c)
+{
+ u32 status;
+ int ret;
+
+ mtk_dma_chan_write(c, VFF_FLUSH, VFF_FLUSH_CLR_B);
+ /* Wait for flush */
+ ret = readx_poll_timeout(readl,
+ c->base + VFF_FLUSH,
+ status,
+ (status & VFF_FLUSH_B) != VFF_FLUSH_B,
+ 10, 100);
+ if (ret)
+ dev_err(c->vc.chan.device->dev,
+ "dma stop: polling FLUSH fail, DEBUG=0x%x\n",
+ mtk_dma_chan_read(c, VFF_DEBUG_STATUS));
+
+ /*set stop as 1 -> wait until en is 0 -> set stop as 0*/
+ mtk_dma_chan_write(c, VFF_STOP, VFF_STOP_B);
+ ret = readx_poll_timeout(readl,
+ c->base + VFF_EN,
+ status, status == 0, 10, 100);
+ if (ret)
+ dev_err(c->vc.chan.device->dev,
+ "dma stop: polling VFF_EN fail, DEBUG=0x%x\n",
+ mtk_dma_chan_read(c, VFF_DEBUG_STATUS));
+
+ mtk_dma_chan_write(c, VFF_STOP, VFF_STOP_CLR_B);
+ mtk_dma_chan_write(c, VFF_INT_EN, VFF_INT_EN_CLR_B);
+
+ if (c->cfg.direction == DMA_DEV_TO_MEM)
+ mtk_dma_chan_write(c, VFF_INT_FLAG, VFF_RX_INT_FLAG_CLR_B);
+ else
+ mtk_dma_chan_write(c, VFF_INT_FLAG, VFF_TX_INT_FLAG_CLR_B);
+
+ c->stop = true;
+}
+
+/*
+ * This callback schedules all pending channels. We could be more
+ * clever here by postponing allocation of the real DMA channels to
+ * this point, and freeing them when our virtual channel becomes idle.
+ *
+ * We would then need to deal with 'all channels in-use'
+ */
+static void mtk_dma_sched(unsigned long data)
+{
+ struct mtk_dmadev *mtkd = (struct mtk_dmadev *)data;
+ struct virt_dma_desc *vd;
+ struct mtk_chan *c;
+ unsigned long flags;
+ LIST_HEAD(head);
+
+ spin_lock_irq(&mtkd->lock);
+ list_splice_tail_init(&mtkd->pending, &head);
+ spin_unlock_irq(&mtkd->lock);
+
+ if (!list_empty(&head)) {
+ c = list_first_entry(&head, struct mtk_chan, node);
+
+ spin_lock_irqsave(&c->vc.lock, flags);
+ if (c->cfg.direction == DMA_DEV_TO_MEM) {
+ list_del_init(&c->node);
+ mtk_dma_start_rx(c);
+ } else if (c->cfg.direction == DMA_MEM_TO_DEV) {
+ vd = vchan_next_desc(&c->vc);
+ c->desc = to_mtk_dma_desc(&vd->tx);
+ list_del_init(&c->node);
+ mtk_dma_start_tx(c);
+ }
+ spin_unlock_irqrestore(&c->vc.lock, flags);
+ }
+}
+
+static int mtk_dma_alloc_chan_resources(struct dma_chan *chan)
+{
+ struct mtk_dmadev *mtkd = to_mtk_dma_dev(chan->device);
+ struct mtk_chan *c = to_mtk_dma_chan(chan);
+ int ret = -EBUSY;
+
+ pm_runtime_get_sync(mtkd->ddev.dev);
+
+ if (!mtkd->ch[chan->chan_id]) {
+ c->base = mtkd->mem_base[chan->chan_id];
+ mtkd->ch[chan->chan_id] = c;
+ ret = 1;
+ }
+ c->requested = false;
+ mtk_dma_reset(c);
+
+ return ret;
+}
+
+static void mtk_dma_free_chan_resources(struct dma_chan *chan)
+{
+ struct mtk_dmadev *mtkd = to_mtk_dma_dev(chan->device);
+ struct mtk_chan *c = to_mtk_dma_chan(chan);
+
+ if (c->requested) {
+ c->requested = false;
+ free_irq(mtkd->dma_irq[chan->chan_id], chan);
+ }
+
+ tasklet_kill(&mtkd->task);
+ tasklet_kill(&c->vc.task);
+
+ c->base = NULL;
+ mtkd->ch[chan->chan_id] = NULL;
+ vchan_free_chan_resources(&c->vc);
+
+ pm_runtime_put_sync(mtkd->ddev.dev);
+}
+
+static enum dma_status mtk_dma_tx_status(struct dma_chan *chan,
+ dma_cookie_t cookie,
+ struct dma_tx_state *txstate)
+{
+ struct mtk_chan *c = to_mtk_dma_chan(chan);
+ enum dma_status ret;
+ unsigned long flags;
+
+ if (!txstate)
+ return DMA_ERROR;
+
+ ret = dma_cookie_status(chan, cookie, txstate);
+ spin_lock_irqsave(&c->vc.lock, flags);
+ if (ret == DMA_IN_PROGRESS) {
+ c->rx_status = mtk_dma_chan_read(c, VFF_RPT)
+ & MTK_DMA_RING_SIZE;
+ dma_set_residue(txstate, c->rx_status);
+ } else if (ret == DMA_COMPLETE && c->cfg.direction == DMA_DEV_TO_MEM) {
+ dma_set_residue(txstate, c->rx_status);
+ } else {
+ dma_set_residue(txstate, 0);
+ }
+ spin_unlock_irqrestore(&c->vc.lock, flags);
+
+ return ret;
+}
+
+static struct dma_async_tx_descriptor *mtk_dma_prep_slave_sg
+ (struct dma_chan *chan, struct scatterlist *sgl,
+ unsigned int sglen, enum dma_transfer_direction dir,
+ unsigned long tx_flags, void *context)
+{
+ struct mtk_chan *c = to_mtk_dma_chan(chan);
+ struct scatterlist *sgent;
+ struct mtk_dma_desc *d;
+ struct mtk_dma_sg *sg;
+ unsigned int size, i, j, en;
+
+ en = 1;
+
+ if ((dir != DMA_DEV_TO_MEM) &&
+ (dir != DMA_MEM_TO_DEV)) {
+ dev_err(chan->device->dev, "bad direction\n");
+ return NULL;
+ }
+
+ /* Now allocate and setup the descriptor. */
+ d = kzalloc(sizeof(*d) + sglen * sizeof(d->sg[0]), GFP_ATOMIC);
+ if (!d)
+ return NULL;
+
+ d->dir = dir;
+
+ j = 0;
+ for_each_sg(sgl, sgent, sglen, i) {
+ d->sg[j].addr = sg_dma_address(sgent);
+ d->sg[j].en = en;
+ d->sg[j].fn = sg_dma_len(sgent) / en;
+ j++;
+ }
+
+ d->sglen = j;
+
+ if (dir == DMA_MEM_TO_DEV) {
+ for (size = i = 0; i < d->sglen; i++) {
+ sg = &d->sg[i];
+ size += sg->en * sg->fn;
+ }
+ d->len = size;
+ }
+
+ return vchan_tx_prep(&c->vc, &d->vd, tx_flags);
+}
+
+static void mtk_dma_issue_pending(struct dma_chan *chan)
+{
+ struct mtk_chan *c = to_mtk_dma_chan(chan);
+ struct virt_dma_desc *vd;
+ struct mtk_dmadev *mtkd;
+ unsigned long flags;
+
+ spin_lock_irqsave(&c->vc.lock, flags);
+ if (c->cfg.direction == DMA_DEV_TO_MEM) {
+ mtkd = to_mtk_dma_dev(chan->device);
+ if (vchan_issue_pending(&c->vc) && !c->desc) {
+ vd = vchan_next_desc(&c->vc);
+ c->desc = to_mtk_dma_desc(&vd->tx);
+ }
+ } else if (c->cfg.direction == DMA_MEM_TO_DEV) {
+ if (vchan_issue_pending(&c->vc) && !c->desc) {
+ vd = vchan_next_desc(&c->vc);
+ c->desc = to_mtk_dma_desc(&vd->tx);
+ mtk_dma_start_tx(c);
+ }
+ }
+ spin_unlock_irqrestore(&c->vc.lock, flags);
+}
+
+static irqreturn_t mtk_dma_rx_interrupt(int irq, void *dev_id)
+{
+ struct dma_chan *chan = (struct dma_chan *)dev_id;
+ struct mtk_chan *c = to_mtk_dma_chan(chan);
+ unsigned long flags;
+
+ spin_lock_irqsave(&c->vc.lock, flags);
+ mtk_dma_chan_write(c, VFF_INT_FLAG, VFF_RX_INT_FLAG_CLR_B);
+
+ mtk_dma_start_rx(c);
+
+ spin_unlock_irqrestore(&c->vc.lock, flags);
+
+ return IRQ_HANDLED;
+}
+
+static irqreturn_t mtk_dma_tx_interrupt(int irq, void *dev_id)
+{
+ struct dma_chan *chan = (struct dma_chan *)dev_id;
+ struct mtk_dmadev *mtkd = to_mtk_dma_dev(chan->device);
+ struct mtk_chan *c = to_mtk_dma_chan(chan);
+ struct mtk_dma_desc *d = c->desc;
+ unsigned long flags;
+
+ spin_lock_irqsave(&c->vc.lock, flags);
+ if (d->len != 0U) {
+ list_add_tail(&c->node, &mtkd->pending);
+ tasklet_schedule(&mtkd->task);
+ } else {
+ list_del(&d->vd.node);
+ vchan_cookie_complete(&d->vd);
+ }
+ spin_unlock_irqrestore(&c->vc.lock, flags);
+
+ mtk_dma_chan_write(c, VFF_INT_FLAG, VFF_TX_INT_FLAG_CLR_B);
+
+ return IRQ_HANDLED;
+}
+
+static int mtk_dma_slave_config(struct dma_chan *chan,
+ struct dma_slave_config *cfg)
+{
+ struct mtk_chan *c = to_mtk_dma_chan(chan);
+ struct mtk_dmadev *mtkd = to_mtk_dma_dev(c->vc.chan.device);
+ int ret;
+
+ c->cfg = *cfg;
+
+ if (cfg->direction == DMA_DEV_TO_MEM) {
+ unsigned int rx_len = cfg->src_addr_width * 1024;
+
+ mtk_dma_chan_write(c, VFF_ADDR, cfg->src_addr);
+ mtk_dma_chan_write(c, VFF_LEN, rx_len);
+ mtk_dma_chan_write(c, VFF_THRE, VFF_RX_THRE(rx_len));
+ mtk_dma_chan_write(c,
+ VFF_INT_EN, VFF_RX_INT_EN0_B
+ | VFF_RX_INT_EN1_B);
+ mtk_dma_chan_write(c, VFF_INT_FLAG, VFF_RX_INT_FLAG_CLR_B);
+ mtk_dma_chan_write(c, VFF_EN, VFF_EN_B);
+
+ if (!c->requested) {
+ c->requested = true;
+ ret = request_irq(mtkd->dma_irq[chan->chan_id],
+ mtk_dma_rx_interrupt,
+ IRQF_TRIGGER_NONE,
+ KBUILD_MODNAME, chan);
+ if (ret < 0) {
+ dev_err(chan->device->dev, "Can't request rx dma IRQ\n");
+ return -EINVAL;
+ }
+ }
+ } else if (cfg->direction == DMA_MEM_TO_DEV) {
+ unsigned int tx_len = cfg->dst_addr_width * 1024;
+
+ mtk_dma_chan_write(c, VFF_ADDR, cfg->dst_addr);
+ mtk_dma_chan_write(c, VFF_LEN, tx_len);
+ mtk_dma_chan_write(c, VFF_THRE, VFF_TX_THRE(tx_len));
+ mtk_dma_chan_write(c, VFF_INT_FLAG, VFF_TX_INT_FLAG_CLR_B);
+ mtk_dma_chan_write(c, VFF_EN, VFF_EN_B);
+
+ if (!c->requested) {
+ c->requested = true;
+ ret = request_irq(mtkd->dma_irq[chan->chan_id],
+ mtk_dma_tx_interrupt,
+ IRQF_TRIGGER_NONE,
+ KBUILD_MODNAME, chan);
+ if (ret < 0) {
+ dev_err(chan->device->dev, "Can't request tx dma IRQ\n");
+ return -EINVAL;
+ }
+ }
+ }
+
+ if (mtkd->support_33bits)
+ mtk_dma_chan_write(c, VFF_4G_SUPPORT, VFF_4G_SUPPORT_B);
+
+ if (mtk_dma_chan_read(c, VFF_EN) != VFF_EN_B) {
+ dev_err(chan->device->dev,
+ "config dma dir[%d] fail\n", cfg->direction);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int mtk_dma_terminate_all(struct dma_chan *chan)
+{
+ struct mtk_chan *c = to_mtk_dma_chan(chan);
+ unsigned long flags;
+
+ spin_lock_irqsave(&c->vc.lock, flags);
+ list_del_init(&c->node);
+ mtk_dma_stop(c);
+ spin_unlock_irqrestore(&c->vc.lock, flags);
+
+ return 0;
+}
+
+static int mtk_dma_device_pause(struct dma_chan *chan)
+{
+ /* just for check caps pass */
+ return -EINVAL;
+}
+
+static int mtk_dma_device_resume(struct dma_chan *chan)
+{
+ /* just for check caps pass */
+ return -EINVAL;
+}
+
+static void mtk_dma_free(struct mtk_dmadev *mtkd)
+{
+ tasklet_kill(&mtkd->task);
+ while (list_empty(&mtkd->ddev.channels) == 0) {
+ struct mtk_chan *c = list_first_entry(&mtkd->ddev.channels,
+ struct mtk_chan, vc.chan.device_node);
+
+ list_del(&c->vc.chan.device_node);
+ tasklet_kill(&c->vc.task);
+ devm_kfree(mtkd->ddev.dev, c);
+ }
+}
+
+static const struct of_device_id mtk_uart_dma_match[] = {
+ { .compatible = "mediatek,mt6577-uart-dma", },
+ { /* sentinel */ },
+};
+MODULE_DEVICE_TABLE(of, mtk_uart_dma_match);
+
+static int mtk_apdma_probe(struct platform_device *pdev)
+{
+ struct mtk_dmadev *mtkd;
+ struct resource *res;
+ struct mtk_chan *c;
+ unsigned int i;
+ int rc;
+
+ mtkd = devm_kzalloc(&pdev->dev, sizeof(*mtkd), GFP_KERNEL);
+ if (!mtkd)
+ return -ENOMEM;
+
+ for (i = 0; i < MTK_APDMA_CHANNELS; i++) {
+ res = platform_get_resource(pdev, IORESOURCE_MEM, i);
+ if (!res)
+ return -ENODEV;
+ mtkd->mem_base[i] = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(mtkd->mem_base[i]))
+ return PTR_ERR(mtkd->mem_base[i]);
+ }
+
+ for (i = 0; i < MTK_APDMA_CHANNELS; i++) {
+ mtkd->dma_irq[i] = platform_get_irq(pdev, i);
+ if ((int)mtkd->dma_irq[i] < 0) {
+ dev_err(&pdev->dev, "failed to get IRQ[%d]\n", i);
+ return -EINVAL;
+ }
+ }
+
+ mtkd->clk = devm_clk_get(&pdev->dev, NULL);
+ if (IS_ERR(mtkd->clk)) {
+ dev_err(&pdev->dev, "No clock specified\n");
+ return PTR_ERR(mtkd->clk);
+ }
+
+ if (of_property_read_bool(pdev->dev.of_node, "dma-33bits")) {
+ dev_info(&pdev->dev, "Support dma 33bits\n");
+ mtkd->support_33bits = true;
+ }
+
+ if (mtkd->support_33bits)
+ rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(33));
+ else
+ rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
+ if (rc)
+ return rc;
+
+ dma_cap_set(DMA_SLAVE, mtkd->ddev.cap_mask);
+ mtkd->ddev.device_alloc_chan_resources = mtk_dma_alloc_chan_resources;
+ mtkd->ddev.device_free_chan_resources = mtk_dma_free_chan_resources;
+ mtkd->ddev.device_tx_status = mtk_dma_tx_status;
+ mtkd->ddev.device_issue_pending = mtk_dma_issue_pending;
+ mtkd->ddev.device_prep_slave_sg = mtk_dma_prep_slave_sg;
+ mtkd->ddev.device_config = mtk_dma_slave_config;
+ mtkd->ddev.device_pause = mtk_dma_device_pause;
+ mtkd->ddev.device_resume = mtk_dma_device_resume;
+ mtkd->ddev.device_terminate_all = mtk_dma_terminate_all;
+ mtkd->ddev.src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE);
+ mtkd->ddev.dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE);
+ mtkd->ddev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
+ mtkd->ddev.residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT;
+ mtkd->ddev.dev = &pdev->dev;
+ INIT_LIST_HEAD(&mtkd->ddev.channels);
+ INIT_LIST_HEAD(&mtkd->pending);
+
+ spin_lock_init(&mtkd->lock);
+ tasklet_init(&mtkd->task, mtk_dma_sched, (unsigned long)mtkd);
+
+ mtkd->dma_requests = MTK_APDMA_DEFAULT_REQUESTS;
+ if (of_property_read_u32(pdev->dev.of_node,
+ "dma-requests", &mtkd->dma_requests)) {
+ dev_info(&pdev->dev,
+ "Missing dma-requests property, using %u.\n",
+ MTK_APDMA_DEFAULT_REQUESTS);
+ }
+
+ for (i = 0; i < MTK_APDMA_CHANNELS; i++) {
+ c = devm_kzalloc(mtkd->ddev.dev, sizeof(*c), GFP_KERNEL);
+ if (!c)
+ goto err_no_dma;
+
+ c->vc.desc_free = mtk_dma_desc_free;
+ vchan_init(&c->vc, &mtkd->ddev);
+ INIT_LIST_HEAD(&c->node);
+ }
+
+ pm_runtime_enable(&pdev->dev);
+ pm_runtime_set_active(&pdev->dev);
+
+ rc = dma_async_device_register(&mtkd->ddev);
+ if (rc)
+ goto rpm_disable;
+
+ platform_set_drvdata(pdev, mtkd);
+
+ if (pdev->dev.of_node) {
+ /* Device-tree DMA controller registration */
+ rc = of_dma_controller_register(pdev->dev.of_node,
+ of_dma_xlate_by_chan_id,
+ mtkd);
+ if (rc)
+ goto dma_remove;
+ }
+
+ return rc;
+
+dma_remove:
+ dma_async_device_unregister(&mtkd->ddev);
+rpm_disable:
+ pm_runtime_disable(&pdev->dev);
+err_no_dma:
+ mtk_dma_free(mtkd);
+ return rc;
+}
+
+static int mtk_apdma_remove(struct platform_device *pdev)
+{
+ struct mtk_dmadev *mtkd = platform_get_drvdata(pdev);
+
+ if (pdev->dev.of_node)
+ of_dma_controller_free(pdev->dev.of_node);
+
+ pm_runtime_disable(&pdev->dev);
+ pm_runtime_put_noidle(&pdev->dev);
+
+ dma_async_device_unregister(&mtkd->ddev);
+
+ mtk_dma_free(mtkd);
+
+ return 0;
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int mtk_dma_suspend(struct device *dev)
+{
+ struct mtk_dmadev *mtkd = dev_get_drvdata(dev);
+
+ if (!pm_runtime_suspended(dev))
+ clk_disable_unprepare(mtkd->clk);
+
+ return 0;
+}
+
+static int mtk_dma_resume(struct device *dev)
+{
+ int ret;
+ struct mtk_dmadev *mtkd = dev_get_drvdata(dev);
+
+ if (!pm_runtime_suspended(dev)) {
+ ret = clk_prepare_enable(mtkd->clk);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+#endif /* CONFIG_PM_SLEEP */
+
+#ifdef CONFIG_PM
+static int mtk_dma_runtime_suspend(struct device *dev)
+{
+ struct mtk_dmadev *mtkd = dev_get_drvdata(dev);
+
+ clk_disable_unprepare(mtkd->clk);
+
+ return 0;
+}
+
+static int mtk_dma_runtime_resume(struct device *dev)
+{
+ int ret;
+ struct mtk_dmadev *mtkd = dev_get_drvdata(dev);
+
+ ret = clk_prepare_enable(mtkd->clk);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+#endif /* CONFIG_PM */
+
+static const struct dev_pm_ops mtk_dma_pm_ops = {
+ SET_SYSTEM_SLEEP_PM_OPS(mtk_dma_suspend, mtk_dma_resume)
+ SET_RUNTIME_PM_OPS(mtk_dma_runtime_suspend,
+ mtk_dma_runtime_resume, NULL)
+};
+
+static struct platform_driver mtk_dma_driver = {
+ .probe = mtk_apdma_probe,
+ .remove = mtk_apdma_remove,
+ .driver = {
+ .name = KBUILD_MODNAME,
+ .pm = &mtk_dma_pm_ops,
+ .of_match_table = of_match_ptr(mtk_uart_dma_match),
+ },
+};
+
+module_platform_driver(mtk_dma_driver);
+
+MODULE_DESCRIPTION("MediaTek UART APDMA Controller Driver");
+MODULE_AUTHOR("Long Cheng <long.cheng@mediatek.com>");
+MODULE_LICENSE("GPL v2");
+
diff --git a/drivers/dma/mediatek/Kconfig b/drivers/dma/mediatek/Kconfig
index 27bac0b..d399624 100644
--- a/drivers/dma/mediatek/Kconfig
+++ b/drivers/dma/mediatek/Kconfig
@@ -1,4 +1,15 @@
+config DMA_MTK_UART
+ tristate "MediaTek SoCs APDMA support for UART"
+ depends on OF && SERIAL_8250_MT6577
+ select DMA_ENGINE
+ select DMA_VIRTUAL_CHANNELS
+ help
+ Support for the UART DMA engine found on MediaTek MTK SoCs.
+ when 8250 mtk uart is enabled, and if you want to using DMA,
+ you can enable the config. the DMA engine just only be used
+ with MediaTek Socs.
+
config MTK_HSDMA
tristate "MediaTek High-Speed DMA controller support"
depends on ARCH_MEDIATEK || COMPILE_TEST
diff --git a/drivers/dma/mediatek/Makefile b/drivers/dma/mediatek/Makefile
index 6e778f8..2f2efd9 100644
--- a/drivers/dma/mediatek/Makefile
+++ b/drivers/dma/mediatek/Makefile
@@ -1 +1,2 @@
+obj-$(CONFIG_DMA_MTK_UART) += 8250_mtk_dma.o
obj-$(CONFIG_MTK_HSDMA) += mtk-hsdma.o
^ permalink raw reply related
* dmaengine: fsl-qdma: add MODULE_LICENSE
From: Arnd Bergmann @ 2018-12-10 20:55 UTC (permalink / raw)
To: Vinod Koul
Cc: Arnd Bergmann, Dan Williams, Wen He, Jiaheng Fan, Peng Ma,
dmaengine, linux-kernel
The newly added driver lacks a MODULE_LICENSE tag, which now produces
a warning:
WARNING: modpost: missing MODULE_LICENSE() in drivers/dma/fsl-qdma.o
Add the license according to the SPDX specifier.
Fixes: 75628c149b0d ("dmaengine: fsl-qdma: Add qDMA controller driver for Layerscape SoCs")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
drivers/dma/fsl-qdma.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/dma/fsl-qdma.c b/drivers/dma/fsl-qdma.c
index c18e3492090b..aa1d0ae3d207 100644
--- a/drivers/dma/fsl-qdma.c
+++ b/drivers/dma/fsl-qdma.c
@@ -1255,4 +1255,5 @@ static struct platform_driver fsl_qdma_driver = {
module_platform_driver(fsl_qdma_driver);
MODULE_ALIAS("platform:fsl-qdma");
+MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("NXP Layerscape qDMA engine driver");
^ permalink raw reply related
* [v4,1/2] dmaengine: 8250_mtk_dma: add Mediatek uart DMA support
From: kbuild test robot @ 2018-12-10 10:07 UTC (permalink / raw)
To: Long Cheng
Cc: kbuild-all, Vinod Koul, Rob Herring, Mark Rutland,
Matthias Brugger, Dan Williams, Greg Kroah-Hartman, Jiri Slaby,
Sean Wang, Sean Wang, dmaengine, devicetree, linux-arm-kernel,
linux-mediatek, linux-kernel, linux-serial, srv_heupstream,
Yingjoe Chen, YT Shen
Hi Long,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on linus/master]
[also build test ERROR on v4.20-rc6 next-20181207]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
url: https://github.com/0day-ci/linux/commits/Long-Cheng/add-uart-DMA-function/20181210-125624
config: s390-allmodconfig (attached as .config)
compiler: s390x-linux-gnu-gcc (Debian 7.2.0-11) 7.2.0
reproduce:
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
GCC_VERSION=7.2.0 make.cross ARCH=s390
All error/warnings (new ones prefixed by >>):
>> drivers/dma/mediatek/8250_mtk_dma.c:29:30: error: 'CONFIG_SERIAL_8250_NR_UARTS' undeclared here (not in a function); did you mean 'CONFIG_SERIAL_RP2_NR_UARTS'?
#define MTK_APDMA_CHANNELS (CONFIG_SERIAL_8250_NR_UARTS * 2)
^
>> drivers/dma/mediatek/8250_mtk_dma.c:75:25: note: in expansion of macro 'MTK_APDMA_CHANNELS'
void __iomem *mem_base[MTK_APDMA_CHANNELS];
^~~~~~~~~~~~~~~~~~
vim +29 drivers/dma/mediatek/8250_mtk_dma.c
27
28 #define MTK_APDMA_DEFAULT_REQUESTS 127
> 29 #define MTK_APDMA_CHANNELS (CONFIG_SERIAL_8250_NR_UARTS * 2)
30
31 #define VFF_EN_B BIT(0)
32 #define VFF_STOP_B BIT(0)
33 #define VFF_FLUSH_B BIT(0)
34 #define VFF_4G_SUPPORT_B BIT(0)
35 #define VFF_RX_INT_EN0_B BIT(0) /*rx valid size >= vff thre*/
36 #define VFF_RX_INT_EN1_B BIT(1)
37 #define VFF_TX_INT_EN_B BIT(0) /*tx left size >= vff thre*/
38 #define VFF_WARM_RST_B BIT(0)
39 #define VFF_RX_INT_FLAG_CLR_B (BIT(0) | BIT(1))
40 #define VFF_TX_INT_FLAG_CLR_B 0
41 #define VFF_STOP_CLR_B 0
42 #define VFF_FLUSH_CLR_B 0
43 #define VFF_INT_EN_CLR_B 0
44 #define VFF_4G_SUPPORT_CLR_B 0
45
46 /* interrupt trigger level for tx */
47 #define VFF_TX_THRE(n) ((n) * 7 / 8)
48 /* interrupt trigger level for rx */
49 #define VFF_RX_THRE(n) ((n) * 3 / 4)
50
51 #define MTK_DMA_RING_SIZE 0xffffU
52 /* invert this bit when wrap ring head again*/
53 #define MTK_DMA_RING_WRAP 0x10000U
54
55 #define VFF_INT_FLAG 0x00
56 #define VFF_INT_EN 0x04
57 #define VFF_EN 0x08
58 #define VFF_RST 0x0c
59 #define VFF_STOP 0x10
60 #define VFF_FLUSH 0x14
61 #define VFF_ADDR 0x1c
62 #define VFF_LEN 0x24
63 #define VFF_THRE 0x28
64 #define VFF_WPT 0x2c
65 #define VFF_RPT 0x30
66 /*TX: the buffer size HW can read. RX: the buffer size SW can read.*/
67 #define VFF_VALID_SIZE 0x3c
68 /*TX: the buffer size SW can write. RX: the buffer size HW can write.*/
69 #define VFF_LEFT_SIZE 0x40
70 #define VFF_DEBUG_STATUS 0x50
71 #define VFF_4G_SUPPORT 0x54
72
73 struct mtk_dmadev {
74 struct dma_device ddev;
> 75 void __iomem *mem_base[MTK_APDMA_CHANNELS];
76 spinlock_t lock; /* dma dev lock */
77 struct tasklet_struct task;
78 struct list_head pending;
79 struct clk *clk;
80 unsigned int dma_requests;
81 bool support_33bits;
82 unsigned int dma_irq[MTK_APDMA_CHANNELS];
83 struct mtk_chan *ch[MTK_APDMA_CHANNELS];
84 };
85
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
^ permalink raw reply
* [V4,5/5] dmaengine: Documentation: Add documentation for multi chan testing
From: Seraj Alijan @ 2018-12-10 8:52 UTC (permalink / raw)
To: vkoul@kernel.org
Cc: dmaengine@vger.kernel.org, dan.j.williams@intel.com,
James Hartley, Sifan Naeem, Ed Blake, Seraj Mohammed
Modify documentation to add multi channel testing support.
Signed-off-by: Seraj Alijan <seraj.alijan@sondrel.com>
---
Documentation/driver-api/dmaengine/dmatest.rst | 109 +++++++++++++++++++++++--
1 file changed, 103 insertions(+), 6 deletions(-)
diff --git a/Documentation/driver-api/dmaengine/dmatest.rst b/Documentation/driver-api/dmaengine/dmatest.rst
index 7ce5e71..dd5263a 100644
--- a/Documentation/driver-api/dmaengine/dmatest.rst
+++ b/Documentation/driver-api/dmaengine/dmatest.rst
@@ -26,28 +26,43 @@ Part 2 - When dmatest is built as a module
Example of usage::
- % modprobe dmatest channel=dma0chan0 timeout=2000 iterations=1 run=1
+ % modprobe dmatest timeout=2000 iterations=1 channel=dma0chan0 run=1
...or::
% modprobe dmatest
- % echo dma0chan0 > /sys/module/dmatest/parameters/channel
% echo 2000 > /sys/module/dmatest/parameters/timeout
% echo 1 > /sys/module/dmatest/parameters/iterations
+ % echo dma0chan0 > /sys/module/dmatest/parameters/channel
% echo 1 > /sys/module/dmatest/parameters/run
...or on the kernel command line::
- dmatest.channel=dma0chan0 dmatest.timeout=2000 dmatest.iterations=1 dmatest.run=1
+ dmatest.timeout=2000 dmatest.iterations=1 dmatest.channel=dma0chan0 dmatest.run=1
+
+Example of multi-channel test usage:
+ % modprobe dmatest
+ % echo 2000 > /sys/module/dmatest/parameters/timeout
+ % echo 1 > /sys/module/dmatest/parameters/iterations
+ % echo dma0chan0 > /sys/module/dmatest/parameters/channel
+ % echo dma0chan1 > /sys/module/dmatest/parameters/channel
+ % echo dma0chan2 > /sys/module/dmatest/parameters/channel
+ % echo 1 > /sys/module/dmatest/parameters/run
+Note: the channel parameter should always be the last parameter set prior to
+running the test (setting run=1), this is because upon setting the channel
+parameter, that specific channel is requested using the dmaengine and a thread
+is created with the existing parameters. This thread is set as pending
+and will be executed once run is set to 1. Any parameters set after the thread
+is created are not applied.
.. hint::
available channel list could be extracted by running the following command::
% ls -1 /sys/class/dma/
-Once started a message like "dmatest: Started 1 threads using dma0chan0" is
-emitted. After that only test failure messages are reported until the test
-stops.
+Once started a message like " dmatest: Added 1 threads using dma0chan0" is
+emitted. A thread for that specific channel is created and is now pending, the
+pending thread is started once run is to 1.
Note that running a new test will not stop any in progress test.
@@ -112,3 +127,85 @@ Example::
The details of a data miscompare error are also emitted, but do not follow the
above format.
+
+Part 5 - Handling channel allocation
+====================================
+
+Allocating Channels
+-------------------
+
+Channels are required to be configured prior to starting the test run.
+Attempting to run the test without configuring the channels will fail.
+
+Example::
+
+ % echo 1 > /sys/module/dmatest/parameters/run
+ dmatest: Could not start test, no channels configured
+
+Channels are registered using the "channel" parameter. Channels can be requested by their
+name, once requested, the channel is registered and a pending thread is added to the test list.
+
+Example::
+
+ % echo dma0chan2 > /sys/module/dmatest/parameters/channel
+ dmatest: Added 1 threads using dma0chan2
+
+More channels can be added by repeating the example above.
+Reading back the channel parameter will return the name of last channel that was added successfully.
+
+Example::
+
+ % echo dma0chan1 > /sys/module/dmatest/parameters/channel
+ dmatest: Added 1 threads using dma0chan1
+ % echo dma0chan2 > /sys/module/dmatest/parameters/channel
+ dmatest: Added 1 threads using dma0chan2
+ % cat /sys/module/dmatest/parameters/channel
+ dma0chan2
+
+Another method of requesting channels is to request a channel with an empty string, Doing so
+will request all channels available to be tested:
+
+Example::
+
+ % echo "" > /sys/module/dmatest/parameters/channel
+ dmatest: Added 1 threads using dma0chan0
+ dmatest: Added 1 threads using dma0chan3
+ dmatest: Added 1 threads using dma0chan4
+ dmatest: Added 1 threads using dma0chan5
+ dmatest: Added 1 threads using dma0chan6
+ dmatest: Added 1 threads using dma0chan7
+ dmatest: Added 1 threads using dma0chan8
+
+At any point during the test configuration, reading the "test_list" parameter will
+print the list of currently pending tests.
+
+Example::
+
+ % cat /sys/module/dmatest/parameters/test_list
+ dmatest: 1 threads using dma0chan0
+ dmatest: 1 threads using dma0chan3
+ dmatest: 1 threads using dma0chan4
+ dmatest: 1 threads using dma0chan5
+ dmatest: 1 threads using dma0chan6
+ dmatest: 1 threads using dma0chan7
+ dmatest: 1 threads using dma0chan8
+
+Note: Channels will have to be configured for each test run as channel configurations do not
+carry across to the next test run.
+
+Releasing Channels
+-------------------
+
+Channels can be freed by setting run to 0.
+
+Example::
+ % echo dma0chan1 > /sys/module/dmatest/parameters/channel
+ dmatest: Added 1 threads using dma0chan1
+ % cat /sys/class/dma/dma0chan1/in_use
+ 1
+ % echo 0 > /sys/module/dmatest/parameters/run
+ % cat /sys/class/dma/dma0chan1/in_use
+ 0
+
+Channels allocated by previous test runs are automatically freed when a new
+channel is requested after completing a successful test run.
^ permalink raw reply related
* [V4,4/5] dmaengine: dmatest: Add transfer_size parameter
From: Seraj Alijan @ 2018-12-10 8:52 UTC (permalink / raw)
To: vkoul@kernel.org
Cc: dmaengine@vger.kernel.org, dan.j.williams@intel.com,
James Hartley, Sifan Naeem, Ed Blake, Seraj Mohammed
Existing transfer size "len" is either generated randomly or set to the
size of test_buf_size. In some cases we need to explicitly specify a
transfer size that is different from the buffer size and non aligned to
test the target device's ability to handle unaligned transfers.
This patch adds optional parameter "transfer_size" to allow setting
explicit transfer size for dma transfers.
Signed-off-by: Seraj Alijan <seraj.alijan@sondrel.com>
---
drivers/dma/dmatest.c | 28 ++++++++++++++++++++++------
1 file changed, 22 insertions(+), 6 deletions(-)
diff --git a/drivers/dma/dmatest.c b/drivers/dma/dmatest.c
index 6302ebe..2eea4ef 100644
--- a/drivers/dma/dmatest.c
+++ b/drivers/dma/dmatest.c
@@ -83,6 +83,10 @@ static int alignment = -1;
module_param(alignment, int, 0644);
MODULE_PARM_DESC(alignment, "Custom data address alignment taken as 2^(alignment) (default: not used (-1))");
+static unsigned int transfer_size;
+module_param(transfer_size, uint, 0644);
+MODULE_PARM_DESC(transfer_size, "Optional custom transfer size in bytes (default: not used (0))");
+
/**
* struct dmatest_params - test parameters.
* @buf_size: size of the memcpy test buffer
@@ -108,6 +112,7 @@ struct dmatest_params {
bool noverify;
bool norandom;
int alignment;
+ unsigned int transfer_size;
};
/**
@@ -643,15 +648,25 @@ static int dmatest_func(void *data)
total_tests++;
- if (params->norandom)
+ if (params->transfer_size) {
+ if (params->transfer_size >= params->buf_size) {
+ pr_err("%u-byte transfer size must be lower than %u-buffer size\n",
+ params->transfer_size, params->buf_size);
+ break;
+ }
+ len = params->transfer_size;
+ } else if (params->norandom) {
len = params->buf_size;
- else
+ } else {
len = dmatest_random() % params->buf_size + 1;
+ }
- len = (len >> align) << align;
- if (!len)
- len = 1 << align;
-
+ /* Do not alter transfer size explicitly defined by user */
+ if (!params->transfer_size) {
+ len = (len >> align) << align;
+ if (!len)
+ len = 1 << align;
+ }
total_len += len;
if (params->norandom) {
@@ -1047,6 +1062,7 @@ static void add_threaded_test(struct dmatest_info *info)
params->noverify = noverify;
params->norandom = norandom;
params->alignment = alignment;
+ params->transfer_size = transfer_size;
request_channels(info, DMA_MEMCPY);
request_channels(info, DMA_MEMSET);
^ permalink raw reply related
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