* [V3] dmaengine: axi-dmac: Don't check the number of frames for alignment
From: Alexandru Ardelean @ 2019-03-26 14:05 UTC (permalink / raw)
To: dmaengine; +Cc: Alexandru Ardelean
In 2D transfers (for the AXI DMAC), the number of frames (numf) represents
Y_LENGTH, and the length of a frame is X_LENGTH. 2D transfers are useful
for video transfers where screen resolutions ( X * Y ) are typically
aligned for X, but not for Y.
There is no requirement for Y_LENGTH to be aligned to the bus-width (or
anything), and this is also true for AXI DMAC.
Checking the Y_LENGTH for alignment causes false errors when initiating DMA
transfers. This change fixes this by checking only that the Y_LENGTH is
non-zero.
Fixes: 0e3b67b348b8 ("dmaengine: Add support for the Analog Devices AXI-DMAC DMA controller")
Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com>
---
Changelog v2->v3:
* Fixed typo in `Fixes` commit
drivers/dma/dma-axi-dmac.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/dma/dma-axi-dmac.c b/drivers/dma/dma-axi-dmac.c
index 0fe3a931d8d5..0e0c457a7b27 100644
--- a/drivers/dma/dma-axi-dmac.c
+++ b/drivers/dma/dma-axi-dmac.c
@@ -526,7 +526,7 @@ static struct dma_async_tx_descriptor *axi_dmac_prep_interleaved(
if (chan->hw_2d) {
if (!axi_dmac_check_len(chan, xt->sgl[0].size) ||
- !axi_dmac_check_len(chan, xt->numf))
+ xt->numf == 0)
return NULL;
if (xt->sgl[0].size + dst_icg > chan->max_length ||
xt->sgl[0].size + src_icg > chan->max_length)
^ permalink raw reply related
* dmaengine: axi-dmac: Infer synthesis configuration parameters hardware
From: Alexandru Ardelean @ 2019-03-26 13:06 UTC (permalink / raw)
To: dmaengine; +Cc: Lars-Peter Clausen, Alexandru Ardelean
From: Lars-Peter Clausen <lars@metafoo.de>
Some synthesis time configuration parameters of the DMA controller can be
inferred from the hardware itself.
Use this information as it is more reliably than the information specified
in the devicetree which might be outdated if the HDL project got changed.
Deprecate the devicetree properties that can be inferred from the hardware
itself.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com>
---
.../devicetree/bindings/dma/adi,axi-dmac.txt | 4 +--
drivers/dma/dma-axi-dmac.c | 32 ++++++++++++-------
2 files changed, 22 insertions(+), 14 deletions(-)
diff --git a/Documentation/devicetree/bindings/dma/adi,axi-dmac.txt b/Documentation/devicetree/bindings/dma/adi,axi-dmac.txt
index 47cb1d14b690..b38ee732efa9 100644
--- a/Documentation/devicetree/bindings/dma/adi,axi-dmac.txt
+++ b/Documentation/devicetree/bindings/dma/adi,axi-dmac.txt
@@ -18,7 +18,6 @@ Required properties for adi,channels sub-node:
Required channel sub-node properties:
- reg: Which channel this node refers to.
- - adi,length-width: Width of the DMA transfer length register.
- adi,source-bus-width,
adi,destination-bus-width: Width of the source or destination bus in bits.
- adi,source-bus-type,
@@ -28,7 +27,8 @@ Required channel sub-node properties:
1 (AXI_DMAC_TYPE_AXI_STREAM): Streaming AXI interface
2 (AXI_DMAC_TYPE_AXI_FIFO): FIFO interface
-Optional channel properties:
+Deprecated optional channel properties:
+ - adi,length-width: Width of the DMA transfer length register.
- adi,cyclic: Must be set if the channel supports hardware cyclic DMA
transfers.
- adi,2d: Must be set if the channel supports hardware 2D DMA transfers.
diff --git a/drivers/dma/dma-axi-dmac.c b/drivers/dma/dma-axi-dmac.c
index 0fe3a931d8d5..eecb367b4f3e 100644
--- a/drivers/dma/dma-axi-dmac.c
+++ b/drivers/dma/dma-axi-dmac.c
@@ -618,15 +618,6 @@ static int axi_dmac_parse_chan_dt(struct device_node *of_chan,
return ret;
chan->dest_width = val / 8;
- ret = of_property_read_u32(of_chan, "adi,length-width", &val);
- if (ret)
- return ret;
-
- if (val >= 32)
- chan->max_length = UINT_MAX;
- else
- chan->max_length = (1ULL << val) - 1;
-
chan->align_mask = max(chan->dest_width, chan->src_width) - 1;
if (axi_dmac_dest_is_mem(chan) && axi_dmac_src_is_mem(chan))
@@ -638,12 +629,27 @@ static int axi_dmac_parse_chan_dt(struct device_node *of_chan,
else
chan->direction = DMA_DEV_TO_DEV;
- chan->hw_cyclic = of_property_read_bool(of_chan, "adi,cyclic");
- chan->hw_2d = of_property_read_bool(of_chan, "adi,2d");
-
return 0;
}
+static void axi_dmac_detect_caps(struct axi_dmac *dmac)
+{
+ struct axi_dmac_chan *chan = &dmac->chan;
+
+ axi_dmac_write(dmac, AXI_DMAC_REG_FLAGS, AXI_DMAC_FLAG_CYCLIC);
+ if (axi_dmac_read(dmac, AXI_DMAC_REG_FLAGS) == AXI_DMAC_FLAG_CYCLIC)
+ chan->hw_cyclic = true;
+
+ axi_dmac_write(dmac, AXI_DMAC_REG_Y_LENGTH, 1);
+ if (axi_dmac_read(dmac, AXI_DMAC_REG_Y_LENGTH) == 1)
+ chan->hw_2d = true;
+
+ axi_dmac_write(dmac, AXI_DMAC_REG_X_LENGTH, 0xffffffff);
+ chan->max_length = axi_dmac_read(dmac, AXI_DMAC_REG_X_LENGTH);
+ if (chan->max_length != UINT_MAX)
+ chan->max_length++;
+}
+
static int axi_dmac_probe(struct platform_device *pdev)
{
struct device_node *of_channels, *of_chan;
@@ -716,6 +722,8 @@ static int axi_dmac_probe(struct platform_device *pdev)
if (ret < 0)
return ret;
+ axi_dmac_detect_caps(dmac);
+
axi_dmac_write(dmac, AXI_DMAC_REG_IRQ_MASK, 0x00);
ret = dma_async_device_register(dma_dev);
^ permalink raw reply related
* [v2] dmaengine: stm32-mdma: Revert "Add a check on read_u32_array"
From: Pierre Yves MORDRET @ 2019-03-26 8:55 UTC (permalink / raw)
To: Vinod Koul
Cc: Dan Williams, Maxime Coquelin, Alexandre Torgue, dmaengine,
linux-stm32, linux-arm-kernel, linux-kernel
On 3/25/19 5:28 PM, Vinod Koul wrote:
> On 25-03-19, 17:21, Pierre-Yves MORDRET wrote:
>> This reverts commit 906b40b246b0 ("Add a check on read_u32_array")
>
> This and patch title should contain:
> 906b40b246b0 ("dmaengine: stm32-mdma: Add a check on read_u32_array")
>
> I have fixed it up and applied.
Darn it, sorry.
Many thanks btw :)
>
> Thanks
>
>> As stated by bindings "st,ahb-addr-masks" is optional.
>> The statement inserted by this commit makes this property
>> mandatory and prevents MDMA to be probed in case property not present.
>>
>> Signed-off-by: Pierre-Yves MORDRET <pierre-yves.mordret@st.com>
>> ---
>> Version history:
>> v2:
>> * review commit message
>> v1:
>> * Initial
>> ---
>> ---
>> drivers/dma/stm32-mdma.c | 4 +---
>> 1 file changed, 1 insertion(+), 3 deletions(-)
>>
>> diff --git a/drivers/dma/stm32-mdma.c b/drivers/dma/stm32-mdma.c
>> index 4e0eede..ac0301b 100644
>> --- a/drivers/dma/stm32-mdma.c
>> +++ b/drivers/dma/stm32-mdma.c
>> @@ -1578,11 +1578,9 @@ static int stm32_mdma_probe(struct platform_device *pdev)
>>
>> dmadev->nr_channels = nr_channels;
>> dmadev->nr_requests = nr_requests;
>> - ret = device_property_read_u32_array(&pdev->dev, "st,ahb-addr-masks",
>> + device_property_read_u32_array(&pdev->dev, "st,ahb-addr-masks",
>> dmadev->ahb_addr_masks,
>> count);
>> - if (ret)
>> - return ret;
>> dmadev->nr_ahb_addr_masks = count;
>>
>> res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>> --
>> 2.7.4
>
^ permalink raw reply
* [v2,1/1] dmaengine: imx-sdma: revert: add clock ratio 1:1 check
From: Fugang Duan @ 2019-03-26 2:10 UTC (permalink / raw)
To: Angus Ainslie, Lucas Stach
Cc: festevam@gmail.com, vinod.koul@intel.com,
dmaengine@vger.kernel.org
From: Angus Ainslie <angus@akkea.ca> Sent: Friday, March 22, 2019 9:20 PM
> Hi Lucas,
>
> On 2019-03-21 20:36, Andy Duan wrote:
> > This reverts commit 25aaa75df1e6 (dmaengine: imx-sdma: add clock ratio
> > 1:1 check) due to break SDMA function on i.MX6SX platform.
> >
> > Log:
> > imx-sdma 20ec000.sdma: Timeout waiting for CH0 ready
> >
> > Fixes: 25aaa75df1e6 (dmaengine: imx-sdma: add clock ratio 1:1 check)
> > Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
> > ---
> > drivers/dma/imx-sdma.c | 18 ++++--------------
> > 1 file changed, 4 insertions(+), 14 deletions(-)
> >
> > diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c index
> > 5f3c137..7fae4bf 100644
> > --- a/drivers/dma/imx-sdma.c
> > +++ b/drivers/dma/imx-sdma.c
> > @@ -441,8 +441,6 @@ struct sdma_engine {
> > unsigned int irq;
> > dma_addr_t bd0_phys;
> > struct sdma_buffer_descriptor *bd0;
> > - /* clock ratio for AHB:SDMA core. 1:1 is 1, 2:1 is 0*/
> > - bool clk_ratio;
> > };
> >
> > static int sdma_config_write(struct dma_chan *chan, @@ -665,11 +663,8
> > @@ static int sdma_run_channel0(struct sdma_engine
> > *sdma)
> > dev_err(sdma->dev, "Timeout waiting for CH0 ready\n");
> >
> > /* Set bits of CONFIG register with dynamic context switching */
> > - reg = readl(sdma->regs + SDMA_H_CONFIG);
> > - if ((reg & SDMA_H_CONFIG_CSM) == 0) {
> > - reg |= SDMA_H_CONFIG_CSM;
> > - writel_relaxed(reg, sdma->regs + SDMA_H_CONFIG);
> > - }
> > + if (readl(sdma->regs + SDMA_H_CONFIG) == 0)
> > + writel_relaxed(SDMA_H_CONFIG_CSM, sdma->regs +
> SDMA_H_CONFIG);
> >
> > return ret;
> > }
> > @@ -1852,9 +1847,6 @@ static int sdma_init(struct sdma_engine *sdma)
> > if (ret)
> > goto disable_clk_ipg;
> >
> > - if (clk_get_rate(sdma->clk_ahb) == clk_get_rate(sdma->clk_ipg))
> > - sdma->clk_ratio = 1;
> > -
> > /* Be sure SDMA has not started yet */
> > writel_relaxed(0, sdma->regs + SDMA_H_C0PTR);
> >
> > @@ -1895,10 +1887,8 @@ static int sdma_init(struct sdma_engine *sdma)
> > writel_relaxed(0x4050, sdma->regs + SDMA_CHN0ADDR);
> >
> > /* Set bits of CONFIG register but with static context switching */
> > - if (sdma->clk_ratio)
> > - writel_relaxed(SDMA_H_CONFIG_ACR, sdma->regs +
> SDMA_H_CONFIG);
> > - else
> > - writel_relaxed(0, sdma->regs + SDMA_H_CONFIG);
> > + /* FIXME: Check whether to set ACR bit depending on clock ratios */
> > + writel_relaxed(0, sdma->regs + SDMA_H_CONFIG);
>
> It looks like the automated check breaks some imx chips. Are you ok if I
> resubmit with the original devicetree switch ?
>
> I guess another way would be to have a different compatible string and have
> some kind of "quirks".
>
> Thanks
> Angus
Since current SDMA driver break imx legacy platforms, please apply the patch firstly.
Then we can submit the correct patch for clock ratio 1:1 check.
Andy
>
> >
> > writel_relaxed(ccb_phys, sdma->regs + SDMA_H_C0PTR);
^ permalink raw reply
* [v2] dmaengine: stm32-mdma: Revert "Add a check on read_u32_array"
From: Vinod Koul @ 2019-03-25 16:28 UTC (permalink / raw)
To: Pierre-Yves MORDRET
Cc: Dan Williams, Maxime Coquelin, Alexandre Torgue, dmaengine,
linux-stm32, linux-arm-kernel, linux-kernel
On 25-03-19, 17:21, Pierre-Yves MORDRET wrote:
> This reverts commit 906b40b246b0 ("Add a check on read_u32_array")
This and patch title should contain:
906b40b246b0 ("dmaengine: stm32-mdma: Add a check on read_u32_array")
I have fixed it up and applied.
Thanks
> As stated by bindings "st,ahb-addr-masks" is optional.
> The statement inserted by this commit makes this property
> mandatory and prevents MDMA to be probed in case property not present.
>
> Signed-off-by: Pierre-Yves MORDRET <pierre-yves.mordret@st.com>
> ---
> Version history:
> v2:
> * review commit message
> v1:
> * Initial
> ---
> ---
> drivers/dma/stm32-mdma.c | 4 +---
> 1 file changed, 1 insertion(+), 3 deletions(-)
>
> diff --git a/drivers/dma/stm32-mdma.c b/drivers/dma/stm32-mdma.c
> index 4e0eede..ac0301b 100644
> --- a/drivers/dma/stm32-mdma.c
> +++ b/drivers/dma/stm32-mdma.c
> @@ -1578,11 +1578,9 @@ static int stm32_mdma_probe(struct platform_device *pdev)
>
> dmadev->nr_channels = nr_channels;
> dmadev->nr_requests = nr_requests;
> - ret = device_property_read_u32_array(&pdev->dev, "st,ahb-addr-masks",
> + device_property_read_u32_array(&pdev->dev, "st,ahb-addr-masks",
> dmadev->ahb_addr_masks,
> count);
> - if (ret)
> - return ret;
> dmadev->nr_ahb_addr_masks = count;
>
> res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> --
> 2.7.4
^ permalink raw reply
* [v2] dmaengine: stm32-mdma: Revert "Add a check on read_u32_array"
From: Pierre Yves MORDRET @ 2019-03-25 16:21 UTC (permalink / raw)
To: Dan Williams, Vinod Koul, Maxime Coquelin, Alexandre Torgue,
dmaengine, linux-stm32, linux-arm-kernel, linux-kernel
Cc: Pierre-Yves MORDRET
This reverts commit 906b40b246b0 ("Add a check on read_u32_array")
As stated by bindings "st,ahb-addr-masks" is optional.
The statement inserted by this commit makes this property
mandatory and prevents MDMA to be probed in case property not present.
Signed-off-by: Pierre-Yves MORDRET <pierre-yves.mordret@st.com>
---
Version history:
v2:
* review commit message
v1:
* Initial
---
---
drivers/dma/stm32-mdma.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/dma/stm32-mdma.c b/drivers/dma/stm32-mdma.c
index 4e0eede..ac0301b 100644
--- a/drivers/dma/stm32-mdma.c
+++ b/drivers/dma/stm32-mdma.c
@@ -1578,11 +1578,9 @@ static int stm32_mdma_probe(struct platform_device *pdev)
dmadev->nr_channels = nr_channels;
dmadev->nr_requests = nr_requests;
- ret = device_property_read_u32_array(&pdev->dev, "st,ahb-addr-masks",
+ device_property_read_u32_array(&pdev->dev, "st,ahb-addr-masks",
dmadev->ahb_addr_masks,
count);
- if (ret)
- return ret;
dmadev->nr_ahb_addr_masks = count;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^ permalink raw reply related
* [v1] Revert "dmaengine: stm32-mdma: Add a check on read_u32_array"
From: Pierre Yves MORDRET @ 2019-03-25 16:17 UTC (permalink / raw)
To: Vinod Koul
Cc: Dan Williams, Maxime Coquelin, Alexandre Torgue, dmaengine,
linux-stm32, linux-arm-kernel, linux-kernel
On 3/25/19 4:25 PM, Vinod Koul wrote:
> On 25-03-19, 15:46, Pierre-Yves MORDRET wrote:
>
> Please use the right subsystem name dmaengine, revert is not a subsystem
> name!
ok. sorry. I thought revert keyword was correct.
>
>> This reverts commit 906b40b246b0acb54c4dc97e815cf734761c9820.
>
> This should use the cannonical form for commits commit-sha1: ("title....")
ok.
>>
>> As stated by bindings "st,ahb-addr-masks" is optional.
>> The statement inserted by this commit makes this property
>> mandatory and prevents MDMA to be probed in case property not present.
>>
>> Signed-off-by: Pierre-Yves MORDRET <pierre-yves.mordret@st.com>
>> ---
>> drivers/dma/stm32-mdma.c | 4 +---
>> 1 file changed, 1 insertion(+), 3 deletions(-)
>>
>> diff --git a/drivers/dma/stm32-mdma.c b/drivers/dma/stm32-mdma.c
>> index 4e0eede..ac0301b 100644
>> --- a/drivers/dma/stm32-mdma.c
>> +++ b/drivers/dma/stm32-mdma.c
>> @@ -1578,11 +1578,9 @@ static int stm32_mdma_probe(struct platform_device *pdev)
>>
>> dmadev->nr_channels = nr_channels;
>> dmadev->nr_requests = nr_requests;
>> - ret = device_property_read_u32_array(&pdev->dev, "st,ahb-addr-masks",
>> + device_property_read_u32_array(&pdev->dev, "st,ahb-addr-masks",
>> dmadev->ahb_addr_masks,
>> count);
>> - if (ret)
>> - return ret;
>> dmadev->nr_ahb_addr_masks = count;
>
> so if st,ahb-addr-masks is not present what value does count contain?
whether "st,ahb-addr-masks" present count will hold the number of mask.
otherwise sets to "0" by driver.
count = device_property_read_u32_array(&pdev->dev, "st,ahb-addr-masks",
NULL, 0);
if (count < 0)
count = 0;
>
>>
>> res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>> --
>> 2.7.4
>
^ permalink raw reply
* [v1] Revert "dmaengine: stm32-mdma: Add a check on read_u32_array"
From: Vinod Koul @ 2019-03-25 15:25 UTC (permalink / raw)
To: Pierre-Yves MORDRET
Cc: Dan Williams, Maxime Coquelin, Alexandre Torgue, dmaengine,
linux-stm32, linux-arm-kernel, linux-kernel
On 25-03-19, 15:46, Pierre-Yves MORDRET wrote:
Please use the right subsystem name dmaengine, revert is not a subsystem
name!
> This reverts commit 906b40b246b0acb54c4dc97e815cf734761c9820.
This should use the cannonical form for commits commit-sha1: ("title....")
>
> As stated by bindings "st,ahb-addr-masks" is optional.
> The statement inserted by this commit makes this property
> mandatory and prevents MDMA to be probed in case property not present.
>
> Signed-off-by: Pierre-Yves MORDRET <pierre-yves.mordret@st.com>
> ---
> drivers/dma/stm32-mdma.c | 4 +---
> 1 file changed, 1 insertion(+), 3 deletions(-)
>
> diff --git a/drivers/dma/stm32-mdma.c b/drivers/dma/stm32-mdma.c
> index 4e0eede..ac0301b 100644
> --- a/drivers/dma/stm32-mdma.c
> +++ b/drivers/dma/stm32-mdma.c
> @@ -1578,11 +1578,9 @@ static int stm32_mdma_probe(struct platform_device *pdev)
>
> dmadev->nr_channels = nr_channels;
> dmadev->nr_requests = nr_requests;
> - ret = device_property_read_u32_array(&pdev->dev, "st,ahb-addr-masks",
> + device_property_read_u32_array(&pdev->dev, "st,ahb-addr-masks",
> dmadev->ahb_addr_masks,
> count);
> - if (ret)
> - return ret;
> dmadev->nr_ahb_addr_masks = count;
so if st,ahb-addr-masks is not present what value does count contain?
>
> res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> --
> 2.7.4
^ permalink raw reply
* [v1] Revert "dmaengine: stm32-mdma: Add a check on read_u32_array"
From: Pierre Yves MORDRET @ 2019-03-25 14:46 UTC (permalink / raw)
To: Dan Williams, Vinod Koul, Maxime Coquelin, Alexandre Torgue,
dmaengine, linux-stm32, linux-arm-kernel, linux-kernel
Cc: Pierre-Yves MORDRET
This reverts commit 906b40b246b0acb54c4dc97e815cf734761c9820.
As stated by bindings "st,ahb-addr-masks" is optional.
The statement inserted by this commit makes this property
mandatory and prevents MDMA to be probed in case property not present.
Signed-off-by: Pierre-Yves MORDRET <pierre-yves.mordret@st.com>
---
drivers/dma/stm32-mdma.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/dma/stm32-mdma.c b/drivers/dma/stm32-mdma.c
index 4e0eede..ac0301b 100644
--- a/drivers/dma/stm32-mdma.c
+++ b/drivers/dma/stm32-mdma.c
@@ -1578,11 +1578,9 @@ static int stm32_mdma_probe(struct platform_device *pdev)
dmadev->nr_channels = nr_channels;
dmadev->nr_requests = nr_requests;
- ret = device_property_read_u32_array(&pdev->dev, "st,ahb-addr-masks",
+ device_property_read_u32_array(&pdev->dev, "st,ahb-addr-masks",
dmadev->ahb_addr_masks,
count);
- if (ret)
- return ret;
dmadev->nr_ahb_addr_masks = count;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^ permalink raw reply related
* dmaengine: pl08x: be fair when re-assigning physical channel
From: Jean-Nicolas Graux @ 2019-03-25 8:15 UTC (permalink / raw)
To: Vinod Koul
Cc: Linus Walleij, linux-arm-kernel@lists.infradead.org,
dmaengine@vger.kernel.org
On 3/25/19 6:13 AM, Vinod Koul wrote:
> On 04-03-19, 16:03, Jean-Nicolas Graux wrote:
>> Current way we find a waiting virtual channel for the next transfer
>> at the time one physical channel becomes free is not really fair.
>>
>> More in details, in case there is more than one channel waiting at a time,
>> by just going through the arrays of memcpy and slave channels and stopping
>> as soon as state match waiting state, channels with high indexes can be
>> penalized.
>>
>> Whenever dma engine is substantially overloaded so that we constantly
>> get several channels waiting, channels with highest indexes might not
>> be served for a substantial time which in the worse case, might hang
>> task that wait for dma transfer to complete.
>>
>> This patch makes physical channel re-assignment more fair by storing
>> time in jiffies when a channel is put in waiting state. Whenever a
>> physical channel has to be re-assigned, this time is used to select
>> channel that is waiting for the longest time.
> Applied, thanks
>
Hello Vinod, You are welcome.
Regards. Jean-Nicolas.
^ permalink raw reply
* dmaengine: axi-dmac: extend support for ZynqMP arch
From: Vinod Koul @ 2019-03-25 5:54 UTC (permalink / raw)
To: Alexandru Ardelean; +Cc: dmaengine, Michael Hennerich
On 28-02-19, 14:39, Alexandru Ardelean wrote:
> From: Michael Hennerich <michael.hennerich@analog.com>
>
> The AXI DMAC driver is currently supported also on the Xilinx ZynqMP
> architecture. This change allows this driver to be enabled & used on it as
> well.
Applied, thanks
^ permalink raw reply
* dma:xgene-dma:move spin_lock_bh to spin_lock in tasklet
From: Vinod Koul @ 2019-03-25 5:52 UTC (permalink / raw)
To: Jeff Xie; +Cc: dan.j.williams, dmaengine, linux-kernel
On 20-03-19, 00:45, Jeff Xie wrote:
> It is unnecessary to call spin_lock_bh in a tasklet.
1. Please use the right subsystem name, dmaengine: xxx (you cna find
that by git log on that subsystem)
2. Space after each :, like dmaengine: xgene-dma: move...
3. Please explain a bit more about the change on why it is unnecessary
:)
Nevertheless, I have fixed 1 & 2 above and applied it
^ permalink raw reply
* dmaengine: pl08x: be fair when re-assigning physical channel
From: Vinod Koul @ 2019-03-25 5:13 UTC (permalink / raw)
To: Jean-Nicolas Graux; +Cc: Linus Walleij, linux-arm-kernel, dmaengine
On 04-03-19, 16:03, Jean-Nicolas Graux wrote:
> Current way we find a waiting virtual channel for the next transfer
> at the time one physical channel becomes free is not really fair.
>
> More in details, in case there is more than one channel waiting at a time,
> by just going through the arrays of memcpy and slave channels and stopping
> as soon as state match waiting state, channels with high indexes can be
> penalized.
>
> Whenever dma engine is substantially overloaded so that we constantly
> get several channels waiting, channels with highest indexes might not
> be served for a substantial time which in the worse case, might hang
> task that wait for dma transfer to complete.
>
> This patch makes physical channel re-assignment more fair by storing
> time in jiffies when a channel is put in waiting state. Whenever a
> physical channel has to be re-assigned, this time is used to select
> channel that is waiting for the longest time.
Applied, thanks
^ permalink raw reply
* [V4] dmaengine: axi-dmac: Split too large segments
From: Vinod Koul @ 2019-03-25 5:04 UTC (permalink / raw)
To: Alexandru Ardelean
Cc: dmaengine, andy.shevchenko, Lars-Peter Clausen, Bogdan Togorean
On 08-03-19, 15:02, Alexandru Ardelean wrote:
> From: Lars-Peter Clausen <lars@metafoo.de>
>
> The axi-dmac driver currently rejects transfers with segments that are
> larger than what the hardware can handle.
>
> Re-work the driver so that these large segments are split into multiple
> segments instead where each segment is smaller or equal to the maximum
> segment size.
>
> This allows the driver to handle transfers with segments of arbitrary size.
Applied, thanks
^ permalink raw reply
* [v2] dmaengine: pl330: introduce debugfs interface
From: Vinod Koul @ 2019-03-25 4:58 UTC (permalink / raw)
To: Katsuhiro Suzuki; +Cc: dmaengine, linux-kernel
On 17-03-19, 19:03, Katsuhiro Suzuki wrote:
> This patch adds debugfs interface to show the relationship between
> DMA threads (hardware resource for transferring data) and DMA
> channel ID of DMA slave.
>
> Typically, PL330 has many slaves than number of DMA threads.
> So sometimes PL330 cannot allocate DMA threads for all slaves even
> if a user specify DMA channel ID in devicetree. This interface will
> be useful for checking that DMA threads are allocated or not.
>
> Below is an output sample:
>
> $ sudo cat /sys/kernel/debug/ff1f0000.dmac
> PL330 physical channels:
> THREAD: CHANNEL:
> -------- -----
> 0 8
> 1 9
> 2 11
> 3 12
> 4 14
> 5 15
> 6 10
> 7 --
>
Applied, thanks
^ permalink raw reply
* [3/3] dmaengine: edma: make edma_filter_fn private
From: Vinod Koul @ 2019-03-25 4:56 UTC (permalink / raw)
To: Arnd Bergmann
Cc: Mark Brown, Peter Ujfalusi, dmaengine, alsa-devel, Dan Williams,
linux-kernel
On 07-03-19, 16:16, Arnd Bergmann wrote:
> With the audio driver no longer referring to this function, it
> can be made private to the dmaengine driver itself, and the
> header file removed.
Applied, thanks
^ permalink raw reply
* [2/3] dmaengine: omap-dma: make omap_dma_filter_fn private
From: Vinod Koul @ 2019-03-25 4:56 UTC (permalink / raw)
To: Peter Ujfalusi
Cc: Arnd Bergmann, Mark Brown, Janusz Krzysztofik, dmaengine,
alsa-devel, Dan Williams, linux-kernel
On 08-03-19, 16:32, Peter Ujfalusi wrote:
>
>
> On 07/03/2019 17.16, Arnd Bergmann wrote:
> > With the audio driver no longer referring to this function, it
> > can be made private to the dmaengine driver itself, and the
> > header file removed.
Applied, thanks
^ permalink raw reply
* [v3,1/2] dmaengine: tegra210-adma: use devm_clk_*() helpers
From: Vinod Koul @ 2019-03-25 4:54 UTC (permalink / raw)
To: Sameer Pujar
Cc: dan.j.williams, treding, jonathanh, dmaengine, linux-tegra,
linux-kernel
On 13-03-19, 17:02, Sameer Pujar wrote:
> adma driver is using pm_clk_*() interface for managing clock resources.
> With this it is observed that clocks remain ON always. This happens on
> Tegra devices which use BPMP co-processor to manage clock resources,
> where clocks are enabled during prepare phase. This is necessary because
> clocks to BPMP are always blocking. When pm_clk_*() interface is used on
> such Tegra devices, clock prepare count is not balanced till remove call
> happens for the driver and hence clocks are seen ON always. Thus this
> patch replaces pm_clk_*() with devm_clk_*() framework.
Both applied, thanks
^ permalink raw reply
* [2/2] dmaengine: milbeaut: Add Milbeaut AXI DMA controller
From: Kazuhiro Kasai @ 2019-03-25 4:15 UTC (permalink / raw)
To: vkoul, robh+dt, mark.rutland
Cc: dmaengine, devicetree, orito.takao, sugaya.taichi,
kanematsu.shinji, jaswinder.singh, masami.hiramatsu, linux-kernel,
Kazuhiro Kasai
Add Milbeaut AXI DMA controller. This DMA controller has
only capable of memory to memory transfer.
Signed-off-by: Kazuhiro Kasai <kasai.kazuhiro@socionext.com>
---
drivers/dma/Kconfig | 8 +
drivers/dma/Makefile | 1 +
drivers/dma/xdmac-milbeaut.c | 353 +++++++++++++++++++++++++++++++++++++++++++
3 files changed, 362 insertions(+)
create mode 100644 drivers/dma/xdmac-milbeaut.c
diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index 0b1dfb5..733fe5f 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -612,6 +612,14 @@ config UNIPHIER_MDMAC
UniPhier platform. This DMA controller is used as the external
DMA engine of the SD/eMMC controllers of the LD4, Pro4, sLD8 SoCs.
+config XDMAC_MILBEAUT
+ tristate "Milbeaut AXI DMA support"
+ depends on ARCH_MILBEAUT || COMPILE_TEST
+ select DMA_ENGINE
+ help
+ Support for Milbeaut AXI DMA controller driver. The DMA controller
+ has only memory to memory capability.
+
config XGENE_DMA
tristate "APM X-Gene DMA support"
depends on ARCH_XGENE || COMPILE_TEST
diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
index 6126e1c..4aab810 100644
--- a/drivers/dma/Makefile
+++ b/drivers/dma/Makefile
@@ -72,6 +72,7 @@ obj-$(CONFIG_TEGRA20_APB_DMA) += tegra20-apb-dma.o
obj-$(CONFIG_TEGRA210_ADMA) += tegra210-adma.o
obj-$(CONFIG_TIMB_DMA) += timb_dma.o
obj-$(CONFIG_UNIPHIER_MDMAC) += uniphier-mdmac.o
+obj-$(CONFIG_XDMAC_MILBEAUT) += xdmac-milbeaut.o
obj-$(CONFIG_XGENE_DMA) += xgene-dma.o
obj-$(CONFIG_ZX_DMA) += zx_dma.o
obj-$(CONFIG_ST_FDMA) += st_fdma.o
diff --git a/drivers/dma/xdmac-milbeaut.c b/drivers/dma/xdmac-milbeaut.c
new file mode 100644
index 0000000..7035c61
--- /dev/null
+++ b/drivers/dma/xdmac-milbeaut.c
@@ -0,0 +1,353 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Socionext Inc.
+ */
+
+#include <linux/bitfield.h>
+#include <linux/interrupt.h>
+#include <linux/module.h>
+#include <linux/of_dma.h>
+#include <linux/platform_device.h>
+
+#include "dmaengine.h"
+
+/* global register */
+#define M10V_XDACS 0x00
+
+/* channel local register */
+#define M10V_XDTBC 0x10
+#define M10V_XDSSA 0x14
+#define M10V_XDDSA 0x18
+#define M10V_XDSAC 0x1C
+#define M10V_XDDAC 0x20
+#define M10V_XDDCC 0x24
+#define M10V_XDDES 0x28
+#define M10V_XDDPC 0x2C
+#define M10V_XDDSD 0x30
+
+#define M10V_XDACS_XE BIT(28)
+
+#define M10V_XDSAC_SBS GENMASK(17, 16)
+#define M10V_XDSAC_SBL GENMASK(11, 8)
+
+#define M10V_XDDAC_DBS GENMASK(17, 16)
+#define M10V_XDDAC_DBL GENMASK(11, 8)
+
+#define M10V_XDDES_CE BIT(28)
+#define M10V_XDDES_SE BIT(24)
+#define M10V_XDDES_SA BIT(15)
+#define M10V_XDDES_TF GENMASK(23, 20)
+#define M10V_XDDES_EI BIT(1)
+#define M10V_XDDES_TI BIT(0)
+
+#define M10V_XDDSD_IS_MASK GENMASK(3, 0)
+#define M10V_XDDSD_IS_NORMAL 0x8
+
+#define M10V_XDMAC_BUSWIDTHS (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
+ BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
+ BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | \
+ BIT(DMA_SLAVE_BUSWIDTH_8_BYTES))
+
+#define M10V_XDMAC_CHAN_BASE(base, i) ((base) + (i) * 0x30)
+
+#define to_m10v_dma_chan(c) container_of((c), struct m10v_dma_chan, chan)
+
+struct m10v_dma_desc {
+ struct dma_async_tx_descriptor txd;
+ size_t len;
+ dma_addr_t src;
+ dma_addr_t dst;
+};
+
+struct m10v_dma_chan {
+ struct dma_chan chan;
+ struct m10v_dma_device *mdmac;
+ void __iomem *regs;
+ int irq;
+ struct m10v_dma_desc mdesc;
+ spinlock_t lock;
+};
+
+struct m10v_dma_device {
+ struct dma_device dmac;
+ void __iomem *regs;
+ unsigned int channels;
+ struct m10v_dma_chan mchan[0];
+};
+
+static void m10v_xdmac_enable_dma(struct m10v_dma_device *mdmac)
+{
+ unsigned int val;
+
+ val = readl(mdmac->regs + M10V_XDACS);
+ val &= ~M10V_XDACS_XE;
+ val |= FIELD_PREP(M10V_XDACS_XE, 1);
+ writel(val, mdmac->regs + M10V_XDACS);
+}
+
+static void m10v_xdmac_disable_dma(struct m10v_dma_device *mdmac)
+{
+ unsigned int val;
+
+ val = readl(mdmac->regs + M10V_XDACS);
+ val &= ~M10V_XDACS_XE;
+ val |= FIELD_PREP(M10V_XDACS_XE, 0);
+ writel(val, mdmac->regs + M10V_XDACS);
+}
+
+static void m10v_xdmac_config_chan(struct m10v_dma_chan *mchan)
+{
+ u32 val;
+
+ val = mchan->mdesc.len - 1;
+ writel(val, mchan->regs + M10V_XDTBC);
+
+ val = mchan->mdesc.src;
+ writel(val, mchan->regs + M10V_XDSSA);
+
+ val = mchan->mdesc.dst;
+ writel(val, mchan->regs + M10V_XDDSA);
+
+ val = readl(mchan->regs + M10V_XDSAC);
+ val &= ~(M10V_XDSAC_SBS | M10V_XDSAC_SBL);
+ val |= FIELD_PREP(M10V_XDSAC_SBS, 0x3) |
+ FIELD_PREP(M10V_XDSAC_SBL, 0xf);
+ writel(val, mchan->regs + M10V_XDSAC);
+
+ val = readl(mchan->regs + M10V_XDDAC);
+ val &= ~(M10V_XDDAC_DBS | M10V_XDDAC_DBL);
+ val |= FIELD_PREP(M10V_XDDAC_DBS, 0x3) |
+ FIELD_PREP(M10V_XDDAC_DBL, 0xf);
+ writel(val, mchan->regs + M10V_XDDAC);
+}
+
+static void m10v_xdmac_enable_chan(struct m10v_dma_chan *mchan)
+{
+ u32 val;
+
+ val = readl(mchan->regs + M10V_XDDES);
+ val &= ~(M10V_XDDES_CE |
+ M10V_XDDES_SE |
+ M10V_XDDES_TF |
+ M10V_XDDES_EI |
+ M10V_XDDES_TI);
+ val |= FIELD_PREP(M10V_XDDES_CE, 1) |
+ FIELD_PREP(M10V_XDDES_SE, 1) |
+ FIELD_PREP(M10V_XDDES_TF, 1) |
+ FIELD_PREP(M10V_XDDES_EI, 1) |
+ FIELD_PREP(M10V_XDDES_TI, 1);
+ writel(val, mchan->regs + M10V_XDDES);
+}
+
+static void m10v_xdmac_disable_chan(struct m10v_dma_chan *mchan)
+{
+ u32 val;
+
+ val = readl(mchan->regs + M10V_XDDES);
+ val &= ~M10V_XDDES_CE;
+ val |= FIELD_PREP(M10V_XDDES_CE, 0);
+ writel(val, mchan->regs + M10V_XDDES);
+}
+
+static irqreturn_t m10v_xdmac_irq(int irq, void *data)
+{
+ struct m10v_dma_chan *mchan = data;
+ unsigned long flags;
+ u32 val;
+
+ val = readl(mchan->regs + M10V_XDDSD);
+ val = FIELD_GET(M10V_XDDSD_IS_MASK, val);
+
+ if (val != M10V_XDDSD_IS_NORMAL)
+ dev_err(mchan->chan.device->dev, "XDMAC error with status: %x", val);
+
+ val = FIELD_PREP(M10V_XDDSD_IS_MASK, 0x0);
+ writel(val, mchan->regs + M10V_XDDSD);
+
+ spin_lock_irqsave(&mchan->lock, flags);
+ dma_cookie_complete(&mchan->mdesc.txd);
+ spin_unlock_irqrestore(&mchan->lock, flags);
+
+ if (mchan->mdesc.txd.flags & DMA_PREP_INTERRUPT)
+ dmaengine_desc_get_callback_invoke(&mchan->mdesc.txd, NULL);
+
+ return IRQ_HANDLED;
+}
+
+static void m10v_xdmac_issue_pending(struct dma_chan *chan)
+{
+ struct m10v_dma_chan *mchan = to_m10v_dma_chan(chan);
+
+ m10v_xdmac_config_chan(mchan);
+
+ m10v_xdmac_enable_chan(mchan);
+}
+
+static dma_cookie_t m10v_xdmac_tx_submit(struct dma_async_tx_descriptor *txd)
+{
+ struct m10v_dma_chan *mchan = to_m10v_dma_chan(txd->chan);
+ dma_cookie_t cookie;
+ unsigned long flags;
+
+ spin_lock_irqsave(&mchan->lock, flags);
+ cookie = dma_cookie_assign(txd);
+ spin_unlock_irqrestore(&mchan->lock, flags);
+
+ return cookie;
+}
+
+static struct dma_async_tx_descriptor *
+m10v_xdmac_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dst,
+ dma_addr_t src, size_t len, unsigned long flags)
+{
+ struct m10v_dma_chan *mchan = to_m10v_dma_chan(chan);
+
+ dma_async_tx_descriptor_init(&mchan->mdesc.txd, chan);
+ mchan->mdesc.txd.tx_submit = m10v_xdmac_tx_submit;
+ mchan->mdesc.txd.callback = NULL;
+ mchan->mdesc.txd.flags = flags;
+ mchan->mdesc.txd.cookie = -EBUSY;
+
+ mchan->mdesc.len = len;
+ mchan->mdesc.src = src;
+ mchan->mdesc.dst = dst;
+
+ return &mchan->mdesc.txd;
+}
+
+static int m10v_xdmac_device_terminate_all(struct dma_chan *chan)
+{
+ struct m10v_dma_chan *mchan = to_m10v_dma_chan(chan);
+
+ m10v_xdmac_disable_chan(mchan);
+
+ return 0;
+}
+
+static int m10v_xdmac_alloc_chan_resources(struct dma_chan *chan)
+{
+ struct m10v_dma_chan *mchan = to_m10v_dma_chan(chan);
+ unsigned long flags;
+
+ spin_lock_irqsave(&mchan->lock, flags);
+ dma_cookie_init(chan);
+ spin_unlock_irqrestore(&mchan->lock, flags);
+
+ return 1;
+}
+
+static int m10v_xdmac_probe(struct platform_device *pdev)
+{
+ struct device_node *np = pdev->dev.of_node;
+ struct m10v_dma_chan *mchan;
+ struct m10v_dma_device *mdmac;
+ struct resource *res;
+ unsigned int channels;
+ int ret, i;
+
+ ret = device_property_read_u32(&pdev->dev, "dma-channels", &channels);
+ if (ret) {
+ dev_err(&pdev->dev, "get dma-channels failed\n");
+ return ret;
+ }
+
+ mdmac = devm_kzalloc(&pdev->dev,
+ struct_size(mdmac, mchan, channels),
+ GFP_KERNEL);
+ if (!mdmac)
+ return -ENOMEM;
+
+ mdmac->channels = channels;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ mdmac->regs = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(mdmac->regs))
+ return PTR_ERR(mdmac->regs);
+
+ INIT_LIST_HEAD(&mdmac->dmac.channels);
+ for (i = 0; i < mdmac->channels; i++) {
+ mchan = &mdmac->mchan[i];
+ mchan->irq = platform_get_irq(pdev, i);
+ ret = devm_request_irq(&pdev->dev, mchan->irq, m10v_xdmac_irq,
+ IRQF_SHARED, dev_name(&pdev->dev), mchan);
+ if (ret) {
+ dev_err(&pdev->dev, "failed to request IRQ\n");
+ return ret;
+ }
+ mchan->mdmac = mdmac;
+ mchan->chan.device = &mdmac->dmac;
+ list_add_tail(&mchan->chan.device_node,
+ &mdmac->dmac.channels);
+
+ mchan->regs = M10V_XDMAC_CHAN_BASE(mdmac->regs, i);
+ spin_lock_init(&mchan->lock);
+ }
+
+ dma_cap_set(DMA_MEMCPY, mdmac->dmac.cap_mask);
+
+ mdmac->dmac.device_alloc_chan_resources = m10v_xdmac_alloc_chan_resources;
+ mdmac->dmac.device_prep_dma_memcpy = m10v_xdmac_prep_dma_memcpy;
+ mdmac->dmac.device_issue_pending = m10v_xdmac_issue_pending;
+ mdmac->dmac.device_tx_status = dma_cookie_status;
+ mdmac->dmac.device_terminate_all = m10v_xdmac_device_terminate_all;
+ mdmac->dmac.src_addr_widths = M10V_XDMAC_BUSWIDTHS;
+ mdmac->dmac.dst_addr_widths = M10V_XDMAC_BUSWIDTHS;
+ mdmac->dmac.residue_granularity = DMA_RESIDUE_GRANULARITY_DESCRIPTOR;
+ mdmac->dmac.dev = &pdev->dev;
+
+ platform_set_drvdata(pdev, mdmac);
+
+ m10v_xdmac_enable_dma(mdmac);
+
+ ret = dmaenginem_async_device_register(&mdmac->dmac);
+ if (ret) {
+ dev_err(&pdev->dev, "failed to register dmaengine device\n");
+ return ret;
+ }
+
+ ret = of_dma_controller_register(np, of_dma_simple_xlate, mdmac);
+ if (ret) {
+ dev_err(&pdev->dev, "failed to register OF DMA controller\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+static int m10v_xdmac_remove(struct platform_device *pdev)
+{
+ struct m10v_dma_chan *mchan;
+ struct m10v_dma_device *mdmac = platform_get_drvdata(pdev);
+ int i;
+
+ m10v_xdmac_disable_dma(mdmac);
+
+ for (i = 0; i < mdmac->channels; i++) {
+ mchan = &mdmac->mchan[i];
+ devm_free_irq(&pdev->dev, mchan->irq, mchan);
+ }
+
+ of_dma_controller_free(pdev->dev.of_node);
+
+ return 0;
+}
+
+static const struct of_device_id m10v_xdmac_dt_ids[] = {
+ {.compatible = "socionext,milbeaut-m10v-xdmac",},
+ {},
+};
+MODULE_DEVICE_TABLE(of, m10v_xdmac_dt_ids);
+
+static struct platform_driver m10v_xdmac_driver = {
+ .driver = {
+ .name = "m10v-xdmac",
+ .of_match_table = of_match_ptr(m10v_xdmac_dt_ids),
+ },
+ .probe = m10v_xdmac_probe,
+ .remove = m10v_xdmac_remove,
+};
+module_platform_driver(m10v_xdmac_driver);
+
+MODULE_AUTHOR("Kazuhiro Kasai <kasai.kazuhiro@socionext.com>");
+MODULE_DESCRIPTION("Socionext Milbeaut XDMAC driver");
+MODULE_LICENSE("GPL v2");
^ permalink raw reply related
* [1/2] dt-bindings: dmaengine: Add Milbeaut AXI DMA controller bindings
From: Kazuhiro Kasai @ 2019-03-25 4:15 UTC (permalink / raw)
To: vkoul, robh+dt, mark.rutland
Cc: dmaengine, devicetree, orito.takao, sugaya.taichi,
kanematsu.shinji, jaswinder.singh, masami.hiramatsu, linux-kernel,
Kazuhiro Kasai
Add Milbeaut AXI DMA controller bindings. This DMA controller has
only capable of memory to memory transfer.
Signed-off-by: Kazuhiro Kasai <kasai.kazuhiro@socionext.com>
---
.../devicetree/bindings/dma/xdmac-milbeaut.txt | 24 ++++++++++++++++++++++
1 file changed, 24 insertions(+)
create mode 100644 Documentation/devicetree/bindings/dma/xdmac-milbeaut.txt
diff --git a/Documentation/devicetree/bindings/dma/xdmac-milbeaut.txt b/Documentation/devicetree/bindings/dma/xdmac-milbeaut.txt
new file mode 100644
index 0000000..3a77fb1
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/xdmac-milbeaut.txt
@@ -0,0 +1,24 @@
+* Milbeaut AXI DMA Controller
+
+Milbeaut AXI DMA controller has only memory to memory transfer capability.
+
+* DMA controller
+
+Required property:
+- compatible: Should be "socionext,milbeaut-m10v-xdmac"
+- reg: Should contain DMA registers location and length.
+- interrupts: Should contain all of the per-channel DMA interrupts.
+- #dma-cells: Should be 1.
+- dma-channels: Number of DMA channels supported by the controller.
+
+Example:
+ xdmac0: dma-controller@1c250000 {
+ compatible = "socionext,milbeaut-m10v-xdmac";
+ reg = <0x1c250000 0x1000>;
+ interrupts = <0 17 0x4>,
+ <0 18 0x4>,
+ <0 19 0x4>,
+ <0 20 0x4>;
+ #dma-cells = <1>;
+ dma-channels = <4>;
+ };
^ permalink raw reply related
* dma: ti: fix a missing check in omap_dma_prep_dma_cyclic
From: Kangjie Lu @ 2019-03-23 22:39 UTC (permalink / raw)
To: kjlu
Cc: pakki001, Vinod Koul, Dan Williams, Peter Ujfalusi,
Janusz Krzysztofik, dmaengine, linux-kernel
It is invalid when "buf_len" is not aligned with "period_len".
The fix adds a check for the alignment.
Signed-off-by: Kangjie Lu <kjlu@umn.edu>
---
drivers/dma/ti/omap-dma.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/dma/ti/omap-dma.c b/drivers/dma/ti/omap-dma.c
index a4a931ddf6f6..5f0ce1975e52 100644
--- a/drivers/dma/ti/omap-dma.c
+++ b/drivers/dma/ti/omap-dma.c
@@ -1065,6 +1065,9 @@ static struct dma_async_tx_descriptor *omap_dma_prep_dma_cyclic(
unsigned es;
u32 burst;
+ if (buf_len % period_len)
+ return NULL;
+
if (dir == DMA_DEV_TO_MEM) {
dev_addr = c->cfg.src_addr;
dev_width = c->cfg.src_addr_width;
^ permalink raw reply related
* [v2,1/1] dmaengine: imx-sdma: revert: add clock ratio 1:1 check
From: Angus Ainslie @ 2019-03-22 13:20 UTC (permalink / raw)
To: Lucas Stach; +Cc: festevam, vinod.koul, dmaengine, Andy Duan
Hi Lucas,
On 2019-03-21 20:36, Andy Duan wrote:
> This reverts commit 25aaa75df1e6 (dmaengine: imx-sdma: add clock ratio
> 1:1 check) due to break SDMA function on i.MX6SX platform.
>
> Log:
> imx-sdma 20ec000.sdma: Timeout waiting for CH0 ready
>
> Fixes: 25aaa75df1e6 (dmaengine: imx-sdma: add clock ratio 1:1 check)
> Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
> ---
> drivers/dma/imx-sdma.c | 18 ++++--------------
> 1 file changed, 4 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c
> index 5f3c137..7fae4bf 100644
> --- a/drivers/dma/imx-sdma.c
> +++ b/drivers/dma/imx-sdma.c
> @@ -441,8 +441,6 @@ struct sdma_engine {
> unsigned int irq;
> dma_addr_t bd0_phys;
> struct sdma_buffer_descriptor *bd0;
> - /* clock ratio for AHB:SDMA core. 1:1 is 1, 2:1 is 0*/
> - bool clk_ratio;
> };
>
> static int sdma_config_write(struct dma_chan *chan,
> @@ -665,11 +663,8 @@ static int sdma_run_channel0(struct sdma_engine
> *sdma)
> dev_err(sdma->dev, "Timeout waiting for CH0 ready\n");
>
> /* Set bits of CONFIG register with dynamic context switching */
> - reg = readl(sdma->regs + SDMA_H_CONFIG);
> - if ((reg & SDMA_H_CONFIG_CSM) == 0) {
> - reg |= SDMA_H_CONFIG_CSM;
> - writel_relaxed(reg, sdma->regs + SDMA_H_CONFIG);
> - }
> + if (readl(sdma->regs + SDMA_H_CONFIG) == 0)
> + writel_relaxed(SDMA_H_CONFIG_CSM, sdma->regs + SDMA_H_CONFIG);
>
> return ret;
> }
> @@ -1852,9 +1847,6 @@ static int sdma_init(struct sdma_engine *sdma)
> if (ret)
> goto disable_clk_ipg;
>
> - if (clk_get_rate(sdma->clk_ahb) == clk_get_rate(sdma->clk_ipg))
> - sdma->clk_ratio = 1;
> -
> /* Be sure SDMA has not started yet */
> writel_relaxed(0, sdma->regs + SDMA_H_C0PTR);
>
> @@ -1895,10 +1887,8 @@ static int sdma_init(struct sdma_engine *sdma)
> writel_relaxed(0x4050, sdma->regs + SDMA_CHN0ADDR);
>
> /* Set bits of CONFIG register but with static context switching */
> - if (sdma->clk_ratio)
> - writel_relaxed(SDMA_H_CONFIG_ACR, sdma->regs + SDMA_H_CONFIG);
> - else
> - writel_relaxed(0, sdma->regs + SDMA_H_CONFIG);
> + /* FIXME: Check whether to set ACR bit depending on clock ratios */
> + writel_relaxed(0, sdma->regs + SDMA_H_CONFIG);
It looks like the automated check breaks some imx chips. Are you ok if I
resubmit with the original devicetree switch ?
I guess another way would be to have a different compatible string and
have some kind of "quirks".
Thanks
Angus
>
> writel_relaxed(ccb_phys, sdma->regs + SDMA_H_C0PTR);
^ permalink raw reply
* [2/6] dmaengine: sun6i: Add a quirk for additional mbus clock
From: Maxime Ripard @ 2019-03-22 13:03 UTC (permalink / raw)
To: Vinod Koul
Cc: Jernej Škrabec, wens, robh+dt, mark.rutland, dan.j.williams,
dmaengine, devicetree, linux-arm-kernel, linux-kernel,
linux-sunxi
On Fri, Mar 22, 2019 at 06:29:40PM +0530, Vinod Koul wrote:
> On 16-03-19, 12:23, Jernej Škrabec wrote:
> > Hi!
> >
> > Dne sobota, 16. marec 2019 ob 12:07:53 CET je Vinod Koul napisal(a):
> > > On 07-03-19, 17:58, Jernej Skrabec wrote:
> > > > H6 DMA controller needs additional mbus clock to be enabled.
> > > >
> > > > Add a quirk for it and handle it accordingly.
> > > >
> > > > Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
> > > > ---
> > > >
> > > > drivers/dma/sun6i-dma.c | 23 ++++++++++++++++++++++-
> > > > 1 file changed, 22 insertions(+), 1 deletion(-)
> > > >
> > > > diff --git a/drivers/dma/sun6i-dma.c b/drivers/dma/sun6i-dma.c
> > > > index 0cd13f17fc11..761555080325 100644
> > > > --- a/drivers/dma/sun6i-dma.c
> > > > +++ b/drivers/dma/sun6i-dma.c
> > > > @@ -129,6 +129,7 @@ struct sun6i_dma_config {
> > > >
> > > > u32 dst_burst_lengths;
> > > > u32 src_addr_widths;
> > > > u32 dst_addr_widths;
> > > >
> > > > + bool mbus_clk;
> > > >
> > > > };
> > > >
> > > > /*
> > > >
> > > > @@ -182,6 +183,7 @@ struct sun6i_dma_dev {
> > > >
> > > > struct dma_device slave;
> > > > void __iomem *base;
> > > > struct clk *clk;
> > > >
> > > > + struct clk *clk_mbus;
> > >
> > > So rather than have mbus_clk and then a ptr, why not use the ptr and use
> > > NULL value to check for..?
> > >
> >
> > I'm not sure what you mean here. clk_mbus will hold a reference to a clock
> > retrieved by devm_clk_get() so it has to be "struct clk *".
> >
> > What I'm missing here?
>
> IIRC there were two variable one clk ptr and one an integer to mark
> presence, you may be able to skip variable and use ptr..
If we're doing that, then we would effectively make it optional. That
DMA engine cannot operate without it.
Maxime
---
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
^ permalink raw reply
* [2/6] dmaengine: sun6i: Add a quirk for additional mbus clock
From: Vinod Koul @ 2019-03-22 12:59 UTC (permalink / raw)
To: Jernej Škrabec
Cc: maxime.ripard, wens, robh+dt, mark.rutland, dan.j.williams,
dmaengine, devicetree, linux-arm-kernel, linux-kernel,
linux-sunxi
On 16-03-19, 12:23, Jernej Škrabec wrote:
> Hi!
>
> Dne sobota, 16. marec 2019 ob 12:07:53 CET je Vinod Koul napisal(a):
> > On 07-03-19, 17:58, Jernej Skrabec wrote:
> > > H6 DMA controller needs additional mbus clock to be enabled.
> > >
> > > Add a quirk for it and handle it accordingly.
> > >
> > > Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
> > > ---
> > >
> > > drivers/dma/sun6i-dma.c | 23 ++++++++++++++++++++++-
> > > 1 file changed, 22 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/dma/sun6i-dma.c b/drivers/dma/sun6i-dma.c
> > > index 0cd13f17fc11..761555080325 100644
> > > --- a/drivers/dma/sun6i-dma.c
> > > +++ b/drivers/dma/sun6i-dma.c
> > > @@ -129,6 +129,7 @@ struct sun6i_dma_config {
> > >
> > > u32 dst_burst_lengths;
> > > u32 src_addr_widths;
> > > u32 dst_addr_widths;
> > >
> > > + bool mbus_clk;
> > >
> > > };
> > >
> > > /*
> > >
> > > @@ -182,6 +183,7 @@ struct sun6i_dma_dev {
> > >
> > > struct dma_device slave;
> > > void __iomem *base;
> > > struct clk *clk;
> > >
> > > + struct clk *clk_mbus;
> >
> > So rather than have mbus_clk and then a ptr, why not use the ptr and use
> > NULL value to check for..?
> >
>
> I'm not sure what you mean here. clk_mbus will hold a reference to a clock
> retrieved by devm_clk_get() so it has to be "struct clk *".
>
> What I'm missing here?
IIRC there were two variable one clk ptr and one an integer to mark
presence, you may be able to skip variable and use ptr..
^ permalink raw reply
* [v2,1/1] dmaengine: imx-sdma: revert: add clock ratio 1:1 check
From: Fugang Duan @ 2019-03-22 3:36 UTC (permalink / raw)
To: festevam@gmail.com, vinod.koul@intel.com, angus@akkea.ca
Cc: dmaengine@vger.kernel.org, Andy Duan
This reverts commit 25aaa75df1e6 (dmaengine: imx-sdma: add clock ratio
1:1 check) due to break SDMA function on i.MX6SX platform.
Log:
imx-sdma 20ec000.sdma: Timeout waiting for CH0 ready
Fixes: 25aaa75df1e6 (dmaengine: imx-sdma: add clock ratio 1:1 check)
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
---
drivers/dma/imx-sdma.c | 18 ++++--------------
1 file changed, 4 insertions(+), 14 deletions(-)
diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c
index 5f3c137..7fae4bf 100644
--- a/drivers/dma/imx-sdma.c
+++ b/drivers/dma/imx-sdma.c
@@ -441,8 +441,6 @@ struct sdma_engine {
unsigned int irq;
dma_addr_t bd0_phys;
struct sdma_buffer_descriptor *bd0;
- /* clock ratio for AHB:SDMA core. 1:1 is 1, 2:1 is 0*/
- bool clk_ratio;
};
static int sdma_config_write(struct dma_chan *chan,
@@ -665,11 +663,8 @@ static int sdma_run_channel0(struct sdma_engine *sdma)
dev_err(sdma->dev, "Timeout waiting for CH0 ready\n");
/* Set bits of CONFIG register with dynamic context switching */
- reg = readl(sdma->regs + SDMA_H_CONFIG);
- if ((reg & SDMA_H_CONFIG_CSM) == 0) {
- reg |= SDMA_H_CONFIG_CSM;
- writel_relaxed(reg, sdma->regs + SDMA_H_CONFIG);
- }
+ if (readl(sdma->regs + SDMA_H_CONFIG) == 0)
+ writel_relaxed(SDMA_H_CONFIG_CSM, sdma->regs + SDMA_H_CONFIG);
return ret;
}
@@ -1852,9 +1847,6 @@ static int sdma_init(struct sdma_engine *sdma)
if (ret)
goto disable_clk_ipg;
- if (clk_get_rate(sdma->clk_ahb) == clk_get_rate(sdma->clk_ipg))
- sdma->clk_ratio = 1;
-
/* Be sure SDMA has not started yet */
writel_relaxed(0, sdma->regs + SDMA_H_C0PTR);
@@ -1895,10 +1887,8 @@ static int sdma_init(struct sdma_engine *sdma)
writel_relaxed(0x4050, sdma->regs + SDMA_CHN0ADDR);
/* Set bits of CONFIG register but with static context switching */
- if (sdma->clk_ratio)
- writel_relaxed(SDMA_H_CONFIG_ACR, sdma->regs + SDMA_H_CONFIG);
- else
- writel_relaxed(0, sdma->regs + SDMA_H_CONFIG);
+ /* FIXME: Check whether to set ACR bit depending on clock ratios */
+ writel_relaxed(0, sdma->regs + SDMA_H_CONFIG);
writel_relaxed(ccb_phys, sdma->regs + SDMA_H_C0PTR);
^ permalink raw reply related
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