* [v2,10/15] dt-bindings: dma: imx-sdma: add i.mx6ul/6sx compatible name
From: Robin Gong @ 2019-04-26 8:06 UTC (permalink / raw)
To: broonie@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de,
festevam@gmail.com, robh+dt@kernel.org, mark.rutland@arm.com,
u.kleine-koenig@pengutronix.de, plyatov@gmail.com,
dan.j.williams@intel.com, catalin.marinas@arm.com,
will.deacon@arm.com
Cc: dl-linux-imx, linux-spi@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org,
devicetree@vger.kernel.org, kernel@pengutronix.de
Add i.mx6ul and i.mx6sx compatible name.
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
---
Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt | 2 ++
1 file changed, 2 insertions(+)
--
2.7.4
diff --git a/Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt b/Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt
index 9d8bbac..d024a83 100644
--- a/Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt
+++ b/Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt
@@ -9,6 +9,8 @@ Required properties:
"fsl,imx53-sdma"
"fsl,imx6q-sdma"
"fsl,imx7d-sdma"
+ "fsl,imx6sx-sdma"
+ "fsl,imx6ul-sdma"
"fsl,imx8mq-sdma"
The -to variants should be preferred since they allow to determine the
correct ROM script addresses needed for the driver to work without additional
^ permalink raw reply related
* [v2,09/15] dmaengine: imx-sdma: remove ERR009165 on i.mx6ul
From: Robin Gong @ 2019-04-26 8:05 UTC (permalink / raw)
To: broonie@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de,
festevam@gmail.com, robh+dt@kernel.org, mark.rutland@arm.com,
u.kleine-koenig@pengutronix.de, plyatov@gmail.com,
dan.j.williams@intel.com, catalin.marinas@arm.com,
will.deacon@arm.com
Cc: dl-linux-imx, linux-spi@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org,
devicetree@vger.kernel.org, kernel@pengutronix.de
ECSPI issue fixed from i.mx6ul at hardware level, no need
ERR009165 anymore on those chips such as i.mx8mq. Add i.mx6sx
from where i.mx6ul source.
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
---
drivers/dma/imx-sdma.c | 52 +++++++++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 51 insertions(+), 1 deletion(-)
--
2.7.4
diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c
index 352b0d5..3e912b6 100644
--- a/drivers/dma/imx-sdma.c
+++ b/drivers/dma/imx-sdma.c
@@ -419,6 +419,13 @@ struct sdma_driver_data {
int num_events;
struct sdma_script_start_addrs *script_addrs;
bool check_ratio;
+ /*
+ * ecspi ERR009165 fixed should be done in sdma script
+ * and it be fixed in soc from i.mx6ul.
+ * please get more information from below link:
+ * https://www.nxp.com/docs/en/errata/IMX6DQCE.pdf
+ */
+ bool ecspi_fixed;
};
struct sdma_engine {
@@ -539,6 +546,31 @@ static struct sdma_driver_data sdma_imx6q = {
.script_addrs = &sdma_script_imx6q,
};
+static struct sdma_script_start_addrs sdma_script_imx6sx = {
+ .ap_2_ap_addr = 642,
+ .uart_2_mcu_addr = 817,
+ .mcu_2_app_addr = 747,
+ .uartsh_2_mcu_addr = 1032,
+ .mcu_2_shp_addr = 960,
+ .app_2_mcu_addr = 683,
+ .shp_2_mcu_addr = 891,
+ .spdif_2_mcu_addr = 1100,
+ .mcu_2_spdif_addr = 1134,
+};
+
+static struct sdma_driver_data sdma_imx6sx = {
+ .chnenbl0 = SDMA_CHNENBL0_IMX35,
+ .num_events = 48,
+ .script_addrs = &sdma_script_imx6sx,
+};
+
+static struct sdma_driver_data sdma_imx6ul = {
+ .chnenbl0 = SDMA_CHNENBL0_IMX35,
+ .num_events = 48,
+ .script_addrs = &sdma_script_imx6sx,
+ .ecspi_fixed = true,
+};
+
static struct sdma_script_start_addrs sdma_script_imx7d = {
.ap_2_ap_addr = 644,
.uart_2_mcu_addr = 819,
@@ -562,6 +594,7 @@ static struct sdma_driver_data sdma_imx8mq = {
.num_events = 48,
.script_addrs = &sdma_script_imx7d,
.check_ratio = 1,
+ .ecspi_fixed = true,
};
static const struct platform_device_id sdma_devtypes[] = {
@@ -584,9 +617,15 @@ static const struct platform_device_id sdma_devtypes[] = {
.name = "imx6q-sdma",
.driver_data = (unsigned long)&sdma_imx6q,
}, {
+ .name = "imx6sx-sdma",
+ .driver_data = (unsigned long)&sdma_imx6sx,
+ }, {
.name = "imx7d-sdma",
.driver_data = (unsigned long)&sdma_imx7d,
}, {
+ .name = "imx6ul-sdma",
+ .driver_data = (unsigned long)&sdma_imx6ul,
+ }, {
.name = "imx8mq-sdma",
.driver_data = (unsigned long)&sdma_imx8mq,
}, {
@@ -602,7 +641,9 @@ static const struct of_device_id sdma_dt_ids[] = {
{ .compatible = "fsl,imx35-sdma", .data = &sdma_imx35, },
{ .compatible = "fsl,imx31-sdma", .data = &sdma_imx31, },
{ .compatible = "fsl,imx25-sdma", .data = &sdma_imx25, },
+ { .compatible = "fsl,imx6sx-sdma", .data = &sdma_imx6sx, },
{ .compatible = "fsl,imx7d-sdma", .data = &sdma_imx7d, },
+ { .compatible = "fsl,imx6ul-sdma", .data = &sdma_imx6ul, },
{ .compatible = "fsl,imx8mq-sdma", .data = &sdma_imx8mq, },
{ /* sentinel */ }
};
@@ -1166,8 +1207,17 @@ static int sdma_config_channel(struct dma_chan *chan)
if (sdmac->peripheral_type == IMX_DMATYPE_ASRC_SP ||
sdmac->peripheral_type == IMX_DMATYPE_ASRC)
sdma_set_watermarklevel_for_p2p(sdmac);
- } else
+ } else {
+ /*
+ * ERR009165 fixed from i.mx6ul, no errata need,
+ * set bit31 to let sdma script skip the errata.
+ */
+ if (sdmac->peripheral_type == IMX_DMATYPE_CSPI &&
+ sdmac->direction == DMA_MEM_TO_DEV &&
+ sdmac->sdma->drvdata->ecspi_fixed)
+ __set_bit(31, &sdmac->watermark_level);
__set_bit(sdmac->event_id0, sdmac->event_mask);
+ }
/* Address */
sdmac->shp_addr = sdmac->per_address;
^ permalink raw reply related
* [PATCH v2 06/15] spi: imx: fix ERR009165
From: Robin Gong @ 2019-04-26 8:05 UTC (permalink / raw)
To: broonie@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de,
festevam@gmail.com, robh+dt@kernel.org, mark.rutland@arm.com,
u.kleine-koenig@pengutronix.de, plyatov@gmail.com,
dan.j.williams@intel.com, catalin.marinas@arm.com,
will.deacon@arm.com
Cc: dl-linux-imx, linux-spi@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org,
devicetree@vger.kernel.org, kernel@pengutronix.de
In-Reply-To: <1556265512-9130-1-git-send-email-yibin.gong@nxp.com>
Change to XCH mode even in dma mode, please refer to the below
errata:
https://www.nxp.com/docs/en/errata/IMX6DQCE.pdf
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
---
drivers/spi/spi-imx.c | 11 +++++------
1 file changed, 5 insertions(+), 6 deletions(-)
diff --git a/drivers/spi/spi-imx.c b/drivers/spi/spi-imx.c
index 09c9a1e..eb56eac 100644
--- a/drivers/spi/spi-imx.c
+++ b/drivers/spi/spi-imx.c
@@ -585,8 +585,9 @@ static int mx51_ecspi_prepare_transfer(struct spi_imx_data *spi_imx,
ctrl |= mx51_ecspi_clkdiv(spi_imx, t->speed_hz, &clk);
spi_imx->spi_bus_clk = clk;
+ /* ERR009165: work in XHC mode as PIO */
if (spi_imx->usedma)
- ctrl |= MX51_ECSPI_CTRL_SMC;
+ ctrl &= ~MX51_ECSPI_CTRL_SMC;
writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
@@ -612,12 +613,14 @@ static int mx51_ecspi_prepare_transfer(struct spi_imx_data *spi_imx,
static void mx51_setup_wml(struct spi_imx_data *spi_imx)
{
+ u32 tx_wml = 0;
+
/*
* Configure the DMA register: setup the watermark
* and enable DMA request.
*/
writel(MX51_ECSPI_DMA_RX_WML(spi_imx->wml - 1) |
- MX51_ECSPI_DMA_TX_WML(spi_imx->wml) |
+ MX51_ECSPI_DMA_TX_WML(tx_wml) |
MX51_ECSPI_DMA_RXT_WML(spi_imx->wml) |
MX51_ECSPI_DMA_TEDEN | MX51_ECSPI_DMA_RXDEN |
MX51_ECSPI_DMA_RXTDEN, spi_imx->base + MX51_ECSPI_DMA);
@@ -1265,10 +1268,6 @@ static int spi_imx_sdma_init(struct device *dev, struct spi_imx_data *spi_imx,
{
int ret;
- /* use pio mode for i.mx6dl chip TKT238285 */
- if (of_machine_is_compatible("fsl,imx6dl"))
- return 0;
-
spi_imx->wml = spi_imx->devtype_data->fifo_size / 2;
/* Prepare for TX DMA: */
--
2.7.4
^ permalink raw reply related
* [v2,08/15] dt-bindings: spi: imx: add i.mx6ul to state errata fixed
From: Robin Gong @ 2019-04-26 8:05 UTC (permalink / raw)
To: broonie@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de,
festevam@gmail.com, robh+dt@kernel.org, mark.rutland@arm.com,
u.kleine-koenig@pengutronix.de, plyatov@gmail.com,
dan.j.williams@intel.com, catalin.marinas@arm.com,
will.deacon@arm.com
Cc: dl-linux-imx, linux-spi@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org,
devicetree@vger.kernel.org, kernel@pengutronix.de
ERR009165 fixed from i.mx6ul, add it to show the errata fixed.
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
---
Documentation/devicetree/bindings/spi/fsl-imx-cspi.txt | 2 ++
1 file changed, 2 insertions(+)
--
2.7.4
diff --git a/Documentation/devicetree/bindings/spi/fsl-imx-cspi.txt b/Documentation/devicetree/bindings/spi/fsl-imx-cspi.txt
index 2d32641..32c4263d 100644
--- a/Documentation/devicetree/bindings/spi/fsl-imx-cspi.txt
+++ b/Documentation/devicetree/bindings/spi/fsl-imx-cspi.txt
@@ -10,6 +10,8 @@ Required properties:
- "fsl,imx35-cspi" for SPI compatible with the one integrated on i.MX35
- "fsl,imx51-ecspi" for SPI compatible with the one integrated on i.MX51
- "fsl,imx53-ecspi" for SPI compatible with the one integrated on i.MX53 and later Soc
+ - "fsl,imx6ul-ecspi" ERR009165 fixed on i.MX6UL and later Soc
+ (https://www.nxp.com/docs/en/errata/IMX6DQCE.pdf)
- "fsl,imx8mq-ecspi" for SPI compatible with the one integrated on i.MX8M
- reg : Offset and length of the register set for the device
- interrupts : Should contain CSPI/eCSPI interrupt
^ permalink raw reply related
* [v2,07/15] spi: imx: remove ERR009165 workaround on i.mx6ul
From: Robin Gong @ 2019-04-26 8:05 UTC (permalink / raw)
To: broonie@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de,
festevam@gmail.com, robh+dt@kernel.org, mark.rutland@arm.com,
u.kleine-koenig@pengutronix.de, plyatov@gmail.com,
dan.j.williams@intel.com, catalin.marinas@arm.com,
will.deacon@arm.com
Cc: dl-linux-imx, linux-spi@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org,
devicetree@vger.kernel.org, kernel@pengutronix.de
ERR009165 fix on i.mx6ul and next chip, such as i.mx6ull/i.mx8mq/i.mx8mm.
Remove workaround on those chips. Add new i.mx6ul type for that.
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
---
drivers/spi/spi-imx.c | 39 +++++++++++++++++++++++++++++++++++----
1 file changed, 35 insertions(+), 4 deletions(-)
--
2.7.4
diff --git a/drivers/spi/spi-imx.c b/drivers/spi/spi-imx.c
index eb56eac..2e5e978 100644
--- a/drivers/spi/spi-imx.c
+++ b/drivers/spi/spi-imx.c
@@ -57,6 +57,7 @@ enum spi_imx_devtype {
IMX35_CSPI, /* CSPI on all i.mx except above */
IMX51_ECSPI, /* ECSPI on i.mx51 */
IMX53_ECSPI, /* ECSPI on i.mx53 and later */
+ IMX6UL_ECSPI, /* ERR009165 fix from i.mx6ul */
};
struct spi_imx_data;
@@ -128,7 +129,8 @@ static inline int is_imx35_cspi(struct spi_imx_data *d)
static inline int is_imx51_ecspi(struct spi_imx_data *d)
{
- return d->devtype_data->devtype == IMX51_ECSPI;
+ return d->devtype_data->devtype == IMX51_ECSPI ||
+ d->devtype_data->devtype == IMX6UL_ECSPI;
}
static inline int is_imx53_ecspi(struct spi_imx_data *d)
@@ -585,9 +587,16 @@ static int mx51_ecspi_prepare_transfer(struct spi_imx_data *spi_imx,
ctrl |= mx51_ecspi_clkdiv(spi_imx, t->speed_hz, &clk);
spi_imx->spi_bus_clk = clk;
- /* ERR009165: work in XHC mode as PIO */
- if (spi_imx->usedma)
- ctrl &= ~MX51_ECSPI_CTRL_SMC;
+ /*
+ * ERR009165: work in XHC mode instead of SMC as PIO on the chips
+ * before i.mx6ul.
+ */
+ if (spi_imx->usedma) {
+ if (spi_imx->devtype_data->devtype == IMX6UL_ECSPI)
+ ctrl |= MX51_ECSPI_CTRL_SMC;
+ else
+ ctrl &= ~MX51_ECSPI_CTRL_SMC;
+ }
writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
@@ -615,6 +624,8 @@ static void mx51_setup_wml(struct spi_imx_data *spi_imx)
{
u32 tx_wml = 0;
+ if (spi_imx->devtype_data->devtype == IMX6UL_ECSPI)
+ tx_wml = spi_imx->wml;
/*
* Configure the DMA register: setup the watermark
* and enable DMA request.
@@ -1012,6 +1023,22 @@ static struct spi_imx_devtype_data imx53_ecspi_devtype_data = {
.devtype = IMX53_ECSPI,
};
+static struct spi_imx_devtype_data imx6ul_ecspi_devtype_data = {
+ .intctrl = mx51_ecspi_intctrl,
+ .prepare_message = mx51_ecspi_prepare_message,
+ .prepare_transfer = mx51_ecspi_prepare_transfer,
+ .trigger = mx51_ecspi_trigger,
+ .rx_available = mx51_ecspi_rx_available,
+ .reset = mx51_ecspi_reset,
+ .setup_wml = mx51_setup_wml,
+ .fifo_size = 64,
+ .has_dmamode = true,
+ .dynamic_burst = true,
+ .has_slavemode = true,
+ .disable = mx51_ecspi_disable,
+ .devtype = IMX6UL_ECSPI,
+};
+
static const struct platform_device_id spi_imx_devtype[] = {
{
.name = "imx1-cspi",
@@ -1035,6 +1062,9 @@ static const struct platform_device_id spi_imx_devtype[] = {
.name = "imx53-ecspi",
.driver_data = (kernel_ulong_t) &imx53_ecspi_devtype_data,
}, {
+ .name = "imx6ul-ecspi",
+ .driver_data = (kernel_ulong_t) &imx6ul_ecspi_devtype_data,
+ }, {
/* sentinel */
}
};
@@ -1047,6 +1077,7 @@ static const struct of_device_id spi_imx_dt_ids[] = {
{ .compatible = "fsl,imx35-cspi", .data = &imx35_cspi_devtype_data, },
{ .compatible = "fsl,imx51-ecspi", .data = &imx51_ecspi_devtype_data, },
{ .compatible = "fsl,imx53-ecspi", .data = &imx53_ecspi_devtype_data, },
+ { .compatible = "fsl,imx6ul-ecspi", .data = &imx6ul_ecspi_devtype_data, },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, spi_imx_dt_ids);
^ permalink raw reply related
* [v2,06/15] spi: imx: fix ERR009165
From: Robin Gong @ 2019-04-26 8:05 UTC (permalink / raw)
To: broonie@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de,
festevam@gmail.com, robh+dt@kernel.org, mark.rutland@arm.com,
u.kleine-koenig@pengutronix.de, plyatov@gmail.com,
dan.j.williams@intel.com, catalin.marinas@arm.com,
will.deacon@arm.com
Cc: dl-linux-imx, linux-spi@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org,
devicetree@vger.kernel.org, kernel@pengutronix.de
Change to XCH mode even in dma mode, please refer to the below
errata:
https://www.nxp.com/docs/en/errata/IMX6DQCE.pdf
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
---
drivers/spi/spi-imx.c | 11 +++++------
1 file changed, 5 insertions(+), 6 deletions(-)
--
2.7.4
diff --git a/drivers/spi/spi-imx.c b/drivers/spi/spi-imx.c
index 09c9a1e..eb56eac 100644
--- a/drivers/spi/spi-imx.c
+++ b/drivers/spi/spi-imx.c
@@ -585,8 +585,9 @@ static int mx51_ecspi_prepare_transfer(struct spi_imx_data *spi_imx,
ctrl |= mx51_ecspi_clkdiv(spi_imx, t->speed_hz, &clk);
spi_imx->spi_bus_clk = clk;
+ /* ERR009165: work in XHC mode as PIO */
if (spi_imx->usedma)
- ctrl |= MX51_ECSPI_CTRL_SMC;
+ ctrl &= ~MX51_ECSPI_CTRL_SMC;
writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
@@ -612,12 +613,14 @@ static int mx51_ecspi_prepare_transfer(struct spi_imx_data *spi_imx,
static void mx51_setup_wml(struct spi_imx_data *spi_imx)
{
+ u32 tx_wml = 0;
+
/*
* Configure the DMA register: setup the watermark
* and enable DMA request.
*/
writel(MX51_ECSPI_DMA_RX_WML(spi_imx->wml - 1) |
- MX51_ECSPI_DMA_TX_WML(spi_imx->wml) |
+ MX51_ECSPI_DMA_TX_WML(tx_wml) |
MX51_ECSPI_DMA_RXT_WML(spi_imx->wml) |
MX51_ECSPI_DMA_TEDEN | MX51_ECSPI_DMA_RXDEN |
MX51_ECSPI_DMA_RXTDEN, spi_imx->base + MX51_ECSPI_DMA);
@@ -1265,10 +1268,6 @@ static int spi_imx_sdma_init(struct device *dev, struct spi_imx_data *spi_imx,
{
int ret;
- /* use pio mode for i.mx6dl chip TKT238285 */
- if (of_machine_is_compatible("fsl,imx6dl"))
- return 0;
-
spi_imx->wml = spi_imx->devtype_data->fifo_size / 2;
/* Prepare for TX DMA: */
^ permalink raw reply related
* [v2,05/15] dmaengine: imx-sdma: add mcu_2_ecspi script
From: Robin Gong @ 2019-04-26 8:05 UTC (permalink / raw)
To: broonie@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de,
festevam@gmail.com, robh+dt@kernel.org, mark.rutland@arm.com,
u.kleine-koenig@pengutronix.de, plyatov@gmail.com,
dan.j.williams@intel.com, catalin.marinas@arm.com,
will.deacon@arm.com
Cc: dl-linux-imx, linux-spi@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org,
devicetree@vger.kernel.org, kernel@pengutronix.de
Add mcu_2_ecspi script to fix ecspi errata ERR009165.
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
---
drivers/dma/imx-sdma.c | 3 +++
include/linux/platform_data/dma-imx-sdma.h | 1 +
2 files changed, 4 insertions(+)
--
2.7.4
diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c
index 86a31b4..352b0d5 100644
--- a/drivers/dma/imx-sdma.c
+++ b/drivers/dma/imx-sdma.c
@@ -924,6 +924,9 @@ static void sdma_get_pc(struct sdma_channel *sdmac,
emi_2_per = sdma->script_addrs->mcu_2_ata_addr;
break;
case IMX_DMATYPE_CSPI:
+ per_2_emi = sdma->script_addrs->app_2_mcu_addr;
+ emi_2_per = sdma->script_addrs->mcu_2_ecspi_addr;
+ break;
case IMX_DMATYPE_EXT:
case IMX_DMATYPE_SSI:
case IMX_DMATYPE_SAI:
diff --git a/include/linux/platform_data/dma-imx-sdma.h b/include/linux/platform_data/dma-imx-sdma.h
index 6eaa53c..f794fee 100644
--- a/include/linux/platform_data/dma-imx-sdma.h
+++ b/include/linux/platform_data/dma-imx-sdma.h
@@ -51,6 +51,7 @@ struct sdma_script_start_addrs {
/* End of v2 array */
s32 zcanfd_2_mcu_addr;
s32 zqspi_2_mcu_addr;
+ s32 mcu_2_ecspi_addr;
/* End of v3 array */
};
^ permalink raw reply related
* [PATCH v2 00/15] add ecspi ERR009165 for i.mx6/7 soc family
From: Robin Gong @ 2019-04-26 8:05 UTC (permalink / raw)
To: broonie@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de,
festevam@gmail.com, robh+dt@kernel.org, mark.rutland@arm.com,
u.kleine-koenig@pengutronix.de, plyatov@gmail.com,
dan.j.williams@intel.com, catalin.marinas@arm.com,
will.deacon@arm.com
Cc: dl-linux-imx, linux-spi@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org,
devicetree@vger.kernel.org, kernel@pengutronix.de
There is ecspi ERR009165 on i.mx6/7 soc family, which cause FIFO
transfer to be send twice in DMA mode. Please get more information from:
https://www.nxp.com/docs/en/errata/IMX6DQCE.pdf. The workaround is adding
new sdma ram script which works in XCH mode as PIO inside sdma instead
of SMC mode, meanwhile, 'TX_THRESHOLD' should be 0.
The issue should be exist on all legacy i.mx6/7 soc family before i.mx6ul,
NXP fix this design issue from i.mx6ul, so newer chips such as i.mx6ull/
i.mx8mq/i.mx8mm, don't need this workaroud anymore. This patch set
add new 'fsl,imx6ul-ecspi' for ecspi driver and 'ecspi_fixed' in sdma
driver to choose if need errata or not.
The first two reverted patches should be the same issue, though, it
seems 'fixed' by changing to other shp script. Hope Sean or Sascha could
have the chance to test this patch set if could fix their issues.
Besides, enable sdma support for i.mx8mm/8mq and fix ecspi1 not work
on i.mx8mm because the event id is zero.
PS:
Please get sdma firmware from below linux-firmware and copy it to your
local rootfs /lib/firmware/imx/sdma.
https://git.kernel.org/pub/scm/linux/kernel/git/firmware/linux-firmware.git/tree/imx/sdma
v2:
1. add commit log for reverted patches.
2. add comment for 'ecspi_fixed' in sdma driver.
3. add 'fsl,imx6sll-ecspi' compatible instead of 'fsl,imx6ul-ecspi'
rather than remove.
Robin Gong (15):
Revert "ARM: dts: imx6q: Use correct SDMA script for SPI5 core"
Revert "ARM: dts: imx6: Use correct SDMA script for SPI cores"
Revert "dmaengine: imx-sdma: refine to load context only once"
dmaengine: imx-sdma: remove dupilicated sdma_load_context
dma: engine: imx-sdma: add mcu_2_ecspi script
spi: imx: fix ERR009165
spi: imx: remove ERR009165 workaround on i.mx6ul
dt-bindings: spi: imx: add i.mx6ul to state errata fixed
dmaengine: imx-sdma: remove ERR009165 on i.mx6ul
dt-bindings: dma: imx-sdma: add i.mx6ul/6sx compatible name
dmaengine: imx-sdma: fix ecspi1 rx dma not work on i.mx8mm
ARM64: dts: freescale: imx8mm/8mq: update new compatible name for
ecspi and sdma
ARM: dts: imx6ul: add dma support on ecspi
ARM: dts: imx6sll: correct ecspi/sdma compatible
arm64: defconfig: Enable SDMA on i.mx8mq/8mm
.../devicetree/bindings/dma/fsl-imx-sdma.txt | 2 +
.../devicetree/bindings/spi/fsl-imx-cspi.txt | 2 +
arch/arm/boot/dts/imx6q.dtsi | 2 +-
arch/arm/boot/dts/imx6qdl.dtsi | 8 +--
arch/arm/boot/dts/imx6sll.dtsi | 10 ++--
arch/arm/boot/dts/imx6ul.dtsi | 8 +++
arch/arm64/boot/dts/freescale/imx8mm.dtsi | 14 ++---
arch/arm64/boot/dts/freescale/imx8mq.dtsi | 6 +-
arch/arm64/configs/defconfig | 3 +
drivers/dma/imx-sdma.c | 67 ++++++++++++++++------
drivers/spi/spi-imx.c | 46 ++++++++++++---
include/linux/platform_data/dma-imx-sdma.h | 1 +
12 files changed, 124 insertions(+), 45 deletions(-)
--
2.7.4
^ permalink raw reply
* [v2,04/15] dmaengine: imx-sdma: remove dupilicated sdma_load_context
From: Robin Gong @ 2019-04-26 8:05 UTC (permalink / raw)
To: broonie@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de,
festevam@gmail.com, robh+dt@kernel.org, mark.rutland@arm.com,
u.kleine-koenig@pengutronix.de, plyatov@gmail.com,
dan.j.williams@intel.com, catalin.marinas@arm.com,
will.deacon@arm.com
Cc: dl-linux-imx, linux-spi@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org,
devicetree@vger.kernel.org, kernel@pengutronix.de
Since sdma_transfer_init() will do sdma_load_context before any
sdma transfer, no need once more in sdma_config_channel().
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
---
drivers/dma/imx-sdma.c | 5 +----
1 file changed, 1 insertion(+), 4 deletions(-)
--
2.7.4
diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c
index 407a56e..86a31b4 100644
--- a/drivers/dma/imx-sdma.c
+++ b/drivers/dma/imx-sdma.c
@@ -1134,7 +1134,6 @@ static void sdma_set_watermarklevel_for_p2p(struct sdma_channel *sdmac)
static int sdma_config_channel(struct dma_chan *chan)
{
struct sdma_channel *sdmac = to_sdma_chan(chan);
- int ret;
sdma_disable_channel(chan);
@@ -1174,9 +1173,7 @@ static int sdma_config_channel(struct dma_chan *chan)
sdmac->watermark_level = 0; /* FIXME: M3_BASE_ADDRESS */
}
- ret = sdma_load_context(sdmac);
-
- return ret;
+ return 0;
}
static int sdma_set_channel_priority(struct sdma_channel *sdmac,
^ permalink raw reply related
* [v2,03/15] Revert "dmaengine: imx-sdma: refine to load context only once"
From: Robin Gong @ 2019-04-26 8:05 UTC (permalink / raw)
To: broonie@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de,
festevam@gmail.com, robh+dt@kernel.org, mark.rutland@arm.com,
u.kleine-koenig@pengutronix.de, plyatov@gmail.com,
dan.j.williams@intel.com, catalin.marinas@arm.com,
will.deacon@arm.com
Cc: dl-linux-imx, linux-spi@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org,
devicetree@vger.kernel.org, kernel@pengutronix.de
This reverts commit ad0d92d7ba6aecbe2705907c38ff8d8be4da1e9c, because
in spi-imx case, burst length may be changed dynamically.
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
---
drivers/dma/imx-sdma.c | 7 -------
1 file changed, 7 deletions(-)
--
2.7.4
diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c
index 99d9f43..407a56e 100644
--- a/drivers/dma/imx-sdma.c
+++ b/drivers/dma/imx-sdma.c
@@ -377,7 +377,6 @@ struct sdma_channel {
unsigned long watermark_level;
u32 shp_addr, per_addr;
enum dma_status status;
- bool context_loaded;
struct imx_dma_data data;
struct work_struct terminate_worker;
};
@@ -988,9 +987,6 @@ static int sdma_load_context(struct sdma_channel *sdmac)
int ret;
unsigned long flags;
- if (sdmac->context_loaded)
- return 0;
-
if (sdmac->direction == DMA_DEV_TO_MEM)
load_address = sdmac->pc_from_device;
else if (sdmac->direction == DMA_DEV_TO_DEV)
@@ -1033,8 +1029,6 @@ static int sdma_load_context(struct sdma_channel *sdmac)
spin_unlock_irqrestore(&sdma->channel_0_lock, flags);
- sdmac->context_loaded = true;
-
return ret;
}
@@ -1074,7 +1068,6 @@ static void sdma_channel_terminate_work(struct work_struct *work)
sdmac->desc = NULL;
spin_unlock_irqrestore(&sdmac->vc.lock, flags);
vchan_dma_desc_free_list(&sdmac->vc, &head);
- sdmac->context_loaded = false;
}
static int sdma_disable_channel_async(struct dma_chan *chan)
^ permalink raw reply related
* [v2,02/15] Revert "ARM: dts: imx6: Use correct SDMA script for SPI cores"
From: Robin Gong @ 2019-04-26 8:05 UTC (permalink / raw)
To: broonie@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de,
festevam@gmail.com, robh+dt@kernel.org, mark.rutland@arm.com,
u.kleine-koenig@pengutronix.de, plyatov@gmail.com,
dan.j.williams@intel.com, catalin.marinas@arm.com,
will.deacon@arm.com
Cc: dl-linux-imx, linux-spi@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org,
devicetree@vger.kernel.org, kernel@pengutronix.de
There are two ways for SDMA accessing SPBA devices: one is SDMA->AIPS
->SPBA(masterA port), another is SDMA->SPBA(masterC port). Please refer
to the 'Figure 58-1. i.MX 6Dual/6Quad SPBA connectivity' of i.mx6DQ
Reference Manual. SDMA provide the corresponding app_2_mcu/mcu_2_app and
shp_2_mcu/mcu_2_shp script for such two options. So both AIPS and SPBA
scripts should keep the same behaviour, the issue only caught in AIPS
script sounds not solide.
The issue is more likely as the ecspi errata
ERR009165(http://www.nxp.com/docs/en/errata/IMX6DQCE.pdf):
eCSPI: TXFIFO empty flag glitch can cause the current FIFO transfer to
be sent twice
So revert commit 'dd4b487b32a3' firstly.
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
---
arch/arm/boot/dts/imx6qdl.dtsi | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
--
2.7.4
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index b3a77bc..a90f217 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -339,7 +339,7 @@
clocks = <&clks IMX6QDL_CLK_ECSPI1>,
<&clks IMX6QDL_CLK_ECSPI1>;
clock-names = "ipg", "per";
- dmas = <&sdma 3 8 1>, <&sdma 4 8 2>;
+ dmas = <&sdma 3 7 1>, <&sdma 4 7 2>;
dma-names = "rx", "tx";
status = "disabled";
};
@@ -353,7 +353,7 @@
clocks = <&clks IMX6QDL_CLK_ECSPI2>,
<&clks IMX6QDL_CLK_ECSPI2>;
clock-names = "ipg", "per";
- dmas = <&sdma 5 8 1>, <&sdma 6 8 2>;
+ dmas = <&sdma 5 7 1>, <&sdma 6 7 2>;
dma-names = "rx", "tx";
status = "disabled";
};
@@ -367,7 +367,7 @@
clocks = <&clks IMX6QDL_CLK_ECSPI3>,
<&clks IMX6QDL_CLK_ECSPI3>;
clock-names = "ipg", "per";
- dmas = <&sdma 7 8 1>, <&sdma 8 8 2>;
+ dmas = <&sdma 7 7 1>, <&sdma 8 7 2>;
dma-names = "rx", "tx";
status = "disabled";
};
@@ -381,7 +381,7 @@
clocks = <&clks IMX6QDL_CLK_ECSPI4>,
<&clks IMX6QDL_CLK_ECSPI4>;
clock-names = "ipg", "per";
- dmas = <&sdma 9 8 1>, <&sdma 10 8 2>;
+ dmas = <&sdma 9 7 1>, <&sdma 10 7 2>;
dma-names = "rx", "tx";
status = "disabled";
};
^ permalink raw reply related
* [v2,01/15] Revert "ARM: dts: imx6q: Use correct SDMA script for SPI5 core"
From: Robin Gong @ 2019-04-26 8:05 UTC (permalink / raw)
To: broonie@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de,
festevam@gmail.com, robh+dt@kernel.org, mark.rutland@arm.com,
u.kleine-koenig@pengutronix.de, plyatov@gmail.com,
dan.j.williams@intel.com, catalin.marinas@arm.com,
will.deacon@arm.com
Cc: dl-linux-imx, linux-spi@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org,
devicetree@vger.kernel.org, kernel@pengutronix.de
There are two ways for SDMA accessing SPBA devices: one is SDMA->AIPS
->SPBA(masterA port), another is SDMA->SPBA(masterC port). Please refer
to the 'Figure 58-1. i.MX 6Dual/6Quad SPBA connectivity' of i.mx6DQ
Reference Manual. SDMA provide the corresponding app_2_mcu/mcu_2_app and
shp_2_mcu/mcu_2_shp script for such two options. So both AIPS and SPBA
scripts should keep the same behaviour, the issue only caught in AIPS
script sounds not solide.
The issue is more likely as the ecspi errata
ERR009165(http://www.nxp.com/docs/en/errata/IMX6DQCE.pdf):
eCSPI: TXFIFO empty flag glitch can cause the current FIFO transfer to
be sent twice
So revert commit 'df07101e1c4a' firstly.
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
---
arch/arm/boot/dts/imx6q.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--
2.7.4
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index d038f41..7175898 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -172,7 +172,7 @@
clocks = <&clks IMX6Q_CLK_ECSPI5>,
<&clks IMX6Q_CLK_ECSPI5>;
clock-names = "ipg", "per";
- dmas = <&sdma 11 8 1>, <&sdma 12 8 2>;
+ dmas = <&sdma 11 7 1>, <&sdma 12 7 2>;
dma-names = "rx", "tx";
status = "disabled";
};
^ permalink raw reply related
* [PATCH 1/1] dmaengine: mediatek-cqdma: fix wrong register usage in mtk_cqdma_start
From: shun-chih.yu @ 2019-04-25 3:53 UTC (permalink / raw)
To: Sean Wang, Vinod Koul, Matthias Brugger, Dan Williams
Cc: dmaengine, linux-arm-kernel, linux-mediatek, devicetree,
linux-kernel, srv_wsdupstream, Shun-Chih Yu
From: Shun-Chih Yu <shun-chih.yu@mediatek.com>
This patch fixes wrong register usage in the mtk_cqdma_start. The
destination register should be MTK_CQDMA_DST2 instead.
Fixes: b1f01e48df5a ("dmaengine: mediatek: Add MediaTek Command-Queue DMA controller for MT6765 SoC")
Signed-off-by: Shun-Chih Yu <shun-chih.yu@mediatek.com>
---
drivers/dma/mediatek/mtk-cqdma.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/dma/mediatek/mtk-cqdma.c b/drivers/dma/mediatek/mtk-cqdma.c
index 131f397..8148538 100644
--- a/drivers/dma/mediatek/mtk-cqdma.c
+++ b/drivers/dma/mediatek/mtk-cqdma.c
@@ -253,7 +253,7 @@ static void mtk_cqdma_start(struct mtk_cqdma_pchan *pc,
#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
mtk_dma_set(pc, MTK_CQDMA_DST2, cvd->dest >> MTK_CQDMA_ADDR2_SHFIT);
#else
- mtk_dma_set(pc, MTK_CQDMA_SRC2, 0);
+ mtk_dma_set(pc, MTK_CQDMA_DST2, 0);
#endif
/* setup the length */
--
1.7.9.5
^ permalink raw reply related
* [1/1] dmaengine: mediatek-cqdma: fix wrong register usage in mtk_cqdma_start
From: shun-chih.yu @ 2019-04-25 3:53 UTC (permalink / raw)
To: Sean Wang, Vinod Koul, Matthias Brugger, Dan Williams
Cc: dmaengine, linux-arm-kernel, linux-mediatek, devicetree,
linux-kernel, srv_wsdupstream, Shun-Chih Yu
From: Shun-Chih Yu <shun-chih.yu@mediatek.com>
This patch fixes wrong register usage in the mtk_cqdma_start. The
destination register should be MTK_CQDMA_DST2 instead.
Fixes: b1f01e48df5a ("dmaengine: mediatek: Add MediaTek Command-Queue DMA controller for MT6765 SoC")
Signed-off-by: Shun-Chih Yu <shun-chih.yu@mediatek.com>
---
drivers/dma/mediatek/mtk-cqdma.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/dma/mediatek/mtk-cqdma.c b/drivers/dma/mediatek/mtk-cqdma.c
index 131f397..8148538 100644
--- a/drivers/dma/mediatek/mtk-cqdma.c
+++ b/drivers/dma/mediatek/mtk-cqdma.c
@@ -253,7 +253,7 @@ static void mtk_cqdma_start(struct mtk_cqdma_pchan *pc,
#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
mtk_dma_set(pc, MTK_CQDMA_DST2, cvd->dest >> MTK_CQDMA_ADDR2_SHFIT);
#else
- mtk_dma_set(pc, MTK_CQDMA_SRC2, 0);
+ mtk_dma_set(pc, MTK_CQDMA_DST2, 0);
#endif
/* setup the length */
^ permalink raw reply related
* RE: [PATCH] dmaengine: rcar-dmac: Update copyright information
From: Yoshihiro Shimoda @ 2019-04-25 3:52 UTC (permalink / raw)
To: Geert Uytterhoeven, Niklas Söderlund
Cc: Simon Horman, dmaengine@vger.kernel.org, Linux-Renesas,
HIROYUKI YOKOYAMA
In-Reply-To: <CAMuHMdXLM0hkUva4AukBpYy+=mRQ_tWT4XCGb=ZGbuT5nYMzjA@mail.gmail.com>
Hi Geert-san,
> From: Geert Uytterhoeven, Sent: Wednesday, April 24, 2019 9:22 PM
>
> Hi Niklas, Shimoda-san,
>
> On Thu, Apr 11, 2019 at 5:18 PM Niklas Söderlund
> <niklas.soderlund@ragnatech.se> wrote:
> > On 2019-04-11 10:49:37 +0200, Simon Horman wrote:
> > > On Wed, Apr 10, 2019 at 08:26:57PM +0200, Niklas Söderlund wrote:
> > > Not strictly related, but is it appropriate to:
> > >
> > > 1. Move this driver and drivers/dma/sh/usb-dmac.c to drivers/dma/renesas/
>
> That may make sense...
>
> > > 2. Remove drivers/dma/sh/sudmac.c which appears unused
> >
> > I let someone with a better grasp of history answer this one. From my
> > side removing drivers which are unused seems like a good idea :-)
>
> There seem to be some (half-baked?) interaction between sudmac.c and
> drivers/usb/gadget/udc/r8a66597-udc.c and drivers/usb/renesas_usbhs/fifo.c.
> These don't seem to be used at all on Renesas ARM platforms, but
> CONFIG_USB_R8A66597_HCD is enabled in shmobile_defconfig and
> multi_v7_defconfig?
>
> Shimoda-san: can you please enlighten us?
> Thanks!
Sure.
- SH4A / sh7757 has SUDMAC. (any other Renesas ARM platforms don't have it).
# sh7757 is not public product though...
- At first, I added this SUDMAC support into r8a66597-udc.
- But, our direction is changed by some reason. So, we use renesas_usbhs driver anyway.
- The renesas_usbhs supports dmaengine, so I added dma/sh/sudmac driver.
- However, for some reasons (maybe I'm busy for other projects?),
I didn't add using the sudmac support into arch/sh/kernel/cpu/sh4a/setup-sh7757.c.
- So, no one uses both r8a66597-udc and sudmac now.
From 2013 (added the sudmac driver) to now, since no one integrated the sudmac for sh7757,
I think we can remove the driver.
Best regards,
Yoshihiro Shimoda
^ permalink raw reply
* dmaengine: rcar-dmac: Update copyright information
From: Yoshihiro Shimoda @ 2019-04-25 3:52 UTC (permalink / raw)
To: Geert Uytterhoeven, Niklas Söderlund
Cc: Simon Horman, dmaengine@vger.kernel.org, Linux-Renesas,
HIROYUKI YOKOYAMA
Hi Geert-san,
> From: Geert Uytterhoeven, Sent: Wednesday, April 24, 2019 9:22 PM
>
> Hi Niklas, Shimoda-san,
>
> On Thu, Apr 11, 2019 at 5:18 PM Niklas Söderlund
> <niklas.soderlund@ragnatech.se> wrote:
> > On 2019-04-11 10:49:37 +0200, Simon Horman wrote:
> > > On Wed, Apr 10, 2019 at 08:26:57PM +0200, Niklas Söderlund wrote:
> > > Not strictly related, but is it appropriate to:
> > >
> > > 1. Move this driver and drivers/dma/sh/usb-dmac.c to drivers/dma/renesas/
>
> That may make sense...
>
> > > 2. Remove drivers/dma/sh/sudmac.c which appears unused
> >
> > I let someone with a better grasp of history answer this one. From my
> > side removing drivers which are unused seems like a good idea :-)
>
> There seem to be some (half-baked?) interaction between sudmac.c and
> drivers/usb/gadget/udc/r8a66597-udc.c and drivers/usb/renesas_usbhs/fifo.c.
> These don't seem to be used at all on Renesas ARM platforms, but
> CONFIG_USB_R8A66597_HCD is enabled in shmobile_defconfig and
> multi_v7_defconfig?
>
> Shimoda-san: can you please enlighten us?
> Thanks!
Sure.
- SH4A / sh7757 has SUDMAC. (any other Renesas ARM platforms don't have it).
# sh7757 is not public product though...
- At first, I added this SUDMAC support into r8a66597-udc.
- But, our direction is changed by some reason. So, we use renesas_usbhs driver anyway.
- The renesas_usbhs supports dmaengine, so I added dma/sh/sudmac driver.
- However, for some reasons (maybe I'm busy for other projects?),
I didn't add using the sudmac support into arch/sh/kernel/cpu/sh4a/setup-sh7757.c.
- So, no one uses both r8a66597-udc and sudmac now.
From 2013 (added the sudmac driver) to now, since no one integrated the sudmac for sh7757,
I think we can remove the driver.
Best regards,
Yoshihiro Shimoda
^ permalink raw reply
* [PATCH v1] dmaengine: tegra: Use relaxed versions of readl/writel
From: Dmitry Osipenko @ 2019-04-24 23:17 UTC (permalink / raw)
To: Laxman Dewangan, Vinod Koul, Thierry Reding, Jonathan Hunter
Cc: dmaengine, linux-tegra, linux-kernel
The readl/writel functions are inserting memory barrier in order to
ensure that memory stores are completed. On Tegra20 and Tegra30 this
results in L2 cache syncing which isn't a cheapest operation. The
tegra20-apb-dma driver doesn't need to synchronize generic memory
accesses, hence use the relaxed versions of the functions.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
drivers/dma/tegra20-apb-dma.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/dma/tegra20-apb-dma.c b/drivers/dma/tegra20-apb-dma.c
index cf462b1abc0b..e646e1c7b299 100644
--- a/drivers/dma/tegra20-apb-dma.c
+++ b/drivers/dma/tegra20-apb-dma.c
@@ -241,23 +241,23 @@ struct tegra_dma {
static inline void tdma_write(struct tegra_dma *tdma, u32 reg, u32 val)
{
- writel(val, tdma->base_addr + reg);
+ writel_relaxed(val, tdma->base_addr + reg);
}
static inline u32 tdma_read(struct tegra_dma *tdma, u32 reg)
{
- return readl(tdma->base_addr + reg);
+ return readl_relaxed(tdma->base_addr + reg);
}
static inline void tdc_write(struct tegra_dma_channel *tdc,
u32 reg, u32 val)
{
- writel(val, tdc->chan_addr + reg);
+ writel_relaxed(val, tdc->chan_addr + reg);
}
static inline u32 tdc_read(struct tegra_dma_channel *tdc, u32 reg)
{
- return readl(tdc->chan_addr + reg);
+ return readl_relaxed(tdc->chan_addr + reg);
}
static inline struct tegra_dma_channel *to_tegra_dma_chan(struct dma_chan *dc)
--
2.21.0
^ permalink raw reply related
* [v1] dmaengine: tegra: Use relaxed versions of readl/writel
From: Dmitry Osipenko @ 2019-04-24 23:17 UTC (permalink / raw)
To: Laxman Dewangan, Vinod Koul, Thierry Reding, Jonathan Hunter
Cc: dmaengine, linux-tegra, linux-kernel
The readl/writel functions are inserting memory barrier in order to
ensure that memory stores are completed. On Tegra20 and Tegra30 this
results in L2 cache syncing which isn't a cheapest operation. The
tegra20-apb-dma driver doesn't need to synchronize generic memory
accesses, hence use the relaxed versions of the functions.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
drivers/dma/tegra20-apb-dma.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/dma/tegra20-apb-dma.c b/drivers/dma/tegra20-apb-dma.c
index cf462b1abc0b..e646e1c7b299 100644
--- a/drivers/dma/tegra20-apb-dma.c
+++ b/drivers/dma/tegra20-apb-dma.c
@@ -241,23 +241,23 @@ struct tegra_dma {
static inline void tdma_write(struct tegra_dma *tdma, u32 reg, u32 val)
{
- writel(val, tdma->base_addr + reg);
+ writel_relaxed(val, tdma->base_addr + reg);
}
static inline u32 tdma_read(struct tegra_dma *tdma, u32 reg)
{
- return readl(tdma->base_addr + reg);
+ return readl_relaxed(tdma->base_addr + reg);
}
static inline void tdc_write(struct tegra_dma_channel *tdc,
u32 reg, u32 val)
{
- writel(val, tdc->chan_addr + reg);
+ writel_relaxed(val, tdc->chan_addr + reg);
}
static inline u32 tdc_read(struct tegra_dma_channel *tdc, u32 reg)
{
- return readl(tdc->chan_addr + reg);
+ return readl_relaxed(tdc->chan_addr + reg);
}
static inline struct tegra_dma_channel *to_tegra_dma_chan(struct dma_chan *dc)
^ permalink raw reply related
* Re: [PATCH] dma: tegra: add accurate reporting of dma state
From: Dmitry Osipenko @ 2019-04-24 18:17 UTC (permalink / raw)
To: Ben Dooks, linux-kernel
Cc: Laxman Dewangan, Jon Hunter, Vinod Koul, Dan Williams,
Thierry Reding, dmaengine, linux-tegra, linux-kernel
In-Reply-To: <20190424162348.23692-1-ben.dooks@codethink.co.uk>
24.04.2019 19:23, Ben Dooks пишет:
> The tx_status callback does not report the state of the transfer
> beyond complete segments. This causes problems with users such as
> ALSA when applications want to know accurately how much data has
> been moved.
>
> This patch addes a function tegra_dma_update_residual() to query
> the hardware and modify the residual information accordinly. It
> takes into account any hardware issues when trying to read the
> state, such as delays between finishing a buffer and signalling
> the interrupt.
>
> Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
Hello Ben,
Thank you very much for keeping it up. I have couple comments, please see them below.
> Cc: Dmitry Osipenko <digetx@gmail.com>
> Cc: Laxman Dewangan <ldewangan@nvidia.com> (supporter:TEGRA DMA DRIVERS)
> Cc: Jon Hunter <jonathanh@nvidia.com> (supporter:TEGRA DMA DRIVERS)
> Cc: Vinod Koul <vkoul@kernel.org> (maintainer:DMA GENERIC OFFLOAD ENGINE SUBSYSTEM)
> Cc: Dan Williams <dan.j.williams@intel.com> (reviewer:ASYNCHRONOUS TRANSFERS/TRANSFORMS (IOAT) API)
> Cc: Thierry Reding <thierry.reding@gmail.com> (supporter:TEGRA ARCHITECTURE SUPPORT)
> Cc: dmaengine@vger.kernel.org (open list:DMA GENERIC OFFLOAD ENGINE SUBSYSTEM)
> Cc: linux-tegra@vger.kernel.org (open list:TEGRA ARCHITECTURE SUPPORT)
> Cc: linux-kernel@vger.kernel.org (open list)
> ---
> drivers/dma/tegra20-apb-dma.c | 92 ++++++++++++++++++++++++++++++++---
> 1 file changed, 86 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/dma/tegra20-apb-dma.c b/drivers/dma/tegra20-apb-dma.c
> index cf462b1abc0b..544e7273e741 100644
> --- a/drivers/dma/tegra20-apb-dma.c
> +++ b/drivers/dma/tegra20-apb-dma.c
> @@ -808,6 +808,90 @@ static int tegra_dma_terminate_all(struct dma_chan *dc)
> return 0;
> }
>
> +static unsigned int tegra_dma_update_residual(struct tegra_dma_channel *tdc,
> + struct tegra_dma_sg_req *sg_req,
> + struct tegra_dma_desc *dma_desc,
> + unsigned int residual)
> +{
> + unsigned long status = 0x0;
> + unsigned long wcount;
> + unsigned long ahbptr;
> + unsigned long tmp = 0x0;
> + unsigned int result;
You could pre-assign ahbptr=0xffffffff and result=residual here, then you could remove all the duplicated assigns below.
> + int retries = TEGRA_APBDMA_BURST_COMPLETE_TIME * 10;
> + int done;
> +
> + /* if we're not the current request, then don't alter the residual */
> + if (sg_req != list_first_entry(&tdc->pending_sg_req,
> + struct tegra_dma_sg_req, node)) {
> + result = residual;
> + ahbptr = 0xffffffff;
> + goto done;
> + }
> +
> + /* loop until we have a reliable result for residual */
> + do {
> + ahbptr = tdc_read(tdc, TEGRA_APBDMA_CHAN_AHBPTR);
> + status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS);
> + tmp = tdc_read(tdc, 0x08); /* total count for debug */
The "tmp" variable isn't used anywhere in the code, please remove it.
> +
> + /* check status, if channel isn't busy then skip */
> + if (!(status & TEGRA_APBDMA_STATUS_BUSY)) {
> + result = residual;
> + break;
> + }
This doesn't look correct because TRM says "Busy bit gets set as soon as a channel is enabled and gets cleared after transfer completes", hence a cleared BUSY bit means that all transfers are completed and result=residual is incorrect here. Given that there is a check for EOC bit being set below, this hunk should be removed.
> +
> + /* if we've got an interrupt pending on the channel, don't
> + * try and deal with the residue as the hardware has likely
> + * moved on to the next buffer. return all data moved.
> + */
> + if (status & TEGRA_APBDMA_STATUS_ISE_EOC) {
> + result = residual - sg_req->req_len;
> + break;
> + }
> +
> + if (tdc->tdma->chip_data->support_separate_wcount_reg)
> + wcount = tdc_read(tdc, TEGRA_APBDMA_CHAN_WORD_TRANSFER);
> + else
> + wcount = status;
> +
> + /* If the request is at the full point, then there is a
> + * chance that we have read the status register in the
> + * middle of the hardware reloading the next buffer.
> + *
> + * The sequence seems to be at the end of the buffer, to
> + * load the new word count before raising the EOC flag (or
> + * changing the ping-pong flag which could have also been
> + * used to determine a new buffer). This means there is a
> + * small window where we cannot determine zero-done for the
> + * current buffer, or moved to next buffer.
> + *
> + * If done shows 0, then retry the load, as it may hit the
> + * above hardware race. We will either get a new value which
> + * is from the first buffer, or we get an EOC (new buffer)
> + * or both a new value and an EOC...
> + */
> + done = get_current_xferred_count(tdc, sg_req, wcount);
> + if (done != 0) {
> + result = residual - done;
> + break;
> + }
> +
> + ndelay(100);
Please use udelay(1) because there is no ndelay on arm32 and ndelay(100) is getting rounded up to 1usec. AFAIK, arm64 doesn't have reliable ndelay on Tegra either because timer rate changes with the CPU frequency scaling.
Secondly done=0 isn't a error case, technically this could be the case when tegra_dma_update_residual() is invoked just after starting the transfer. Hence I think this do-while loop and timeout checking aren't needed at all since done=0 is a perfectly valid case.
Altogether seems the tegra_dma_update_residual() could be reduced to:
static unsigned int tegra_dma_update_residual(struct tegra_dma_channel *tdc,
struct tegra_dma_sg_req *sg_req,
struct tegra_dma_desc *dma_desc,
unsigned int residual)
{
unsigned long status, wcount;
if (list_is_first(&sg_req->node, &tdc->pending_sg_req))
return residual;
if (tdc->tdma->chip_data->support_separate_wcount_reg)
wcount = tdc_read(tdc, TEGRA_APBDMA_CHAN_WORD_TRANSFER);
status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS);
if (!tdc->tdma->chip_data->support_separate_wcount_reg)
wcount = status;
if (status & TEGRA_APBDMA_STATUS_ISE_EOC)
return residual - sg_req->req_len;
return residual - get_current_xferred_count(tdc, sg_req, wcount);
}
^ permalink raw reply
* dma: tegra: add accurate reporting of dma state
From: Dmitry Osipenko @ 2019-04-24 18:17 UTC (permalink / raw)
To: Ben Dooks, linux-kernel
Cc: Laxman Dewangan, Jon Hunter, Vinod Koul, Dan Williams,
Thierry Reding, dmaengine, linux-tegra, linux-kernel
24.04.2019 19:23, Ben Dooks пишет:
> The tx_status callback does not report the state of the transfer
> beyond complete segments. This causes problems with users such as
> ALSA when applications want to know accurately how much data has
> been moved.
>
> This patch addes a function tegra_dma_update_residual() to query
> the hardware and modify the residual information accordinly. It
> takes into account any hardware issues when trying to read the
> state, such as delays between finishing a buffer and signalling
> the interrupt.
>
> Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
Hello Ben,
Thank you very much for keeping it up. I have couple comments, please see them below.
> Cc: Dmitry Osipenko <digetx@gmail.com>
> Cc: Laxman Dewangan <ldewangan@nvidia.com> (supporter:TEGRA DMA DRIVERS)
> Cc: Jon Hunter <jonathanh@nvidia.com> (supporter:TEGRA DMA DRIVERS)
> Cc: Vinod Koul <vkoul@kernel.org> (maintainer:DMA GENERIC OFFLOAD ENGINE SUBSYSTEM)
> Cc: Dan Williams <dan.j.williams@intel.com> (reviewer:ASYNCHRONOUS TRANSFERS/TRANSFORMS (IOAT) API)
> Cc: Thierry Reding <thierry.reding@gmail.com> (supporter:TEGRA ARCHITECTURE SUPPORT)
> Cc: dmaengine@vger.kernel.org (open list:DMA GENERIC OFFLOAD ENGINE SUBSYSTEM)
> Cc: linux-tegra@vger.kernel.org (open list:TEGRA ARCHITECTURE SUPPORT)
> Cc: linux-kernel@vger.kernel.org (open list)
> ---
> drivers/dma/tegra20-apb-dma.c | 92 ++++++++++++++++++++++++++++++++---
> 1 file changed, 86 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/dma/tegra20-apb-dma.c b/drivers/dma/tegra20-apb-dma.c
> index cf462b1abc0b..544e7273e741 100644
> --- a/drivers/dma/tegra20-apb-dma.c
> +++ b/drivers/dma/tegra20-apb-dma.c
> @@ -808,6 +808,90 @@ static int tegra_dma_terminate_all(struct dma_chan *dc)
> return 0;
> }
>
> +static unsigned int tegra_dma_update_residual(struct tegra_dma_channel *tdc,
> + struct tegra_dma_sg_req *sg_req,
> + struct tegra_dma_desc *dma_desc,
> + unsigned int residual)
> +{
> + unsigned long status = 0x0;
> + unsigned long wcount;
> + unsigned long ahbptr;
> + unsigned long tmp = 0x0;
> + unsigned int result;
You could pre-assign ahbptr=0xffffffff and result=residual here, then you could remove all the duplicated assigns below.
> + int retries = TEGRA_APBDMA_BURST_COMPLETE_TIME * 10;
> + int done;
> +
> + /* if we're not the current request, then don't alter the residual */
> + if (sg_req != list_first_entry(&tdc->pending_sg_req,
> + struct tegra_dma_sg_req, node)) {
> + result = residual;
> + ahbptr = 0xffffffff;
> + goto done;
> + }
> +
> + /* loop until we have a reliable result for residual */
> + do {
> + ahbptr = tdc_read(tdc, TEGRA_APBDMA_CHAN_AHBPTR);
> + status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS);
> + tmp = tdc_read(tdc, 0x08); /* total count for debug */
The "tmp" variable isn't used anywhere in the code, please remove it.
> +
> + /* check status, if channel isn't busy then skip */
> + if (!(status & TEGRA_APBDMA_STATUS_BUSY)) {
> + result = residual;
> + break;
> + }
This doesn't look correct because TRM says "Busy bit gets set as soon as a channel is enabled and gets cleared after transfer completes", hence a cleared BUSY bit means that all transfers are completed and result=residual is incorrect here. Given that there is a check for EOC bit being set below, this hunk should be removed.
> +
> + /* if we've got an interrupt pending on the channel, don't
> + * try and deal with the residue as the hardware has likely
> + * moved on to the next buffer. return all data moved.
> + */
> + if (status & TEGRA_APBDMA_STATUS_ISE_EOC) {
> + result = residual - sg_req->req_len;
> + break;
> + }
> +
> + if (tdc->tdma->chip_data->support_separate_wcount_reg)
> + wcount = tdc_read(tdc, TEGRA_APBDMA_CHAN_WORD_TRANSFER);
> + else
> + wcount = status;
> +
> + /* If the request is at the full point, then there is a
> + * chance that we have read the status register in the
> + * middle of the hardware reloading the next buffer.
> + *
> + * The sequence seems to be at the end of the buffer, to
> + * load the new word count before raising the EOC flag (or
> + * changing the ping-pong flag which could have also been
> + * used to determine a new buffer). This means there is a
> + * small window where we cannot determine zero-done for the
> + * current buffer, or moved to next buffer.
> + *
> + * If done shows 0, then retry the load, as it may hit the
> + * above hardware race. We will either get a new value which
> + * is from the first buffer, or we get an EOC (new buffer)
> + * or both a new value and an EOC...
> + */
> + done = get_current_xferred_count(tdc, sg_req, wcount);
> + if (done != 0) {
> + result = residual - done;
> + break;
> + }
> +
> + ndelay(100);
Please use udelay(1) because there is no ndelay on arm32 and ndelay(100) is getting rounded up to 1usec. AFAIK, arm64 doesn't have reliable ndelay on Tegra either because timer rate changes with the CPU frequency scaling.
Secondly done=0 isn't a error case, technically this could be the case when tegra_dma_update_residual() is invoked just after starting the transfer. Hence I think this do-while loop and timeout checking aren't needed at all since done=0 is a perfectly valid case.
Altogether seems the tegra_dma_update_residual() could be reduced to:
static unsigned int tegra_dma_update_residual(struct tegra_dma_channel *tdc,
struct tegra_dma_sg_req *sg_req,
struct tegra_dma_desc *dma_desc,
unsigned int residual)
{
unsigned long status, wcount;
if (list_is_first(&sg_req->node, &tdc->pending_sg_req))
return residual;
if (tdc->tdma->chip_data->support_separate_wcount_reg)
wcount = tdc_read(tdc, TEGRA_APBDMA_CHAN_WORD_TRANSFER);
status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS);
if (!tdc->tdma->chip_data->support_separate_wcount_reg)
wcount = status;
if (status & TEGRA_APBDMA_STATUS_ISE_EOC)
return residual - sg_req->req_len;
return residual - get_current_xferred_count(tdc, sg_req, wcount);
}
^ permalink raw reply
* [PATCH] dma: tegra: add accurate reporting of dma state
From: Ben Dooks @ 2019-04-24 16:23 UTC (permalink / raw)
To: linux-kernel
Cc: Ben Dooks, Dmitry Osipenko, Laxman Dewangan, Jon Hunter,
Vinod Koul, Dan Williams, Thierry Reding, dmaengine, linux-tegra,
linux-kernel
The tx_status callback does not report the state of the transfer
beyond complete segments. This causes problems with users such as
ALSA when applications want to know accurately how much data has
been moved.
This patch addes a function tegra_dma_update_residual() to query
the hardware and modify the residual information accordinly. It
takes into account any hardware issues when trying to read the
state, such as delays between finishing a buffer and signalling
the interrupt.
Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
---
Cc: Dmitry Osipenko <digetx@gmail.com>
Cc: Laxman Dewangan <ldewangan@nvidia.com> (supporter:TEGRA DMA DRIVERS)
Cc: Jon Hunter <jonathanh@nvidia.com> (supporter:TEGRA DMA DRIVERS)
Cc: Vinod Koul <vkoul@kernel.org> (maintainer:DMA GENERIC OFFLOAD ENGINE SUBSYSTEM)
Cc: Dan Williams <dan.j.williams@intel.com> (reviewer:ASYNCHRONOUS TRANSFERS/TRANSFORMS (IOAT) API)
Cc: Thierry Reding <thierry.reding@gmail.com> (supporter:TEGRA ARCHITECTURE SUPPORT)
Cc: dmaengine@vger.kernel.org (open list:DMA GENERIC OFFLOAD ENGINE SUBSYSTEM)
Cc: linux-tegra@vger.kernel.org (open list:TEGRA ARCHITECTURE SUPPORT)
Cc: linux-kernel@vger.kernel.org (open list)
---
drivers/dma/tegra20-apb-dma.c | 92 ++++++++++++++++++++++++++++++++---
1 file changed, 86 insertions(+), 6 deletions(-)
diff --git a/drivers/dma/tegra20-apb-dma.c b/drivers/dma/tegra20-apb-dma.c
index cf462b1abc0b..544e7273e741 100644
--- a/drivers/dma/tegra20-apb-dma.c
+++ b/drivers/dma/tegra20-apb-dma.c
@@ -808,6 +808,90 @@ static int tegra_dma_terminate_all(struct dma_chan *dc)
return 0;
}
+static unsigned int tegra_dma_update_residual(struct tegra_dma_channel *tdc,
+ struct tegra_dma_sg_req *sg_req,
+ struct tegra_dma_desc *dma_desc,
+ unsigned int residual)
+{
+ unsigned long status = 0x0;
+ unsigned long wcount;
+ unsigned long ahbptr;
+ unsigned long tmp = 0x0;
+ unsigned int result;
+ int retries = TEGRA_APBDMA_BURST_COMPLETE_TIME * 10;
+ int done;
+
+ /* if we're not the current request, then don't alter the residual */
+ if (sg_req != list_first_entry(&tdc->pending_sg_req,
+ struct tegra_dma_sg_req, node)) {
+ result = residual;
+ ahbptr = 0xffffffff;
+ goto done;
+ }
+
+ /* loop until we have a reliable result for residual */
+ do {
+ ahbptr = tdc_read(tdc, TEGRA_APBDMA_CHAN_AHBPTR);
+ status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS);
+ tmp = tdc_read(tdc, 0x08); /* total count for debug */
+
+ /* check status, if channel isn't busy then skip */
+ if (!(status & TEGRA_APBDMA_STATUS_BUSY)) {
+ result = residual;
+ break;
+ }
+
+ /* if we've got an interrupt pending on the channel, don't
+ * try and deal with the residue as the hardware has likely
+ * moved on to the next buffer. return all data moved.
+ */
+ if (status & TEGRA_APBDMA_STATUS_ISE_EOC) {
+ result = residual - sg_req->req_len;
+ break;
+ }
+
+ if (tdc->tdma->chip_data->support_separate_wcount_reg)
+ wcount = tdc_read(tdc, TEGRA_APBDMA_CHAN_WORD_TRANSFER);
+ else
+ wcount = status;
+
+ /* If the request is at the full point, then there is a
+ * chance that we have read the status register in the
+ * middle of the hardware reloading the next buffer.
+ *
+ * The sequence seems to be at the end of the buffer, to
+ * load the new word count before raising the EOC flag (or
+ * changing the ping-pong flag which could have also been
+ * used to determine a new buffer). This means there is a
+ * small window where we cannot determine zero-done for the
+ * current buffer, or moved to next buffer.
+ *
+ * If done shows 0, then retry the load, as it may hit the
+ * above hardware race. We will either get a new value which
+ * is from the first buffer, or we get an EOC (new buffer)
+ * or both a new value and an EOC...
+ */
+ done = get_current_xferred_count(tdc, sg_req, wcount);
+ if (done != 0) {
+ result = residual - done;
+ break;
+ }
+
+ ndelay(100);
+ } while (--retries > 0);
+
+ if (retries <= 0) {
+ dev_err(tdc2dev(tdc), "timeout waiting for dma load\n");
+ result = residual;
+ }
+
+done:
+ dev_dbg(tdc2dev(tdc), "residual: req %08lx, ahb@%08lx, wcount %08lx, done %d\n",
+ sg_req->ch_regs.ahb_ptr, ahbptr, wcount, done);
+
+ return result;
+}
+
static enum dma_status tegra_dma_tx_status(struct dma_chan *dc,
dma_cookie_t cookie, struct dma_tx_state *txstate)
{
@@ -849,6 +933,7 @@ static enum dma_status tegra_dma_tx_status(struct dma_chan *dc,
residual = dma_desc->bytes_requested -
(dma_desc->bytes_transferred %
dma_desc->bytes_requested);
+ residual = tegra_dma_update_residual(tdc, sg_req, dma_desc, residual);
dma_set_residue(txstate, residual);
}
@@ -1444,12 +1529,7 @@ static int tegra_dma_probe(struct platform_device *pdev)
BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) |
BIT(DMA_SLAVE_BUSWIDTH_8_BYTES);
tdma->dma_dev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
- /*
- * XXX The hardware appears to support
- * DMA_RESIDUE_GRANULARITY_BURST-level reporting, but it's
- * only used by this driver during tegra_dma_terminate_all()
- */
- tdma->dma_dev.residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT;
+ tdma->dma_dev.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
tdma->dma_dev.device_config = tegra_dma_slave_config;
tdma->dma_dev.device_terminate_all = tegra_dma_terminate_all;
tdma->dma_dev.device_tx_status = tegra_dma_tx_status;
--
2.20.1
^ permalink raw reply related
* dma: tegra: add accurate reporting of dma state
From: Ben Dooks @ 2019-04-24 16:23 UTC (permalink / raw)
To: linux-kernel
Cc: Ben Dooks, Dmitry Osipenko, Laxman Dewangan, Jon Hunter,
Vinod Koul, Dan Williams, Thierry Reding, dmaengine, linux-tegra,
linux-kernel
The tx_status callback does not report the state of the transfer
beyond complete segments. This causes problems with users such as
ALSA when applications want to know accurately how much data has
been moved.
This patch addes a function tegra_dma_update_residual() to query
the hardware and modify the residual information accordinly. It
takes into account any hardware issues when trying to read the
state, such as delays between finishing a buffer and signalling
the interrupt.
Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
---
Cc: Dmitry Osipenko <digetx@gmail.com>
Cc: Laxman Dewangan <ldewangan@nvidia.com> (supporter:TEGRA DMA DRIVERS)
Cc: Jon Hunter <jonathanh@nvidia.com> (supporter:TEGRA DMA DRIVERS)
Cc: Vinod Koul <vkoul@kernel.org> (maintainer:DMA GENERIC OFFLOAD ENGINE SUBSYSTEM)
Cc: Dan Williams <dan.j.williams@intel.com> (reviewer:ASYNCHRONOUS TRANSFERS/TRANSFORMS (IOAT) API)
Cc: Thierry Reding <thierry.reding@gmail.com> (supporter:TEGRA ARCHITECTURE SUPPORT)
Cc: dmaengine@vger.kernel.org (open list:DMA GENERIC OFFLOAD ENGINE SUBSYSTEM)
Cc: linux-tegra@vger.kernel.org (open list:TEGRA ARCHITECTURE SUPPORT)
Cc: linux-kernel@vger.kernel.org (open list)
---
drivers/dma/tegra20-apb-dma.c | 92 ++++++++++++++++++++++++++++++++---
1 file changed, 86 insertions(+), 6 deletions(-)
diff --git a/drivers/dma/tegra20-apb-dma.c b/drivers/dma/tegra20-apb-dma.c
index cf462b1abc0b..544e7273e741 100644
--- a/drivers/dma/tegra20-apb-dma.c
+++ b/drivers/dma/tegra20-apb-dma.c
@@ -808,6 +808,90 @@ static int tegra_dma_terminate_all(struct dma_chan *dc)
return 0;
}
+static unsigned int tegra_dma_update_residual(struct tegra_dma_channel *tdc,
+ struct tegra_dma_sg_req *sg_req,
+ struct tegra_dma_desc *dma_desc,
+ unsigned int residual)
+{
+ unsigned long status = 0x0;
+ unsigned long wcount;
+ unsigned long ahbptr;
+ unsigned long tmp = 0x0;
+ unsigned int result;
+ int retries = TEGRA_APBDMA_BURST_COMPLETE_TIME * 10;
+ int done;
+
+ /* if we're not the current request, then don't alter the residual */
+ if (sg_req != list_first_entry(&tdc->pending_sg_req,
+ struct tegra_dma_sg_req, node)) {
+ result = residual;
+ ahbptr = 0xffffffff;
+ goto done;
+ }
+
+ /* loop until we have a reliable result for residual */
+ do {
+ ahbptr = tdc_read(tdc, TEGRA_APBDMA_CHAN_AHBPTR);
+ status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS);
+ tmp = tdc_read(tdc, 0x08); /* total count for debug */
+
+ /* check status, if channel isn't busy then skip */
+ if (!(status & TEGRA_APBDMA_STATUS_BUSY)) {
+ result = residual;
+ break;
+ }
+
+ /* if we've got an interrupt pending on the channel, don't
+ * try and deal with the residue as the hardware has likely
+ * moved on to the next buffer. return all data moved.
+ */
+ if (status & TEGRA_APBDMA_STATUS_ISE_EOC) {
+ result = residual - sg_req->req_len;
+ break;
+ }
+
+ if (tdc->tdma->chip_data->support_separate_wcount_reg)
+ wcount = tdc_read(tdc, TEGRA_APBDMA_CHAN_WORD_TRANSFER);
+ else
+ wcount = status;
+
+ /* If the request is at the full point, then there is a
+ * chance that we have read the status register in the
+ * middle of the hardware reloading the next buffer.
+ *
+ * The sequence seems to be at the end of the buffer, to
+ * load the new word count before raising the EOC flag (or
+ * changing the ping-pong flag which could have also been
+ * used to determine a new buffer). This means there is a
+ * small window where we cannot determine zero-done for the
+ * current buffer, or moved to next buffer.
+ *
+ * If done shows 0, then retry the load, as it may hit the
+ * above hardware race. We will either get a new value which
+ * is from the first buffer, or we get an EOC (new buffer)
+ * or both a new value and an EOC...
+ */
+ done = get_current_xferred_count(tdc, sg_req, wcount);
+ if (done != 0) {
+ result = residual - done;
+ break;
+ }
+
+ ndelay(100);
+ } while (--retries > 0);
+
+ if (retries <= 0) {
+ dev_err(tdc2dev(tdc), "timeout waiting for dma load\n");
+ result = residual;
+ }
+
+done:
+ dev_dbg(tdc2dev(tdc), "residual: req %08lx, ahb@%08lx, wcount %08lx, done %d\n",
+ sg_req->ch_regs.ahb_ptr, ahbptr, wcount, done);
+
+ return result;
+}
+
static enum dma_status tegra_dma_tx_status(struct dma_chan *dc,
dma_cookie_t cookie, struct dma_tx_state *txstate)
{
@@ -849,6 +933,7 @@ static enum dma_status tegra_dma_tx_status(struct dma_chan *dc,
residual = dma_desc->bytes_requested -
(dma_desc->bytes_transferred %
dma_desc->bytes_requested);
+ residual = tegra_dma_update_residual(tdc, sg_req, dma_desc, residual);
dma_set_residue(txstate, residual);
}
@@ -1444,12 +1529,7 @@ static int tegra_dma_probe(struct platform_device *pdev)
BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) |
BIT(DMA_SLAVE_BUSWIDTH_8_BYTES);
tdma->dma_dev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
- /*
- * XXX The hardware appears to support
- * DMA_RESIDUE_GRANULARITY_BURST-level reporting, but it's
- * only used by this driver during tegra_dma_terminate_all()
- */
- tdma->dma_dev.residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT;
+ tdma->dma_dev.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
tdma->dma_dev.device_config = tegra_dma_slave_config;
tdma->dma_dev.device_terminate_all = tegra_dma_terminate_all;
tdma->dma_dev.device_tx_status = tegra_dma_tx_status;
^ permalink raw reply related
* Re: [PATCH] dmaengine: rcar-dmac: Update copyright information
From: Geert Uytterhoeven @ 2019-04-24 12:22 UTC (permalink / raw)
To: Niklas Söderlund, Yoshihiro Shimoda
Cc: Simon Horman, dmaengine, Linux-Renesas, Hiroyuki Yokoyama
In-Reply-To: <20190411151756.GC30887@bigcity.dyn.berto.se>
Hi Niklas, Shimoda-san,
On Thu, Apr 11, 2019 at 5:18 PM Niklas Söderlund
<niklas.soderlund@ragnatech.se> wrote:
> On 2019-04-11 10:49:37 +0200, Simon Horman wrote:
> > On Wed, Apr 10, 2019 at 08:26:57PM +0200, Niklas Söderlund wrote:
> > Not strictly related, but is it appropriate to:
> >
> > 1. Move this driver and drivers/dma/sh/usb-dmac.c to drivers/dma/renesas/
That may make sense...
> > 2. Remove drivers/dma/sh/sudmac.c which appears unused
>
> I let someone with a better grasp of history answer this one. From my
> side removing drivers which are unused seems like a good idea :-)
There seem to be some (half-baked?) interaction between sudmac.c and
drivers/usb/gadget/udc/r8a66597-udc.c and drivers/usb/renesas_usbhs/fifo.c.
These don't seem to be used at all on Renesas ARM platforms, but
CONFIG_USB_R8A66597_HCD is enabled in shmobile_defconfig and
multi_v7_defconfig?
Shimoda-san: can you please enlighten us?
Thanks!
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply
* dmaengine: rcar-dmac: Update copyright information
From: Geert Uytterhoeven @ 2019-04-24 12:22 UTC (permalink / raw)
To: Niklas Söderlund, Yoshihiro Shimoda
Cc: Simon Horman, dmaengine, Linux-Renesas, Hiroyuki Yokoyama
Hi Niklas, Shimoda-san,
On Thu, Apr 11, 2019 at 5:18 PM Niklas Söderlund
<niklas.soderlund@ragnatech.se> wrote:
> On 2019-04-11 10:49:37 +0200, Simon Horman wrote:
> > On Wed, Apr 10, 2019 at 08:26:57PM +0200, Niklas Söderlund wrote:
> > Not strictly related, but is it appropriate to:
> >
> > 1. Move this driver and drivers/dma/sh/usb-dmac.c to drivers/dma/renesas/
That may make sense...
> > 2. Remove drivers/dma/sh/sudmac.c which appears unused
>
> I let someone with a better grasp of history answer this one. From my
> side removing drivers which are unused seems like a good idea :-)
There seem to be some (half-baked?) interaction between sudmac.c and
drivers/usb/gadget/udc/r8a66597-udc.c and drivers/usb/renesas_usbhs/fifo.c.
These don't seem to be used at all on Renesas ARM platforms, but
CONFIG_USB_R8A66597_HCD is enabled in shmobile_defconfig and
multi_v7_defconfig?
Shimoda-san: can you please enlighten us?
Thanks!
Gr{oetje,eeting}s,
Geert
^ permalink raw reply
* Re: [PATCH] dmaengine: stm32-dma: dmaengine: stm32-dma: use platform_get_irq()
From: Pierre Yves MORDRET @ 2019-04-24 9:27 UTC (permalink / raw)
To: Fabien Dessenne, Vinod Koul, Dan Williams, Maxime Coquelin,
Alexandre Torgue, dmaengine, linux-stm32, linux-arm-kernel,
linux-kernel
In-Reply-To: <1556097685-7236-1-git-send-email-fabien.dessenne@st.com>
Hello
Reviewed-by: Pierre-Yves MORDRET <pierre-yves.mordret@st.com>
Thanks
On 4/24/19 11:21 AM, Fabien Dessenne wrote:
> platform_get_resource(pdev, IORESOURCE_IRQ) is not recommended for
> requesting IRQ's resources, as they can be not ready yet. Using
> platform_get_irq() instead is preferred for getting IRQ even if it was
> not retrieved earlier.
>
> Signed-off-by: Fabien Dessenne <fabien.dessenne@st.com>
> ---
> drivers/dma/stm32-dma.c | 11 ++++++-----
> 1 file changed, 6 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/dma/stm32-dma.c b/drivers/dma/stm32-dma.c
> index ba239b5..3306818 100644
> --- a/drivers/dma/stm32-dma.c
> +++ b/drivers/dma/stm32-dma.c
> @@ -1302,13 +1302,14 @@ static int stm32_dma_probe(struct platform_device *pdev)
>
> for (i = 0; i < STM32_DMA_MAX_CHANNELS; i++) {
> chan = &dmadev->chan[i];
> - res = platform_get_resource(pdev, IORESOURCE_IRQ, i);
> - if (!res) {
> - ret = -EINVAL;
> - dev_err(&pdev->dev, "No irq resource for chan %d\n", i);
> + chan->irq = platform_get_irq(pdev, i);
> + if (chan->irq < 0) {
> + ret = chan->irq;
> + if (ret != -EPROBE_DEFER)
> + dev_err(&pdev->dev,
> + "No irq resource for chan %d\n", i);
> goto err_unregister;
> }
> - chan->irq = res->start;
> ret = devm_request_irq(&pdev->dev, chan->irq,
> stm32_dma_chan_irq, 0,
> dev_name(chan2dev(chan)), chan);
>
^ permalink raw reply
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