From: Tejasree Kondoj <ktejasree@marvell.com>
To: Akhil Goyal <gakhil@marvell.com>
Cc: Anoob Joseph <anoobj@marvell.com>,
Nithinsen Kaithakadan <nkaithakadan@marvell.com>, <dev@dpdk.org>
Subject: [PATCH 0/2] align crypto CPTR as per platform
Date: Mon, 12 Jan 2026 17:53:07 +0530 [thread overview]
Message-ID: <20260112122309.2448535-1-ktejasree@marvell.com> (raw)
Aligning CPTR as per HW requirements for
cnxk crypto PMD.
Nithinsen Kaithakadan (1):
common/cnxk: set CPT cache line size per platform
Tejasree Kondoj (1):
crypto/cnxk: align TLS CPTR to 256B
drivers/common/cnxk/roc_cpt.c | 4 +--
drivers/common/cnxk/roc_cpt.h | 5 +++
drivers/crypto/cnxk/cn20k_tls.c | 47 +++++++++++++++++++++++------
drivers/crypto/cnxk/cn20k_tls.h | 15 ++++++---
drivers/crypto/cnxk/cn20k_tls_ops.h | 6 +++-
5 files changed, 60 insertions(+), 17 deletions(-)
--
2.25.1
next reply other threads:[~2026-01-12 12:23 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-01-12 12:23 Tejasree Kondoj [this message]
2026-01-12 12:23 ` [PATCH 1/2] common/cnxk: set CPT cache line size per platform Tejasree Kondoj
2026-01-12 12:23 ` [PATCH 2/2] crypto/cnxk: align TLS CPTR to 256B Tejasree Kondoj
2026-02-10 13:17 ` [PATCH 0/2] align crypto CPTR as per platform Akhil Goyal
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