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From: Tejasree Kondoj <ktejasree@marvell.com>
To: Akhil Goyal <gakhil@marvell.com>
Cc: Nithinsen Kaithakadan <nkaithakadan@marvell.com>,
	Anoob Joseph <anoobj@marvell.com>, <dev@dpdk.org>
Subject: [PATCH 1/2] common/cnxk: set CPT cache line size per platform
Date: Mon, 12 Jan 2026 17:53:08 +0530	[thread overview]
Message-ID: <20260112122309.2448535-2-ktejasree@marvell.com> (raw)
In-Reply-To: <20260112122309.2448535-1-ktejasree@marvell.com>

From: Nithinsen Kaithakadan <nkaithakadan@marvell.com>

Added conditional definition for cache line size:
 - For CN10K and CN9k platform, set cache line size to 128 bytes.
 - For others, default to 256 bytes.

Signed-off-by: Nithinsen Kaithakadan <nkaithakadan@marvell.com>
---
 drivers/common/cnxk/roc_cpt.h | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/common/cnxk/roc_cpt.h b/drivers/common/cnxk/roc_cpt.h
index 67956758be..37873820e2 100644
--- a/drivers/common/cnxk/roc_cpt.h
+++ b/drivers/common/cnxk/roc_cpt.h
@@ -130,7 +130,12 @@
 	 BITS_PER_LONG_LONG)
 
 /* ROC CPTR Cache */
+#if defined(ROC_PLATFORM_CN10K) || defined(ROC_PLATFORM_CN9K)
+#define ROC_CPTR_CACHE_LINE_SZ 128
+#else
 #define ROC_CPTR_CACHE_LINE_SZ 256
+#endif
+
 #define ROC_CPTR_ALIGN	       ROC_CPTR_CACHE_LINE_SZ
 
 #define ROC_CPT_CQ_ENTRY_SIZE_UNIT 32
-- 
2.25.1


  reply	other threads:[~2026-01-12 12:23 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-01-12 12:23 [PATCH 0/2] align crypto CPTR as per platform Tejasree Kondoj
2026-01-12 12:23 ` Tejasree Kondoj [this message]
2026-01-12 12:23 ` [PATCH 2/2] crypto/cnxk: align TLS CPTR to 256B Tejasree Kondoj
2026-02-10 13:17 ` [PATCH 0/2] align crypto CPTR as per platform Akhil Goyal

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