From: Ciara Loftus <ciara.loftus@intel.com>
To: dev@dpdk.org
Cc: Vitaly Lifshits <vitaly.lifshits@intel.com>,
Ciara Loftus <ciara.loftus@intel.com>
Subject: [PATCH 05/10] net/e1000/base: clear DPG enable bit post MAC reset
Date: Wed, 20 May 2026 12:52:42 +0000 [thread overview]
Message-ID: <20260520125256.354336-6-ciara.loftus@intel.com> (raw)
In-Reply-To: <20260520125256.354336-1-ciara.loftus@intel.com>
From: Vitaly Lifshits <vitaly.lifshits@intel.com>
The GbE autonomous power gating feature was added to support G3 to S5
flow. However, this changed the reset value of DPG_EN bit to 1, causing
a possible autonomous transition to power gating state during D0. This
might result in undefined errors such as: packet loss, packet corruption
and Tx/Rx hangs. Therefore, clear DPG_EN bit after hardware reset flow.
Signed-off-by: Vitaly Lifshits <vitaly.lifshits@intel.com>
Signed-off-by: Ciara Loftus <ciara.loftus@intel.com>
---
drivers/net/intel/e1000/base/e1000_defines.h | 1 +
drivers/net/intel/e1000/base/e1000_ich8lan.c | 7 +++++++
2 files changed, 8 insertions(+)
diff --git a/drivers/net/intel/e1000/base/e1000_defines.h b/drivers/net/intel/e1000/base/e1000_defines.h
index eb93675823..6c710300a6 100644
--- a/drivers/net/intel/e1000/base/e1000_defines.h
+++ b/drivers/net/intel/e1000/base/e1000_defines.h
@@ -36,6 +36,7 @@
/* Extended Device Control */
#define E1000_CTRL_EXT_LPCD 0x00000004 /* LCD Power Cycle Done */
+#define E1000_CTRL_EXT_DPG_EN 0x00000008 /* Dynamic Power Gating Enable */
#define E1000_CTRL_EXT_SDP4_DATA 0x00000010 /* SW Definable Pin 4 data */
#define E1000_CTRL_EXT_SDP6_DATA 0x00000040 /* SW Definable Pin 6 data */
#define E1000_CTRL_EXT_SDP3_DATA 0x00000080 /* SW Definable Pin 3 data */
diff --git a/drivers/net/intel/e1000/base/e1000_ich8lan.c b/drivers/net/intel/e1000/base/e1000_ich8lan.c
index 6190052368..96b9ad6a70 100644
--- a/drivers/net/intel/e1000/base/e1000_ich8lan.c
+++ b/drivers/net/intel/e1000/base/e1000_ich8lan.c
@@ -5107,6 +5107,13 @@ STATIC s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
reg |= E1000_KABGTXD_BGSQLBIAS;
E1000_WRITE_REG(hw, E1000_KABGTXD, reg);
+ if (hw->mac.type >= e1000_pch_ptp) {
+ DEBUGOUT("Clearing DPG EN bit post reset\n");
+ reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
+ reg &= ~E1000_CTRL_EXT_DPG_EN;
+ E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
+ }
+
return E1000_SUCCESS;
}
--
2.43.0
next prev parent reply other threads:[~2026-05-20 12:53 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-20 12:52 [PATCH 00/10] e1000 base code update Ciara Loftus
2026-05-20 12:52 ` [PATCH 01/10] net/e1000/base: refactor K1 exit timeout configuration Ciara Loftus
2026-05-20 12:52 ` [PATCH 02/10] net/e1000/base: fix typo in e1000 base code Ciara Loftus
2026-05-20 12:52 ` [PATCH 03/10] net/e1000/base: fix possible variable overflow Ciara Loftus
2026-05-20 12:52 ` [PATCH 04/10] net/e1000/base: reclassify MAC type Ciara Loftus
2026-05-20 12:52 ` Ciara Loftus [this message]
2026-05-21 16:42 ` [PATCH 05/10] net/e1000/base: clear DPG enable bit post MAC reset Bruce Richardson
2026-05-20 12:52 ` [PATCH 06/10] net/e1000/base: fix coding style issues Ciara Loftus
2026-05-20 12:52 ` [PATCH 07/10] net/e1000/base: fix NVM loop bounds and pointer access Ciara Loftus
2026-05-20 12:52 ` [PATCH 08/10] net/e1000/base: propagate PHY control register write error Ciara Loftus
2026-05-20 12:52 ` [PATCH 09/10] net/e1000/base: auto-negotiation status for 1000BASE-T Ciara Loftus
2026-05-20 12:52 ` [PATCH 10/10] net/e1000/base: update version info Ciara Loftus
2026-05-21 16:47 ` [PATCH 00/10] e1000 base code update Bruce Richardson
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