* [PATCH 01/17] net/cnxk: update mbuf next field for multi segment
@ 2026-06-11 7:32 Rahul Bhansali
2026-06-11 7:32 ` [PATCH 02/17] common/cnxk: add API of SA valid for cn20k platform Rahul Bhansali
` (17 more replies)
0 siblings, 18 replies; 41+ messages in thread
From: Rahul Bhansali @ 2026-06-11 7:32 UTC (permalink / raw)
To: dev, Nithin Dabilpuram, Kiran Kumar K, Sunil Kumar Kori,
Satha Rao, Harman Kalra
Cc: jerinj, Rahul Bhansali
As per the requirement of rte_mbuf_raw_reset_bulk(), the mbuf's
'next' and 'nb_segs' fields are required to be reset.
This reset these field for multi-segment mbufs on cn9k platform.
Signed-off-by: Rahul Bhansali <rbhansali@marvell.com>
---
drivers/net/cnxk/cn9k_rx.h | 8 --------
drivers/net/cnxk/cn9k_tx.h | 42 ++++++++++++++++++--------------------
2 files changed, 20 insertions(+), 30 deletions(-)
diff --git a/drivers/net/cnxk/cn9k_rx.h b/drivers/net/cnxk/cn9k_rx.h
index 79b56fe160..5ccdc5dee1 100644
--- a/drivers/net/cnxk/cn9k_rx.h
+++ b/drivers/net/cnxk/cn9k_rx.h
@@ -410,8 +410,6 @@ cn9k_nix_cqe_to_mbuf(const struct nix_cqe_hdr_s *cq, const uint32_t tag,
* Hence, flag argument is not required.
*/
nix_cqe_xtract_mseg(rx, mbuf, val, 0);
- else
- mbuf->next = NULL;
}
static inline uint16_t
@@ -826,12 +824,6 @@ cn9k_nix_recv_pkts_vector(void *rx_queue, struct rte_mbuf **rx_pkts,
nix_cqe_xtract_mseg((union nix_rx_parse_u *)
(cq0 + CQE_SZ(3) + 8), mbuf3,
mbuf_initializer, flags);
- } else {
- /* Update that no more segments */
- mbuf0->next = NULL;
- mbuf1->next = NULL;
- mbuf2->next = NULL;
- mbuf3->next = NULL;
}
/* Store the mbufs to rx_pkts */
diff --git a/drivers/net/cnxk/cn9k_tx.h b/drivers/net/cnxk/cn9k_tx.h
index 32665d2050..0ec448e36c 100644
--- a/drivers/net/cnxk/cn9k_tx.h
+++ b/drivers/net/cnxk/cn9k_tx.h
@@ -665,14 +665,14 @@ cn9k_nix_prepare_mseg(struct cn9k_eth_txq *txq, struct rte_mbuf *m, struct rte_m
#else
RTE_SET_USED(cookie);
#endif
-#ifdef RTE_ENABLE_ASSERT
- m->next = NULL;
- m->nb_segs = 1;
-#endif
- m = m_next;
- if (!m)
+ if (likely(!m_next))
goto done;
+ if (!(flags & NIX_TX_OFFLOAD_MBUF_NOFF_F)) {
+ m->next = NULL;
+ m->nb_segs = 1;
+ }
+ m = m_next;
/* Fill mbuf segments */
do {
m_next = m->next;
@@ -704,12 +704,13 @@ cn9k_nix_prepare_mseg(struct cn9k_eth_txq *txq, struct rte_mbuf *m, struct rte_m
sg_u = sg->u;
slist++;
}
-#ifdef RTE_ENABLE_ASSERT
- m->next = NULL;
-#endif
+ if (!(flags & NIX_TX_OFFLOAD_MBUF_NOFF_F))
+ m->next = NULL;
m = m_next;
} while (nb_segs);
+ if (!(flags & NIX_TX_OFFLOAD_MBUF_NOFF_F))
+ rte_io_wmb();
done:
sg->u = sg_u;
sg->segs = i;
@@ -720,9 +721,6 @@ cn9k_nix_prepare_mseg(struct cn9k_eth_txq *txq, struct rte_mbuf *m, struct rte_m
segdw += (off >> 1) + 1 + !!(flags & NIX_TX_OFFLOAD_TSTAMP_F);
send_hdr->w0.sizem1 = segdw - 1;
-#ifdef RTE_ENABLE_ASSERT
- rte_io_wmb();
-#endif
return segdw;
}
@@ -950,10 +948,10 @@ cn9k_nix_prepare_mseg_vec_list(struct cn9k_eth_txq *txq,
RTE_SET_USED(cookie);
#endif
-#ifdef RTE_ENABLE_ASSERT
- m->next = NULL;
- m->nb_segs = 1;
-#endif
+ if (!(flags & NIX_TX_OFFLOAD_MBUF_NOFF_F)) {
+ m->next = NULL;
+ m->nb_segs = 1;
+ }
m = m_next;
/* Fill mbuf segments */
do {
@@ -984,9 +982,8 @@ cn9k_nix_prepare_mseg_vec_list(struct cn9k_eth_txq *txq,
sg_u = sg->u;
slist++;
}
-#ifdef RTE_ENABLE_ASSERT
- m->next = NULL;
-#endif
+ if (!(flags & NIX_TX_OFFLOAD_MBUF_NOFF_F))
+ m->next = NULL;
m = m_next;
} while (nb_segs);
@@ -1002,9 +999,6 @@ cn9k_nix_prepare_mseg_vec_list(struct cn9k_eth_txq *txq,
!!(flags & NIX_TX_OFFLOAD_TSTAMP_F);
send_hdr->w0.sizem1 = segdw - 1;
-#ifdef RTE_ENABLE_ASSERT
- rte_io_wmb();
-#endif
return segdw;
}
@@ -1089,6 +1083,10 @@ cn9k_nix_xmit_pkts_mseg_vector(uint64x2_t *cmd0, uint64x2_t *cmd1,
}
}
+ /* Multi segment mbufs */
+ if (!(flags & NIX_TX_OFFLOAD_MBUF_NOFF_F))
+ rte_io_wmb();
+
for (j = 0; j < NIX_DESCS_PER_LOOP;) {
/* Fit consecutive packets in same LMTLINE. */
if ((segdw[j] + segdw[j + 1]) <= 8) {
--
2.34.1
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH 02/17] common/cnxk: add API of SA valid for cn20k platform
2026-06-11 7:32 [PATCH 01/17] net/cnxk: update mbuf next field for multi segment Rahul Bhansali
@ 2026-06-11 7:32 ` Rahul Bhansali
2026-06-11 7:32 ` [PATCH 03/17] common/cnxk: additional NIX SQ ctx fields prints Rahul Bhansali
` (16 subsequent siblings)
17 siblings, 0 replies; 41+ messages in thread
From: Rahul Bhansali @ 2026-06-11 7:32 UTC (permalink / raw)
To: dev, Nithin Dabilpuram, Kiran Kumar K, Sunil Kumar Kori,
Satha Rao, Harman Kalra
Cc: jerinj, Rahul Bhansali
Add API to get SA valid configuration for cn20k platform.
Signed-off-by: Rahul Bhansali <rbhansali@marvell.com>
---
drivers/common/cnxk/cnxk_security.c | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/drivers/common/cnxk/cnxk_security.c b/drivers/common/cnxk/cnxk_security.c
index 6b51055100..6f46ad3276 100644
--- a/drivers/common/cnxk/cnxk_security.c
+++ b/drivers/common/cnxk/cnxk_security.c
@@ -606,6 +606,20 @@ cnxk_ot_ipsec_outb_sa_valid(struct roc_ot_ipsec_outb_sa *sa)
return !!sa->w2.s.valid;
}
+RTE_EXPORT_INTERNAL_SYMBOL(cnxk_ow_ipsec_inb_sa_valid)
+bool
+cnxk_ow_ipsec_inb_sa_valid(struct roc_ow_ipsec_inb_sa *sa)
+{
+ return !!sa->w2.s.valid;
+}
+
+RTE_EXPORT_INTERNAL_SYMBOL(cnxk_ow_ipsec_outb_sa_valid)
+bool
+cnxk_ow_ipsec_outb_sa_valid(struct roc_ow_ipsec_outb_sa *sa)
+{
+ return !!sa->w2.s.valid;
+}
+
RTE_EXPORT_INTERNAL_SYMBOL(cnxk_ipsec_ivlen_get)
uint8_t
cnxk_ipsec_ivlen_get(enum rte_crypto_cipher_algorithm c_algo,
--
2.34.1
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH 03/17] common/cnxk: additional NIX SQ ctx fields prints
2026-06-11 7:32 [PATCH 01/17] net/cnxk: update mbuf next field for multi segment Rahul Bhansali
2026-06-11 7:32 ` [PATCH 02/17] common/cnxk: add API of SA valid for cn20k platform Rahul Bhansali
@ 2026-06-11 7:32 ` Rahul Bhansali
2026-06-11 7:32 ` [PATCH 04/17] common/cnxk: update NIX irq handler Rahul Bhansali
` (15 subsequent siblings)
17 siblings, 0 replies; 41+ messages in thread
From: Rahul Bhansali @ 2026-06-11 7:32 UTC (permalink / raw)
To: dev, Nithin Dabilpuram, Kiran Kumar K, Sunil Kumar Kori,
Satha Rao, Harman Kalra
Cc: jerinj, Rahul Bhansali
Additional debug prints for CN20k NIX SQ ctx dump
Signed-off-by: Rahul Bhansali <rbhansali@marvell.com>
---
drivers/common/cnxk/roc_nix_debug.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/common/cnxk/roc_nix_debug.c b/drivers/common/cnxk/roc_nix_debug.c
index 11994bf131..07a18d4503 100644
--- a/drivers/common/cnxk/roc_nix_debug.c
+++ b/drivers/common/cnxk/roc_nix_debug.c
@@ -540,6 +540,8 @@ nix_cn10k_lf_sq_dump(__io struct nix_cn10k_sq_ctx_s *ctx, uint32_t *sqb_aura_p,
static inline void
nix_lf_sq_dump(__io struct nix_cn20k_sq_ctx_s *ctx, uint32_t *sqb_aura_p, FILE *file)
{
+ int64_t *sq_cnt_ptr = NULL;
+
nix_dump(file, "W0: sqe_way_mask \t\t%d\nW0: cq \t\t\t\t%d",
ctx->sqe_way_mask, ctx->cq);
nix_dump(file, "W0: sdp_mcast \t\t\t%d\nW0: substream \t\t\t0x%03x",
@@ -561,6 +563,7 @@ nix_lf_sq_dump(__io struct nix_cn20k_sq_ctx_s *ctx, uint32_t *sqb_aura_p, FILE *
nix_dump(file, "W2: smq_rr_count[ub:lb] \t\t%x:%x\n", ctx->smq_rr_count_ub,
ctx->smq_rr_count_lb);
+ nix_dump(file, "W3: update_sq_count\t\t%d\n", ctx->update_sq_count);
nix_dump(file, "W3: smq_next_sq_vld\t\t%d\nW3: smq_pend\t\t\t%d",
ctx->smq_next_sq_vld, ctx->smq_pend);
nix_dump(file, "W3: smenq_next_sqb_vld \t%d\nW3: head_offset\t\t\t%d",
@@ -588,6 +591,11 @@ nix_lf_sq_dump(__io struct nix_cn20k_sq_ctx_s *ctx, uint32_t *sqb_aura_p, FILE *
ctx->vfi_lso_sizem1);
nix_dump(file, "W9: vfi_lso_total\t\t%d", ctx->vfi_lso_total);
+ nix_dump(file, "W10: sq_count_iova \t\t0x%" PRIx64 "", (uint64_t)ctx->sq_count_iova);
+ sq_cnt_ptr = (int64_t *)(uintptr_t)(ctx->sq_count_iova << 3);
+ if (sq_cnt_ptr && ctx->update_sq_count)
+ nix_dump(file, "sq_count value \t\t0x%" PRIx64 "",
+ plt_atomic_load_explicit(sq_cnt_ptr, plt_memory_order_relaxed));
nix_dump(file, "W10: scm_lso_rem \t\t0x%" PRIx64 "", (uint64_t)ctx->scm_lso_rem);
nix_dump(file, "W11: octs \t\t\t0x%" PRIx64 "", (uint64_t)ctx->octs);
nix_dump(file, "W12: pkts \t\t\t0x%" PRIx64 "", (uint64_t)ctx->pkts);
--
2.34.1
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH 04/17] common/cnxk: update NIX irq handler
2026-06-11 7:32 [PATCH 01/17] net/cnxk: update mbuf next field for multi segment Rahul Bhansali
2026-06-11 7:32 ` [PATCH 02/17] common/cnxk: add API of SA valid for cn20k platform Rahul Bhansali
2026-06-11 7:32 ` [PATCH 03/17] common/cnxk: additional NIX SQ ctx fields prints Rahul Bhansali
@ 2026-06-11 7:32 ` Rahul Bhansali
2026-06-11 7:32 ` [PATCH 05/17] common/cnxk: configure LSO mask for single segments Rahul Bhansali
` (14 subsequent siblings)
17 siblings, 0 replies; 41+ messages in thread
From: Rahul Bhansali @ 2026-06-11 7:32 UTC (permalink / raw)
To: dev, Nithin Dabilpuram, Kiran Kumar K, Sunil Kumar Kori,
Satha Rao, Harman Kalra
Cc: jerinj, Rahul Bhansali
Move queue context dump and register print before interrupt
clear in NIX irq handler.
Signed-off-by: Rahul Bhansali <rbhansali@marvell.com>
---
drivers/common/cnxk/roc_nix_irq.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/common/cnxk/roc_nix_irq.c b/drivers/common/cnxk/roc_nix_irq.c
index 2b731302cd..6874435a4e 100644
--- a/drivers/common/cnxk/roc_nix_irq.c
+++ b/drivers/common/cnxk/roc_nix_irq.c
@@ -168,7 +168,7 @@ nix_lf_q_irq_get_and_clear(struct nix *nix, uint16_t q, uint32_t off,
reg = roc_atomic64_add_nosync(wdata, (int64_t *)(nix->base + off));
if (reg & BIT_ULL(42) /* OP_ERR */) {
- plt_err("Failed execute irq get off=0x%x", off);
+ plt_err("Failed execute irq get queue=%d off=0x%x", q, off);
return 0;
}
qint = reg & 0xff;
@@ -262,6 +262,10 @@ nix_lf_q_irq(void *param)
plt_err("Queue_intr=0x%" PRIx64 " qintx=%d pf=%d, vf=%d", intr, qintx,
dev->pf, dev->vf);
+ /* Dump registers to std out */
+ roc_nix_lf_reg_dump(nix_priv_to_roc_nix(nix), NULL);
+ roc_nix_queues_ctx_dump(nix_priv_to_roc_nix(nix), NULL);
+
/* Handle RQ interrupts */
for (q = 0; q < nix->nb_rx_queues; q++) {
rq = q % nix->qints;
@@ -323,10 +327,6 @@ nix_lf_q_irq(void *param)
/* Clear interrupt */
plt_write64(intr, nix->base + NIX_LF_QINTX_INT(qintx));
- /* Dump registers to std out */
- roc_nix_lf_reg_dump(nix_priv_to_roc_nix(nix), NULL);
- roc_nix_queues_ctx_dump(nix_priv_to_roc_nix(nix), NULL);
-
/* Call reset callback */
if (intr_cb && dev->ops->q_err_cb)
dev->ops->q_err_cb(nix_priv_to_roc_nix(nix), NULL);
--
2.34.1
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH 05/17] common/cnxk: configure LSO mask for single segments
2026-06-11 7:32 [PATCH 01/17] net/cnxk: update mbuf next field for multi segment Rahul Bhansali
` (2 preceding siblings ...)
2026-06-11 7:32 ` [PATCH 04/17] common/cnxk: update NIX irq handler Rahul Bhansali
@ 2026-06-11 7:32 ` Rahul Bhansali
2026-06-11 7:33 ` [PATCH 06/17] net/cnxk: reserve memory for lookup mem at probe Rahul Bhansali
` (13 subsequent siblings)
17 siblings, 0 replies; 41+ messages in thread
From: Rahul Bhansali @ 2026-06-11 7:32 UTC (permalink / raw)
To: dev, Nithin Dabilpuram, Kiran Kumar K, Sunil Kumar Kori,
Satha Rao, Harman Kalra
Cc: jerinj, Rahul Bhansali
Configures LSO flag mask for single packets.
Signed-off-by: Rahul Bhansali <rbhansali@marvell.com>
---
drivers/common/cnxk/roc_nix_ops.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/common/cnxk/roc_nix_ops.c b/drivers/common/cnxk/roc_nix_ops.c
index 12a12c6e35..4653bb2049 100644
--- a/drivers/common/cnxk/roc_nix_ops.c
+++ b/drivers/common/cnxk/roc_nix_ops.c
@@ -239,6 +239,8 @@ nix_lso_ipv4(struct roc_nix *roc_nix)
/* First get flags profile to update v4 flags */
memset(&alt_flags, 0, sizeof(alt_flags));
+ alt_flags.s.alt_ssf_set = 0;
+ alt_flags.s.alt_ssf_mask = 0xFFFF;
alt_flags.s.alt_fsf_set = 0x2000;
alt_flags.s.alt_fsf_mask = 0x5FFF;
alt_flags.s.alt_msf_set = 0x2000;
--
2.34.1
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH 06/17] net/cnxk: reserve memory for lookup mem at probe
2026-06-11 7:32 [PATCH 01/17] net/cnxk: update mbuf next field for multi segment Rahul Bhansali
` (3 preceding siblings ...)
2026-06-11 7:32 ` [PATCH 05/17] common/cnxk: configure LSO mask for single segments Rahul Bhansali
@ 2026-06-11 7:33 ` Rahul Bhansali
2026-06-11 7:33 ` [PATCH 07/17] drivers: add support for devargs skip size Rahul Bhansali
` (12 subsequent siblings)
17 siblings, 0 replies; 41+ messages in thread
From: Rahul Bhansali @ 2026-06-11 7:33 UTC (permalink / raw)
To: dev, Nithin Dabilpuram, Kiran Kumar K, Sunil Kumar Kori,
Satha Rao, Harman Kalra
Cc: jerinj
From: Nithin Dabilpuram <ndabilpuram@marvell.com>
Reserve memory for lookup mem at probe that is global for
all cnxk ethdev devices to avoid race at later stage.
Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
---
drivers/net/cnxk/cnxk_ethdev.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/net/cnxk/cnxk_ethdev.c b/drivers/net/cnxk/cnxk_ethdev.c
index 06d1c9b362..c782dc51a8 100644
--- a/drivers/net/cnxk/cnxk_ethdev.c
+++ b/drivers/net/cnxk/cnxk_ethdev.c
@@ -2220,6 +2220,12 @@ cnxk_eth_dev_init(struct rte_eth_dev *eth_dev)
/* Register callback for inline meta pool create 1:N pool:aura */
roc_nix_inl_custom_meta_pool_cb_register(cnxk_nix_inl_custom_meta_pool_cb);
+ /* Reserve memory for lookup_memory */
+ if (!cnxk_nix_fastpath_lookup_mem_get()) {
+ plt_err("Failed to reserve lookup memory rc=%d", rc);
+ goto dev_fini;
+ }
+
dev->eth_dev = eth_dev;
dev->configured = 0;
dev->ptype_disable = 0;
--
2.34.1
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH 07/17] drivers: add support for devargs skip size
2026-06-11 7:32 [PATCH 01/17] net/cnxk: update mbuf next field for multi segment Rahul Bhansali
` (4 preceding siblings ...)
2026-06-11 7:33 ` [PATCH 06/17] net/cnxk: reserve memory for lookup mem at probe Rahul Bhansali
@ 2026-06-11 7:33 ` Rahul Bhansali
2026-06-11 7:33 ` [PATCH 08/17] net/cnxk: update inbound SA pkind for " Rahul Bhansali
` (11 subsequent siblings)
17 siblings, 0 replies; 41+ messages in thread
From: Rahul Bhansali @ 2026-06-11 7:33 UTC (permalink / raw)
To: dev, Nithin Dabilpuram, Kiran Kumar K, Sunil Kumar Kori,
Satha Rao, Harman Kalra
Cc: jerinj
From: Kiran Kumar K <kirankumark@marvell.com>
Adding support for devargs skip_size to cnxk driver.
This allows users to specify the number of bytes to skip in the packet
parsing before L2.
Signed-off-by: Kiran Kumar K <kirankumark@marvell.com>
---
doc/guides/nics/cnxk.rst | 19 +++++++-
drivers/common/cnxk/roc_mbox.h | 12 ++++-
drivers/common/cnxk/roc_nix.h | 14 ++----
drivers/common/cnxk/roc_nix_ops.c | 46 +++++++++++++++++--
drivers/common/cnxk/roc_npc.c | 44 +++++++++++++++++-
drivers/common/cnxk/roc_npc.h | 2 +
drivers/common/cnxk/roc_npc_priv.h | 11 +++++
.../common/cnxk/roc_platform_base_symbols.c | 1 +
drivers/net/cnxk/cnxk_eswitch.c | 2 +-
drivers/net/cnxk/cnxk_ethdev.c | 7 ++-
drivers/net/cnxk/cnxk_ethdev_devargs.c | 29 +++++++++++-
11 files changed, 163 insertions(+), 24 deletions(-)
diff --git a/doc/guides/nics/cnxk.rst b/doc/guides/nics/cnxk.rst
index b5bd50ceea..239ebcd05c 100644
--- a/doc/guides/nics/cnxk.rst
+++ b/doc/guides/nics/cnxk.rst
@@ -183,8 +183,8 @@ Runtime Config Options
With the above configuration, higig2 will be enabled on that port and the
traffic on this port should be higig2 traffic only. Supported switch header
- types are "chlen24b", "chlen90b", "dsa", "exdsa", "higig2", "vlan_exdsa" and
- "pre_l2".
+ types are "chlen24b", "chlen90b", "dsa", "exdsa", "higig2", "vlan_exdsa",
+ "pre_l2" and "skip_size".
- ``Flow pre_l2 info`` (default ``0x0/0x0/0x0``)
@@ -212,6 +212,21 @@ Runtime Config Options
is 0 (i.e., left shift) then the shift count will be 1, that is, (8 - n),
where n is the absolute position of leftmost set bit.
+- ``Skip size info`` (default ``0x0``)
+
+ When the switch header type is set to "skip_size", the number of bytes to
+ skip before the Ethernet header can be configured using ``skip_size_info``
+ ``devargs`` parameter. The value is in hexadecimal format and the valid
+ range is 0x0 to 0xff. This configures the PKIND so that the NPC parser
+ skips the specified number of bytes.
+
+ For example::
+
+ -a 0002:02:00.0,switch_header="skip_size",skip_size_info=0x2
+
+ With the above configuration, 2 bytes will be skipped before the Ethernet
+ header when parsing the incoming packets.
+
- ``RSS tag as XOR`` (default ``0``)
The HW gives two options to configure the RSS adder i.e
diff --git a/drivers/common/cnxk/roc_mbox.h b/drivers/common/cnxk/roc_mbox.h
index e31abf2234..1158ff50a7 100644
--- a/drivers/common/cnxk/roc_mbox.h
+++ b/drivers/common/cnxk/roc_mbox.h
@@ -462,8 +462,11 @@ struct ready_msg_rsp {
};
enum npc_pkind_type {
+ NPC_RX_SKIP_SIZE_PKIND = 46ULL,
+ NPC_RX_CPT_SKIP_SIZE_PKIND = 50ULL,
+ NPC_RX_CPT_HDR_PTP_PKIND = 54ULL,
NPC_RX_CUSTOM_PRE_L2_PKIND = 55ULL,
- NPC_RX_VLAN_EXDSA_PKIND = 56ULL,
+ NPC_RX_VLAN_EXDSA_PKIND,
NPC_RX_CHLEN24B_PKIND,
NPC_RX_CPT_HDR_PKIND,
NPC_RX_CHLEN90B_PKIND,
@@ -474,6 +477,8 @@ enum npc_pkind_type {
NPC_TX_DEF_PKIND,
};
+#define NPC_SKIP_SIZE_PKIND_MAX 4
+
/* Struct to set pkind */
struct npc_set_pkind {
struct mbox_msghdr hdr;
@@ -484,6 +489,7 @@ struct npc_set_pkind {
#define ROC_PRIV_FLAGS_EXDSA BIT_ULL(4)
#define ROC_PRIV_FLAGS_VLAN_EXDSA BIT_ULL(5)
#define ROC_PRIV_FLAGS_PRE_L2 BIT_ULL(6)
+#define ROC_PRIV_FLAGS_SKIP_SIZE BIT_ULL(7)
#define ROC_PRIV_FLAGS_CUSTOM BIT_ULL(63)
uint64_t __io mode;
#define PKIND_TX BIT_ULL(0)
@@ -499,6 +505,10 @@ struct npc_set_pkind {
/* Shift direction to get length of the
* header at var_len_off
*/
+ uint8_t __io skip_size;
+ /* Number of bytes to skip before the Ethernet header.
+ * Valid only in case custom flag.
+ */
};
/* Structure for requesting resource provisioning.
diff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h
index 8ba8b3e0b6..49ede85f9a 100644
--- a/drivers/common/cnxk/roc_nix.h
+++ b/drivers/common/cnxk/roc_nix.h
@@ -990,18 +990,14 @@ int __roc_api roc_nix_mac_stats_reset(struct roc_nix *roc_nix);
int __roc_api roc_nix_mac_fwdata_get(struct roc_nix *roc_nix, struct roc_nix_mac_fwdata *fwdata);
/* Ops */
-int __roc_api roc_nix_switch_hdr_set(struct roc_nix *roc_nix,
- uint64_t switch_header_type,
- uint8_t pre_l2_size_offset,
- uint8_t pre_l2_size_offset_mask,
- uint8_t pre_l2_size_shift_dir);
+int __roc_api roc_nix_switch_hdr_set(struct roc_nix *roc_nix, uint64_t switch_header_type,
+ uint8_t pre_l2_size_offset, uint8_t pre_l2_size_offset_mask,
+ uint8_t pre_l2_size_shift_dir, uint8_t skip_size);
int __roc_api roc_nix_lso_fmt_setup(struct roc_nix *roc_nix);
-int __roc_api roc_nix_lso_fmt_get(struct roc_nix *roc_nix,
- uint8_t udp_tun[ROC_NIX_LSO_TUN_MAX],
+int __roc_api roc_nix_lso_fmt_get(struct roc_nix *roc_nix, uint8_t udp_tun[ROC_NIX_LSO_TUN_MAX],
uint8_t tun[ROC_NIX_LSO_TUN_MAX]);
int __roc_api roc_nix_lso_fmt_ipv4_frag_get(struct roc_nix *roc_nix);
-int __roc_api roc_nix_lso_custom_fmt_setup(struct roc_nix *roc_nix,
- struct nix_lso_format *fields,
+int __roc_api roc_nix_lso_custom_fmt_setup(struct roc_nix *roc_nix, struct nix_lso_format *fields,
uint16_t nb_fields);
int __roc_api roc_nix_lso_alt_flags_profile_setup(struct roc_nix *roc_nix,
nix_lso_alt_flg_format_t *fmt);
diff --git a/drivers/common/cnxk/roc_nix_ops.c b/drivers/common/cnxk/roc_nix_ops.c
index 4653bb2049..13a548216b 100644
--- a/drivers/common/cnxk/roc_nix_ops.c
+++ b/drivers/common/cnxk/roc_nix_ops.c
@@ -501,17 +501,49 @@ roc_nix_lso_fmt_get(struct roc_nix *roc_nix,
return 0;
}
+static int
+skip_size_pkind_get(uint8_t skip_size, uint8_t *pkind)
+{
+ struct skip_size_pkind_cfg *cfg;
+ const struct plt_memzone *mz;
+ int i;
+
+ mz = plt_memzone_lookup(SKIP_SIZE_PKIND_MEMZONE);
+ if (!mz)
+ return -ENOMEM;
+ cfg = mz->addr;
+
+ for (i = 0; i < cfg->count; i++) {
+ if (cfg->entries[i].skip_size == skip_size) {
+ *pkind = cfg->entries[i].pkind;
+ return 0;
+ }
+ }
+
+ if (cfg->count >= NPC_SKIP_SIZE_PKIND_MAX) {
+ plt_err("skip_size PKIND limit (%d) reached", NPC_SKIP_SIZE_PKIND_MAX);
+ return -ENOSPC;
+ }
+
+ i = cfg->count;
+ cfg->entries[i].skip_size = skip_size;
+ cfg->entries[i].pkind = NPC_RX_SKIP_SIZE_PKIND + i;
+ *pkind = cfg->entries[i].pkind;
+ cfg->count++;
+ return 0;
+}
+
int
roc_nix_switch_hdr_set(struct roc_nix *roc_nix, uint64_t switch_header_type,
- uint8_t pre_l2_size_offset,
- uint8_t pre_l2_size_offset_mask,
- uint8_t pre_l2_size_shift_dir)
+ uint8_t pre_l2_size_offset, uint8_t pre_l2_size_offset_mask,
+ uint8_t pre_l2_size_shift_dir, uint8_t skip_size)
{
struct nix *nix = roc_nix_to_nix_priv(roc_nix);
struct dev *dev = &nix->dev;
struct mbox *mbox = mbox_get(dev->mbox);
struct npc_set_pkind *req;
struct msg_resp *rsp;
+ uint8_t pkind = 0;
int rc = -ENOSPC;
if (switch_header_type == 0)
@@ -524,6 +556,7 @@ roc_nix_switch_hdr_set(struct roc_nix *roc_nix, uint64_t switch_header_type,
switch_header_type != ROC_PRIV_FLAGS_EXDSA &&
switch_header_type != ROC_PRIV_FLAGS_VLAN_EXDSA &&
switch_header_type != ROC_PRIV_FLAGS_PRE_L2 &&
+ switch_header_type != ROC_PRIV_FLAGS_SKIP_SIZE &&
switch_header_type != ROC_PRIV_FLAGS_CUSTOM) {
plt_err("switch header type is not supported");
rc = NIX_ERR_PARAM;
@@ -564,6 +597,13 @@ roc_nix_switch_hdr_set(struct roc_nix *roc_nix, uint64_t switch_header_type,
req->var_len_off = pre_l2_size_offset;
req->var_len_off_mask = pre_l2_size_offset_mask;
req->shift_dir = pre_l2_size_shift_dir;
+ } else if (switch_header_type == ROC_PRIV_FLAGS_SKIP_SIZE) {
+ rc = skip_size_pkind_get(skip_size, &pkind);
+ if (rc)
+ goto exit;
+ req->mode = ROC_PRIV_FLAGS_CUSTOM;
+ req->pkind = pkind;
+ req->skip_size = skip_size;
}
req->dir = PKIND_RX;
diff --git a/drivers/common/cnxk/roc_npc.c b/drivers/common/cnxk/roc_npc.c
index a906fe0413..111ad0e8bb 100644
--- a/drivers/common/cnxk/roc_npc.c
+++ b/drivers/common/cnxk/roc_npc.c
@@ -420,6 +420,16 @@ roc_npc_init(struct roc_npc *roc_npc)
roc_npc->flow_age.age_flow_refcnt = 0;
+ /* Create skip-size PKIND memzone if it doesn't exist */
+ if (!plt_memzone_lookup(SKIP_SIZE_PKIND_MEMZONE)) {
+ const struct plt_memzone *mz;
+
+ mz = plt_memzone_reserve_cache_align(SKIP_SIZE_PKIND_MEMZONE,
+ sizeof(struct skip_size_pkind_cfg));
+ if (mz != NULL)
+ memset(mz->addr, 0, sizeof(struct skip_size_pkind_cfg));
+ }
+
return rc;
done:
@@ -457,12 +467,42 @@ roc_npc_fini(struct roc_npc *roc_npc)
npc->prio_flow_list = NULL;
}
+ {
+ const struct plt_memzone *mz;
+
+ mz = plt_memzone_lookup(SKIP_SIZE_PKIND_MEMZONE);
+ if (mz)
+ plt_memzone_free(mz);
+ }
+
return 0;
}
int
-roc_npc_validate_portid_action(struct roc_npc *roc_npc_src,
- struct roc_npc *roc_npc_dst)
+roc_npc_skip_size_pkind_get(struct roc_npc *roc_npc)
+{
+ struct skip_size_pkind_cfg *cfg;
+ const struct plt_memzone *mz;
+ int i;
+
+ if (roc_npc->switch_header_type != ROC_PRIV_FLAGS_SKIP_SIZE)
+ return -1;
+
+ mz = plt_memzone_lookup(SKIP_SIZE_PKIND_MEMZONE);
+ if (!mz)
+ return -1;
+ cfg = mz->addr;
+
+ for (i = 0; i < cfg->count; i++) {
+ if (cfg->entries[i].skip_size == roc_npc->skip_size)
+ return cfg->entries[i].pkind + NPC_SKIP_SIZE_PKIND_MAX;
+ }
+
+ return -1;
+}
+
+int
+roc_npc_validate_portid_action(struct roc_npc *roc_npc_src, struct roc_npc *roc_npc_dst)
{
struct roc_nix *roc_nix_src = roc_npc_src->roc_nix;
struct nix *nix_src = roc_nix_to_nix_priv(roc_nix_src);
diff --git a/drivers/common/cnxk/roc_npc.h b/drivers/common/cnxk/roc_npc.h
index 130990bda7..a7254f35ca 100644
--- a/drivers/common/cnxk/roc_npc.h
+++ b/drivers/common/cnxk/roc_npc.h
@@ -423,6 +423,7 @@ struct roc_npc {
*/
uint8_t pre_l2_size_shift_dir; /**< Shift direction to calculate size
*/
+ uint8_t skip_size; /**< Switch header skip size */
uint16_t flow_prealloc_size;
uint16_t flow_max_priority;
uint16_t channel;
@@ -506,4 +507,5 @@ void __roc_api roc_npc_sdp_channel_get(struct roc_npc *roc_npc, uint16_t *chan_b
uint16_t *chan_mask);
int __roc_api roc_npc_mcam_get_stats(struct roc_npc *roc_npc, struct roc_npc_flow *flow,
uint64_t *count);
+int __roc_api roc_npc_skip_size_pkind_get(struct roc_npc *roc_npc);
#endif /* _ROC_NPC_H_ */
diff --git a/drivers/common/cnxk/roc_npc_priv.h b/drivers/common/cnxk/roc_npc_priv.h
index f8f4489f06..6a27f0e0fa 100644
--- a/drivers/common/cnxk/roc_npc_priv.h
+++ b/drivers/common/cnxk/roc_npc_priv.h
@@ -554,4 +554,15 @@ int npc_aging_ctrl_thread_create(struct roc_npc *roc_npc, const struct roc_npc_a
struct roc_npc_flow *flow);
void npc_aging_ctrl_thread_destroy(struct roc_npc *roc_npc);
int npc_rss_free_grp_get(struct npc *npc, uint32_t *pos);
+
+#define SKIP_SIZE_PKIND_MEMZONE "roc_skip_size_pkind_cfg"
+
+struct skip_size_pkind_cfg {
+ uint8_t count;
+ struct {
+ uint8_t skip_size;
+ uint8_t pkind;
+ } entries[NPC_SKIP_SIZE_PKIND_MAX];
+};
+
#endif /* _ROC_NPC_PRIV_H_ */
diff --git a/drivers/common/cnxk/roc_platform_base_symbols.c b/drivers/common/cnxk/roc_platform_base_symbols.c
index ed34d4b05b..d1c9f2304d 100644
--- a/drivers/common/cnxk/roc_platform_base_symbols.c
+++ b/drivers/common/cnxk/roc_platform_base_symbols.c
@@ -492,6 +492,7 @@ RTE_EXPORT_INTERNAL_SYMBOL(roc_npc_fini)
RTE_EXPORT_INTERNAL_SYMBOL(roc_npc_validate_portid_action)
RTE_EXPORT_INTERNAL_SYMBOL(roc_npc_flow_parse)
RTE_EXPORT_INTERNAL_SYMBOL(roc_npc_sdp_channel_get)
+RTE_EXPORT_INTERNAL_SYMBOL(roc_npc_skip_size_pkind_get)
RTE_EXPORT_INTERNAL_SYMBOL(roc_npc_flow_create)
RTE_EXPORT_INTERNAL_SYMBOL(roc_npc_flow_destroy)
RTE_EXPORT_INTERNAL_SYMBOL(roc_npc_flow_dump)
diff --git a/drivers/net/cnxk/cnxk_eswitch.c b/drivers/net/cnxk/cnxk_eswitch.c
index e45c7dfd07..7e717a2fbf 100644
--- a/drivers/net/cnxk/cnxk_eswitch.c
+++ b/drivers/net/cnxk/cnxk_eswitch.c
@@ -553,7 +553,7 @@ nix_lf_setup(struct cnxk_eswitch_dev *eswitch_dev)
goto free_cqs;
}
- rc = roc_nix_switch_hdr_set(nix, 0, 0, 0, 0);
+ rc = roc_nix_switch_hdr_set(nix, 0, 0, 0, 0, 0);
if (rc) {
plt_err("switch hdr set failed = %s(%d)", roc_error_msg_get(rc), rc);
goto free_cqs;
diff --git a/drivers/net/cnxk/cnxk_ethdev.c b/drivers/net/cnxk/cnxk_ethdev.c
index c782dc51a8..a21e170229 100644
--- a/drivers/net/cnxk/cnxk_ethdev.c
+++ b/drivers/net/cnxk/cnxk_ethdev.c
@@ -1639,10 +1639,9 @@ cnxk_nix_configure(struct rte_eth_dev *eth_dev)
goto free_nix_lf;
}
- rc = roc_nix_switch_hdr_set(nix, dev->npc.switch_header_type,
- dev->npc.pre_l2_size_offset,
+ rc = roc_nix_switch_hdr_set(nix, dev->npc.switch_header_type, dev->npc.pre_l2_size_offset,
dev->npc.pre_l2_size_offset_mask,
- dev->npc.pre_l2_size_shift_dir);
+ dev->npc.pre_l2_size_shift_dir, dev->npc.skip_size);
if (rc) {
plt_err("Failed to enable switch type nix_lf rc=%d", rc);
goto free_nix_lf;
@@ -2364,7 +2363,7 @@ cnxk_eth_dev_uninit(struct rte_eth_dev *eth_dev, bool reset)
return 0;
/* Disable switch hdr pkind */
- roc_nix_switch_hdr_set(&dev->nix, 0, 0, 0, 0);
+ roc_nix_switch_hdr_set(&dev->nix, 0, 0, 0, 0, 0);
/* Clear the flag since we are closing down */
dev->configured = 0;
diff --git a/drivers/net/cnxk/cnxk_ethdev_devargs.c b/drivers/net/cnxk/cnxk_ethdev_devargs.c
index da8fc83f9d..ea18090919 100644
--- a/drivers/net/cnxk/cnxk_ethdev_devargs.c
+++ b/drivers/net/cnxk/cnxk_ethdev_devargs.c
@@ -239,6 +239,25 @@ parse_switch_header_type(const char *key, const char *value, void *extra_args)
if (strcmp(value, "pre_l2") == 0)
*(uint16_t *)extra_args = ROC_PRIV_FLAGS_PRE_L2;
+ if (strcmp(value, "skip_size") == 0)
+ *(uint16_t *)extra_args = ROC_PRIV_FLAGS_SKIP_SIZE;
+
+ return 0;
+}
+
+static int
+parse_skip_size_info(const char *key, const char *value, void *extra_args)
+{
+ RTE_SET_USED(key);
+ uint32_t val;
+
+ errno = 0;
+ val = strtoul(value, NULL, 0);
+ if (errno || val > 255)
+ return -EINVAL;
+
+ *(uint16_t *)extra_args = val;
+
return 0;
}
@@ -303,6 +322,7 @@ parse_val_u16(const char *key, const char *value, void *extra_args)
#define CNXK_FORCE_TAIL_DROP "force_tail_drop"
#define CNXK_DIS_XQE_DROP "disable_xqe_drop"
#define CNXK_RXC_STEP "rxc_step"
+#define CNXK_SKIP_SIZE_INFO "skip_size_info"
int
cnxk_ethdev_parse_devargs(struct rte_devargs *devargs, struct cnxk_eth_dev *dev)
@@ -317,6 +337,7 @@ cnxk_ethdev_parse_devargs(struct rte_devargs *devargs, struct cnxk_eth_dev *dev)
uint16_t custom_meta_aura_dis = 0;
uint16_t flow_prealloc_size = 1;
uint16_t switch_header_type = 0;
+ uint16_t skip_size_info = 0;
uint16_t flow_max_priority = 3;
uint16_t outb_nb_crypto_qs = 1;
uint32_t ipsec_in_min_spi = 0;
@@ -392,6 +413,8 @@ cnxk_ethdev_parse_devargs(struct rte_devargs *devargs, struct cnxk_eth_dev *dev)
rte_kvargs_process(kvlist, CNXK_FORCE_TAIL_DROP, &parse_flag, &force_tail_drop);
rte_kvargs_process(kvlist, CNXK_DIS_XQE_DROP, &parse_flag, &dis_xqe_drop);
rte_kvargs_process(kvlist, CNXK_RXC_STEP, &parse_rxc_step, &rxc_step);
+ rte_kvargs_process(kvlist, CNXK_SKIP_SIZE_INFO, &parse_skip_size_info,
+ &skip_size_info);
rte_kvargs_free(kvlist);
null_devargs:
@@ -424,6 +447,7 @@ cnxk_ethdev_parse_devargs(struct rte_devargs *devargs, struct cnxk_eth_dev *dev)
dev->npc.flow_max_priority = flow_max_priority;
dev->npc.switch_header_type = switch_header_type;
+ dev->npc.skip_size = skip_size_info;
dev->npc.sdp_channel = sdp_chan.channel;
dev->npc.sdp_channel_mask = sdp_chan.mask;
dev->npc.is_sdp_mask_set = sdp_chan.is_sdp_mask_set;
@@ -448,7 +472,7 @@ RTE_PMD_REGISTER_PARAM_STRING(net_cnxk,
CNXK_MAX_SQB_COUNT "=<8-512>"
CNXK_FLOW_PREALLOC_SIZE "=<1-32>"
CNXK_FLOW_MAX_PRIORITY "=<1-32>"
- CNXK_SWITCH_HEADER_TYPE "=<higig2|dsa|chlen90b>"
+ CNXK_SWITCH_HEADER_TYPE "=<higig2|dsa|chlen90b|skip_size>"
CNXK_RSS_TAG_AS_XOR "=1"
CNXK_IPSEC_IN_MAX_SPI "=<1-65535>"
CNXK_OUTB_NB_DESC "=<1-65535>"
@@ -463,4 +487,5 @@ RTE_PMD_REGISTER_PARAM_STRING(net_cnxk,
CNXK_CUSTOM_META_AURA_DIS "=1"
CNXK_FORCE_TAIL_DROP "=1"
CNXK_DIS_XQE_DROP "=1"
- CNXK_RXC_STEP "=<0-1048575>");
+ CNXK_RXC_STEP "=<0-1048575>"
+ CNXK_SKIP_SIZE_INFO "=<0x0-0xff>");
--
2.34.1
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH 08/17] net/cnxk: update inbound SA pkind for skip size
2026-06-11 7:32 [PATCH 01/17] net/cnxk: update mbuf next field for multi segment Rahul Bhansali
` (5 preceding siblings ...)
2026-06-11 7:33 ` [PATCH 07/17] drivers: add support for devargs skip size Rahul Bhansali
@ 2026-06-11 7:33 ` Rahul Bhansali
2026-06-11 7:33 ` [PATCH 09/17] common/cnxk: fix cnxk xstats names Rahul Bhansali
` (10 subsequent siblings)
17 siblings, 0 replies; 41+ messages in thread
From: Rahul Bhansali @ 2026-06-11 7:33 UTC (permalink / raw)
To: dev, Nithin Dabilpuram, Kiran Kumar K, Sunil Kumar Kori,
Satha Rao, Harman Kalra
Cc: jerinj, Rakesh Kudurumalla
From: Rakesh Kudurumalla <rkudurumalla@marvell.com>
Update the inbound SA pkind using roc_npc_skip_size_pkind_get()
during session create and session update for both CN10K and CN20K.
This ensures the CPT second pass uses the correct pkind when
skip size is configured, retaining the default pkind otherwise.
Signed-off-by: Rakesh Kudurumalla <rkudurumalla@marvell.com>
---
drivers/net/cnxk/cn10k_ethdev_sec.c | 9 +++++++++
drivers/net/cnxk/cn20k_ethdev_sec.c | 8 ++++++++
2 files changed, 17 insertions(+)
diff --git a/drivers/net/cnxk/cn10k_ethdev_sec.c b/drivers/net/cnxk/cn10k_ethdev_sec.c
index 855bea1796..2f1fdf34fc 100644
--- a/drivers/net/cnxk/cn10k_ethdev_sec.c
+++ b/drivers/net/cnxk/cn10k_ethdev_sec.c
@@ -853,6 +853,10 @@ cn10k_eth_sec_session_create(void *device,
goto err;
}
+ rc = roc_npc_skip_size_pkind_get(&dev->npc);
+ if (rc >= 0)
+ inb_sa_dptr->w0.s.pkind = rc;
+
inb_priv = roc_nix_inl_ot_ipsec_inb_sa_sw_rsvd(inb_sa);
/* Back pointer to get eth_sec */
inb_priv->eth_sec = eth_sec;
@@ -1151,6 +1155,11 @@ cn10k_eth_sec_session_update(void *device, struct rte_security_session *sess,
rc = cnxk_ot_ipsec_inb_sa_fill(inb_sa_dptr, ipsec, crypto, 0);
if (rc)
goto err;
+
+ rc = roc_npc_skip_size_pkind_get(&dev->npc);
+ if (rc >= 0)
+ inb_sa_dptr->w0.s.pkind = rc;
+
/* Use cookie for original data */
inb_sa_dptr->w1.s.cookie = inb_sa->w1.s.cookie;
diff --git a/drivers/net/cnxk/cn20k_ethdev_sec.c b/drivers/net/cnxk/cn20k_ethdev_sec.c
index 5d0debb81d..31f2518ea3 100644
--- a/drivers/net/cnxk/cn20k_ethdev_sec.c
+++ b/drivers/net/cnxk/cn20k_ethdev_sec.c
@@ -865,6 +865,10 @@ cn20k_eth_sec_session_create(void *device, struct rte_security_session_conf *con
goto err;
}
+ rc = roc_npc_skip_size_pkind_get(&dev->npc);
+ if (rc >= 0)
+ inb_sa_dptr->w0.s.pkind = rc;
+
cn20k_eth_sec_inb_sa_misc_fill(inb_sa_dptr, ipsec);
inb_priv = roc_nix_inl_ow_ipsec_inb_sa_sw_rsvd(inb_sa);
@@ -1137,6 +1141,10 @@ cn20k_eth_sec_session_update(void *device, struct rte_security_session *sess,
if (rc)
return -EINVAL;
+ rc = roc_npc_skip_size_pkind_get(&dev->npc);
+ if (rc >= 0)
+ inb_sa_dptr->w0.s.pkind = rc;
+
cn20k_eth_sec_inb_sa_misc_fill(inb_sa_dptr, ipsec);
/* Use cookie for original data */
--
2.34.1
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH 09/17] common/cnxk: fix cnxk xstats names
2026-06-11 7:32 [PATCH 01/17] net/cnxk: update mbuf next field for multi segment Rahul Bhansali
` (6 preceding siblings ...)
2026-06-11 7:33 ` [PATCH 08/17] net/cnxk: update inbound SA pkind for " Rahul Bhansali
@ 2026-06-11 7:33 ` Rahul Bhansali
2026-06-11 7:33 ` [PATCH 10/17] common/cnxk: fix event type for soft expiry Rahul Bhansali
` (9 subsequent siblings)
17 siblings, 0 replies; 41+ messages in thread
From: Rahul Bhansali @ 2026-06-11 7:33 UTC (permalink / raw)
To: dev, Thomas Monjalon, Nithin Dabilpuram, Kiran Kumar K,
Sunil Kumar Kori, Satha Rao, Harman Kalra, Rakesh Kudurumalla
Cc: jerinj, Alok Mishra, stable
From: Alok Mishra <almishra@marvell.com>
Prevent out of bounds writes when application provides a smaller
xstat name array. Return required count when xstats_names is NULL
or when the provided buffer is too small,
Fixes: 825bd1d9d8e6 ("common/cnxk: update extra stats for inline device")
Cc: stable@dpdk.org
Signed-off-by: Alok Mishra <almishra@marvell.com>
---
.mailmap | 1 +
drivers/common/cnxk/roc_nix_stats.c | 46 ++++++++++++++++-------------
2 files changed, 26 insertions(+), 21 deletions(-)
diff --git a/.mailmap b/.mailmap
index 0e0d83e1c6..efcb38b6bd 100644
--- a/.mailmap
+++ b/.mailmap
@@ -80,6 +80,7 @@ Alin Rauta <alin.rauta@intel.com>
Allain Legacy <allain.legacy@windriver.com>
Allen Hubbe <allen.hubbe@amd.com>
Alok Makhariya <alok.makhariya@nxp.com>
+Alok Mishra <almishra@marvell.com>
Alok Prasad <palok@marvell.com>
Alvaro Karsz <alvaro.karsz@solid-run.com>
Alvin Zhang <alvinx.zhang@intel.com>
diff --git a/drivers/common/cnxk/roc_nix_stats.c b/drivers/common/cnxk/roc_nix_stats.c
index 6f241c72de..ec2aca8164 100644
--- a/drivers/common/cnxk/roc_nix_stats.c
+++ b/drivers/common/cnxk/roc_nix_stats.c
@@ -503,46 +503,51 @@ roc_nix_xstats_names_get(struct roc_nix *roc_nix,
struct idev_cfg *idev = idev_get_cfg();
uint64_t i, count = 0;
- PLT_SET_USED(limit);
-
for (i = 0; i < CNXK_NIX_NUM_TX_XSTATS; i++) {
- NIX_XSTATS_NAME_PRINT(xstats_names, count, nix_tx_xstats, i);
+ if (xstats_names && count < limit)
+ NIX_XSTATS_NAME_PRINT(xstats_names, count, nix_tx_xstats, i);
count++;
}
for (i = 0; i < CNXK_NIX_NUM_RX_XSTATS; i++) {
- NIX_XSTATS_NAME_PRINT(xstats_names, count, nix_rx_xstats, i);
+ if (xstats_names && count < limit)
+ NIX_XSTATS_NAME_PRINT(xstats_names, count, nix_rx_xstats, i);
count++;
}
if (nix->inb_inl_dev && idev) {
if (idev->nix_inl_dev) {
for (i = 0; i < CNXK_INL_NIX_NUM_RX_XSTATS; i++) {
- NIX_XSTATS_NAME_PRINT(xstats_names, count,
- inl_nix_rx_xstats, i);
+ if (xstats_names && count < limit)
+ NIX_XSTATS_NAME_PRINT(xstats_names, count,
+ inl_nix_rx_xstats, i);
count++;
}
for (i = 0; i < CNXK_INL_NIX_RQ_XSTATS; i++) {
- NIX_XSTATS_NAME_PRINT(xstats_names, count,
- inl_nix_rq_xstats, i);
+ if (xstats_names && count < limit)
+ NIX_XSTATS_NAME_PRINT(xstats_names, count,
+ inl_nix_rq_xstats, i);
count++;
}
for (i = 0; i < PLT_DIM(inl_sw_xstats); i++) {
- NIX_XSTATS_NAME_PRINT(xstats_names, count, inl_sw_xstats, i);
+ if (xstats_names && count < limit)
+ NIX_XSTATS_NAME_PRINT(xstats_names, count, inl_sw_xstats,
+ i);
count++;
}
}
}
for (i = 0; i < CNXK_NIX_NUM_QUEUE_XSTATS; i++) {
- NIX_XSTATS_NAME_PRINT(xstats_names, count, nix_q_xstats, i);
+ if (xstats_names && count < limit)
+ NIX_XSTATS_NAME_PRINT(xstats_names, count, nix_q_xstats, i);
count++;
}
if (roc_model_is_cn10k() || roc_model_is_cn20k()) {
for (i = 0; i < CNXK_NIX_NUM_CN10K_RX_XSTATS; i++) {
- NIX_XSTATS_NAME_PRINT(xstats_names, count,
- nix_cn10k_rx_xstats, i);
+ if (xstats_names && count < limit)
+ NIX_XSTATS_NAME_PRINT(xstats_names, count, nix_cn10k_rx_xstats, i);
count++;
}
}
@@ -552,30 +557,29 @@ roc_nix_xstats_names_get(struct roc_nix *roc_nix,
if (roc_model_is_cn9k()) {
for (i = 0; i < CNXK_NIX_NUM_RX_XSTATS_CGX; i++) {
- NIX_XSTATS_NAME_PRINT(xstats_names, count,
- nix_rx_xstats_cgx, i);
+ if (xstats_names && count < limit)
+ NIX_XSTATS_NAME_PRINT(xstats_names, count, nix_rx_xstats_cgx, i);
count++;
}
for (i = 0; i < CNXK_NIX_NUM_TX_XSTATS_CGX; i++) {
- NIX_XSTATS_NAME_PRINT(xstats_names, count,
- nix_tx_xstats_cgx, i);
+ if (xstats_names && count < limit)
+ NIX_XSTATS_NAME_PRINT(xstats_names, count, nix_tx_xstats_cgx, i);
count++;
}
} else {
for (i = 0; i < CNXK_NIX_NUM_RX_XSTATS_RPM; i++) {
- NIX_XSTATS_NAME_PRINT(xstats_names, count,
- nix_rx_xstats_rpm, i);
+ if (xstats_names && count < limit)
+ NIX_XSTATS_NAME_PRINT(xstats_names, count, nix_rx_xstats_rpm, i);
count++;
}
for (i = 0; i < CNXK_NIX_NUM_TX_XSTATS_RPM; i++) {
- NIX_XSTATS_NAME_PRINT(xstats_names, count,
- nix_tx_xstats_rpm, i);
+ if (xstats_names && count < limit)
+ NIX_XSTATS_NAME_PRINT(xstats_names, count, nix_tx_xstats_rpm, i);
count++;
}
}
-
return count;
}
--
2.34.1
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH 10/17] common/cnxk: fix event type for soft expiry
2026-06-11 7:32 [PATCH 01/17] net/cnxk: update mbuf next field for multi segment Rahul Bhansali
` (7 preceding siblings ...)
2026-06-11 7:33 ` [PATCH 09/17] common/cnxk: fix cnxk xstats names Rahul Bhansali
@ 2026-06-11 7:33 ` Rahul Bhansali
2026-06-11 7:33 ` [PATCH 11/17] net/cnxk: enable CPT CQ by default for inline IPsec Rahul Bhansali
` (8 subsequent siblings)
17 siblings, 0 replies; 41+ messages in thread
From: Rahul Bhansali @ 2026-06-11 7:33 UTC (permalink / raw)
To: dev, Nithin Dabilpuram, Kiran Kumar K, Sunil Kumar Kori,
Satha Rao, Harman Kalra, Stephen Hemminger
Cc: jerinj, Rahul Bhansali
Fix event type to default for inline soft expiry processing.
Fixes: 4a6154a7bd27 ("common/cnxk: fix array out-of-bounds")
Signed-off-by: Rahul Bhansali <rbhansali@marvell.com>
---
drivers/common/cnxk/roc_nix_inl_dev.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/common/cnxk/roc_nix_inl_dev.c b/drivers/common/cnxk/roc_nix_inl_dev.c
index 667209b8a0..bfdeef2688 100644
--- a/drivers/common/cnxk/roc_nix_inl_dev.c
+++ b/drivers/common/cnxk/roc_nix_inl_dev.c
@@ -1234,6 +1234,7 @@ inl_outb_soft_exp_poll(struct nix_inl_dev *inl_dev, uint32_t ring_idx)
if (sa != NULL) {
uint64_t tmp[2];
+ tmp[0] = ~0ULL;
inl_dev->work_cb(tmp, sa, NIX_INL_SOFT_EXPIRY_THRD, NULL, port_id);
__atomic_store_n(ring_base + tail_l + 1, 0ULL, __ATOMIC_RELAXED);
__atomic_fetch_add((uint32_t *)ring_base, 1, __ATOMIC_ACQ_REL);
--
2.34.1
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH 11/17] net/cnxk: enable CPT CQ by default for inline IPsec
2026-06-11 7:32 [PATCH 01/17] net/cnxk: update mbuf next field for multi segment Rahul Bhansali
` (8 preceding siblings ...)
2026-06-11 7:33 ` [PATCH 10/17] common/cnxk: fix event type for soft expiry Rahul Bhansali
@ 2026-06-11 7:33 ` Rahul Bhansali
2026-06-11 7:33 ` [PATCH 12/17] net/cnxk: fix unsigned integer underflow in LSO calculation Rahul Bhansali
` (7 subsequent siblings)
17 siblings, 0 replies; 41+ messages in thread
From: Rahul Bhansali @ 2026-06-11 7:33 UTC (permalink / raw)
To: dev, Nithin Dabilpuram, Kiran Kumar K, Sunil Kumar Kori,
Satha Rao, Harman Kalra
Cc: jerinj, Aarnav JP
From: Aarnav JP <ajp@marvell.com>
CPT Completion Queue is supported on CN20K and provides
hardware-based completion notification, eliminating the
need for software polling. Change the default value of
cpt_cq_enable devarg from 0 to 1 so that CPT CQ is
enabled by default.
Signed-off-by: Aarnav JP <ajp@marvell.com>
---
doc/guides/nics/cnxk.rst | 13 +++++++++++++
drivers/net/cnxk/cnxk_ethdev_sec.c | 2 +-
2 files changed, 14 insertions(+), 1 deletion(-)
diff --git a/doc/guides/nics/cnxk.rst b/doc/guides/nics/cnxk.rst
index 239ebcd05c..c71029e1dc 100644
--- a/doc/guides/nics/cnxk.rst
+++ b/doc/guides/nics/cnxk.rst
@@ -745,6 +745,19 @@ Runtime Config Options for inline device
With the above configuration, inline inbound IPsec post-processing
should be done by the application.
+- ``Enable CPT Completion Queue for inline IPsec`` (default ``1`` for CN20K, ``0`` otherwise)
+
+ CPT Completion Queue for inline IPsec event delivery can be enabled or disabled
+ by ``cpt_cq_enable`` devargs parameter.
+ This option is supported on OCTEON CN20K SoC family.
+
+ For example::
+
+ -a 0002:1d:00.0,cpt_cq_enable=1
+
+ With the above configuration, driver would enable CPT completion queue
+ for inline IPsec event delivery instead of using the err-ring poll thread.
+
Port Representors
-----------------
diff --git a/drivers/net/cnxk/cnxk_ethdev_sec.c b/drivers/net/cnxk/cnxk_ethdev_sec.c
index fa7eacfbe4..61eb55ba43 100644
--- a/drivers/net/cnxk/cnxk_ethdev_sec.c
+++ b/drivers/net/cnxk/cnxk_ethdev_sec.c
@@ -742,7 +742,7 @@ nix_inl_parse_devargs(struct rte_devargs *devargs,
uint32_t meta_buf_sz = 0;
uint8_t rx_inj_ena = 0;
uint8_t selftest = 0;
- uint8_t cpt_cq_enable = 0;
+ uint8_t cpt_cq_enable = roc_feature_nix_has_cpt_cq_support() ? 1 : 0;
memset(&cpt_channel, 0, sizeof(cpt_channel));
--
2.34.1
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH 12/17] net/cnxk: fix unsigned integer underflow in LSO calculation
2026-06-11 7:32 [PATCH 01/17] net/cnxk: update mbuf next field for multi segment Rahul Bhansali
` (9 preceding siblings ...)
2026-06-11 7:33 ` [PATCH 11/17] net/cnxk: enable CPT CQ by default for inline IPsec Rahul Bhansali
@ 2026-06-11 7:33 ` Rahul Bhansali
2026-06-11 7:33 ` [PATCH 13/17] net/cnxk: derive ethdev from SA for inbound CPT CQ events Rahul Bhansali
` (6 subsequent siblings)
17 siblings, 0 replies; 41+ messages in thread
From: Rahul Bhansali @ 2026-06-11 7:33 UTC (permalink / raw)
To: dev, Nithin Dabilpuram, Kiran Kumar K, Sunil Kumar Kori,
Satha Rao, Harman Kalra, Pavan Nikhilesh, Jerin Jacob,
Rahul Bhansali
Cc: Aarnav JP, stable
From: Aarnav JP <ajp@marvell.com>
Replace branchless mask-based selection with a ternary operator
to resolve Coverity integer underflow warning. The expression
-(!w1.il3type) assigned -1 to a uint64_t variable, which is
well-defined but flagged as an unsigned integer underflow.
Coverity issue: 502004
Fixes: 19f3af2371a7 ("net/cnxk: add Tx burst for CN10K")
Fixes: 39dc567c1955 ("net/cnxk: add Tx burst for CN9K")
Fixes: 006c1daa89b9 ("net/cnxk: support Tx burst scalar for CN20K")
Cc: stable@dpdk.org
Signed-off-by: Aarnav JP <ajp@marvell.com>
---
drivers/net/cnxk/cn10k_tx.h | 8 ++------
drivers/net/cnxk/cn20k_tx.h | 8 ++------
drivers/net/cnxk/cn9k_tx.h | 8 ++------
3 files changed, 6 insertions(+), 18 deletions(-)
diff --git a/drivers/net/cnxk/cn10k_tx.h b/drivers/net/cnxk/cn10k_tx.h
index 8c912a1f35..d5cb2c3294 100644
--- a/drivers/net/cnxk/cn10k_tx.h
+++ b/drivers/net/cnxk/cn10k_tx.h
@@ -1138,10 +1138,8 @@ cn10k_nix_xmit_prepare(struct cn10k_eth_txq *txq,
if (flags & NIX_TX_NEED_EXT_HDR && flags & NIX_TX_OFFLOAD_TSO_F &&
(ol_flags & RTE_MBUF_F_TX_TCP_SEG)) {
uint16_t lso_sb;
- uint64_t mask;
- mask = -(!w1.il3type);
- lso_sb = (mask & w1.ol4ptr) + (~mask & w1.il4ptr) + m->l4_len;
+ lso_sb = (w1.il3type ? w1.il4ptr : w1.ol4ptr) + m->l4_len;
send_hdr_ext->w0.lso_sb = lso_sb;
send_hdr_ext->w0.lso = 1;
@@ -1766,13 +1764,11 @@ cn10k_nix_prepare_tso(struct rte_mbuf *m, union nix_send_hdr_w1_u *w1,
const uint64_t flags, const uint64_t lso_tun_fmt)
{
uint16_t lso_sb;
- uint64_t mask;
if (!(ol_flags & RTE_MBUF_F_TX_TCP_SEG))
return;
- mask = -(!w1->il3type);
- lso_sb = (mask & w1->ol4ptr) + (~mask & w1->il4ptr) + m->l4_len;
+ lso_sb = (w1->il3type ? w1->il4ptr : w1->ol4ptr) + m->l4_len;
w0->u |= BIT(14);
w0->lso_sb = lso_sb;
diff --git a/drivers/net/cnxk/cn20k_tx.h b/drivers/net/cnxk/cn20k_tx.h
index 8e64d2e352..a1c71f2761 100644
--- a/drivers/net/cnxk/cn20k_tx.h
+++ b/drivers/net/cnxk/cn20k_tx.h
@@ -1117,10 +1117,8 @@ cn20k_nix_xmit_prepare(struct cn20k_eth_txq *txq, struct rte_mbuf *m, struct rte
if (flags & NIX_TX_NEED_EXT_HDR && flags & NIX_TX_OFFLOAD_TSO_F &&
(ol_flags & RTE_MBUF_F_TX_TCP_SEG)) {
uint16_t lso_sb;
- uint64_t mask;
- mask = -(!w1.il3type);
- lso_sb = (mask & w1.ol4ptr) + (~mask & w1.il4ptr) + m->l4_len;
+ lso_sb = (w1.il3type ? w1.il4ptr : w1.ol4ptr) + m->l4_len;
send_hdr_ext->w0.lso_sb = lso_sb;
send_hdr_ext->w0.lso = 1;
@@ -1732,13 +1730,11 @@ cn20k_nix_prepare_tso(struct rte_mbuf *m, union nix_send_hdr_w1_u *w1, union nix
uint64_t ol_flags, const uint64_t flags, const uint64_t lso_tun_fmt)
{
uint16_t lso_sb;
- uint64_t mask;
if (!(ol_flags & RTE_MBUF_F_TX_TCP_SEG))
return;
- mask = -(!w1->il3type);
- lso_sb = (mask & w1->ol4ptr) + (~mask & w1->il4ptr) + m->l4_len;
+ lso_sb = (w1->il3type ? w1->il4ptr : w1->ol4ptr) + m->l4_len;
w0->u |= BIT(14);
w0->lso_sb = lso_sb;
diff --git a/drivers/net/cnxk/cn9k_tx.h b/drivers/net/cnxk/cn9k_tx.h
index 0ec448e36c..2f9b936d56 100644
--- a/drivers/net/cnxk/cn9k_tx.h
+++ b/drivers/net/cnxk/cn9k_tx.h
@@ -478,10 +478,8 @@ cn9k_nix_xmit_prepare(struct cn9k_eth_txq *txq, struct rte_mbuf *m, struct rte_m
if (flags & NIX_TX_OFFLOAD_TSO_F && (ol_flags & RTE_MBUF_F_TX_TCP_SEG)) {
uint16_t lso_sb;
- uint64_t mask;
- mask = -(!w1.il3type);
- lso_sb = (mask & w1.ol4ptr) + (~mask & w1.il4ptr) + m->l4_len;
+ lso_sb = (w1.il3type ? w1.il4ptr : w1.ol4ptr) + m->l4_len;
send_hdr_ext->w0.lso_sb = lso_sb;
send_hdr_ext->w0.lso = 1;
@@ -875,13 +873,11 @@ cn9k_nix_prepare_tso(struct rte_mbuf *m, union nix_send_hdr_w1_u *w1,
uint64_t flags)
{
uint16_t lso_sb;
- uint64_t mask;
if (!(ol_flags & RTE_MBUF_F_TX_TCP_SEG))
return;
- mask = -(!w1->il3type);
- lso_sb = (mask & w1->ol4ptr) + (~mask & w1->il4ptr) + m->l4_len;
+ lso_sb = (w1->il3type ? w1->il4ptr : w1->ol4ptr) + m->l4_len;
w0->u |= BIT(14);
w0->lso_sb = lso_sb;
--
2.34.1
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH 13/17] net/cnxk: derive ethdev from SA for inbound CPT CQ events
2026-06-11 7:32 [PATCH 01/17] net/cnxk: update mbuf next field for multi segment Rahul Bhansali
` (10 preceding siblings ...)
2026-06-11 7:33 ` [PATCH 12/17] net/cnxk: fix unsigned integer underflow in LSO calculation Rahul Bhansali
@ 2026-06-11 7:33 ` Rahul Bhansali
2026-06-11 7:33 ` [PATCH 14/17] net/cnxk: fix bitwise operand size mismatch in link mode Rahul Bhansali
` (5 subsequent siblings)
17 siblings, 0 replies; 41+ messages in thread
From: Rahul Bhansali @ 2026-06-11 7:33 UTC (permalink / raw)
To: dev, Nithin Dabilpuram, Kiran Kumar K, Sunil Kumar Kori,
Satha Rao, Harman Kalra
Cc: jerinj, Aarnav JP
From: Aarnav JP <ajp@marvell.com>
With inbound CPT CQ events, port_id is unavailable since the inline
device has no roc_nix. Resolve eth_dev for inbound CQ events in the
cn20k PMD callback via the SA private data chain instead of relying
on port_id.
Add an eth_dev back pointer to cnxk_eth_sec_sess, populated at
session creation, to complete the SA-to-ethdev lookup path
(inb_priv->eth_sec->eth_dev).
Signed-off-by: Aarnav JP <ajp@marvell.com>
---
drivers/net/cnxk/cn20k_ethdev_sec.c | 22 ++++++++++++++++++++--
drivers/net/cnxk/cnxk_ethdev.h | 3 +++
2 files changed, 23 insertions(+), 2 deletions(-)
diff --git a/drivers/net/cnxk/cn20k_ethdev_sec.c b/drivers/net/cnxk/cn20k_ethdev_sec.c
index 31f2518ea3..a5be85901f 100644
--- a/drivers/net/cnxk/cn20k_ethdev_sec.c
+++ b/drivers/net/cnxk/cn20k_ethdev_sec.c
@@ -541,7 +541,6 @@ cn20k_eth_sec_sso_work_cb(uint64_t *gw, void *args, enum nix_inl_event_type type
uintptr_t nixtx;
uint8_t port;
- RTE_SET_USED(args);
plt_nix_dbg("Received %s event", get_inl_event_type(type));
switch ((gw[0] >> 28) & 0xF) {
@@ -561,8 +560,26 @@ cn20k_eth_sec_sso_work_cb(uint64_t *gw, void *args, enum nix_inl_event_type type
/* Fall through */
default:
if (type) {
- eth_dev = &rte_eth_devices[port_id];
struct cpt_cq_s *cqs = (struct cpt_cq_s *)cq_s;
+
+ if (type == NIX_INL_INB_CPT_CQ) {
+ struct cn20k_inb_priv_data *inb_priv;
+
+ inb_priv = roc_nix_inl_ow_ipsec_inb_sa_sw_rsvd(args);
+ if (inb_priv->eth_sec && inb_priv->eth_sec->eth_dev) {
+ eth_dev = inb_priv->eth_sec->eth_dev;
+ } else {
+ plt_err("Inbound CPT CQ event: no eth_dev in SA priv");
+ return;
+ }
+ } else {
+ if (port_id >= RTE_MAX_ETHPORTS) {
+ plt_err("CPT CQ event: invalid port_id %u", port_id);
+ return;
+ }
+ eth_dev = &rte_eth_devices[port_id];
+ }
+
if (type < NIX_INL_SSO) {
cn20k_eth_sec_post_event(eth_dev, args, type,
(uint16_t)cqs->w0.s.uc_compcode,
@@ -804,6 +821,7 @@ cn20k_eth_sec_session_create(void *device, struct rte_security_session_conf *con
inl_dev = !!dev->inb.inl_dev;
memset(eth_sec, 0, sizeof(struct cnxk_eth_sec_sess));
+ eth_sec->eth_dev = eth_dev;
sess_priv.u64 = 0;
lock = inbound ? &dev->inb.lock : &dev->outb.lock;
diff --git a/drivers/net/cnxk/cnxk_ethdev.h b/drivers/net/cnxk/cnxk_ethdev.h
index ea6a2be30e..6686fdba31 100644
--- a/drivers/net/cnxk/cnxk_ethdev.h
+++ b/drivers/net/cnxk/cnxk_ethdev.h
@@ -225,6 +225,9 @@ struct cnxk_eth_sec_sess {
/* Out-Of-Place processing */
bool inb_oop;
+
+ /* Back pointer to eth_dev for port_id derivation in CQ callbacks */
+ struct rte_eth_dev *eth_dev;
};
TAILQ_HEAD(cnxk_eth_sec_sess_list, cnxk_eth_sec_sess);
--
2.34.1
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH 14/17] net/cnxk: fix bitwise operand size mismatch in link mode
2026-06-11 7:32 [PATCH 01/17] net/cnxk: update mbuf next field for multi segment Rahul Bhansali
` (11 preceding siblings ...)
2026-06-11 7:33 ` [PATCH 13/17] net/cnxk: derive ethdev from SA for inbound CPT CQ events Rahul Bhansali
@ 2026-06-11 7:33 ` Rahul Bhansali
2026-06-11 7:33 ` [PATCH 15/17] common/cnxk: add cipher key length check in key set Rahul Bhansali
` (4 subsequent siblings)
17 siblings, 0 replies; 41+ messages in thread
From: Rahul Bhansali @ 2026-06-11 7:33 UTC (permalink / raw)
To: dev, Nithin Dabilpuram, Kiran Kumar K, Sunil Kumar Kori,
Satha Rao, Harman Kalra
Cc: jerinj, Aarnav JP, stable
From: Aarnav JP <ajp@marvell.com>
Cast enum roc_nix_link_mode values to uint64_t before bitwise
OR with uint64_t advertise variable to ensure consistent
operand sizes.
Fixes: 292fcbb3d290 ("net/cnxk: support link mode configuration")
Cc: stable@dpdk.org
Signed-off-by: Aarnav JP <ajp@marvell.com>
---
drivers/net/cnxk/cnxk_link.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/net/cnxk/cnxk_link.c b/drivers/net/cnxk/cnxk_link.c
index dde2c3a313..f6682b4697 100644
--- a/drivers/net/cnxk/cnxk_link.c
+++ b/drivers/net/cnxk/cnxk_link.c
@@ -61,13 +61,13 @@ nix_link_advertising_get(struct cnxk_eth_dev *dev, struct roc_nix_link_info *lin
} else {
for (bit = 0; bit < ROC_NIX_LINK_SPEED_MAX; bit++) {
if (link_info->speed_bitmask & BIT_ULL(bit))
- advertise |= rte_to_ethtool_mode[bit];
+ advertise |= (uint64_t)rte_to_ethtool_mode[bit];
}
goto exit;
}
}
- advertise |= mac_to_ethtool_mode[linfo.lmac_type_id][link_info->full_duplex];
+ advertise |= (uint64_t)mac_to_ethtool_mode[linfo.lmac_type_id][link_info->full_duplex];
exit:
return advertise;
}
--
2.34.1
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH 15/17] common/cnxk: add cipher key length check in key set
2026-06-11 7:32 [PATCH 01/17] net/cnxk: update mbuf next field for multi segment Rahul Bhansali
` (12 preceding siblings ...)
2026-06-11 7:33 ` [PATCH 14/17] net/cnxk: fix bitwise operand size mismatch in link mode Rahul Bhansali
@ 2026-06-11 7:33 ` Rahul Bhansali
2026-06-11 7:33 ` [PATCH 16/17] common/cnxk: fix Klocwork static analysis issues Rahul Bhansali
` (3 subsequent siblings)
17 siblings, 0 replies; 41+ messages in thread
From: Rahul Bhansali @ 2026-06-11 7:33 UTC (permalink / raw)
To: dev, Nithin Dabilpuram, Kiran Kumar K, Sunil Kumar Kori,
Satha Rao, Harman Kalra, Ankur Dwivedi, Akhil Goyal
Cc: jerinj, Aarnav JP, stable
From: Aarnav JP <ajp@marvell.com>
Add upper-bound checks before memcpy into encr_key[32]
in roc_se_ciph_key_set() to prevent buffer overflow into
adjacent encr_iv[16]. Covers all write paths including
AES-DOCSISBPI and DES-DOCSISBPI branches that bypass
the generic copy via goto.
Fixes: 5e076b609f2a ("common/cnxk: add SE set key for crypto")
Cc: stable@dpdk.org
Signed-off-by: Aarnav JP <ajp@marvell.com>
---
drivers/common/cnxk/roc_se.c | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/drivers/common/cnxk/roc_se.c b/drivers/common/cnxk/roc_se.c
index d841a926a4..1cec536169 100644
--- a/drivers/common/cnxk/roc_se.c
+++ b/drivers/common/cnxk/roc_se.c
@@ -545,12 +545,22 @@ roc_se_ciph_key_set(struct roc_se_ctx *se_ctx, roc_se_cipher_type type, const ui
* less than 128. Pass it as regular AES-CBC cipher to CPT, but keep type in
* se_ctx as AES_DOCSISBPI to skip block size checks in instruction preparation.
*/
+ if (key_len > sizeof(fctx->enc.encr_key)) {
+ plt_err("Cipher key length %u exceeds max %zu", key_len,
+ sizeof(fctx->enc.encr_key));
+ return -1;
+ }
cpt_ciph_aes_key_type_set(fctx, key_len);
fctx->enc.enc_cipher = ROC_SE_AES_CBC;
memcpy(fctx->enc.encr_key, key, key_len);
goto success;
case ROC_SE_DES_DOCSISBPI:
/* See case ROC_SE_DES3_CBC: for explanation */
+ if (key_len * 3 > sizeof(fctx->enc.encr_key)) {
+ plt_err("DES-DOCSISBPI key length %u exceeds max %zu", key_len,
+ sizeof(fctx->enc.encr_key) / 3);
+ return -1;
+ }
for (i = 0; i < 3; i++)
memcpy(fctx->enc.encr_key + key_len * i, key, key_len);
/*
@@ -628,6 +638,11 @@ roc_se_ciph_key_set(struct roc_se_ctx *se_ctx, roc_se_cipher_type type, const ui
if (se_ctx->hash_type != ROC_SE_GMAC_TYPE)
fctx->enc.enc_cipher = type;
+ if (key_len > sizeof(fctx->enc.encr_key)) {
+ plt_err("Cipher key length %u exceeds max %zu", key_len,
+ sizeof(fctx->enc.encr_key));
+ return -1;
+ }
memcpy(fctx->enc.encr_key, key, key_len);
success:
--
2.34.1
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH 16/17] common/cnxk: fix Klocwork static analysis issues
2026-06-11 7:32 [PATCH 01/17] net/cnxk: update mbuf next field for multi segment Rahul Bhansali
` (13 preceding siblings ...)
2026-06-11 7:33 ` [PATCH 15/17] common/cnxk: add cipher key length check in key set Rahul Bhansali
@ 2026-06-11 7:33 ` Rahul Bhansali
2026-06-11 7:33 ` [PATCH 17/17] common/cnxk: add auth key len check in inbound SA Rahul Bhansali
` (2 subsequent siblings)
17 siblings, 0 replies; 41+ messages in thread
From: Rahul Bhansali @ 2026-06-11 7:33 UTC (permalink / raw)
To: dev, Nithin Dabilpuram, Kiran Kumar K, Sunil Kumar Kori,
Satha Rao, Harman Kalra, Satheesh Paul, Jerin Jacob,
Rakesh Kudurumalla
Cc: Aarnav JP, stable
From: Aarnav JP <ajp@marvell.com>
Fix NULL pointer dereferences (roc_dev.c, roc_npa.c, roc_nix_inl.c),
resource leaks in error paths (roc_dev.c, roc_dpi.c, roc_ree.c,
roc_nix.c, roc_emdev.c), uninitialized variables (roc_npa_debug.c,
roc_emdev.c), array out-of-bounds access (roc_npc_utils.c, roc_emdev.c),
bitwise operand size mismatches (roc_mbox.h, roc_emdev_irq.c), and
format string type mismatches (roc_cpt_debug.c).
Fixes: 5d8ff275433a ("common/cnxk: fix race condition between up and down mailbox")
Fixes: 9a92937cf0c8 ("common/cnxk: fix possible out-of-bounds access")
Fixes: 7557e3f5b9fa ("common/cnxk: replace direct API usage in REE")
Fixes: 3fdf3e53f3c4 ("common/cnxk: enable CPT CQ for inline IPsec inbound")
Fixes: c758279fee32 ("common/cnxk: support debug dump to file")
Cc: stable@dpdk.org
Signed-off-by: Aarnav JP <ajp@marvell.com>
---
drivers/common/cnxk/roc_cpt_debug.c | 29 ++++++++++++++---------------
drivers/common/cnxk/roc_dev.c | 15 +++++++++++----
drivers/common/cnxk/roc_mbox.h | 4 ++--
drivers/common/cnxk/roc_nix_inl.c | 3 +--
drivers/common/cnxk/roc_npa.c | 3 +++
drivers/common/cnxk/roc_npa_debug.c | 8 +++++++-
drivers/common/cnxk/roc_npc_utils.c | 10 +++++++---
drivers/common/cnxk/roc_ree.c | 17 ++++++++++++-----
8 files changed, 57 insertions(+), 32 deletions(-)
diff --git a/drivers/common/cnxk/roc_cpt_debug.c b/drivers/common/cnxk/roc_cpt_debug.c
index 3b3e678c20..3c1c052e50 100644
--- a/drivers/common/cnxk/roc_cpt_debug.c
+++ b/drivers/common/cnxk/roc_cpt_debug.c
@@ -33,7 +33,7 @@ cpt_cnxk_parse_hdr_dump(FILE *file, const struct cpt_parse_hdr_s *cpth)
cpth->w0.num_frags, cpth->w0.pkt_out);
/* W1 */
- cpt_dump(file, "W1: wqe_ptr \t0x%016lx\t", cpth->wqe_ptr);
+ cpt_dump(file, "W1: wqe_ptr \t0x%016" PRIx64 "\t", cpth->wqe_ptr);
/* W2 */
cpt_dump(file, "W2: pkt_inline \t0x%x\t\torig_pkt_aura \t0x%x", cpth->w2.pkt_inline,
@@ -135,29 +135,28 @@ cpt_cn10k_parse_hdr_dump(FILE *file, const struct cpt_cn10k_parse_hdr_s *cpth)
cpt_dump(file, "W0: cookie \t0x%x\t\tmatch_id \t0x%04x \t",
cpth->w0.cookie, cpth->w0.match_id);
cpt_dump(file, "W0: err_sum \t%u \t", cpth->w0.err_sum);
- cpt_dump(file, "W0: reas_sts \t0x%x\t\tet_owr \t%u\t\tpkt_fmt \t%u \t",
- cpth->w0.reas_sts, cpth->w0.et_owr, cpth->w0.pkt_fmt);
- cpt_dump(file, "W0: pad_len \t%u\t\tnum_frags \t%u\t\tpkt_out \t%u \t",
- cpth->w0.pad_len, cpth->w0.num_frags, cpth->w0.pkt_out);
+ cpt_dump(file, "W0: reas_sts \t0x%x\t\tet_owr \t%u\t\tpkt_fmt \t%u \t", cpth->w0.reas_sts,
+ cpth->w0.et_owr, cpth->w0.pkt_fmt);
+ cpt_dump(file, "W0: pad_len \t%u\t\tnum_frags \t%u\t\tpkt_out \t%u \t", cpth->w0.pad_len,
+ cpth->w0.num_frags, cpth->w0.pkt_out);
/* W1 */
- cpt_dump(file, "W1: wqe_ptr \t0x%016lx\t",
- plt_be_to_cpu_64(cpth->wqe_ptr));
+ cpt_dump(file, "W1: wqe_ptr \t0x%016" PRIx64 "\t",
+ (uint64_t)plt_be_to_cpu_64(cpth->wqe_ptr));
/* W2 */
- cpt_dump(file, "W2: frag_age \t0x%x\t\torig_pf_func \t0x%04x",
- cpth->w2.frag_age, cpth->w2.orig_pf_func);
- cpt_dump(file, "W2: il3_off \t0x%x\t\tfi_pad \t0x%x \t",
- cpth->w2.il3_off, cpth->w2.fi_pad);
+ cpt_dump(file, "W2: frag_age \t0x%x\t\torig_pf_func \t0x%04x", cpth->w2.frag_age,
+ cpth->w2.orig_pf_func);
+ cpt_dump(file, "W2: il3_off \t0x%x\t\tfi_pad \t0x%x \t", cpth->w2.il3_off, cpth->w2.fi_pad);
cpt_dump(file, "W2: fi_offset \t0x%x \t", cpth->w2.fi_offset);
/* W3 */
- cpt_dump(file, "W3: hw_ccode \t0x%x\t\tuc_ccode \t0x%x\t\tspi \t0x%08x",
- cpth->w3.hw_ccode, cpth->w3.uc_ccode, cpth->w3.spi);
+ cpt_dump(file, "W3: hw_ccode \t0x%x\t\tuc_ccode \t0x%x\t\tspi \t0x%08x", cpth->w3.hw_ccode,
+ cpth->w3.uc_ccode, cpth->w3.spi);
/* W4 */
- cpt_dump(file, "W4: esn \t%" PRIx64 " \t OR frag1_wqe_ptr \t0x%" PRIx64,
- cpth->esn, plt_be_to_cpu_64(cpth->frag1_wqe_ptr));
+ cpt_dump(file, "W4: esn \t%" PRIx64 " \t OR frag1_wqe_ptr \t0x%" PRIx64, cpth->esn,
+ (uint64_t)plt_be_to_cpu_64(cpth->frag1_wqe_ptr));
/* offset of 0 implies 256B, otherwise it implies offset*8B */
offset = cpth->w2.fi_offset;
diff --git a/drivers/common/cnxk/roc_dev.c b/drivers/common/cnxk/roc_dev.c
index 32409f2ef3..61aa4b3075 100644
--- a/drivers/common/cnxk/roc_dev.c
+++ b/drivers/common/cnxk/roc_dev.c
@@ -1796,14 +1796,17 @@ dev_init(struct dev *dev, struct plt_pci_device *pci_dev)
rc = npa_lf_init(dev, pci_dev);
if (rc)
- goto stop_msg_thrd;
+ goto vf_flr_unregister;
/* Setup LMT line base */
rc = dev_lmt_setup(dev);
if (rc)
- goto stop_msg_thrd;
+ goto vf_flr_unregister;
return rc;
+vf_flr_unregister:
+ if (!is_vf)
+ dev_vf_flr_unregister_irqs(pci_dev, dev);
stop_msg_thrd:
/* Exiting the mbox sync thread */
if (dev->sync.start_thread) {
@@ -1812,10 +1815,14 @@ dev_init(struct dev *dev, struct plt_pci_device *pci_dev)
plt_thread_join(dev->sync.pfvf_msg_thread, NULL);
}
thread_fail:
- pthread_mutex_destroy(&dev->sync.mutex);
- pthread_cond_destroy(&dev->sync.pfvf_msg_cond);
+ if (pci_dev->max_vfs > 0) {
+ pthread_mutex_destroy(&dev->sync.mutex);
+ pthread_cond_destroy(&dev->sync.pfvf_msg_cond);
+ }
iounmap:
dev_vf_mbase_put(pci_dev, vf_mbase);
+ mbox_fini(&dev->mbox_vfpf);
+ mbox_fini(&dev->mbox_vfpf_up);
mbox_unregister:
dev_mbox_unregister_irq(pci_dev, dev);
if (dev->ops)
diff --git a/drivers/common/cnxk/roc_mbox.h b/drivers/common/cnxk/roc_mbox.h
index 1158ff50a7..52ecde6563 100644
--- a/drivers/common/cnxk/roc_mbox.h
+++ b/drivers/common/cnxk/roc_mbox.h
@@ -47,8 +47,8 @@ struct mbox_msghdr {
#define RVU_VF_VFPF_MBOX0 (0x0000)
#define RVU_VF_VFPF_MBOX1 (0x0008)
-#define MBOX_DOWN_MSG 1
-#define MBOX_UP_MSG 2
+#define MBOX_DOWN_MSG 1ULL
+#define MBOX_UP_MSG 2ULL
/* Mailbox message types */
#define MBOX_MSG_MASK 0xFFFF
diff --git a/drivers/common/cnxk/roc_nix_inl.c b/drivers/common/cnxk/roc_nix_inl.c
index b515d52534..db101e71a5 100644
--- a/drivers/common/cnxk/roc_nix_inl.c
+++ b/drivers/common/cnxk/roc_nix_inl.c
@@ -638,9 +638,8 @@ nix_inl_reass_inb_sa_tbl_setup(struct roc_nix *roc_nix)
res_addr_offset = (uint64_t)(inl_dev->res_addr_offset & 0xFF) << 48;
if (res_addr_offset)
res_addr_offset |= (1UL << 56);
+ cpt_cq_ena = (uint64_t)inl_dev->cpt_cq_ena << 63;
}
-
- cpt_cq_ena = (uint64_t)inl_dev->cpt_cq_ena << 63;
lf_cfg->enable = 1;
lf_cfg->profile_id = profile_id;
lf_cfg->rx_inline_sa_base = (uintptr_t)nix->inb_sa_base[profile_id] | cpt_cq_ena;
diff --git a/drivers/common/cnxk/roc_npa.c b/drivers/common/cnxk/roc_npa.c
index 88e328105a..4a3e96a97a 100644
--- a/drivers/common/cnxk/roc_npa.c
+++ b/drivers/common/cnxk/roc_npa.c
@@ -1113,6 +1113,9 @@ roc_npa_pool_destroy(uint64_t aura_handle)
struct npa_lf *lf = idev_npa_obj_get();
int rc = 0, aura_id;
+ if (lf == NULL)
+ return NPA_ERR_DEVICE_NOT_BOUNDED;
+
plt_npa_dbg("lf=%p aura_handle=0x%" PRIx64, lf, aura_handle);
aura_id = roc_npa_aura_handle_to_aura(aura_handle);
diff --git a/drivers/common/cnxk/roc_npa_debug.c b/drivers/common/cnxk/roc_npa_debug.c
index e64696730f..f978be9642 100644
--- a/drivers/common/cnxk/roc_npa_debug.c
+++ b/drivers/common/cnxk/roc_npa_debug.c
@@ -283,6 +283,9 @@ roc_npa_ctx_dump(void)
if (lf->aura_attr[q].halo) {
aq->ctype = NPA_AQ_CTYPE_HALO;
rc = mbox_process_msg(mbox, (void *)&rsp_cn20k);
+ } else if (roc_model_is_cn20k()) {
+ aq->ctype = NPA_AQ_CTYPE_AURA;
+ rc = mbox_process_msg(mbox, (void *)&rsp_cn20k);
} else {
aq->ctype = NPA_AQ_CTYPE_AURA;
rc = mbox_process_msg(mbox, (void *)&rsp);
@@ -323,7 +326,10 @@ roc_npa_ctx_dump(void)
aq->ctype = NPA_AQ_CTYPE_POOL;
aq->op = NPA_AQ_INSTOP_READ;
- rc = mbox_process_msg(mbox, (void *)&rsp);
+ if (roc_model_is_cn20k())
+ rc = mbox_process_msg(mbox, (void *)&rsp_cn20k);
+ else
+ rc = mbox_process_msg(mbox, (void *)&rsp);
if (rc) {
plt_err("Failed to get pool(%d) context", q);
goto exit;
diff --git a/drivers/common/cnxk/roc_npc_utils.c b/drivers/common/cnxk/roc_npc_utils.c
index 3c05e46e1b..8e83b8662d 100644
--- a/drivers/common/cnxk/roc_npc_utils.c
+++ b/drivers/common/cnxk/roc_npc_utils.c
@@ -486,7 +486,7 @@ npc_process_ipv6_field_hash_o20k(const struct roc_npc_flow_item_ipv6 *ipv6_spec,
uint8_t hash_field[ROC_IPV6_ADDR_LEN];
struct npc_xtract_info *xinfo;
uint32_t hash = 0, mask;
- int intf, i, rc = 0;
+ int intf, i, hash_idx = 0, rc = 0;
memset(hash_field, 0, sizeof(hash_field));
@@ -505,14 +505,18 @@ npc_process_ipv6_field_hash_o20k(const struct roc_npc_flow_item_ipv6 *ipv6_spec,
if (rc == 0)
continue;
- rc = npc_ipv6_field_hash_get(pst->npc, (const uint32_t *)hash_field, intf, i,
- &hash);
+ if (hash_idx >= NPC_MAX_HASH)
+ break;
+
+ rc = npc_ipv6_field_hash_get(pst->npc, (const uint32_t *)hash_field, intf,
+ hash_idx, &hash);
if (rc)
return rc;
mask = GENMASK(31, 0);
memcpy(pst->mcam_mask + xinfo->key_off, (uint8_t *)&mask, 4);
memcpy(pst->mcam_data + xinfo->key_off, (uint8_t *)&hash, 4);
+ hash_idx++;
}
return 0;
diff --git a/drivers/common/cnxk/roc_ree.c b/drivers/common/cnxk/roc_ree.c
index b6392658c3..923d9251ad 100644
--- a/drivers/common/cnxk/roc_ree.c
+++ b/drivers/common/cnxk/roc_ree.c
@@ -592,14 +592,15 @@ roc_ree_dev_init(struct roc_ree_vf *vf)
vf->block_address = ree_get_blkaddr(dev);
if (!vf->block_address) {
plt_err("Could not determine block PF number");
- goto fail;
+ rc = -ENODEV;
+ goto dev_fini;
}
/* Get number of queues available on the device */
rc = roc_ree_available_queues_get(vf, &nb_queues);
if (rc) {
plt_err("Could not determine the number of queues available");
- goto fail;
+ goto dev_fini;
}
/* Don't exceed the limits set per VF */
@@ -607,7 +608,8 @@ roc_ree_dev_init(struct roc_ree_vf *vf)
if (nb_queues == 0) {
plt_err("No free queues available on the device");
- goto fail;
+ rc = -ENOSPC;
+ goto dev_fini;
}
vf->max_queues = nb_queues;
@@ -618,18 +620,23 @@ roc_ree_dev_init(struct roc_ree_vf *vf)
rc = roc_ree_max_matches_get(vf, &max_matches);
if (rc) {
plt_err("Could not determine the maximum matches supported");
- goto fail;
+ goto dev_fini;
}
/* Don't exceed the limits set per VF */
max_matches = RTE_MIN(max_matches, REE_MAX_MATCHES_PER_VF);
if (max_matches == 0) {
plt_err("Could not determine the maximum matches supported");
- goto fail;
+ rc = -EIO;
+ goto dev_fini;
}
vf->max_matches = max_matches;
plt_ree_dbg("Max matches supported by device: %d", vf->max_matches);
+
+ return 0;
+dev_fini:
+ dev_fini(dev, pci_dev);
fail:
return rc;
}
--
2.34.1
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH 17/17] common/cnxk: add auth key len check in inbound SA
2026-06-11 7:32 [PATCH 01/17] net/cnxk: update mbuf next field for multi segment Rahul Bhansali
` (14 preceding siblings ...)
2026-06-11 7:33 ` [PATCH 16/17] common/cnxk: fix Klocwork static analysis issues Rahul Bhansali
@ 2026-06-11 7:33 ` Rahul Bhansali
2026-06-11 14:20 ` [PATCH v2 01/22] net/cnxk: update mbuf next field for multi segment Rahul Bhansali
2026-06-11 17:23 ` [PATCH 01/17] " Stephen Hemminger
17 siblings, 0 replies; 41+ messages in thread
From: Rahul Bhansali @ 2026-06-11 7:33 UTC (permalink / raw)
To: dev, Nithin Dabilpuram, Kiran Kumar K, Sunil Kumar Kori,
Satha Rao, Harman Kalra, Archana Muniganti, Vidya Sagar Velumuri,
Akhil Goyal
Cc: jerinj, Aarnav JP, stable
From: Aarnav JP <ajp@marvell.com>
Add auth key length validation before memcpy in
cnxk_on_ipsec_inb_sa_create() to prevent caller-provided
keys from overflowing fixed-size in-struct buffers and
corrupting adjacent fields.
Fixes: 532963b80707 ("crypto/cnxk: move IPsec SA creation to common")
Cc: stable@dpdk.org
Signed-off-by: Aarnav JP <ajp@marvell.com>
---
drivers/common/cnxk/cnxk_security.c | 27 +++++++++++++++++++--------
1 file changed, 19 insertions(+), 8 deletions(-)
diff --git a/drivers/common/cnxk/cnxk_security.c b/drivers/common/cnxk/cnxk_security.c
index 6f46ad3276..228ff2781d 100644
--- a/drivers/common/cnxk/cnxk_security.c
+++ b/drivers/common/cnxk/cnxk_security.c
@@ -1199,22 +1199,33 @@ cnxk_on_ipsec_inb_sa_create(struct rte_security_ipsec_xform *ipsec,
break;
case RTE_CRYPTO_AUTH_MD5_HMAC:
case RTE_CRYPTO_AUTH_SHA1_HMAC:
- memcpy(in_sa->sha1_or_gcm.hmac_key, auth_key,
- auth_key_len);
- ctx_len = offsetof(struct roc_ie_on_inb_sa,
- sha1_or_gcm.selector);
+ if (auth_key_len > (int)sizeof(in_sa->sha1_or_gcm.hmac_key)) {
+ plt_err("Auth key len %d exceeds max %zu for algo %u", auth_key_len,
+ sizeof(in_sa->sha1_or_gcm.hmac_key), auth_xform->auth.algo);
+ return -EINVAL;
+ }
+ memcpy(in_sa->sha1_or_gcm.hmac_key, auth_key, auth_key_len);
+ ctx_len = offsetof(struct roc_ie_on_inb_sa, sha1_or_gcm.selector);
break;
case RTE_CRYPTO_AUTH_SHA256_HMAC:
case RTE_CRYPTO_AUTH_SHA384_HMAC:
case RTE_CRYPTO_AUTH_SHA512_HMAC:
+ if (auth_key_len > (int)sizeof(in_sa->sha2.hmac_key)) {
+ plt_err("Auth key len %d exceeds max %zu for algo %u", auth_key_len,
+ sizeof(in_sa->sha2.hmac_key), auth_xform->auth.algo);
+ return -EINVAL;
+ }
memcpy(in_sa->sha2.hmac_key, auth_key, auth_key_len);
- ctx_len = offsetof(struct roc_ie_on_inb_sa,
- sha2.selector);
+ ctx_len = offsetof(struct roc_ie_on_inb_sa, sha2.selector);
break;
case RTE_CRYPTO_AUTH_AES_XCBC_MAC:
+ if (auth_key_len > (int)sizeof(in_sa->aes_xcbc.key)) {
+ plt_err("Auth key len %d exceeds max %zu for algo %u", auth_key_len,
+ sizeof(in_sa->aes_xcbc.key), auth_xform->auth.algo);
+ return -EINVAL;
+ }
memcpy(in_sa->aes_xcbc.key, auth_key, auth_key_len);
- ctx_len = offsetof(struct roc_ie_on_inb_sa,
- aes_xcbc.selector);
+ ctx_len = offsetof(struct roc_ie_on_inb_sa, aes_xcbc.selector);
break;
default:
plt_err("Unsupported auth algorithm %u", auth_xform->auth.algo);
--
2.34.1
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH v2 01/22] net/cnxk: update mbuf next field for multi segment
2026-06-11 7:32 [PATCH 01/17] net/cnxk: update mbuf next field for multi segment Rahul Bhansali
` (15 preceding siblings ...)
2026-06-11 7:33 ` [PATCH 17/17] common/cnxk: add auth key len check in inbound SA Rahul Bhansali
@ 2026-06-11 14:20 ` Rahul Bhansali
2026-06-11 14:20 ` [PATCH v2 02/22] common/cnxk: add API of SA valid for cn20k platform Rahul Bhansali
` (21 more replies)
2026-06-11 17:23 ` [PATCH 01/17] " Stephen Hemminger
17 siblings, 22 replies; 41+ messages in thread
From: Rahul Bhansali @ 2026-06-11 14:20 UTC (permalink / raw)
To: dev, Nithin Dabilpuram, Kiran Kumar K, Sunil Kumar Kori,
Satha Rao, Harman Kalra
Cc: jerinj, Rahul Bhansali
As per the requirement of rte_mbuf_raw_reset_bulk(), the mbuf's
'next' and 'nb_segs' fields are required to be reset.
This reset these field for multi-segment mbufs on cn9k platform.
Signed-off-by: Rahul Bhansali <rbhansali@marvell.com>
---
Changes in v2: No change.
drivers/net/cnxk/cn9k_rx.h | 8 --------
drivers/net/cnxk/cn9k_tx.h | 42 ++++++++++++++++++--------------------
2 files changed, 20 insertions(+), 30 deletions(-)
diff --git a/drivers/net/cnxk/cn9k_rx.h b/drivers/net/cnxk/cn9k_rx.h
index 79b56fe160..5ccdc5dee1 100644
--- a/drivers/net/cnxk/cn9k_rx.h
+++ b/drivers/net/cnxk/cn9k_rx.h
@@ -410,8 +410,6 @@ cn9k_nix_cqe_to_mbuf(const struct nix_cqe_hdr_s *cq, const uint32_t tag,
* Hence, flag argument is not required.
*/
nix_cqe_xtract_mseg(rx, mbuf, val, 0);
- else
- mbuf->next = NULL;
}
static inline uint16_t
@@ -826,12 +824,6 @@ cn9k_nix_recv_pkts_vector(void *rx_queue, struct rte_mbuf **rx_pkts,
nix_cqe_xtract_mseg((union nix_rx_parse_u *)
(cq0 + CQE_SZ(3) + 8), mbuf3,
mbuf_initializer, flags);
- } else {
- /* Update that no more segments */
- mbuf0->next = NULL;
- mbuf1->next = NULL;
- mbuf2->next = NULL;
- mbuf3->next = NULL;
}
/* Store the mbufs to rx_pkts */
diff --git a/drivers/net/cnxk/cn9k_tx.h b/drivers/net/cnxk/cn9k_tx.h
index 32665d2050..0ec448e36c 100644
--- a/drivers/net/cnxk/cn9k_tx.h
+++ b/drivers/net/cnxk/cn9k_tx.h
@@ -665,14 +665,14 @@ cn9k_nix_prepare_mseg(struct cn9k_eth_txq *txq, struct rte_mbuf *m, struct rte_m
#else
RTE_SET_USED(cookie);
#endif
-#ifdef RTE_ENABLE_ASSERT
- m->next = NULL;
- m->nb_segs = 1;
-#endif
- m = m_next;
- if (!m)
+ if (likely(!m_next))
goto done;
+ if (!(flags & NIX_TX_OFFLOAD_MBUF_NOFF_F)) {
+ m->next = NULL;
+ m->nb_segs = 1;
+ }
+ m = m_next;
/* Fill mbuf segments */
do {
m_next = m->next;
@@ -704,12 +704,13 @@ cn9k_nix_prepare_mseg(struct cn9k_eth_txq *txq, struct rte_mbuf *m, struct rte_m
sg_u = sg->u;
slist++;
}
-#ifdef RTE_ENABLE_ASSERT
- m->next = NULL;
-#endif
+ if (!(flags & NIX_TX_OFFLOAD_MBUF_NOFF_F))
+ m->next = NULL;
m = m_next;
} while (nb_segs);
+ if (!(flags & NIX_TX_OFFLOAD_MBUF_NOFF_F))
+ rte_io_wmb();
done:
sg->u = sg_u;
sg->segs = i;
@@ -720,9 +721,6 @@ cn9k_nix_prepare_mseg(struct cn9k_eth_txq *txq, struct rte_mbuf *m, struct rte_m
segdw += (off >> 1) + 1 + !!(flags & NIX_TX_OFFLOAD_TSTAMP_F);
send_hdr->w0.sizem1 = segdw - 1;
-#ifdef RTE_ENABLE_ASSERT
- rte_io_wmb();
-#endif
return segdw;
}
@@ -950,10 +948,10 @@ cn9k_nix_prepare_mseg_vec_list(struct cn9k_eth_txq *txq,
RTE_SET_USED(cookie);
#endif
-#ifdef RTE_ENABLE_ASSERT
- m->next = NULL;
- m->nb_segs = 1;
-#endif
+ if (!(flags & NIX_TX_OFFLOAD_MBUF_NOFF_F)) {
+ m->next = NULL;
+ m->nb_segs = 1;
+ }
m = m_next;
/* Fill mbuf segments */
do {
@@ -984,9 +982,8 @@ cn9k_nix_prepare_mseg_vec_list(struct cn9k_eth_txq *txq,
sg_u = sg->u;
slist++;
}
-#ifdef RTE_ENABLE_ASSERT
- m->next = NULL;
-#endif
+ if (!(flags & NIX_TX_OFFLOAD_MBUF_NOFF_F))
+ m->next = NULL;
m = m_next;
} while (nb_segs);
@@ -1002,9 +999,6 @@ cn9k_nix_prepare_mseg_vec_list(struct cn9k_eth_txq *txq,
!!(flags & NIX_TX_OFFLOAD_TSTAMP_F);
send_hdr->w0.sizem1 = segdw - 1;
-#ifdef RTE_ENABLE_ASSERT
- rte_io_wmb();
-#endif
return segdw;
}
@@ -1089,6 +1083,10 @@ cn9k_nix_xmit_pkts_mseg_vector(uint64x2_t *cmd0, uint64x2_t *cmd1,
}
}
+ /* Multi segment mbufs */
+ if (!(flags & NIX_TX_OFFLOAD_MBUF_NOFF_F))
+ rte_io_wmb();
+
for (j = 0; j < NIX_DESCS_PER_LOOP;) {
/* Fit consecutive packets in same LMTLINE. */
if ((segdw[j] + segdw[j + 1]) <= 8) {
--
2.34.1
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH v2 02/22] common/cnxk: add API of SA valid for cn20k platform
2026-06-11 14:20 ` [PATCH v2 01/22] net/cnxk: update mbuf next field for multi segment Rahul Bhansali
@ 2026-06-11 14:20 ` Rahul Bhansali
2026-06-11 14:20 ` [PATCH v2 03/22] common/cnxk: additional NIX SQ ctx fields prints Rahul Bhansali
` (20 subsequent siblings)
21 siblings, 0 replies; 41+ messages in thread
From: Rahul Bhansali @ 2026-06-11 14:20 UTC (permalink / raw)
To: dev, Nithin Dabilpuram, Kiran Kumar K, Sunil Kumar Kori,
Satha Rao, Harman Kalra
Cc: jerinj, Rahul Bhansali
Add API to get SA valid configuration for cn20k platform.
Signed-off-by: Rahul Bhansali <rbhansali@marvell.com>
---
Changes in v2: No change.
drivers/common/cnxk/cnxk_security.c | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/drivers/common/cnxk/cnxk_security.c b/drivers/common/cnxk/cnxk_security.c
index 6b51055100..6f46ad3276 100644
--- a/drivers/common/cnxk/cnxk_security.c
+++ b/drivers/common/cnxk/cnxk_security.c
@@ -606,6 +606,20 @@ cnxk_ot_ipsec_outb_sa_valid(struct roc_ot_ipsec_outb_sa *sa)
return !!sa->w2.s.valid;
}
+RTE_EXPORT_INTERNAL_SYMBOL(cnxk_ow_ipsec_inb_sa_valid)
+bool
+cnxk_ow_ipsec_inb_sa_valid(struct roc_ow_ipsec_inb_sa *sa)
+{
+ return !!sa->w2.s.valid;
+}
+
+RTE_EXPORT_INTERNAL_SYMBOL(cnxk_ow_ipsec_outb_sa_valid)
+bool
+cnxk_ow_ipsec_outb_sa_valid(struct roc_ow_ipsec_outb_sa *sa)
+{
+ return !!sa->w2.s.valid;
+}
+
RTE_EXPORT_INTERNAL_SYMBOL(cnxk_ipsec_ivlen_get)
uint8_t
cnxk_ipsec_ivlen_get(enum rte_crypto_cipher_algorithm c_algo,
--
2.34.1
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH v2 03/22] common/cnxk: additional NIX SQ ctx fields prints
2026-06-11 14:20 ` [PATCH v2 01/22] net/cnxk: update mbuf next field for multi segment Rahul Bhansali
2026-06-11 14:20 ` [PATCH v2 02/22] common/cnxk: add API of SA valid for cn20k platform Rahul Bhansali
@ 2026-06-11 14:20 ` Rahul Bhansali
2026-06-11 14:20 ` [PATCH v2 04/22] common/cnxk: update NIX irq handler Rahul Bhansali
` (19 subsequent siblings)
21 siblings, 0 replies; 41+ messages in thread
From: Rahul Bhansali @ 2026-06-11 14:20 UTC (permalink / raw)
To: dev, Nithin Dabilpuram, Kiran Kumar K, Sunil Kumar Kori,
Satha Rao, Harman Kalra
Cc: jerinj, Rahul Bhansali
Additional debug prints for CN20k NIX SQ ctx dump
Signed-off-by: Rahul Bhansali <rbhansali@marvell.com>
---
Changes in v2: fix ubuntu clang stdatmoic compile failure.
drivers/common/cnxk/roc_nix_debug.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/drivers/common/cnxk/roc_nix_debug.c b/drivers/common/cnxk/roc_nix_debug.c
index 11994bf131..d4b2b86916 100644
--- a/drivers/common/cnxk/roc_nix_debug.c
+++ b/drivers/common/cnxk/roc_nix_debug.c
@@ -540,6 +540,8 @@ nix_cn10k_lf_sq_dump(__io struct nix_cn10k_sq_ctx_s *ctx, uint32_t *sqb_aura_p,
static inline void
nix_lf_sq_dump(__io struct nix_cn20k_sq_ctx_s *ctx, uint32_t *sqb_aura_p, FILE *file)
{
+ int64_t *sq_cnt_ptr = NULL;
+
nix_dump(file, "W0: sqe_way_mask \t\t%d\nW0: cq \t\t\t\t%d",
ctx->sqe_way_mask, ctx->cq);
nix_dump(file, "W0: sdp_mcast \t\t\t%d\nW0: substream \t\t\t0x%03x",
@@ -561,6 +563,7 @@ nix_lf_sq_dump(__io struct nix_cn20k_sq_ctx_s *ctx, uint32_t *sqb_aura_p, FILE *
nix_dump(file, "W2: smq_rr_count[ub:lb] \t\t%x:%x\n", ctx->smq_rr_count_ub,
ctx->smq_rr_count_lb);
+ nix_dump(file, "W3: update_sq_count\t\t%d\n", ctx->update_sq_count);
nix_dump(file, "W3: smq_next_sq_vld\t\t%d\nW3: smq_pend\t\t\t%d",
ctx->smq_next_sq_vld, ctx->smq_pend);
nix_dump(file, "W3: smenq_next_sqb_vld \t%d\nW3: head_offset\t\t\t%d",
@@ -588,6 +591,12 @@ nix_lf_sq_dump(__io struct nix_cn20k_sq_ctx_s *ctx, uint32_t *sqb_aura_p, FILE *
ctx->vfi_lso_sizem1);
nix_dump(file, "W9: vfi_lso_total\t\t%d", ctx->vfi_lso_total);
+ nix_dump(file, "W10: sq_count_iova \t\t0x%" PRIx64 "", (uint64_t)ctx->sq_count_iova);
+ sq_cnt_ptr = (int64_t *)(uintptr_t)(ctx->sq_count_iova << 3);
+ if (sq_cnt_ptr && ctx->update_sq_count)
+ nix_dump(file, "sq_count value \t\t0x%" PRIx64 "",
+ plt_atomic_load_explicit((uint64_t __plt_atomic *)sq_cnt_ptr,
+ plt_memory_order_relaxed));
nix_dump(file, "W10: scm_lso_rem \t\t0x%" PRIx64 "", (uint64_t)ctx->scm_lso_rem);
nix_dump(file, "W11: octs \t\t\t0x%" PRIx64 "", (uint64_t)ctx->octs);
nix_dump(file, "W12: pkts \t\t\t0x%" PRIx64 "", (uint64_t)ctx->pkts);
--
2.34.1
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH v2 04/22] common/cnxk: update NIX irq handler
2026-06-11 14:20 ` [PATCH v2 01/22] net/cnxk: update mbuf next field for multi segment Rahul Bhansali
2026-06-11 14:20 ` [PATCH v2 02/22] common/cnxk: add API of SA valid for cn20k platform Rahul Bhansali
2026-06-11 14:20 ` [PATCH v2 03/22] common/cnxk: additional NIX SQ ctx fields prints Rahul Bhansali
@ 2026-06-11 14:20 ` Rahul Bhansali
2026-06-11 14:20 ` [PATCH v2 05/22] common/cnxk: configure LSO mask for single segments Rahul Bhansali
` (18 subsequent siblings)
21 siblings, 0 replies; 41+ messages in thread
From: Rahul Bhansali @ 2026-06-11 14:20 UTC (permalink / raw)
To: dev, Nithin Dabilpuram, Kiran Kumar K, Sunil Kumar Kori,
Satha Rao, Harman Kalra
Cc: jerinj, Rahul Bhansali
Move queue context dump and register print before interrupt
clear in NIX irq handler.
Signed-off-by: Rahul Bhansali <rbhansali@marvell.com>
---
Changes in v2: No change.
drivers/common/cnxk/roc_nix_irq.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/common/cnxk/roc_nix_irq.c b/drivers/common/cnxk/roc_nix_irq.c
index 2b731302cd..6874435a4e 100644
--- a/drivers/common/cnxk/roc_nix_irq.c
+++ b/drivers/common/cnxk/roc_nix_irq.c
@@ -168,7 +168,7 @@ nix_lf_q_irq_get_and_clear(struct nix *nix, uint16_t q, uint32_t off,
reg = roc_atomic64_add_nosync(wdata, (int64_t *)(nix->base + off));
if (reg & BIT_ULL(42) /* OP_ERR */) {
- plt_err("Failed execute irq get off=0x%x", off);
+ plt_err("Failed execute irq get queue=%d off=0x%x", q, off);
return 0;
}
qint = reg & 0xff;
@@ -262,6 +262,10 @@ nix_lf_q_irq(void *param)
plt_err("Queue_intr=0x%" PRIx64 " qintx=%d pf=%d, vf=%d", intr, qintx,
dev->pf, dev->vf);
+ /* Dump registers to std out */
+ roc_nix_lf_reg_dump(nix_priv_to_roc_nix(nix), NULL);
+ roc_nix_queues_ctx_dump(nix_priv_to_roc_nix(nix), NULL);
+
/* Handle RQ interrupts */
for (q = 0; q < nix->nb_rx_queues; q++) {
rq = q % nix->qints;
@@ -323,10 +327,6 @@ nix_lf_q_irq(void *param)
/* Clear interrupt */
plt_write64(intr, nix->base + NIX_LF_QINTX_INT(qintx));
- /* Dump registers to std out */
- roc_nix_lf_reg_dump(nix_priv_to_roc_nix(nix), NULL);
- roc_nix_queues_ctx_dump(nix_priv_to_roc_nix(nix), NULL);
-
/* Call reset callback */
if (intr_cb && dev->ops->q_err_cb)
dev->ops->q_err_cb(nix_priv_to_roc_nix(nix), NULL);
--
2.34.1
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH v2 05/22] common/cnxk: configure LSO mask for single segments
2026-06-11 14:20 ` [PATCH v2 01/22] net/cnxk: update mbuf next field for multi segment Rahul Bhansali
` (2 preceding siblings ...)
2026-06-11 14:20 ` [PATCH v2 04/22] common/cnxk: update NIX irq handler Rahul Bhansali
@ 2026-06-11 14:20 ` Rahul Bhansali
2026-06-11 14:20 ` [PATCH v2 06/22] net/cnxk: reserve memory for lookup mem at probe Rahul Bhansali
` (17 subsequent siblings)
21 siblings, 0 replies; 41+ messages in thread
From: Rahul Bhansali @ 2026-06-11 14:20 UTC (permalink / raw)
To: dev, Nithin Dabilpuram, Kiran Kumar K, Sunil Kumar Kori,
Satha Rao, Harman Kalra
Cc: jerinj, Rahul Bhansali
Configures LSO flag mask for single packets.
Signed-off-by: Rahul Bhansali <rbhansali@marvell.com>
---
Changes in v2: No change.
drivers/common/cnxk/roc_nix_ops.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/common/cnxk/roc_nix_ops.c b/drivers/common/cnxk/roc_nix_ops.c
index 12a12c6e35..4653bb2049 100644
--- a/drivers/common/cnxk/roc_nix_ops.c
+++ b/drivers/common/cnxk/roc_nix_ops.c
@@ -239,6 +239,8 @@ nix_lso_ipv4(struct roc_nix *roc_nix)
/* First get flags profile to update v4 flags */
memset(&alt_flags, 0, sizeof(alt_flags));
+ alt_flags.s.alt_ssf_set = 0;
+ alt_flags.s.alt_ssf_mask = 0xFFFF;
alt_flags.s.alt_fsf_set = 0x2000;
alt_flags.s.alt_fsf_mask = 0x5FFF;
alt_flags.s.alt_msf_set = 0x2000;
--
2.34.1
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH v2 06/22] net/cnxk: reserve memory for lookup mem at probe
2026-06-11 14:20 ` [PATCH v2 01/22] net/cnxk: update mbuf next field for multi segment Rahul Bhansali
` (3 preceding siblings ...)
2026-06-11 14:20 ` [PATCH v2 05/22] common/cnxk: configure LSO mask for single segments Rahul Bhansali
@ 2026-06-11 14:20 ` Rahul Bhansali
2026-06-11 14:20 ` [PATCH v2 07/22] drivers: add support for devargs skip size Rahul Bhansali
` (16 subsequent siblings)
21 siblings, 0 replies; 41+ messages in thread
From: Rahul Bhansali @ 2026-06-11 14:20 UTC (permalink / raw)
To: dev, Nithin Dabilpuram, Kiran Kumar K, Sunil Kumar Kori,
Satha Rao, Harman Kalra
Cc: jerinj
From: Nithin Dabilpuram <ndabilpuram@marvell.com>
Reserve memory for lookup mem at probe that is global for
all cnxk ethdev devices to avoid race at later stage.
Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
---
Changes in v2: No change.
drivers/net/cnxk/cnxk_ethdev.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/net/cnxk/cnxk_ethdev.c b/drivers/net/cnxk/cnxk_ethdev.c
index 06d1c9b362..c782dc51a8 100644
--- a/drivers/net/cnxk/cnxk_ethdev.c
+++ b/drivers/net/cnxk/cnxk_ethdev.c
@@ -2220,6 +2220,12 @@ cnxk_eth_dev_init(struct rte_eth_dev *eth_dev)
/* Register callback for inline meta pool create 1:N pool:aura */
roc_nix_inl_custom_meta_pool_cb_register(cnxk_nix_inl_custom_meta_pool_cb);
+ /* Reserve memory for lookup_memory */
+ if (!cnxk_nix_fastpath_lookup_mem_get()) {
+ plt_err("Failed to reserve lookup memory rc=%d", rc);
+ goto dev_fini;
+ }
+
dev->eth_dev = eth_dev;
dev->configured = 0;
dev->ptype_disable = 0;
--
2.34.1
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH v2 07/22] drivers: add support for devargs skip size
2026-06-11 14:20 ` [PATCH v2 01/22] net/cnxk: update mbuf next field for multi segment Rahul Bhansali
` (4 preceding siblings ...)
2026-06-11 14:20 ` [PATCH v2 06/22] net/cnxk: reserve memory for lookup mem at probe Rahul Bhansali
@ 2026-06-11 14:20 ` Rahul Bhansali
2026-06-11 14:20 ` [PATCH v2 08/22] net/cnxk: update inbound SA pkind for " Rahul Bhansali
` (15 subsequent siblings)
21 siblings, 0 replies; 41+ messages in thread
From: Rahul Bhansali @ 2026-06-11 14:20 UTC (permalink / raw)
To: dev, Nithin Dabilpuram, Kiran Kumar K, Sunil Kumar Kori,
Satha Rao, Harman Kalra
Cc: jerinj
From: Kiran Kumar K <kirankumark@marvell.com>
Adding support for devargs skip_size to cnxk driver.
This allows users to specify the number of bytes to skip in the packet
parsing before L2.
Signed-off-by: Kiran Kumar K <kirankumark@marvell.com>
---
Changes in v2: No change.
doc/guides/nics/cnxk.rst | 19 +++++++-
drivers/common/cnxk/roc_mbox.h | 12 ++++-
drivers/common/cnxk/roc_nix.h | 14 ++----
drivers/common/cnxk/roc_nix_ops.c | 46 +++++++++++++++++--
drivers/common/cnxk/roc_npc.c | 44 +++++++++++++++++-
drivers/common/cnxk/roc_npc.h | 2 +
drivers/common/cnxk/roc_npc_priv.h | 11 +++++
.../common/cnxk/roc_platform_base_symbols.c | 1 +
drivers/net/cnxk/cnxk_eswitch.c | 2 +-
drivers/net/cnxk/cnxk_ethdev.c | 7 ++-
drivers/net/cnxk/cnxk_ethdev_devargs.c | 29 +++++++++++-
11 files changed, 163 insertions(+), 24 deletions(-)
diff --git a/doc/guides/nics/cnxk.rst b/doc/guides/nics/cnxk.rst
index b5bd50ceea..239ebcd05c 100644
--- a/doc/guides/nics/cnxk.rst
+++ b/doc/guides/nics/cnxk.rst
@@ -183,8 +183,8 @@ Runtime Config Options
With the above configuration, higig2 will be enabled on that port and the
traffic on this port should be higig2 traffic only. Supported switch header
- types are "chlen24b", "chlen90b", "dsa", "exdsa", "higig2", "vlan_exdsa" and
- "pre_l2".
+ types are "chlen24b", "chlen90b", "dsa", "exdsa", "higig2", "vlan_exdsa",
+ "pre_l2" and "skip_size".
- ``Flow pre_l2 info`` (default ``0x0/0x0/0x0``)
@@ -212,6 +212,21 @@ Runtime Config Options
is 0 (i.e., left shift) then the shift count will be 1, that is, (8 - n),
where n is the absolute position of leftmost set bit.
+- ``Skip size info`` (default ``0x0``)
+
+ When the switch header type is set to "skip_size", the number of bytes to
+ skip before the Ethernet header can be configured using ``skip_size_info``
+ ``devargs`` parameter. The value is in hexadecimal format and the valid
+ range is 0x0 to 0xff. This configures the PKIND so that the NPC parser
+ skips the specified number of bytes.
+
+ For example::
+
+ -a 0002:02:00.0,switch_header="skip_size",skip_size_info=0x2
+
+ With the above configuration, 2 bytes will be skipped before the Ethernet
+ header when parsing the incoming packets.
+
- ``RSS tag as XOR`` (default ``0``)
The HW gives two options to configure the RSS adder i.e
diff --git a/drivers/common/cnxk/roc_mbox.h b/drivers/common/cnxk/roc_mbox.h
index e31abf2234..1158ff50a7 100644
--- a/drivers/common/cnxk/roc_mbox.h
+++ b/drivers/common/cnxk/roc_mbox.h
@@ -462,8 +462,11 @@ struct ready_msg_rsp {
};
enum npc_pkind_type {
+ NPC_RX_SKIP_SIZE_PKIND = 46ULL,
+ NPC_RX_CPT_SKIP_SIZE_PKIND = 50ULL,
+ NPC_RX_CPT_HDR_PTP_PKIND = 54ULL,
NPC_RX_CUSTOM_PRE_L2_PKIND = 55ULL,
- NPC_RX_VLAN_EXDSA_PKIND = 56ULL,
+ NPC_RX_VLAN_EXDSA_PKIND,
NPC_RX_CHLEN24B_PKIND,
NPC_RX_CPT_HDR_PKIND,
NPC_RX_CHLEN90B_PKIND,
@@ -474,6 +477,8 @@ enum npc_pkind_type {
NPC_TX_DEF_PKIND,
};
+#define NPC_SKIP_SIZE_PKIND_MAX 4
+
/* Struct to set pkind */
struct npc_set_pkind {
struct mbox_msghdr hdr;
@@ -484,6 +489,7 @@ struct npc_set_pkind {
#define ROC_PRIV_FLAGS_EXDSA BIT_ULL(4)
#define ROC_PRIV_FLAGS_VLAN_EXDSA BIT_ULL(5)
#define ROC_PRIV_FLAGS_PRE_L2 BIT_ULL(6)
+#define ROC_PRIV_FLAGS_SKIP_SIZE BIT_ULL(7)
#define ROC_PRIV_FLAGS_CUSTOM BIT_ULL(63)
uint64_t __io mode;
#define PKIND_TX BIT_ULL(0)
@@ -499,6 +505,10 @@ struct npc_set_pkind {
/* Shift direction to get length of the
* header at var_len_off
*/
+ uint8_t __io skip_size;
+ /* Number of bytes to skip before the Ethernet header.
+ * Valid only in case custom flag.
+ */
};
/* Structure for requesting resource provisioning.
diff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h
index 8ba8b3e0b6..49ede85f9a 100644
--- a/drivers/common/cnxk/roc_nix.h
+++ b/drivers/common/cnxk/roc_nix.h
@@ -990,18 +990,14 @@ int __roc_api roc_nix_mac_stats_reset(struct roc_nix *roc_nix);
int __roc_api roc_nix_mac_fwdata_get(struct roc_nix *roc_nix, struct roc_nix_mac_fwdata *fwdata);
/* Ops */
-int __roc_api roc_nix_switch_hdr_set(struct roc_nix *roc_nix,
- uint64_t switch_header_type,
- uint8_t pre_l2_size_offset,
- uint8_t pre_l2_size_offset_mask,
- uint8_t pre_l2_size_shift_dir);
+int __roc_api roc_nix_switch_hdr_set(struct roc_nix *roc_nix, uint64_t switch_header_type,
+ uint8_t pre_l2_size_offset, uint8_t pre_l2_size_offset_mask,
+ uint8_t pre_l2_size_shift_dir, uint8_t skip_size);
int __roc_api roc_nix_lso_fmt_setup(struct roc_nix *roc_nix);
-int __roc_api roc_nix_lso_fmt_get(struct roc_nix *roc_nix,
- uint8_t udp_tun[ROC_NIX_LSO_TUN_MAX],
+int __roc_api roc_nix_lso_fmt_get(struct roc_nix *roc_nix, uint8_t udp_tun[ROC_NIX_LSO_TUN_MAX],
uint8_t tun[ROC_NIX_LSO_TUN_MAX]);
int __roc_api roc_nix_lso_fmt_ipv4_frag_get(struct roc_nix *roc_nix);
-int __roc_api roc_nix_lso_custom_fmt_setup(struct roc_nix *roc_nix,
- struct nix_lso_format *fields,
+int __roc_api roc_nix_lso_custom_fmt_setup(struct roc_nix *roc_nix, struct nix_lso_format *fields,
uint16_t nb_fields);
int __roc_api roc_nix_lso_alt_flags_profile_setup(struct roc_nix *roc_nix,
nix_lso_alt_flg_format_t *fmt);
diff --git a/drivers/common/cnxk/roc_nix_ops.c b/drivers/common/cnxk/roc_nix_ops.c
index 4653bb2049..13a548216b 100644
--- a/drivers/common/cnxk/roc_nix_ops.c
+++ b/drivers/common/cnxk/roc_nix_ops.c
@@ -501,17 +501,49 @@ roc_nix_lso_fmt_get(struct roc_nix *roc_nix,
return 0;
}
+static int
+skip_size_pkind_get(uint8_t skip_size, uint8_t *pkind)
+{
+ struct skip_size_pkind_cfg *cfg;
+ const struct plt_memzone *mz;
+ int i;
+
+ mz = plt_memzone_lookup(SKIP_SIZE_PKIND_MEMZONE);
+ if (!mz)
+ return -ENOMEM;
+ cfg = mz->addr;
+
+ for (i = 0; i < cfg->count; i++) {
+ if (cfg->entries[i].skip_size == skip_size) {
+ *pkind = cfg->entries[i].pkind;
+ return 0;
+ }
+ }
+
+ if (cfg->count >= NPC_SKIP_SIZE_PKIND_MAX) {
+ plt_err("skip_size PKIND limit (%d) reached", NPC_SKIP_SIZE_PKIND_MAX);
+ return -ENOSPC;
+ }
+
+ i = cfg->count;
+ cfg->entries[i].skip_size = skip_size;
+ cfg->entries[i].pkind = NPC_RX_SKIP_SIZE_PKIND + i;
+ *pkind = cfg->entries[i].pkind;
+ cfg->count++;
+ return 0;
+}
+
int
roc_nix_switch_hdr_set(struct roc_nix *roc_nix, uint64_t switch_header_type,
- uint8_t pre_l2_size_offset,
- uint8_t pre_l2_size_offset_mask,
- uint8_t pre_l2_size_shift_dir)
+ uint8_t pre_l2_size_offset, uint8_t pre_l2_size_offset_mask,
+ uint8_t pre_l2_size_shift_dir, uint8_t skip_size)
{
struct nix *nix = roc_nix_to_nix_priv(roc_nix);
struct dev *dev = &nix->dev;
struct mbox *mbox = mbox_get(dev->mbox);
struct npc_set_pkind *req;
struct msg_resp *rsp;
+ uint8_t pkind = 0;
int rc = -ENOSPC;
if (switch_header_type == 0)
@@ -524,6 +556,7 @@ roc_nix_switch_hdr_set(struct roc_nix *roc_nix, uint64_t switch_header_type,
switch_header_type != ROC_PRIV_FLAGS_EXDSA &&
switch_header_type != ROC_PRIV_FLAGS_VLAN_EXDSA &&
switch_header_type != ROC_PRIV_FLAGS_PRE_L2 &&
+ switch_header_type != ROC_PRIV_FLAGS_SKIP_SIZE &&
switch_header_type != ROC_PRIV_FLAGS_CUSTOM) {
plt_err("switch header type is not supported");
rc = NIX_ERR_PARAM;
@@ -564,6 +597,13 @@ roc_nix_switch_hdr_set(struct roc_nix *roc_nix, uint64_t switch_header_type,
req->var_len_off = pre_l2_size_offset;
req->var_len_off_mask = pre_l2_size_offset_mask;
req->shift_dir = pre_l2_size_shift_dir;
+ } else if (switch_header_type == ROC_PRIV_FLAGS_SKIP_SIZE) {
+ rc = skip_size_pkind_get(skip_size, &pkind);
+ if (rc)
+ goto exit;
+ req->mode = ROC_PRIV_FLAGS_CUSTOM;
+ req->pkind = pkind;
+ req->skip_size = skip_size;
}
req->dir = PKIND_RX;
diff --git a/drivers/common/cnxk/roc_npc.c b/drivers/common/cnxk/roc_npc.c
index a906fe0413..111ad0e8bb 100644
--- a/drivers/common/cnxk/roc_npc.c
+++ b/drivers/common/cnxk/roc_npc.c
@@ -420,6 +420,16 @@ roc_npc_init(struct roc_npc *roc_npc)
roc_npc->flow_age.age_flow_refcnt = 0;
+ /* Create skip-size PKIND memzone if it doesn't exist */
+ if (!plt_memzone_lookup(SKIP_SIZE_PKIND_MEMZONE)) {
+ const struct plt_memzone *mz;
+
+ mz = plt_memzone_reserve_cache_align(SKIP_SIZE_PKIND_MEMZONE,
+ sizeof(struct skip_size_pkind_cfg));
+ if (mz != NULL)
+ memset(mz->addr, 0, sizeof(struct skip_size_pkind_cfg));
+ }
+
return rc;
done:
@@ -457,12 +467,42 @@ roc_npc_fini(struct roc_npc *roc_npc)
npc->prio_flow_list = NULL;
}
+ {
+ const struct plt_memzone *mz;
+
+ mz = plt_memzone_lookup(SKIP_SIZE_PKIND_MEMZONE);
+ if (mz)
+ plt_memzone_free(mz);
+ }
+
return 0;
}
int
-roc_npc_validate_portid_action(struct roc_npc *roc_npc_src,
- struct roc_npc *roc_npc_dst)
+roc_npc_skip_size_pkind_get(struct roc_npc *roc_npc)
+{
+ struct skip_size_pkind_cfg *cfg;
+ const struct plt_memzone *mz;
+ int i;
+
+ if (roc_npc->switch_header_type != ROC_PRIV_FLAGS_SKIP_SIZE)
+ return -1;
+
+ mz = plt_memzone_lookup(SKIP_SIZE_PKIND_MEMZONE);
+ if (!mz)
+ return -1;
+ cfg = mz->addr;
+
+ for (i = 0; i < cfg->count; i++) {
+ if (cfg->entries[i].skip_size == roc_npc->skip_size)
+ return cfg->entries[i].pkind + NPC_SKIP_SIZE_PKIND_MAX;
+ }
+
+ return -1;
+}
+
+int
+roc_npc_validate_portid_action(struct roc_npc *roc_npc_src, struct roc_npc *roc_npc_dst)
{
struct roc_nix *roc_nix_src = roc_npc_src->roc_nix;
struct nix *nix_src = roc_nix_to_nix_priv(roc_nix_src);
diff --git a/drivers/common/cnxk/roc_npc.h b/drivers/common/cnxk/roc_npc.h
index 130990bda7..a7254f35ca 100644
--- a/drivers/common/cnxk/roc_npc.h
+++ b/drivers/common/cnxk/roc_npc.h
@@ -423,6 +423,7 @@ struct roc_npc {
*/
uint8_t pre_l2_size_shift_dir; /**< Shift direction to calculate size
*/
+ uint8_t skip_size; /**< Switch header skip size */
uint16_t flow_prealloc_size;
uint16_t flow_max_priority;
uint16_t channel;
@@ -506,4 +507,5 @@ void __roc_api roc_npc_sdp_channel_get(struct roc_npc *roc_npc, uint16_t *chan_b
uint16_t *chan_mask);
int __roc_api roc_npc_mcam_get_stats(struct roc_npc *roc_npc, struct roc_npc_flow *flow,
uint64_t *count);
+int __roc_api roc_npc_skip_size_pkind_get(struct roc_npc *roc_npc);
#endif /* _ROC_NPC_H_ */
diff --git a/drivers/common/cnxk/roc_npc_priv.h b/drivers/common/cnxk/roc_npc_priv.h
index f8f4489f06..6a27f0e0fa 100644
--- a/drivers/common/cnxk/roc_npc_priv.h
+++ b/drivers/common/cnxk/roc_npc_priv.h
@@ -554,4 +554,15 @@ int npc_aging_ctrl_thread_create(struct roc_npc *roc_npc, const struct roc_npc_a
struct roc_npc_flow *flow);
void npc_aging_ctrl_thread_destroy(struct roc_npc *roc_npc);
int npc_rss_free_grp_get(struct npc *npc, uint32_t *pos);
+
+#define SKIP_SIZE_PKIND_MEMZONE "roc_skip_size_pkind_cfg"
+
+struct skip_size_pkind_cfg {
+ uint8_t count;
+ struct {
+ uint8_t skip_size;
+ uint8_t pkind;
+ } entries[NPC_SKIP_SIZE_PKIND_MAX];
+};
+
#endif /* _ROC_NPC_PRIV_H_ */
diff --git a/drivers/common/cnxk/roc_platform_base_symbols.c b/drivers/common/cnxk/roc_platform_base_symbols.c
index ed34d4b05b..d1c9f2304d 100644
--- a/drivers/common/cnxk/roc_platform_base_symbols.c
+++ b/drivers/common/cnxk/roc_platform_base_symbols.c
@@ -492,6 +492,7 @@ RTE_EXPORT_INTERNAL_SYMBOL(roc_npc_fini)
RTE_EXPORT_INTERNAL_SYMBOL(roc_npc_validate_portid_action)
RTE_EXPORT_INTERNAL_SYMBOL(roc_npc_flow_parse)
RTE_EXPORT_INTERNAL_SYMBOL(roc_npc_sdp_channel_get)
+RTE_EXPORT_INTERNAL_SYMBOL(roc_npc_skip_size_pkind_get)
RTE_EXPORT_INTERNAL_SYMBOL(roc_npc_flow_create)
RTE_EXPORT_INTERNAL_SYMBOL(roc_npc_flow_destroy)
RTE_EXPORT_INTERNAL_SYMBOL(roc_npc_flow_dump)
diff --git a/drivers/net/cnxk/cnxk_eswitch.c b/drivers/net/cnxk/cnxk_eswitch.c
index e45c7dfd07..7e717a2fbf 100644
--- a/drivers/net/cnxk/cnxk_eswitch.c
+++ b/drivers/net/cnxk/cnxk_eswitch.c
@@ -553,7 +553,7 @@ nix_lf_setup(struct cnxk_eswitch_dev *eswitch_dev)
goto free_cqs;
}
- rc = roc_nix_switch_hdr_set(nix, 0, 0, 0, 0);
+ rc = roc_nix_switch_hdr_set(nix, 0, 0, 0, 0, 0);
if (rc) {
plt_err("switch hdr set failed = %s(%d)", roc_error_msg_get(rc), rc);
goto free_cqs;
diff --git a/drivers/net/cnxk/cnxk_ethdev.c b/drivers/net/cnxk/cnxk_ethdev.c
index c782dc51a8..a21e170229 100644
--- a/drivers/net/cnxk/cnxk_ethdev.c
+++ b/drivers/net/cnxk/cnxk_ethdev.c
@@ -1639,10 +1639,9 @@ cnxk_nix_configure(struct rte_eth_dev *eth_dev)
goto free_nix_lf;
}
- rc = roc_nix_switch_hdr_set(nix, dev->npc.switch_header_type,
- dev->npc.pre_l2_size_offset,
+ rc = roc_nix_switch_hdr_set(nix, dev->npc.switch_header_type, dev->npc.pre_l2_size_offset,
dev->npc.pre_l2_size_offset_mask,
- dev->npc.pre_l2_size_shift_dir);
+ dev->npc.pre_l2_size_shift_dir, dev->npc.skip_size);
if (rc) {
plt_err("Failed to enable switch type nix_lf rc=%d", rc);
goto free_nix_lf;
@@ -2364,7 +2363,7 @@ cnxk_eth_dev_uninit(struct rte_eth_dev *eth_dev, bool reset)
return 0;
/* Disable switch hdr pkind */
- roc_nix_switch_hdr_set(&dev->nix, 0, 0, 0, 0);
+ roc_nix_switch_hdr_set(&dev->nix, 0, 0, 0, 0, 0);
/* Clear the flag since we are closing down */
dev->configured = 0;
diff --git a/drivers/net/cnxk/cnxk_ethdev_devargs.c b/drivers/net/cnxk/cnxk_ethdev_devargs.c
index da8fc83f9d..ea18090919 100644
--- a/drivers/net/cnxk/cnxk_ethdev_devargs.c
+++ b/drivers/net/cnxk/cnxk_ethdev_devargs.c
@@ -239,6 +239,25 @@ parse_switch_header_type(const char *key, const char *value, void *extra_args)
if (strcmp(value, "pre_l2") == 0)
*(uint16_t *)extra_args = ROC_PRIV_FLAGS_PRE_L2;
+ if (strcmp(value, "skip_size") == 0)
+ *(uint16_t *)extra_args = ROC_PRIV_FLAGS_SKIP_SIZE;
+
+ return 0;
+}
+
+static int
+parse_skip_size_info(const char *key, const char *value, void *extra_args)
+{
+ RTE_SET_USED(key);
+ uint32_t val;
+
+ errno = 0;
+ val = strtoul(value, NULL, 0);
+ if (errno || val > 255)
+ return -EINVAL;
+
+ *(uint16_t *)extra_args = val;
+
return 0;
}
@@ -303,6 +322,7 @@ parse_val_u16(const char *key, const char *value, void *extra_args)
#define CNXK_FORCE_TAIL_DROP "force_tail_drop"
#define CNXK_DIS_XQE_DROP "disable_xqe_drop"
#define CNXK_RXC_STEP "rxc_step"
+#define CNXK_SKIP_SIZE_INFO "skip_size_info"
int
cnxk_ethdev_parse_devargs(struct rte_devargs *devargs, struct cnxk_eth_dev *dev)
@@ -317,6 +337,7 @@ cnxk_ethdev_parse_devargs(struct rte_devargs *devargs, struct cnxk_eth_dev *dev)
uint16_t custom_meta_aura_dis = 0;
uint16_t flow_prealloc_size = 1;
uint16_t switch_header_type = 0;
+ uint16_t skip_size_info = 0;
uint16_t flow_max_priority = 3;
uint16_t outb_nb_crypto_qs = 1;
uint32_t ipsec_in_min_spi = 0;
@@ -392,6 +413,8 @@ cnxk_ethdev_parse_devargs(struct rte_devargs *devargs, struct cnxk_eth_dev *dev)
rte_kvargs_process(kvlist, CNXK_FORCE_TAIL_DROP, &parse_flag, &force_tail_drop);
rte_kvargs_process(kvlist, CNXK_DIS_XQE_DROP, &parse_flag, &dis_xqe_drop);
rte_kvargs_process(kvlist, CNXK_RXC_STEP, &parse_rxc_step, &rxc_step);
+ rte_kvargs_process(kvlist, CNXK_SKIP_SIZE_INFO, &parse_skip_size_info,
+ &skip_size_info);
rte_kvargs_free(kvlist);
null_devargs:
@@ -424,6 +447,7 @@ cnxk_ethdev_parse_devargs(struct rte_devargs *devargs, struct cnxk_eth_dev *dev)
dev->npc.flow_max_priority = flow_max_priority;
dev->npc.switch_header_type = switch_header_type;
+ dev->npc.skip_size = skip_size_info;
dev->npc.sdp_channel = sdp_chan.channel;
dev->npc.sdp_channel_mask = sdp_chan.mask;
dev->npc.is_sdp_mask_set = sdp_chan.is_sdp_mask_set;
@@ -448,7 +472,7 @@ RTE_PMD_REGISTER_PARAM_STRING(net_cnxk,
CNXK_MAX_SQB_COUNT "=<8-512>"
CNXK_FLOW_PREALLOC_SIZE "=<1-32>"
CNXK_FLOW_MAX_PRIORITY "=<1-32>"
- CNXK_SWITCH_HEADER_TYPE "=<higig2|dsa|chlen90b>"
+ CNXK_SWITCH_HEADER_TYPE "=<higig2|dsa|chlen90b|skip_size>"
CNXK_RSS_TAG_AS_XOR "=1"
CNXK_IPSEC_IN_MAX_SPI "=<1-65535>"
CNXK_OUTB_NB_DESC "=<1-65535>"
@@ -463,4 +487,5 @@ RTE_PMD_REGISTER_PARAM_STRING(net_cnxk,
CNXK_CUSTOM_META_AURA_DIS "=1"
CNXK_FORCE_TAIL_DROP "=1"
CNXK_DIS_XQE_DROP "=1"
- CNXK_RXC_STEP "=<0-1048575>");
+ CNXK_RXC_STEP "=<0-1048575>"
+ CNXK_SKIP_SIZE_INFO "=<0x0-0xff>");
--
2.34.1
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH v2 08/22] net/cnxk: update inbound SA pkind for skip size
2026-06-11 14:20 ` [PATCH v2 01/22] net/cnxk: update mbuf next field for multi segment Rahul Bhansali
` (5 preceding siblings ...)
2026-06-11 14:20 ` [PATCH v2 07/22] drivers: add support for devargs skip size Rahul Bhansali
@ 2026-06-11 14:20 ` Rahul Bhansali
2026-06-11 14:20 ` [PATCH v2 09/22] common/cnxk: fix cnxk xstats names Rahul Bhansali
` (14 subsequent siblings)
21 siblings, 0 replies; 41+ messages in thread
From: Rahul Bhansali @ 2026-06-11 14:20 UTC (permalink / raw)
To: dev, Nithin Dabilpuram, Kiran Kumar K, Sunil Kumar Kori,
Satha Rao, Harman Kalra
Cc: jerinj, Rakesh Kudurumalla
From: Rakesh Kudurumalla <rkudurumalla@marvell.com>
Update the inbound SA pkind using roc_npc_skip_size_pkind_get()
during session create and session update for both CN10K and CN20K.
This ensures the CPT second pass uses the correct pkind when
skip size is configured, retaining the default pkind otherwise.
Signed-off-by: Rakesh Kudurumalla <rkudurumalla@marvell.com>
---
Changes in v2: No change.
drivers/net/cnxk/cn10k_ethdev_sec.c | 9 +++++++++
drivers/net/cnxk/cn20k_ethdev_sec.c | 8 ++++++++
2 files changed, 17 insertions(+)
diff --git a/drivers/net/cnxk/cn10k_ethdev_sec.c b/drivers/net/cnxk/cn10k_ethdev_sec.c
index 855bea1796..2f1fdf34fc 100644
--- a/drivers/net/cnxk/cn10k_ethdev_sec.c
+++ b/drivers/net/cnxk/cn10k_ethdev_sec.c
@@ -853,6 +853,10 @@ cn10k_eth_sec_session_create(void *device,
goto err;
}
+ rc = roc_npc_skip_size_pkind_get(&dev->npc);
+ if (rc >= 0)
+ inb_sa_dptr->w0.s.pkind = rc;
+
inb_priv = roc_nix_inl_ot_ipsec_inb_sa_sw_rsvd(inb_sa);
/* Back pointer to get eth_sec */
inb_priv->eth_sec = eth_sec;
@@ -1151,6 +1155,11 @@ cn10k_eth_sec_session_update(void *device, struct rte_security_session *sess,
rc = cnxk_ot_ipsec_inb_sa_fill(inb_sa_dptr, ipsec, crypto, 0);
if (rc)
goto err;
+
+ rc = roc_npc_skip_size_pkind_get(&dev->npc);
+ if (rc >= 0)
+ inb_sa_dptr->w0.s.pkind = rc;
+
/* Use cookie for original data */
inb_sa_dptr->w1.s.cookie = inb_sa->w1.s.cookie;
diff --git a/drivers/net/cnxk/cn20k_ethdev_sec.c b/drivers/net/cnxk/cn20k_ethdev_sec.c
index 5d0debb81d..31f2518ea3 100644
--- a/drivers/net/cnxk/cn20k_ethdev_sec.c
+++ b/drivers/net/cnxk/cn20k_ethdev_sec.c
@@ -865,6 +865,10 @@ cn20k_eth_sec_session_create(void *device, struct rte_security_session_conf *con
goto err;
}
+ rc = roc_npc_skip_size_pkind_get(&dev->npc);
+ if (rc >= 0)
+ inb_sa_dptr->w0.s.pkind = rc;
+
cn20k_eth_sec_inb_sa_misc_fill(inb_sa_dptr, ipsec);
inb_priv = roc_nix_inl_ow_ipsec_inb_sa_sw_rsvd(inb_sa);
@@ -1137,6 +1141,10 @@ cn20k_eth_sec_session_update(void *device, struct rte_security_session *sess,
if (rc)
return -EINVAL;
+ rc = roc_npc_skip_size_pkind_get(&dev->npc);
+ if (rc >= 0)
+ inb_sa_dptr->w0.s.pkind = rc;
+
cn20k_eth_sec_inb_sa_misc_fill(inb_sa_dptr, ipsec);
/* Use cookie for original data */
--
2.34.1
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH v2 09/22] common/cnxk: fix cnxk xstats names
2026-06-11 14:20 ` [PATCH v2 01/22] net/cnxk: update mbuf next field for multi segment Rahul Bhansali
` (6 preceding siblings ...)
2026-06-11 14:20 ` [PATCH v2 08/22] net/cnxk: update inbound SA pkind for " Rahul Bhansali
@ 2026-06-11 14:20 ` Rahul Bhansali
2026-06-11 14:20 ` [PATCH v2 10/22] common/cnxk: fix event type for soft expiry Rahul Bhansali
` (13 subsequent siblings)
21 siblings, 0 replies; 41+ messages in thread
From: Rahul Bhansali @ 2026-06-11 14:20 UTC (permalink / raw)
To: dev, Thomas Monjalon, Nithin Dabilpuram, Kiran Kumar K,
Sunil Kumar Kori, Satha Rao, Harman Kalra, Rakesh Kudurumalla
Cc: jerinj, Alok Mishra, stable
From: Alok Mishra <almishra@marvell.com>
Prevent out of bounds writes when application provides a smaller
xstat name array. Return required count when xstats_names is NULL
or when the provided buffer is too small,
Fixes: 825bd1d9d8e6 ("common/cnxk: update extra stats for inline device")
Cc: stable@dpdk.org
Signed-off-by: Alok Mishra <almishra@marvell.com>
---
Changes in v2: No change.
.mailmap | 1 +
drivers/common/cnxk/roc_nix_stats.c | 46 ++++++++++++++++-------------
2 files changed, 26 insertions(+), 21 deletions(-)
diff --git a/.mailmap b/.mailmap
index 0e0d83e1c6..efcb38b6bd 100644
--- a/.mailmap
+++ b/.mailmap
@@ -80,6 +80,7 @@ Alin Rauta <alin.rauta@intel.com>
Allain Legacy <allain.legacy@windriver.com>
Allen Hubbe <allen.hubbe@amd.com>
Alok Makhariya <alok.makhariya@nxp.com>
+Alok Mishra <almishra@marvell.com>
Alok Prasad <palok@marvell.com>
Alvaro Karsz <alvaro.karsz@solid-run.com>
Alvin Zhang <alvinx.zhang@intel.com>
diff --git a/drivers/common/cnxk/roc_nix_stats.c b/drivers/common/cnxk/roc_nix_stats.c
index 6f241c72de..ec2aca8164 100644
--- a/drivers/common/cnxk/roc_nix_stats.c
+++ b/drivers/common/cnxk/roc_nix_stats.c
@@ -503,46 +503,51 @@ roc_nix_xstats_names_get(struct roc_nix *roc_nix,
struct idev_cfg *idev = idev_get_cfg();
uint64_t i, count = 0;
- PLT_SET_USED(limit);
-
for (i = 0; i < CNXK_NIX_NUM_TX_XSTATS; i++) {
- NIX_XSTATS_NAME_PRINT(xstats_names, count, nix_tx_xstats, i);
+ if (xstats_names && count < limit)
+ NIX_XSTATS_NAME_PRINT(xstats_names, count, nix_tx_xstats, i);
count++;
}
for (i = 0; i < CNXK_NIX_NUM_RX_XSTATS; i++) {
- NIX_XSTATS_NAME_PRINT(xstats_names, count, nix_rx_xstats, i);
+ if (xstats_names && count < limit)
+ NIX_XSTATS_NAME_PRINT(xstats_names, count, nix_rx_xstats, i);
count++;
}
if (nix->inb_inl_dev && idev) {
if (idev->nix_inl_dev) {
for (i = 0; i < CNXK_INL_NIX_NUM_RX_XSTATS; i++) {
- NIX_XSTATS_NAME_PRINT(xstats_names, count,
- inl_nix_rx_xstats, i);
+ if (xstats_names && count < limit)
+ NIX_XSTATS_NAME_PRINT(xstats_names, count,
+ inl_nix_rx_xstats, i);
count++;
}
for (i = 0; i < CNXK_INL_NIX_RQ_XSTATS; i++) {
- NIX_XSTATS_NAME_PRINT(xstats_names, count,
- inl_nix_rq_xstats, i);
+ if (xstats_names && count < limit)
+ NIX_XSTATS_NAME_PRINT(xstats_names, count,
+ inl_nix_rq_xstats, i);
count++;
}
for (i = 0; i < PLT_DIM(inl_sw_xstats); i++) {
- NIX_XSTATS_NAME_PRINT(xstats_names, count, inl_sw_xstats, i);
+ if (xstats_names && count < limit)
+ NIX_XSTATS_NAME_PRINT(xstats_names, count, inl_sw_xstats,
+ i);
count++;
}
}
}
for (i = 0; i < CNXK_NIX_NUM_QUEUE_XSTATS; i++) {
- NIX_XSTATS_NAME_PRINT(xstats_names, count, nix_q_xstats, i);
+ if (xstats_names && count < limit)
+ NIX_XSTATS_NAME_PRINT(xstats_names, count, nix_q_xstats, i);
count++;
}
if (roc_model_is_cn10k() || roc_model_is_cn20k()) {
for (i = 0; i < CNXK_NIX_NUM_CN10K_RX_XSTATS; i++) {
- NIX_XSTATS_NAME_PRINT(xstats_names, count,
- nix_cn10k_rx_xstats, i);
+ if (xstats_names && count < limit)
+ NIX_XSTATS_NAME_PRINT(xstats_names, count, nix_cn10k_rx_xstats, i);
count++;
}
}
@@ -552,30 +557,29 @@ roc_nix_xstats_names_get(struct roc_nix *roc_nix,
if (roc_model_is_cn9k()) {
for (i = 0; i < CNXK_NIX_NUM_RX_XSTATS_CGX; i++) {
- NIX_XSTATS_NAME_PRINT(xstats_names, count,
- nix_rx_xstats_cgx, i);
+ if (xstats_names && count < limit)
+ NIX_XSTATS_NAME_PRINT(xstats_names, count, nix_rx_xstats_cgx, i);
count++;
}
for (i = 0; i < CNXK_NIX_NUM_TX_XSTATS_CGX; i++) {
- NIX_XSTATS_NAME_PRINT(xstats_names, count,
- nix_tx_xstats_cgx, i);
+ if (xstats_names && count < limit)
+ NIX_XSTATS_NAME_PRINT(xstats_names, count, nix_tx_xstats_cgx, i);
count++;
}
} else {
for (i = 0; i < CNXK_NIX_NUM_RX_XSTATS_RPM; i++) {
- NIX_XSTATS_NAME_PRINT(xstats_names, count,
- nix_rx_xstats_rpm, i);
+ if (xstats_names && count < limit)
+ NIX_XSTATS_NAME_PRINT(xstats_names, count, nix_rx_xstats_rpm, i);
count++;
}
for (i = 0; i < CNXK_NIX_NUM_TX_XSTATS_RPM; i++) {
- NIX_XSTATS_NAME_PRINT(xstats_names, count,
- nix_tx_xstats_rpm, i);
+ if (xstats_names && count < limit)
+ NIX_XSTATS_NAME_PRINT(xstats_names, count, nix_tx_xstats_rpm, i);
count++;
}
}
-
return count;
}
--
2.34.1
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH v2 10/22] common/cnxk: fix event type for soft expiry
2026-06-11 14:20 ` [PATCH v2 01/22] net/cnxk: update mbuf next field for multi segment Rahul Bhansali
` (7 preceding siblings ...)
2026-06-11 14:20 ` [PATCH v2 09/22] common/cnxk: fix cnxk xstats names Rahul Bhansali
@ 2026-06-11 14:20 ` Rahul Bhansali
2026-06-11 14:20 ` [PATCH v2 11/22] net/cnxk: enable CPT CQ by default for inline IPsec Rahul Bhansali
` (12 subsequent siblings)
21 siblings, 0 replies; 41+ messages in thread
From: Rahul Bhansali @ 2026-06-11 14:20 UTC (permalink / raw)
To: dev, Nithin Dabilpuram, Kiran Kumar K, Sunil Kumar Kori,
Satha Rao, Harman Kalra, Stephen Hemminger
Cc: jerinj, Rahul Bhansali
Fix event type to default for inline soft expiry processing.
Fixes: 4a6154a7bd27 ("common/cnxk: fix array out-of-bounds")
Signed-off-by: Rahul Bhansali <rbhansali@marvell.com>
---
Changes in v2: No change.
drivers/common/cnxk/roc_nix_inl_dev.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/common/cnxk/roc_nix_inl_dev.c b/drivers/common/cnxk/roc_nix_inl_dev.c
index 667209b8a0..bfdeef2688 100644
--- a/drivers/common/cnxk/roc_nix_inl_dev.c
+++ b/drivers/common/cnxk/roc_nix_inl_dev.c
@@ -1234,6 +1234,7 @@ inl_outb_soft_exp_poll(struct nix_inl_dev *inl_dev, uint32_t ring_idx)
if (sa != NULL) {
uint64_t tmp[2];
+ tmp[0] = ~0ULL;
inl_dev->work_cb(tmp, sa, NIX_INL_SOFT_EXPIRY_THRD, NULL, port_id);
__atomic_store_n(ring_base + tail_l + 1, 0ULL, __ATOMIC_RELAXED);
__atomic_fetch_add((uint32_t *)ring_base, 1, __ATOMIC_ACQ_REL);
--
2.34.1
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH v2 11/22] net/cnxk: enable CPT CQ by default for inline IPsec
2026-06-11 14:20 ` [PATCH v2 01/22] net/cnxk: update mbuf next field for multi segment Rahul Bhansali
` (8 preceding siblings ...)
2026-06-11 14:20 ` [PATCH v2 10/22] common/cnxk: fix event type for soft expiry Rahul Bhansali
@ 2026-06-11 14:20 ` Rahul Bhansali
2026-06-11 14:20 ` [PATCH v2 12/22] net/cnxk: fix unsigned integer underflow in LSO calculation Rahul Bhansali
` (11 subsequent siblings)
21 siblings, 0 replies; 41+ messages in thread
From: Rahul Bhansali @ 2026-06-11 14:20 UTC (permalink / raw)
To: dev, Nithin Dabilpuram, Kiran Kumar K, Sunil Kumar Kori,
Satha Rao, Harman Kalra
Cc: jerinj, Aarnav JP
From: Aarnav JP <ajp@marvell.com>
CPT Completion Queue is supported on CN20K and provides
hardware-based completion notification, eliminating the
need for software polling. Change the default value of
cpt_cq_enable devarg from 0 to 1 so that CPT CQ is
enabled by default.
Signed-off-by: Aarnav JP <ajp@marvell.com>
---
Changes in v2: No change.
doc/guides/nics/cnxk.rst | 13 +++++++++++++
drivers/net/cnxk/cnxk_ethdev_sec.c | 2 +-
2 files changed, 14 insertions(+), 1 deletion(-)
diff --git a/doc/guides/nics/cnxk.rst b/doc/guides/nics/cnxk.rst
index 239ebcd05c..c71029e1dc 100644
--- a/doc/guides/nics/cnxk.rst
+++ b/doc/guides/nics/cnxk.rst
@@ -745,6 +745,19 @@ Runtime Config Options for inline device
With the above configuration, inline inbound IPsec post-processing
should be done by the application.
+- ``Enable CPT Completion Queue for inline IPsec`` (default ``1`` for CN20K, ``0`` otherwise)
+
+ CPT Completion Queue for inline IPsec event delivery can be enabled or disabled
+ by ``cpt_cq_enable`` devargs parameter.
+ This option is supported on OCTEON CN20K SoC family.
+
+ For example::
+
+ -a 0002:1d:00.0,cpt_cq_enable=1
+
+ With the above configuration, driver would enable CPT completion queue
+ for inline IPsec event delivery instead of using the err-ring poll thread.
+
Port Representors
-----------------
diff --git a/drivers/net/cnxk/cnxk_ethdev_sec.c b/drivers/net/cnxk/cnxk_ethdev_sec.c
index fa7eacfbe4..61eb55ba43 100644
--- a/drivers/net/cnxk/cnxk_ethdev_sec.c
+++ b/drivers/net/cnxk/cnxk_ethdev_sec.c
@@ -742,7 +742,7 @@ nix_inl_parse_devargs(struct rte_devargs *devargs,
uint32_t meta_buf_sz = 0;
uint8_t rx_inj_ena = 0;
uint8_t selftest = 0;
- uint8_t cpt_cq_enable = 0;
+ uint8_t cpt_cq_enable = roc_feature_nix_has_cpt_cq_support() ? 1 : 0;
memset(&cpt_channel, 0, sizeof(cpt_channel));
--
2.34.1
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH v2 12/22] net/cnxk: fix unsigned integer underflow in LSO calculation
2026-06-11 14:20 ` [PATCH v2 01/22] net/cnxk: update mbuf next field for multi segment Rahul Bhansali
` (9 preceding siblings ...)
2026-06-11 14:20 ` [PATCH v2 11/22] net/cnxk: enable CPT CQ by default for inline IPsec Rahul Bhansali
@ 2026-06-11 14:20 ` Rahul Bhansali
2026-06-11 14:20 ` [PATCH v2 13/22] net/cnxk: derive ethdev from SA for inbound CPT CQ events Rahul Bhansali
` (10 subsequent siblings)
21 siblings, 0 replies; 41+ messages in thread
From: Rahul Bhansali @ 2026-06-11 14:20 UTC (permalink / raw)
To: dev, Nithin Dabilpuram, Kiran Kumar K, Sunil Kumar Kori,
Satha Rao, Harman Kalra, Pavan Nikhilesh, Jerin Jacob,
Rahul Bhansali
Cc: Aarnav JP, stable
From: Aarnav JP <ajp@marvell.com>
Replace branchless mask-based selection with a ternary operator
to resolve Coverity integer underflow warning. The expression
-(!w1.il3type) assigned -1 to a uint64_t variable, which is
well-defined but flagged as an unsigned integer underflow.
Coverity issue: 502004
Fixes: 19f3af2371a7 ("net/cnxk: add Tx burst for CN10K")
Fixes: 39dc567c1955 ("net/cnxk: add Tx burst for CN9K")
Fixes: 006c1daa89b9 ("net/cnxk: support Tx burst scalar for CN20K")
Cc: stable@dpdk.org
Signed-off-by: Aarnav JP <ajp@marvell.com>
---
Changes in v2: No change.
drivers/net/cnxk/cn10k_tx.h | 8 ++------
drivers/net/cnxk/cn20k_tx.h | 8 ++------
drivers/net/cnxk/cn9k_tx.h | 8 ++------
3 files changed, 6 insertions(+), 18 deletions(-)
diff --git a/drivers/net/cnxk/cn10k_tx.h b/drivers/net/cnxk/cn10k_tx.h
index 8c912a1f35..d5cb2c3294 100644
--- a/drivers/net/cnxk/cn10k_tx.h
+++ b/drivers/net/cnxk/cn10k_tx.h
@@ -1138,10 +1138,8 @@ cn10k_nix_xmit_prepare(struct cn10k_eth_txq *txq,
if (flags & NIX_TX_NEED_EXT_HDR && flags & NIX_TX_OFFLOAD_TSO_F &&
(ol_flags & RTE_MBUF_F_TX_TCP_SEG)) {
uint16_t lso_sb;
- uint64_t mask;
- mask = -(!w1.il3type);
- lso_sb = (mask & w1.ol4ptr) + (~mask & w1.il4ptr) + m->l4_len;
+ lso_sb = (w1.il3type ? w1.il4ptr : w1.ol4ptr) + m->l4_len;
send_hdr_ext->w0.lso_sb = lso_sb;
send_hdr_ext->w0.lso = 1;
@@ -1766,13 +1764,11 @@ cn10k_nix_prepare_tso(struct rte_mbuf *m, union nix_send_hdr_w1_u *w1,
const uint64_t flags, const uint64_t lso_tun_fmt)
{
uint16_t lso_sb;
- uint64_t mask;
if (!(ol_flags & RTE_MBUF_F_TX_TCP_SEG))
return;
- mask = -(!w1->il3type);
- lso_sb = (mask & w1->ol4ptr) + (~mask & w1->il4ptr) + m->l4_len;
+ lso_sb = (w1->il3type ? w1->il4ptr : w1->ol4ptr) + m->l4_len;
w0->u |= BIT(14);
w0->lso_sb = lso_sb;
diff --git a/drivers/net/cnxk/cn20k_tx.h b/drivers/net/cnxk/cn20k_tx.h
index 8e64d2e352..a1c71f2761 100644
--- a/drivers/net/cnxk/cn20k_tx.h
+++ b/drivers/net/cnxk/cn20k_tx.h
@@ -1117,10 +1117,8 @@ cn20k_nix_xmit_prepare(struct cn20k_eth_txq *txq, struct rte_mbuf *m, struct rte
if (flags & NIX_TX_NEED_EXT_HDR && flags & NIX_TX_OFFLOAD_TSO_F &&
(ol_flags & RTE_MBUF_F_TX_TCP_SEG)) {
uint16_t lso_sb;
- uint64_t mask;
- mask = -(!w1.il3type);
- lso_sb = (mask & w1.ol4ptr) + (~mask & w1.il4ptr) + m->l4_len;
+ lso_sb = (w1.il3type ? w1.il4ptr : w1.ol4ptr) + m->l4_len;
send_hdr_ext->w0.lso_sb = lso_sb;
send_hdr_ext->w0.lso = 1;
@@ -1732,13 +1730,11 @@ cn20k_nix_prepare_tso(struct rte_mbuf *m, union nix_send_hdr_w1_u *w1, union nix
uint64_t ol_flags, const uint64_t flags, const uint64_t lso_tun_fmt)
{
uint16_t lso_sb;
- uint64_t mask;
if (!(ol_flags & RTE_MBUF_F_TX_TCP_SEG))
return;
- mask = -(!w1->il3type);
- lso_sb = (mask & w1->ol4ptr) + (~mask & w1->il4ptr) + m->l4_len;
+ lso_sb = (w1->il3type ? w1->il4ptr : w1->ol4ptr) + m->l4_len;
w0->u |= BIT(14);
w0->lso_sb = lso_sb;
diff --git a/drivers/net/cnxk/cn9k_tx.h b/drivers/net/cnxk/cn9k_tx.h
index 0ec448e36c..2f9b936d56 100644
--- a/drivers/net/cnxk/cn9k_tx.h
+++ b/drivers/net/cnxk/cn9k_tx.h
@@ -478,10 +478,8 @@ cn9k_nix_xmit_prepare(struct cn9k_eth_txq *txq, struct rte_mbuf *m, struct rte_m
if (flags & NIX_TX_OFFLOAD_TSO_F && (ol_flags & RTE_MBUF_F_TX_TCP_SEG)) {
uint16_t lso_sb;
- uint64_t mask;
- mask = -(!w1.il3type);
- lso_sb = (mask & w1.ol4ptr) + (~mask & w1.il4ptr) + m->l4_len;
+ lso_sb = (w1.il3type ? w1.il4ptr : w1.ol4ptr) + m->l4_len;
send_hdr_ext->w0.lso_sb = lso_sb;
send_hdr_ext->w0.lso = 1;
@@ -875,13 +873,11 @@ cn9k_nix_prepare_tso(struct rte_mbuf *m, union nix_send_hdr_w1_u *w1,
uint64_t flags)
{
uint16_t lso_sb;
- uint64_t mask;
if (!(ol_flags & RTE_MBUF_F_TX_TCP_SEG))
return;
- mask = -(!w1->il3type);
- lso_sb = (mask & w1->ol4ptr) + (~mask & w1->il4ptr) + m->l4_len;
+ lso_sb = (w1->il3type ? w1->il4ptr : w1->ol4ptr) + m->l4_len;
w0->u |= BIT(14);
w0->lso_sb = lso_sb;
--
2.34.1
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH v2 13/22] net/cnxk: derive ethdev from SA for inbound CPT CQ events
2026-06-11 14:20 ` [PATCH v2 01/22] net/cnxk: update mbuf next field for multi segment Rahul Bhansali
` (10 preceding siblings ...)
2026-06-11 14:20 ` [PATCH v2 12/22] net/cnxk: fix unsigned integer underflow in LSO calculation Rahul Bhansali
@ 2026-06-11 14:20 ` Rahul Bhansali
2026-06-11 14:20 ` [PATCH v2 14/22] net/cnxk: fix bitwise operand size mismatch in link mode Rahul Bhansali
` (9 subsequent siblings)
21 siblings, 0 replies; 41+ messages in thread
From: Rahul Bhansali @ 2026-06-11 14:20 UTC (permalink / raw)
To: dev, Nithin Dabilpuram, Kiran Kumar K, Sunil Kumar Kori,
Satha Rao, Harman Kalra
Cc: jerinj, Aarnav JP
From: Aarnav JP <ajp@marvell.com>
With inbound CPT CQ events, port_id is unavailable since the inline
device has no roc_nix. Resolve eth_dev for inbound CQ events in the
cn20k PMD callback via the SA private data chain instead of relying
on port_id.
Add an eth_dev back pointer to cnxk_eth_sec_sess, populated at
session creation, to complete the SA-to-ethdev lookup path
(inb_priv->eth_sec->eth_dev).
Signed-off-by: Aarnav JP <ajp@marvell.com>
---
Changes in v2: No change.
drivers/net/cnxk/cn20k_ethdev_sec.c | 22 ++++++++++++++++++++--
drivers/net/cnxk/cnxk_ethdev.h | 3 +++
2 files changed, 23 insertions(+), 2 deletions(-)
diff --git a/drivers/net/cnxk/cn20k_ethdev_sec.c b/drivers/net/cnxk/cn20k_ethdev_sec.c
index 31f2518ea3..a5be85901f 100644
--- a/drivers/net/cnxk/cn20k_ethdev_sec.c
+++ b/drivers/net/cnxk/cn20k_ethdev_sec.c
@@ -541,7 +541,6 @@ cn20k_eth_sec_sso_work_cb(uint64_t *gw, void *args, enum nix_inl_event_type type
uintptr_t nixtx;
uint8_t port;
- RTE_SET_USED(args);
plt_nix_dbg("Received %s event", get_inl_event_type(type));
switch ((gw[0] >> 28) & 0xF) {
@@ -561,8 +560,26 @@ cn20k_eth_sec_sso_work_cb(uint64_t *gw, void *args, enum nix_inl_event_type type
/* Fall through */
default:
if (type) {
- eth_dev = &rte_eth_devices[port_id];
struct cpt_cq_s *cqs = (struct cpt_cq_s *)cq_s;
+
+ if (type == NIX_INL_INB_CPT_CQ) {
+ struct cn20k_inb_priv_data *inb_priv;
+
+ inb_priv = roc_nix_inl_ow_ipsec_inb_sa_sw_rsvd(args);
+ if (inb_priv->eth_sec && inb_priv->eth_sec->eth_dev) {
+ eth_dev = inb_priv->eth_sec->eth_dev;
+ } else {
+ plt_err("Inbound CPT CQ event: no eth_dev in SA priv");
+ return;
+ }
+ } else {
+ if (port_id >= RTE_MAX_ETHPORTS) {
+ plt_err("CPT CQ event: invalid port_id %u", port_id);
+ return;
+ }
+ eth_dev = &rte_eth_devices[port_id];
+ }
+
if (type < NIX_INL_SSO) {
cn20k_eth_sec_post_event(eth_dev, args, type,
(uint16_t)cqs->w0.s.uc_compcode,
@@ -804,6 +821,7 @@ cn20k_eth_sec_session_create(void *device, struct rte_security_session_conf *con
inl_dev = !!dev->inb.inl_dev;
memset(eth_sec, 0, sizeof(struct cnxk_eth_sec_sess));
+ eth_sec->eth_dev = eth_dev;
sess_priv.u64 = 0;
lock = inbound ? &dev->inb.lock : &dev->outb.lock;
diff --git a/drivers/net/cnxk/cnxk_ethdev.h b/drivers/net/cnxk/cnxk_ethdev.h
index ea6a2be30e..6686fdba31 100644
--- a/drivers/net/cnxk/cnxk_ethdev.h
+++ b/drivers/net/cnxk/cnxk_ethdev.h
@@ -225,6 +225,9 @@ struct cnxk_eth_sec_sess {
/* Out-Of-Place processing */
bool inb_oop;
+
+ /* Back pointer to eth_dev for port_id derivation in CQ callbacks */
+ struct rte_eth_dev *eth_dev;
};
TAILQ_HEAD(cnxk_eth_sec_sess_list, cnxk_eth_sec_sess);
--
2.34.1
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH v2 14/22] net/cnxk: fix bitwise operand size mismatch in link mode
2026-06-11 14:20 ` [PATCH v2 01/22] net/cnxk: update mbuf next field for multi segment Rahul Bhansali
` (11 preceding siblings ...)
2026-06-11 14:20 ` [PATCH v2 13/22] net/cnxk: derive ethdev from SA for inbound CPT CQ events Rahul Bhansali
@ 2026-06-11 14:20 ` Rahul Bhansali
2026-06-11 14:20 ` [PATCH v2 15/22] common/cnxk: add cipher key length check in key set Rahul Bhansali
` (8 subsequent siblings)
21 siblings, 0 replies; 41+ messages in thread
From: Rahul Bhansali @ 2026-06-11 14:20 UTC (permalink / raw)
To: dev, Nithin Dabilpuram, Kiran Kumar K, Sunil Kumar Kori,
Satha Rao, Harman Kalra
Cc: jerinj, Aarnav JP, stable
From: Aarnav JP <ajp@marvell.com>
Cast enum roc_nix_link_mode values to uint64_t before bitwise
OR with uint64_t advertise variable to ensure consistent
operand sizes.
Fixes: 292fcbb3d290 ("net/cnxk: support link mode configuration")
Cc: stable@dpdk.org
Signed-off-by: Aarnav JP <ajp@marvell.com>
---
Changes in v2: No change.
drivers/net/cnxk/cnxk_link.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/net/cnxk/cnxk_link.c b/drivers/net/cnxk/cnxk_link.c
index dde2c3a313..f6682b4697 100644
--- a/drivers/net/cnxk/cnxk_link.c
+++ b/drivers/net/cnxk/cnxk_link.c
@@ -61,13 +61,13 @@ nix_link_advertising_get(struct cnxk_eth_dev *dev, struct roc_nix_link_info *lin
} else {
for (bit = 0; bit < ROC_NIX_LINK_SPEED_MAX; bit++) {
if (link_info->speed_bitmask & BIT_ULL(bit))
- advertise |= rte_to_ethtool_mode[bit];
+ advertise |= (uint64_t)rte_to_ethtool_mode[bit];
}
goto exit;
}
}
- advertise |= mac_to_ethtool_mode[linfo.lmac_type_id][link_info->full_duplex];
+ advertise |= (uint64_t)mac_to_ethtool_mode[linfo.lmac_type_id][link_info->full_duplex];
exit:
return advertise;
}
--
2.34.1
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH v2 15/22] common/cnxk: add cipher key length check in key set
2026-06-11 14:20 ` [PATCH v2 01/22] net/cnxk: update mbuf next field for multi segment Rahul Bhansali
` (12 preceding siblings ...)
2026-06-11 14:20 ` [PATCH v2 14/22] net/cnxk: fix bitwise operand size mismatch in link mode Rahul Bhansali
@ 2026-06-11 14:20 ` Rahul Bhansali
2026-06-11 14:20 ` [PATCH v2 16/22] common/cnxk: fix Klocwork static analysis issues Rahul Bhansali
` (7 subsequent siblings)
21 siblings, 0 replies; 41+ messages in thread
From: Rahul Bhansali @ 2026-06-11 14:20 UTC (permalink / raw)
To: dev, Nithin Dabilpuram, Kiran Kumar K, Sunil Kumar Kori,
Satha Rao, Harman Kalra, Akhil Goyal, Ankur Dwivedi
Cc: jerinj, Aarnav JP, stable
From: Aarnav JP <ajp@marvell.com>
Add upper-bound checks before memcpy into encr_key[32]
in roc_se_ciph_key_set() to prevent buffer overflow into
adjacent encr_iv[16]. Covers all write paths including
AES-DOCSISBPI and DES-DOCSISBPI branches that bypass
the generic copy via goto.
Fixes: 5e076b609f2a ("common/cnxk: add SE set key for crypto")
Cc: stable@dpdk.org
Signed-off-by: Aarnav JP <ajp@marvell.com>
---
Changes in v2: No change.
drivers/common/cnxk/roc_se.c | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/drivers/common/cnxk/roc_se.c b/drivers/common/cnxk/roc_se.c
index d841a926a4..1cec536169 100644
--- a/drivers/common/cnxk/roc_se.c
+++ b/drivers/common/cnxk/roc_se.c
@@ -545,12 +545,22 @@ roc_se_ciph_key_set(struct roc_se_ctx *se_ctx, roc_se_cipher_type type, const ui
* less than 128. Pass it as regular AES-CBC cipher to CPT, but keep type in
* se_ctx as AES_DOCSISBPI to skip block size checks in instruction preparation.
*/
+ if (key_len > sizeof(fctx->enc.encr_key)) {
+ plt_err("Cipher key length %u exceeds max %zu", key_len,
+ sizeof(fctx->enc.encr_key));
+ return -1;
+ }
cpt_ciph_aes_key_type_set(fctx, key_len);
fctx->enc.enc_cipher = ROC_SE_AES_CBC;
memcpy(fctx->enc.encr_key, key, key_len);
goto success;
case ROC_SE_DES_DOCSISBPI:
/* See case ROC_SE_DES3_CBC: for explanation */
+ if (key_len * 3 > sizeof(fctx->enc.encr_key)) {
+ plt_err("DES-DOCSISBPI key length %u exceeds max %zu", key_len,
+ sizeof(fctx->enc.encr_key) / 3);
+ return -1;
+ }
for (i = 0; i < 3; i++)
memcpy(fctx->enc.encr_key + key_len * i, key, key_len);
/*
@@ -628,6 +638,11 @@ roc_se_ciph_key_set(struct roc_se_ctx *se_ctx, roc_se_cipher_type type, const ui
if (se_ctx->hash_type != ROC_SE_GMAC_TYPE)
fctx->enc.enc_cipher = type;
+ if (key_len > sizeof(fctx->enc.encr_key)) {
+ plt_err("Cipher key length %u exceeds max %zu", key_len,
+ sizeof(fctx->enc.encr_key));
+ return -1;
+ }
memcpy(fctx->enc.encr_key, key, key_len);
success:
--
2.34.1
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH v2 16/22] common/cnxk: fix Klocwork static analysis issues
2026-06-11 14:20 ` [PATCH v2 01/22] net/cnxk: update mbuf next field for multi segment Rahul Bhansali
` (13 preceding siblings ...)
2026-06-11 14:20 ` [PATCH v2 15/22] common/cnxk: add cipher key length check in key set Rahul Bhansali
@ 2026-06-11 14:20 ` Rahul Bhansali
2026-06-11 14:20 ` [PATCH v2 17/22] common/cnxk: add auth key len check in inbound SA Rahul Bhansali
` (6 subsequent siblings)
21 siblings, 0 replies; 41+ messages in thread
From: Rahul Bhansali @ 2026-06-11 14:20 UTC (permalink / raw)
To: dev, Nithin Dabilpuram, Kiran Kumar K, Sunil Kumar Kori,
Satha Rao, Harman Kalra, Satheesh Paul, Jerin Jacob,
Rakesh Kudurumalla
Cc: Aarnav JP, stable
From: Aarnav JP <ajp@marvell.com>
Fix NULL pointer dereferences (roc_dev.c, roc_npa.c, roc_nix_inl.c),
resource leaks in error paths (roc_dev.c, roc_dpi.c, roc_ree.c,
roc_nix.c, roc_emdev.c), uninitialized variables (roc_npa_debug.c,
roc_emdev.c), array out-of-bounds access (roc_npc_utils.c, roc_emdev.c),
bitwise operand size mismatches (roc_mbox.h, roc_emdev_irq.c), and
format string type mismatches (roc_cpt_debug.c).
Fixes: 5d8ff275433a ("common/cnxk: fix race condition between up and down mailbox")
Fixes: 9a92937cf0c8 ("common/cnxk: fix possible out-of-bounds access")
Fixes: 7557e3f5b9fa ("common/cnxk: replace direct API usage in REE")
Fixes: 3fdf3e53f3c4 ("common/cnxk: enable CPT CQ for inline IPsec inbound")
Fixes: c758279fee32 ("common/cnxk: support debug dump to file")
Cc: stable@dpdk.org
Signed-off-by: Aarnav JP <ajp@marvell.com>
---
Changes in v2: No change.
drivers/common/cnxk/roc_cpt_debug.c | 29 ++++++++++++++---------------
drivers/common/cnxk/roc_dev.c | 15 +++++++++++----
drivers/common/cnxk/roc_mbox.h | 4 ++--
drivers/common/cnxk/roc_nix_inl.c | 3 +--
drivers/common/cnxk/roc_npa.c | 3 +++
drivers/common/cnxk/roc_npa_debug.c | 8 +++++++-
drivers/common/cnxk/roc_npc_utils.c | 10 +++++++---
drivers/common/cnxk/roc_ree.c | 17 ++++++++++++-----
8 files changed, 57 insertions(+), 32 deletions(-)
diff --git a/drivers/common/cnxk/roc_cpt_debug.c b/drivers/common/cnxk/roc_cpt_debug.c
index 3b3e678c20..3c1c052e50 100644
--- a/drivers/common/cnxk/roc_cpt_debug.c
+++ b/drivers/common/cnxk/roc_cpt_debug.c
@@ -33,7 +33,7 @@ cpt_cnxk_parse_hdr_dump(FILE *file, const struct cpt_parse_hdr_s *cpth)
cpth->w0.num_frags, cpth->w0.pkt_out);
/* W1 */
- cpt_dump(file, "W1: wqe_ptr \t0x%016lx\t", cpth->wqe_ptr);
+ cpt_dump(file, "W1: wqe_ptr \t0x%016" PRIx64 "\t", cpth->wqe_ptr);
/* W2 */
cpt_dump(file, "W2: pkt_inline \t0x%x\t\torig_pkt_aura \t0x%x", cpth->w2.pkt_inline,
@@ -135,29 +135,28 @@ cpt_cn10k_parse_hdr_dump(FILE *file, const struct cpt_cn10k_parse_hdr_s *cpth)
cpt_dump(file, "W0: cookie \t0x%x\t\tmatch_id \t0x%04x \t",
cpth->w0.cookie, cpth->w0.match_id);
cpt_dump(file, "W0: err_sum \t%u \t", cpth->w0.err_sum);
- cpt_dump(file, "W0: reas_sts \t0x%x\t\tet_owr \t%u\t\tpkt_fmt \t%u \t",
- cpth->w0.reas_sts, cpth->w0.et_owr, cpth->w0.pkt_fmt);
- cpt_dump(file, "W0: pad_len \t%u\t\tnum_frags \t%u\t\tpkt_out \t%u \t",
- cpth->w0.pad_len, cpth->w0.num_frags, cpth->w0.pkt_out);
+ cpt_dump(file, "W0: reas_sts \t0x%x\t\tet_owr \t%u\t\tpkt_fmt \t%u \t", cpth->w0.reas_sts,
+ cpth->w0.et_owr, cpth->w0.pkt_fmt);
+ cpt_dump(file, "W0: pad_len \t%u\t\tnum_frags \t%u\t\tpkt_out \t%u \t", cpth->w0.pad_len,
+ cpth->w0.num_frags, cpth->w0.pkt_out);
/* W1 */
- cpt_dump(file, "W1: wqe_ptr \t0x%016lx\t",
- plt_be_to_cpu_64(cpth->wqe_ptr));
+ cpt_dump(file, "W1: wqe_ptr \t0x%016" PRIx64 "\t",
+ (uint64_t)plt_be_to_cpu_64(cpth->wqe_ptr));
/* W2 */
- cpt_dump(file, "W2: frag_age \t0x%x\t\torig_pf_func \t0x%04x",
- cpth->w2.frag_age, cpth->w2.orig_pf_func);
- cpt_dump(file, "W2: il3_off \t0x%x\t\tfi_pad \t0x%x \t",
- cpth->w2.il3_off, cpth->w2.fi_pad);
+ cpt_dump(file, "W2: frag_age \t0x%x\t\torig_pf_func \t0x%04x", cpth->w2.frag_age,
+ cpth->w2.orig_pf_func);
+ cpt_dump(file, "W2: il3_off \t0x%x\t\tfi_pad \t0x%x \t", cpth->w2.il3_off, cpth->w2.fi_pad);
cpt_dump(file, "W2: fi_offset \t0x%x \t", cpth->w2.fi_offset);
/* W3 */
- cpt_dump(file, "W3: hw_ccode \t0x%x\t\tuc_ccode \t0x%x\t\tspi \t0x%08x",
- cpth->w3.hw_ccode, cpth->w3.uc_ccode, cpth->w3.spi);
+ cpt_dump(file, "W3: hw_ccode \t0x%x\t\tuc_ccode \t0x%x\t\tspi \t0x%08x", cpth->w3.hw_ccode,
+ cpth->w3.uc_ccode, cpth->w3.spi);
/* W4 */
- cpt_dump(file, "W4: esn \t%" PRIx64 " \t OR frag1_wqe_ptr \t0x%" PRIx64,
- cpth->esn, plt_be_to_cpu_64(cpth->frag1_wqe_ptr));
+ cpt_dump(file, "W4: esn \t%" PRIx64 " \t OR frag1_wqe_ptr \t0x%" PRIx64, cpth->esn,
+ (uint64_t)plt_be_to_cpu_64(cpth->frag1_wqe_ptr));
/* offset of 0 implies 256B, otherwise it implies offset*8B */
offset = cpth->w2.fi_offset;
diff --git a/drivers/common/cnxk/roc_dev.c b/drivers/common/cnxk/roc_dev.c
index 32409f2ef3..61aa4b3075 100644
--- a/drivers/common/cnxk/roc_dev.c
+++ b/drivers/common/cnxk/roc_dev.c
@@ -1796,14 +1796,17 @@ dev_init(struct dev *dev, struct plt_pci_device *pci_dev)
rc = npa_lf_init(dev, pci_dev);
if (rc)
- goto stop_msg_thrd;
+ goto vf_flr_unregister;
/* Setup LMT line base */
rc = dev_lmt_setup(dev);
if (rc)
- goto stop_msg_thrd;
+ goto vf_flr_unregister;
return rc;
+vf_flr_unregister:
+ if (!is_vf)
+ dev_vf_flr_unregister_irqs(pci_dev, dev);
stop_msg_thrd:
/* Exiting the mbox sync thread */
if (dev->sync.start_thread) {
@@ -1812,10 +1815,14 @@ dev_init(struct dev *dev, struct plt_pci_device *pci_dev)
plt_thread_join(dev->sync.pfvf_msg_thread, NULL);
}
thread_fail:
- pthread_mutex_destroy(&dev->sync.mutex);
- pthread_cond_destroy(&dev->sync.pfvf_msg_cond);
+ if (pci_dev->max_vfs > 0) {
+ pthread_mutex_destroy(&dev->sync.mutex);
+ pthread_cond_destroy(&dev->sync.pfvf_msg_cond);
+ }
iounmap:
dev_vf_mbase_put(pci_dev, vf_mbase);
+ mbox_fini(&dev->mbox_vfpf);
+ mbox_fini(&dev->mbox_vfpf_up);
mbox_unregister:
dev_mbox_unregister_irq(pci_dev, dev);
if (dev->ops)
diff --git a/drivers/common/cnxk/roc_mbox.h b/drivers/common/cnxk/roc_mbox.h
index 1158ff50a7..52ecde6563 100644
--- a/drivers/common/cnxk/roc_mbox.h
+++ b/drivers/common/cnxk/roc_mbox.h
@@ -47,8 +47,8 @@ struct mbox_msghdr {
#define RVU_VF_VFPF_MBOX0 (0x0000)
#define RVU_VF_VFPF_MBOX1 (0x0008)
-#define MBOX_DOWN_MSG 1
-#define MBOX_UP_MSG 2
+#define MBOX_DOWN_MSG 1ULL
+#define MBOX_UP_MSG 2ULL
/* Mailbox message types */
#define MBOX_MSG_MASK 0xFFFF
diff --git a/drivers/common/cnxk/roc_nix_inl.c b/drivers/common/cnxk/roc_nix_inl.c
index b515d52534..db101e71a5 100644
--- a/drivers/common/cnxk/roc_nix_inl.c
+++ b/drivers/common/cnxk/roc_nix_inl.c
@@ -638,9 +638,8 @@ nix_inl_reass_inb_sa_tbl_setup(struct roc_nix *roc_nix)
res_addr_offset = (uint64_t)(inl_dev->res_addr_offset & 0xFF) << 48;
if (res_addr_offset)
res_addr_offset |= (1UL << 56);
+ cpt_cq_ena = (uint64_t)inl_dev->cpt_cq_ena << 63;
}
-
- cpt_cq_ena = (uint64_t)inl_dev->cpt_cq_ena << 63;
lf_cfg->enable = 1;
lf_cfg->profile_id = profile_id;
lf_cfg->rx_inline_sa_base = (uintptr_t)nix->inb_sa_base[profile_id] | cpt_cq_ena;
diff --git a/drivers/common/cnxk/roc_npa.c b/drivers/common/cnxk/roc_npa.c
index 88e328105a..4a3e96a97a 100644
--- a/drivers/common/cnxk/roc_npa.c
+++ b/drivers/common/cnxk/roc_npa.c
@@ -1113,6 +1113,9 @@ roc_npa_pool_destroy(uint64_t aura_handle)
struct npa_lf *lf = idev_npa_obj_get();
int rc = 0, aura_id;
+ if (lf == NULL)
+ return NPA_ERR_DEVICE_NOT_BOUNDED;
+
plt_npa_dbg("lf=%p aura_handle=0x%" PRIx64, lf, aura_handle);
aura_id = roc_npa_aura_handle_to_aura(aura_handle);
diff --git a/drivers/common/cnxk/roc_npa_debug.c b/drivers/common/cnxk/roc_npa_debug.c
index e64696730f..f978be9642 100644
--- a/drivers/common/cnxk/roc_npa_debug.c
+++ b/drivers/common/cnxk/roc_npa_debug.c
@@ -283,6 +283,9 @@ roc_npa_ctx_dump(void)
if (lf->aura_attr[q].halo) {
aq->ctype = NPA_AQ_CTYPE_HALO;
rc = mbox_process_msg(mbox, (void *)&rsp_cn20k);
+ } else if (roc_model_is_cn20k()) {
+ aq->ctype = NPA_AQ_CTYPE_AURA;
+ rc = mbox_process_msg(mbox, (void *)&rsp_cn20k);
} else {
aq->ctype = NPA_AQ_CTYPE_AURA;
rc = mbox_process_msg(mbox, (void *)&rsp);
@@ -323,7 +326,10 @@ roc_npa_ctx_dump(void)
aq->ctype = NPA_AQ_CTYPE_POOL;
aq->op = NPA_AQ_INSTOP_READ;
- rc = mbox_process_msg(mbox, (void *)&rsp);
+ if (roc_model_is_cn20k())
+ rc = mbox_process_msg(mbox, (void *)&rsp_cn20k);
+ else
+ rc = mbox_process_msg(mbox, (void *)&rsp);
if (rc) {
plt_err("Failed to get pool(%d) context", q);
goto exit;
diff --git a/drivers/common/cnxk/roc_npc_utils.c b/drivers/common/cnxk/roc_npc_utils.c
index 3c05e46e1b..8e83b8662d 100644
--- a/drivers/common/cnxk/roc_npc_utils.c
+++ b/drivers/common/cnxk/roc_npc_utils.c
@@ -486,7 +486,7 @@ npc_process_ipv6_field_hash_o20k(const struct roc_npc_flow_item_ipv6 *ipv6_spec,
uint8_t hash_field[ROC_IPV6_ADDR_LEN];
struct npc_xtract_info *xinfo;
uint32_t hash = 0, mask;
- int intf, i, rc = 0;
+ int intf, i, hash_idx = 0, rc = 0;
memset(hash_field, 0, sizeof(hash_field));
@@ -505,14 +505,18 @@ npc_process_ipv6_field_hash_o20k(const struct roc_npc_flow_item_ipv6 *ipv6_spec,
if (rc == 0)
continue;
- rc = npc_ipv6_field_hash_get(pst->npc, (const uint32_t *)hash_field, intf, i,
- &hash);
+ if (hash_idx >= NPC_MAX_HASH)
+ break;
+
+ rc = npc_ipv6_field_hash_get(pst->npc, (const uint32_t *)hash_field, intf,
+ hash_idx, &hash);
if (rc)
return rc;
mask = GENMASK(31, 0);
memcpy(pst->mcam_mask + xinfo->key_off, (uint8_t *)&mask, 4);
memcpy(pst->mcam_data + xinfo->key_off, (uint8_t *)&hash, 4);
+ hash_idx++;
}
return 0;
diff --git a/drivers/common/cnxk/roc_ree.c b/drivers/common/cnxk/roc_ree.c
index b6392658c3..923d9251ad 100644
--- a/drivers/common/cnxk/roc_ree.c
+++ b/drivers/common/cnxk/roc_ree.c
@@ -592,14 +592,15 @@ roc_ree_dev_init(struct roc_ree_vf *vf)
vf->block_address = ree_get_blkaddr(dev);
if (!vf->block_address) {
plt_err("Could not determine block PF number");
- goto fail;
+ rc = -ENODEV;
+ goto dev_fini;
}
/* Get number of queues available on the device */
rc = roc_ree_available_queues_get(vf, &nb_queues);
if (rc) {
plt_err("Could not determine the number of queues available");
- goto fail;
+ goto dev_fini;
}
/* Don't exceed the limits set per VF */
@@ -607,7 +608,8 @@ roc_ree_dev_init(struct roc_ree_vf *vf)
if (nb_queues == 0) {
plt_err("No free queues available on the device");
- goto fail;
+ rc = -ENOSPC;
+ goto dev_fini;
}
vf->max_queues = nb_queues;
@@ -618,18 +620,23 @@ roc_ree_dev_init(struct roc_ree_vf *vf)
rc = roc_ree_max_matches_get(vf, &max_matches);
if (rc) {
plt_err("Could not determine the maximum matches supported");
- goto fail;
+ goto dev_fini;
}
/* Don't exceed the limits set per VF */
max_matches = RTE_MIN(max_matches, REE_MAX_MATCHES_PER_VF);
if (max_matches == 0) {
plt_err("Could not determine the maximum matches supported");
- goto fail;
+ rc = -EIO;
+ goto dev_fini;
}
vf->max_matches = max_matches;
plt_ree_dbg("Max matches supported by device: %d", vf->max_matches);
+
+ return 0;
+dev_fini:
+ dev_fini(dev, pci_dev);
fail:
return rc;
}
--
2.34.1
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH v2 17/22] common/cnxk: add auth key len check in inbound SA
2026-06-11 14:20 ` [PATCH v2 01/22] net/cnxk: update mbuf next field for multi segment Rahul Bhansali
` (14 preceding siblings ...)
2026-06-11 14:20 ` [PATCH v2 16/22] common/cnxk: fix Klocwork static analysis issues Rahul Bhansali
@ 2026-06-11 14:20 ` Rahul Bhansali
2026-06-11 14:20 ` [PATCH v2 18/22] common/cnxk: add FEC configuration support Rahul Bhansali
` (5 subsequent siblings)
21 siblings, 0 replies; 41+ messages in thread
From: Rahul Bhansali @ 2026-06-11 14:20 UTC (permalink / raw)
To: dev, Nithin Dabilpuram, Kiran Kumar K, Sunil Kumar Kori,
Satha Rao, Harman Kalra, Archana Muniganti, Vidya Sagar Velumuri,
Akhil Goyal
Cc: jerinj, Aarnav JP, stable
From: Aarnav JP <ajp@marvell.com>
Add auth key length validation before memcpy in
cnxk_on_ipsec_inb_sa_create() to prevent caller-provided
keys from overflowing fixed-size in-struct buffers and
corrupting adjacent fields.
Fixes: 532963b80707 ("crypto/cnxk: move IPsec SA creation to common")
Cc: stable@dpdk.org
Signed-off-by: Aarnav JP <ajp@marvell.com>
---
Changes in v2: No change.
drivers/common/cnxk/cnxk_security.c | 27 +++++++++++++++++++--------
1 file changed, 19 insertions(+), 8 deletions(-)
diff --git a/drivers/common/cnxk/cnxk_security.c b/drivers/common/cnxk/cnxk_security.c
index 6f46ad3276..228ff2781d 100644
--- a/drivers/common/cnxk/cnxk_security.c
+++ b/drivers/common/cnxk/cnxk_security.c
@@ -1199,22 +1199,33 @@ cnxk_on_ipsec_inb_sa_create(struct rte_security_ipsec_xform *ipsec,
break;
case RTE_CRYPTO_AUTH_MD5_HMAC:
case RTE_CRYPTO_AUTH_SHA1_HMAC:
- memcpy(in_sa->sha1_or_gcm.hmac_key, auth_key,
- auth_key_len);
- ctx_len = offsetof(struct roc_ie_on_inb_sa,
- sha1_or_gcm.selector);
+ if (auth_key_len > (int)sizeof(in_sa->sha1_or_gcm.hmac_key)) {
+ plt_err("Auth key len %d exceeds max %zu for algo %u", auth_key_len,
+ sizeof(in_sa->sha1_or_gcm.hmac_key), auth_xform->auth.algo);
+ return -EINVAL;
+ }
+ memcpy(in_sa->sha1_or_gcm.hmac_key, auth_key, auth_key_len);
+ ctx_len = offsetof(struct roc_ie_on_inb_sa, sha1_or_gcm.selector);
break;
case RTE_CRYPTO_AUTH_SHA256_HMAC:
case RTE_CRYPTO_AUTH_SHA384_HMAC:
case RTE_CRYPTO_AUTH_SHA512_HMAC:
+ if (auth_key_len > (int)sizeof(in_sa->sha2.hmac_key)) {
+ plt_err("Auth key len %d exceeds max %zu for algo %u", auth_key_len,
+ sizeof(in_sa->sha2.hmac_key), auth_xform->auth.algo);
+ return -EINVAL;
+ }
memcpy(in_sa->sha2.hmac_key, auth_key, auth_key_len);
- ctx_len = offsetof(struct roc_ie_on_inb_sa,
- sha2.selector);
+ ctx_len = offsetof(struct roc_ie_on_inb_sa, sha2.selector);
break;
case RTE_CRYPTO_AUTH_AES_XCBC_MAC:
+ if (auth_key_len > (int)sizeof(in_sa->aes_xcbc.key)) {
+ plt_err("Auth key len %d exceeds max %zu for algo %u", auth_key_len,
+ sizeof(in_sa->aes_xcbc.key), auth_xform->auth.algo);
+ return -EINVAL;
+ }
memcpy(in_sa->aes_xcbc.key, auth_key, auth_key_len);
- ctx_len = offsetof(struct roc_ie_on_inb_sa,
- aes_xcbc.selector);
+ ctx_len = offsetof(struct roc_ie_on_inb_sa, aes_xcbc.selector);
break;
default:
plt_err("Unsupported auth algorithm %u", auth_xform->auth.algo);
--
2.34.1
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH v2 18/22] common/cnxk: add FEC configuration support
2026-06-11 14:20 ` [PATCH v2 01/22] net/cnxk: update mbuf next field for multi segment Rahul Bhansali
` (15 preceding siblings ...)
2026-06-11 14:20 ` [PATCH v2 17/22] common/cnxk: add auth key len check in inbound SA Rahul Bhansali
@ 2026-06-11 14:20 ` Rahul Bhansali
2026-06-11 14:20 ` [PATCH v2 19/22] net/cnxk: add FEC get set and capability ops Rahul Bhansali
` (4 subsequent siblings)
21 siblings, 0 replies; 41+ messages in thread
From: Rahul Bhansali @ 2026-06-11 14:20 UTC (permalink / raw)
To: dev, Nithin Dabilpuram, Kiran Kumar K, Sunil Kumar Kori,
Satha Rao, Harman Kalra
Cc: jerinj, Rakesh Kudurumalla
From: Rakesh Kudurumalla <rkudurumalla@marvell.com>
Add ROC APIs for Forward Error Correction (FEC) configuration:
- roc_nix_mac_fec_set: Set FEC mode on the link
- roc_nix_mac_fec_supported_get: Query supported FEC modes
from firmware
These APIs use CGX mailbox messages to configure and query
FEC parameters on PF interfaces.
Signed-off-by: Rakesh Kudurumalla <rkudurumalla@marvell.com>
---
Changes in v2: No change.
drivers/common/cnxk/roc_nix.h | 2 +
drivers/common/cnxk/roc_nix_mac.c | 52 ++++++++++++++++++-
.../common/cnxk/roc_platform_base_symbols.c | 2 +
3 files changed, 55 insertions(+), 1 deletion(-)
diff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h
index 49ede85f9a..802519f5e8 100644
--- a/drivers/common/cnxk/roc_nix.h
+++ b/drivers/common/cnxk/roc_nix.h
@@ -975,6 +975,8 @@ int __roc_api roc_nix_mac_link_info_set(struct roc_nix *roc_nix,
struct roc_nix_link_info *link_info);
int __roc_api roc_nix_mac_link_info_get(struct roc_nix *roc_nix,
struct roc_nix_link_info *link_info);
+int __roc_api roc_nix_mac_fec_set(struct roc_nix *roc_nix, int fec);
+int __roc_api roc_nix_mac_fec_supported_get(struct roc_nix *roc_nix, uint64_t *supported_fec);
int __roc_api roc_nix_mac_mtu_set(struct roc_nix *roc_nix, uint16_t mtu);
int __roc_api roc_nix_mac_max_rx_len_set(struct roc_nix *roc_nix,
uint16_t maxlen);
diff --git a/drivers/common/cnxk/roc_nix_mac.c b/drivers/common/cnxk/roc_nix_mac.c
index 376ff48522..9440cad33d 100644
--- a/drivers/common/cnxk/roc_nix_mac.c
+++ b/drivers/common/cnxk/roc_nix_mac.c
@@ -257,6 +257,57 @@ roc_nix_mac_link_state_set(struct roc_nix *roc_nix, uint8_t up)
return rc;
}
+int
+roc_nix_mac_fec_set(struct roc_nix *roc_nix, int fec)
+{
+ struct nix *nix = roc_nix_to_nix_priv(roc_nix);
+ struct dev *dev = &nix->dev;
+ struct mbox *mbox = mbox_get(dev->mbox);
+ struct fec_mode *req;
+ int rc = -ENOSPC;
+
+ if (roc_nix_is_vf_or_sdp(roc_nix)) {
+ rc = NIX_ERR_OP_NOTSUP;
+ goto exit;
+ }
+
+ req = mbox_alloc_msg_cgx_set_fec_param(mbox);
+ if (req == NULL)
+ goto exit;
+ req->fec = fec;
+
+ rc = mbox_process(mbox);
+exit:
+ mbox_put(mbox);
+ return rc;
+}
+
+int
+roc_nix_mac_fec_supported_get(struct roc_nix *roc_nix, uint64_t *supported_fec)
+{
+ struct nix *nix = roc_nix_to_nix_priv(roc_nix);
+ struct dev *dev = &nix->dev;
+ struct mbox *mbox = mbox_get(dev->mbox);
+ struct cgx_fw_data *rsp = NULL;
+ int rc;
+
+ if (roc_nix_is_vf_or_sdp(roc_nix)) {
+ rc = NIX_ERR_OP_NOTSUP;
+ goto exit;
+ }
+
+ mbox_alloc_msg_cgx_get_aux_link_info(mbox);
+ rc = mbox_process_msg(mbox, (void *)&rsp);
+ if (rc)
+ goto exit;
+
+ *supported_fec = rsp->fwdata.supported_fec;
+ rc = 0;
+exit:
+ mbox_put(mbox);
+ return rc;
+}
+
int
roc_nix_mac_link_info_set(struct roc_nix *roc_nix,
struct roc_nix_link_info *link_info)
@@ -283,7 +334,6 @@ roc_nix_mac_link_info_set(struct roc_nix *roc_nix,
exit:
mbox_put(mbox);
return rc;
-
}
int
diff --git a/drivers/common/cnxk/roc_platform_base_symbols.c b/drivers/common/cnxk/roc_platform_base_symbols.c
index d1c9f2304d..ffae154788 100644
--- a/drivers/common/cnxk/roc_platform_base_symbols.c
+++ b/drivers/common/cnxk/roc_platform_base_symbols.c
@@ -316,6 +316,8 @@ RTE_EXPORT_INTERNAL_SYMBOL(roc_nix_mac_link_state_set)
RTE_EXPORT_INTERNAL_SYMBOL(roc_nix_mac_link_info_set)
RTE_EXPORT_INTERNAL_SYMBOL(roc_nix_mac_mtu_set)
RTE_EXPORT_INTERNAL_SYMBOL(roc_nix_mac_max_rx_len_set)
+RTE_EXPORT_INTERNAL_SYMBOL(roc_nix_mac_fec_set)
+RTE_EXPORT_INTERNAL_SYMBOL(roc_nix_mac_fec_supported_get)
RTE_EXPORT_INTERNAL_SYMBOL(roc_nix_mac_stats_reset)
RTE_EXPORT_INTERNAL_SYMBOL(roc_nix_mac_fwdata_get)
RTE_EXPORT_INTERNAL_SYMBOL(roc_nix_mac_link_cb_register)
--
2.34.1
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH v2 19/22] net/cnxk: add FEC get set and capability ops
2026-06-11 14:20 ` [PATCH v2 01/22] net/cnxk: update mbuf next field for multi segment Rahul Bhansali
` (16 preceding siblings ...)
2026-06-11 14:20 ` [PATCH v2 18/22] common/cnxk: add FEC configuration support Rahul Bhansali
@ 2026-06-11 14:20 ` Rahul Bhansali
2026-06-11 14:20 ` [PATCH v2 20/22] event/cnxk: fix Klocwork static analysis issues Rahul Bhansali
` (3 subsequent siblings)
21 siblings, 0 replies; 41+ messages in thread
From: Rahul Bhansali @ 2026-06-11 14:20 UTC (permalink / raw)
To: dev, Nithin Dabilpuram, Kiran Kumar K, Sunil Kumar Kori,
Satha Rao, Harman Kalra
Cc: jerinj, Rakesh Kudurumalla
From: Rakesh Kudurumalla <rkudurumalla@marvell.com>
Add ethdev FEC operations for cnxk NIX driver:
- fec_get_capability: Report supported FEC modes per speed.
If firmware provides supported FEC info, return actual
capabilities for current link speed. Otherwise, fall back
to a default capability table for common speeds.
- fec_get: Query current FEC mode from link info
- fec_set: Configure FEC mode on the link. AUTO mode
defaults to Reed-Solomon FEC.
Signed-off-by: Rakesh Kudurumalla <rkudurumalla@marvell.com>
---
Changes in v2: No change.
drivers/net/cnxk/cnxk_ethdev.c | 3 +
drivers/net/cnxk/cnxk_ethdev.h | 5 ++
drivers/net/cnxk/cnxk_ethdev_ops.c | 94 ++++++++++++++++++++++++++++++
3 files changed, 102 insertions(+)
diff --git a/drivers/net/cnxk/cnxk_ethdev.c b/drivers/net/cnxk/cnxk_ethdev.c
index a21e170229..f3f5035947 100644
--- a/drivers/net/cnxk/cnxk_ethdev.c
+++ b/drivers/net/cnxk/cnxk_ethdev.c
@@ -2137,6 +2137,9 @@ struct eth_dev_ops cnxk_eth_dev_ops = {
.cman_config_set = cnxk_nix_cman_config_set,
.cman_config_get = cnxk_nix_cman_config_get,
.eth_tx_descriptor_dump = cnxk_nix_tx_descriptor_dump,
+ .fec_get_capability = cnxk_nix_fec_get_capability,
+ .fec_get = cnxk_nix_fec_get,
+ .fec_set = cnxk_nix_fec_set,
};
void
diff --git a/drivers/net/cnxk/cnxk_ethdev.h b/drivers/net/cnxk/cnxk_ethdev.h
index 6686fdba31..9429a81ee8 100644
--- a/drivers/net/cnxk/cnxk_ethdev.h
+++ b/drivers/net/cnxk/cnxk_ethdev.h
@@ -667,6 +667,11 @@ int cnxk_nix_tm_mark_ip_dscp(struct rte_eth_dev *eth_dev, int mark_green,
int cnxk_nix_tx_descriptor_dump(const struct rte_eth_dev *eth_dev, uint16_t qid, uint16_t offset,
uint16_t num, FILE *file);
+/* FEC */
+int cnxk_nix_fec_get_capability(struct rte_eth_dev *eth_dev,
+ struct rte_eth_fec_capa *speed_fec_capa, unsigned int num);
+int cnxk_nix_fec_get(struct rte_eth_dev *eth_dev, uint32_t *fec_capa);
+int cnxk_nix_fec_set(struct rte_eth_dev *eth_dev, uint32_t fec_capa);
/* MTR */
int cnxk_nix_mtr_ops_get(struct rte_eth_dev *dev, void *ops);
diff --git a/drivers/net/cnxk/cnxk_ethdev_ops.c b/drivers/net/cnxk/cnxk_ethdev_ops.c
index 49e77e49a6..a45721d414 100644
--- a/drivers/net/cnxk/cnxk_ethdev_ops.c
+++ b/drivers/net/cnxk/cnxk_ethdev_ops.c
@@ -1414,3 +1414,97 @@ cnxk_nix_tx_descriptor_dump(const struct rte_eth_dev *eth_dev, uint16_t qid, uin
return roc_nix_sq_desc_dump(nix, qid, offset, num, file);
}
+
+static uint32_t
+cnxk_roc_fec_to_ethdev_capa(int roc_fec)
+{
+ switch (roc_fec) {
+ case ROC_FEC_BASER:
+ return RTE_ETH_FEC_MODE_CAPA_MASK(BASER);
+ case ROC_FEC_RS:
+ return RTE_ETH_FEC_MODE_CAPA_MASK(RS);
+ default:
+ return RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC);
+ }
+}
+
+static int
+cnxk_ethdev_fec_to_roc(uint32_t fec_capa)
+{
+ if (fec_capa & RTE_ETH_FEC_MODE_CAPA_MASK(RS))
+ return ROC_FEC_RS;
+ if (fec_capa & RTE_ETH_FEC_MODE_CAPA_MASK(BASER))
+ return ROC_FEC_BASER;
+ return ROC_FEC_NONE;
+}
+
+static uint32_t
+cnxk_fec_capa_from_supported(uint64_t supported_fec)
+{
+ uint32_t capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) | RTE_ETH_FEC_MODE_CAPA_MASK(AUTO);
+
+ if (supported_fec & (1ULL << ROC_FEC_BASER))
+ capa |= RTE_ETH_FEC_MODE_CAPA_MASK(BASER);
+ if (supported_fec & (1ULL << ROC_FEC_RS))
+ capa |= RTE_ETH_FEC_MODE_CAPA_MASK(RS);
+
+ return capa;
+}
+
+int
+cnxk_nix_fec_get_capability(struct rte_eth_dev *eth_dev, struct rte_eth_fec_capa *speed_fec_capa,
+ unsigned int num)
+{
+ struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
+ struct roc_nix *nix = &dev->nix;
+ struct roc_nix_link_info link_info;
+ uint64_t supported_fec = 0;
+ int rc;
+
+ rc = roc_nix_mac_fec_supported_get(nix, &supported_fec);
+ if (rc == 0 && supported_fec != 0) {
+ rc = roc_nix_mac_link_info_get(nix, &link_info);
+ if (rc)
+ return rc;
+
+ if (speed_fec_capa == NULL || num == 0)
+ return 1;
+
+ speed_fec_capa[0].speed = link_info.speed;
+ speed_fec_capa[0].capa = cnxk_fec_capa_from_supported(supported_fec);
+ return 1;
+ }
+
+ return rc;
+}
+
+int
+cnxk_nix_fec_get(struct rte_eth_dev *eth_dev, uint32_t *fec_capa)
+{
+ struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
+ struct roc_nix *nix = &dev->nix;
+ struct roc_nix_link_info link_info;
+ int rc;
+
+ rc = roc_nix_mac_link_info_get(nix, &link_info);
+ if (rc)
+ return rc;
+
+ *fec_capa = cnxk_roc_fec_to_ethdev_capa(link_info.fec);
+ return 0;
+}
+
+int
+cnxk_nix_fec_set(struct rte_eth_dev *eth_dev, uint32_t fec_capa)
+{
+ struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
+ struct roc_nix *nix = &dev->nix;
+ int roc_fec;
+
+ if (fec_capa & RTE_ETH_FEC_MODE_CAPA_MASK(AUTO))
+ roc_fec = ROC_FEC_RS;
+ else
+ roc_fec = cnxk_ethdev_fec_to_roc(fec_capa);
+
+ return roc_nix_mac_fec_set(nix, roc_fec);
+}
--
2.34.1
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH v2 20/22] event/cnxk: fix Klocwork static analysis issues
2026-06-11 14:20 ` [PATCH v2 01/22] net/cnxk: update mbuf next field for multi segment Rahul Bhansali
` (17 preceding siblings ...)
2026-06-11 14:20 ` [PATCH v2 19/22] net/cnxk: add FEC get set and capability ops Rahul Bhansali
@ 2026-06-11 14:20 ` Rahul Bhansali
2026-06-11 14:20 ` [PATCH v2 21/22] crypto/cnxk: enforce DES/3DES cipher key length Rahul Bhansali
` (2 subsequent siblings)
21 siblings, 0 replies; 41+ messages in thread
From: Rahul Bhansali @ 2026-06-11 14:20 UTC (permalink / raw)
To: dev, Pavan Nikhilesh, Shijith Thotton, Rakesh Kudurumalla,
Rahul Bhansali
Cc: jerinj, Aarnav JP, stable
From: Aarnav JP <ajp@marvell.com>
Cast uint16_t operands to uint64_t before bitwise OR with
uint64_t rx_offloads to fix operand size mismatches. Add NULL
check for bracket parser end pointer to prevent undefined
behavior from pointer comparison with NULL.
Fixes: 697883bcb0a8 ("event/cnxk: fix Rx timestamp handling")
Fixes: fe7ed2ebbf37 ("event/cnxk: set Rx offload flags")
Fixes: 38c2e3240ba8 ("event/cnxk: add option to control SSO HWGRP QoS")
Fixes: 8a3d58c189fd ("event/cnxk: add option to control timer adapters")
Cc: stable@dpdk.org
Signed-off-by: Aarnav JP <ajp@marvell.com>
---
Changes in v2: No change.
drivers/event/cnxk/cn10k_eventdev.c | 2 +-
drivers/event/cnxk/cnxk_eventdev.c | 2 +-
drivers/event/cnxk/cnxk_eventdev_adptr.c | 4 ++--
drivers/event/cnxk/cnxk_tim_evdev.c | 2 +-
4 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/event/cnxk/cn10k_eventdev.c b/drivers/event/cnxk/cn10k_eventdev.c
index 2e4b8aab92..62fea93b0b 100644
--- a/drivers/event/cnxk/cn10k_eventdev.c
+++ b/drivers/event/cnxk/cn10k_eventdev.c
@@ -660,7 +660,7 @@ cn10k_sso_tstamp_hdl_update(uint16_t port_id, uint16_t flags, bool ptp_en)
struct rte_eventdev *event_dev = cnxk_eth_dev->evdev_priv;
struct cnxk_sso_evdev *evdev = cnxk_sso_pmd_priv(event_dev);
- evdev->rx_offloads |= flags;
+ evdev->rx_offloads |= (uint64_t)flags;
if (ptp_en)
evdev->tstamp[port_id] = &cnxk_eth_dev->tstamp;
else
diff --git a/drivers/event/cnxk/cnxk_eventdev.c b/drivers/event/cnxk/cnxk_eventdev.c
index be6a487b59..4aa16f9026 100644
--- a/drivers/event/cnxk/cnxk_eventdev.c
+++ b/drivers/event/cnxk/cnxk_eventdev.c
@@ -566,7 +566,7 @@ parse_list(const char *value, void *opaque, param_parse_t fn)
else if (*s == ']')
end = s;
- if (start && start < end) {
+ if (start && end && start < end) {
*end = 0;
fn(start + 1, opaque);
s = end;
diff --git a/drivers/event/cnxk/cnxk_eventdev_adptr.c b/drivers/event/cnxk/cnxk_eventdev_adptr.c
index 8536dee5bf..5678e5d264 100644
--- a/drivers/event/cnxk/cnxk_eventdev_adptr.c
+++ b/drivers/event/cnxk/cnxk_eventdev_adptr.c
@@ -285,7 +285,7 @@ cnxk_sso_rx_adapter_queues_add(const struct rte_eventdev *event_dev,
/* Propagate force bp devarg */
cnxk_eth_dev->nix.force_rx_aura_bp = dev->force_ena_bp;
cnxk_sso_tstamp_cfg(eth_dev->data->port_id, eth_dev, dev);
- dev->rx_offloads |= cnxk_eth_dev->rx_offload_flags;
+ dev->rx_offloads |= (uint64_t)cnxk_eth_dev->rx_offload_flags;
return 0;
fail:
@@ -330,7 +330,7 @@ cnxk_sso_rx_adapter_start(const struct rte_eventdev *event_dev,
{
struct cnxk_eth_dev *cnxk_eth_dev = eth_dev->data->dev_private;
struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
- dev->rx_offloads |= cnxk_eth_dev->rx_offload_flags;
+ dev->rx_offloads |= (uint64_t)cnxk_eth_dev->rx_offload_flags;
return 0;
}
diff --git a/drivers/event/cnxk/cnxk_tim_evdev.c b/drivers/event/cnxk/cnxk_tim_evdev.c
index 994d1d1090..8cdb8a72dd 100644
--- a/drivers/event/cnxk/cnxk_tim_evdev.c
+++ b/drivers/event/cnxk/cnxk_tim_evdev.c
@@ -508,7 +508,7 @@ cnxk_tim_parse_ring_ctl_list(const char *value, void *opaque)
else
continue;
- if (start && start < end) {
+ if (start && end && start < end) {
*end = 0;
cnxk_tim_parse_ring_param(start + 1, opaque);
start = end;
--
2.34.1
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH v2 21/22] crypto/cnxk: enforce DES/3DES cipher key length
2026-06-11 14:20 ` [PATCH v2 01/22] net/cnxk: update mbuf next field for multi segment Rahul Bhansali
` (18 preceding siblings ...)
2026-06-11 14:20 ` [PATCH v2 20/22] event/cnxk: fix Klocwork static analysis issues Rahul Bhansali
@ 2026-06-11 14:20 ` Rahul Bhansali
2026-06-11 14:20 ` [PATCH v2 22/22] common/cnxk: fix TM link config selection in debug dump Rahul Bhansali
2026-06-11 15:26 ` [PATCH v2 01/22] net/cnxk: update mbuf next field for multi segment Stephen Hemminger
21 siblings, 0 replies; 41+ messages in thread
From: Rahul Bhansali @ 2026-06-11 14:20 UTC (permalink / raw)
To: dev, Ankur Dwivedi, Anoob Joseph, Tejasree Kondoj, Akhil Goyal,
Archana Muniganti
Cc: jerinj, Aarnav JP, stable
From: Aarnav JP <ajp@marvell.com>
Enforce exact key length match for DES/3DES algorithms
in fill_sess_cipher(), since these have fixed key sizes
(8 or 24 bytes). The existing check only enforced a lower
bound, allowing oversized keys to pass through.
Fixes: eb43e39851b8 ("crypto/cnxk: add cipher operation in session")
Cc: stable@dpdk.org
Signed-off-by: Aarnav JP <ajp@marvell.com>
---
Changes in v2: No change.
drivers/crypto/cnxk/cnxk_se.h | 11 ++++++++---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/drivers/crypto/cnxk/cnxk_se.h b/drivers/crypto/cnxk/cnxk_se.h
index 8dbf3e73c7..e2d7e10ec9 100644
--- a/drivers/crypto/cnxk/cnxk_se.h
+++ b/drivers/crypto/cnxk/cnxk_se.h
@@ -2297,9 +2297,14 @@ fill_sess_cipher(struct rte_crypto_sym_xform *xform, struct cnxk_se_sess *sess)
return -1;
}
- if (c_form->key.length < cipher_key_len) {
- plt_dp_err("Invalid cipher params keylen %u",
- c_form->key.length);
+ if (enc_type == ROC_SE_DES3_CBC || enc_type == ROC_SE_DES3_ECB ||
+ enc_type == ROC_SE_DES_DOCSISBPI) {
+ if (c_form->key.length != cipher_key_len) {
+ plt_dp_err("Invalid cipher params keylen %u", c_form->key.length);
+ return -1;
+ }
+ } else if (c_form->key.length < cipher_key_len) {
+ plt_dp_err("Invalid cipher params keylen %u", c_form->key.length);
return -1;
}
--
2.34.1
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH v2 22/22] common/cnxk: fix TM link config selection in debug dump
2026-06-11 14:20 ` [PATCH v2 01/22] net/cnxk: update mbuf next field for multi segment Rahul Bhansali
` (19 preceding siblings ...)
2026-06-11 14:20 ` [PATCH v2 21/22] crypto/cnxk: enforce DES/3DES cipher key length Rahul Bhansali
@ 2026-06-11 14:20 ` Rahul Bhansali
2026-06-11 15:26 ` [PATCH v2 01/22] net/cnxk: update mbuf next field for multi segment Stephen Hemminger
21 siblings, 0 replies; 41+ messages in thread
From: Rahul Bhansali @ 2026-06-11 14:20 UTC (permalink / raw)
To: dev, Nithin Dabilpuram, Kiran Kumar K, Sunil Kumar Kori,
Satha Rao, Harman Kalra
Cc: jerinj, stable
From: Satha Rao <skoteshwar@marvell.com>
Only emit the TM link configuration register when the configured TM
link level matches the hardware level being dumped, and use nix->tx_link
for the register and label so the dump reflects the active link.
Fixes: fcdef46b6698 ("common/cnxk: support NIX TM debug and misc utils")
Cc: stable@dpdk.org
Signed-off-by: Satha Rao <skoteshwar@marvell.com>
---
Changes in v2: No change.
drivers/common/cnxk/roc_nix_debug.c | 31 +++++++++++++++++++----------
1 file changed, 20 insertions(+), 11 deletions(-)
diff --git a/drivers/common/cnxk/roc_nix_debug.c b/drivers/common/cnxk/roc_nix_debug.c
index d4b2b86916..9c3bc8abe3 100644
--- a/drivers/common/cnxk/roc_nix_debug.c
+++ b/drivers/common/cnxk/roc_nix_debug.c
@@ -1150,7 +1150,7 @@ roc_nix_sq_dump(struct roc_nix_sq *sq, FILE *file)
};
static uint8_t
-nix_tm_reg_dump_prep(uint16_t hw_lvl, uint16_t schq, uint16_t link,
+nix_tm_reg_dump_prep(struct nix *nix, uint16_t hw_lvl, uint16_t schq,
uint64_t *reg, char regstr[][NIX_REG_NAME_SZ])
{
FILE *file = NULL;
@@ -1228,9 +1228,14 @@ nix_tm_reg_dump_prep(uint16_t hw_lvl, uint16_t schq, uint16_t link,
snprintf(regstr[k++], NIX_REG_NAME_SZ,
"NIX_AF_TL3[%u]_TOPOLOGY", schq);
- reg[k] = NIX_AF_TL3_TL2X_LINKX_CFG(schq, link);
- snprintf(regstr[k++], NIX_REG_NAME_SZ,
- "NIX_AF_TL3_TL2[%u]_LINK[%u]_CFG", schq, link);
+ /* Link configuration */
+ if (!nix->sdp_link &&
+ nix->tm_link_cfg_lvl == NIX_TXSCH_LVL_TL3) {
+ reg[k] = NIX_AF_TL3_TL2X_LINKX_CFG(schq, nix->tx_link);
+ snprintf(regstr[k++], NIX_REG_NAME_SZ,
+ "NIX_AF_TL3_TL2[%u]_LINK[%u]_CFG", schq,
+ nix->tx_link);
+ }
reg[k] = NIX_AF_TL3X_SCHEDULE(schq);
snprintf(regstr[k++], NIX_REG_NAME_SZ,
@@ -1261,9 +1266,14 @@ nix_tm_reg_dump_prep(uint16_t hw_lvl, uint16_t schq, uint16_t link,
snprintf(regstr[k++], NIX_REG_NAME_SZ,
"NIX_AF_TL2[%u]_TOPOLOGY", schq);
- reg[k] = NIX_AF_TL3_TL2X_LINKX_CFG(schq, link);
- snprintf(regstr[k++], NIX_REG_NAME_SZ,
- "NIX_AF_TL3_TL2[%u]_LINK[%u]_CFG", schq, link);
+ /* Link configuration */
+ if (!nix->sdp_link &&
+ nix->tm_link_cfg_lvl == NIX_TXSCH_LVL_TL2) {
+ reg[k] = NIX_AF_TL3_TL2X_LINKX_CFG(schq, nix->tx_link);
+ snprintf(regstr[k++], NIX_REG_NAME_SZ,
+ "NIX_AF_TL3_TL2[%u]_LINK[%u]_CFG", schq,
+ nix->tx_link);
+ }
reg[k] = NIX_AF_TL2X_SCHEDULE(schq);
snprintf(regstr[k++], NIX_REG_NAME_SZ,
@@ -1370,8 +1380,7 @@ nix_tm_dump_lvl(struct nix *nix, struct nix_tm_node_list *list, uint8_t hw_lvl)
root = node;
/* Dump registers only when HWRES is present */
- k = nix_tm_reg_dump_prep(node->hw_lvl, schq, nix->tx_link, reg,
- regstr);
+ k = nix_tm_reg_dump_prep(nix, node->hw_lvl, schq, reg, regstr);
if (!k)
continue;
@@ -1396,8 +1405,8 @@ nix_tm_dump_lvl(struct nix *nix, struct nix_tm_node_list *list, uint8_t hw_lvl)
/* Dump TL1 node data when root level is TL2 */
if (root && root->hw_lvl == NIX_TXSCH_LVL_TL2) {
- k = nix_tm_reg_dump_prep(NIX_TXSCH_LVL_TL1, root->parent_hw_id,
- nix->tx_link, reg, regstr);
+ k = nix_tm_reg_dump_prep(nix, NIX_TXSCH_LVL_TL1,
+ root->parent_hw_id, reg, regstr);
if (!k)
return;
--
2.34.1
^ permalink raw reply related [flat|nested] 41+ messages in thread
* Re: [PATCH v2 01/22] net/cnxk: update mbuf next field for multi segment
2026-06-11 14:20 ` [PATCH v2 01/22] net/cnxk: update mbuf next field for multi segment Rahul Bhansali
` (20 preceding siblings ...)
2026-06-11 14:20 ` [PATCH v2 22/22] common/cnxk: fix TM link config selection in debug dump Rahul Bhansali
@ 2026-06-11 15:26 ` Stephen Hemminger
21 siblings, 0 replies; 41+ messages in thread
From: Stephen Hemminger @ 2026-06-11 15:26 UTC (permalink / raw)
To: Rahul Bhansali
Cc: dev, Nithin Dabilpuram, Kiran Kumar K, Sunil Kumar Kori,
Satha Rao, Harman Kalra, jerinj
On Thu, 11 Jun 2026 19:50:08 +0530
Rahul Bhansali <rbhansali@marvell.com> wrote:
> As per the requirement of rte_mbuf_raw_reset_bulk(), the mbuf's
> 'next' and 'nb_segs' fields are required to be reset.
> This reset these field for multi-segment mbufs on cn9k platform.
>
> Signed-off-by: Rahul Bhansali <rbhansali@marvell.com>
Please put a cover letter on large multi-patch series in future.
The CI AI review doesn't look at original source and uses cost optimized
model (ie. is not that smart). Did a UI based review and it saw:
Reviewed the v2 series. Three issues, rest look good.
[06/22] net/cnxk: reserve memory for lookup mem at probe
Error: error path returns success. At the new check rc is still 0 from
the prior successful roc_nix_dev_init(). When
cnxk_nix_fastpath_lookup_mem_get() returns NULL, "goto dev_fini" falls
through to "return rc" with rc == 0, so dev init reports success and the
rc=%d message prints 0. Set rc before the jump:
if (!cnxk_nix_fastpath_lookup_mem_get()) {
plt_err("Failed to reserve lookup memory");
rc = -ENOMEM;
goto dev_fini;
}
[07/22] drivers: add support for devargs skip size
Warning: shared memzone freed while other ports still use it.
SKIP_SIZE_PKIND_MEMZONE is a single global memzone created once (lookup-
guarded) in roc_npc_init(), but roc_npc_fini() frees it unconditionally.
On a multi-port device the first port closed tears down the table the
other ports still read in roc_npc_skip_size_pkind_get() during inbound SA
creation; the lookup then returns NULL and skip-size pkind selection
silently stops working for the surviving ports. Refcount the memzone or
tie its lifetime to the common/inline layer instead of per-NPC fini.
[19/22] net/cnxk: add FEC get set and capability ops
Warning: feature not reflected in the features matrix. features.rst maps
the FEC feature to fec_get_capability/fec_get/fec_set, which this patch
implements, but doc/guides/nics/features/cnxk.ini is not updated with
"FEC = Y". The ops return NOTSUP on VF/SDP, so cnxk_vf.ini is correct as-
is. Add the matrix entry.
Note on [16/22]: the changes are good. Moving cpt_cq_ena inside the
"if (idev && idev->nix_inl_dev)" block fixes a NULL deref of inl_dev, and
cpt_cq_ena is initialized to 0 so the fall-through default is correct.
The roc_dev.c / roc_ree.c error-path rework fixes real leaks and wrong-
success returns.
Other patches reviewed with no issues.
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH 01/17] net/cnxk: update mbuf next field for multi segment
2026-06-11 7:32 [PATCH 01/17] net/cnxk: update mbuf next field for multi segment Rahul Bhansali
` (16 preceding siblings ...)
2026-06-11 14:20 ` [PATCH v2 01/22] net/cnxk: update mbuf next field for multi segment Rahul Bhansali
@ 2026-06-11 17:23 ` Stephen Hemminger
17 siblings, 0 replies; 41+ messages in thread
From: Stephen Hemminger @ 2026-06-11 17:23 UTC (permalink / raw)
To: Rahul Bhansali
Cc: dev, Nithin Dabilpuram, Kiran Kumar K, Sunil Kumar Kori,
Satha Rao, Harman Kalra, jerinj
On Thu, 11 Jun 2026 13:02:55 +0530
Rahul Bhansali <rbhansali@marvell.com> wrote:
> As per the requirement of rte_mbuf_raw_reset_bulk(), the mbuf's
> 'next' and 'nb_segs' fields are required to be reset.
> This reset these field for multi-segment mbufs on cn9k platform.
>
> Signed-off-by: Rahul Bhansali <rbhansali@marvell.com>
> ---
Please follow code submission guidelines for DPDK and use
cover letter and threading of replies.
https://doc.dpdk.org/guides/contributing/patches.html#sending-patches
What you get wrong:
- Please allow at least 24 hours to pass between posting patch revisions.
- Missing cover letter to explain patchset
- Use versions and in-reply-to. This keeps mail threads organized and
helps maintainers track in patchwork as well.
^ permalink raw reply [flat|nested] 41+ messages in thread
end of thread, other threads:[~2026-06-11 17:23 UTC | newest]
Thread overview: 41+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2026-06-11 7:32 [PATCH 01/17] net/cnxk: update mbuf next field for multi segment Rahul Bhansali
2026-06-11 7:32 ` [PATCH 02/17] common/cnxk: add API of SA valid for cn20k platform Rahul Bhansali
2026-06-11 7:32 ` [PATCH 03/17] common/cnxk: additional NIX SQ ctx fields prints Rahul Bhansali
2026-06-11 7:32 ` [PATCH 04/17] common/cnxk: update NIX irq handler Rahul Bhansali
2026-06-11 7:32 ` [PATCH 05/17] common/cnxk: configure LSO mask for single segments Rahul Bhansali
2026-06-11 7:33 ` [PATCH 06/17] net/cnxk: reserve memory for lookup mem at probe Rahul Bhansali
2026-06-11 7:33 ` [PATCH 07/17] drivers: add support for devargs skip size Rahul Bhansali
2026-06-11 7:33 ` [PATCH 08/17] net/cnxk: update inbound SA pkind for " Rahul Bhansali
2026-06-11 7:33 ` [PATCH 09/17] common/cnxk: fix cnxk xstats names Rahul Bhansali
2026-06-11 7:33 ` [PATCH 10/17] common/cnxk: fix event type for soft expiry Rahul Bhansali
2026-06-11 7:33 ` [PATCH 11/17] net/cnxk: enable CPT CQ by default for inline IPsec Rahul Bhansali
2026-06-11 7:33 ` [PATCH 12/17] net/cnxk: fix unsigned integer underflow in LSO calculation Rahul Bhansali
2026-06-11 7:33 ` [PATCH 13/17] net/cnxk: derive ethdev from SA for inbound CPT CQ events Rahul Bhansali
2026-06-11 7:33 ` [PATCH 14/17] net/cnxk: fix bitwise operand size mismatch in link mode Rahul Bhansali
2026-06-11 7:33 ` [PATCH 15/17] common/cnxk: add cipher key length check in key set Rahul Bhansali
2026-06-11 7:33 ` [PATCH 16/17] common/cnxk: fix Klocwork static analysis issues Rahul Bhansali
2026-06-11 7:33 ` [PATCH 17/17] common/cnxk: add auth key len check in inbound SA Rahul Bhansali
2026-06-11 14:20 ` [PATCH v2 01/22] net/cnxk: update mbuf next field for multi segment Rahul Bhansali
2026-06-11 14:20 ` [PATCH v2 02/22] common/cnxk: add API of SA valid for cn20k platform Rahul Bhansali
2026-06-11 14:20 ` [PATCH v2 03/22] common/cnxk: additional NIX SQ ctx fields prints Rahul Bhansali
2026-06-11 14:20 ` [PATCH v2 04/22] common/cnxk: update NIX irq handler Rahul Bhansali
2026-06-11 14:20 ` [PATCH v2 05/22] common/cnxk: configure LSO mask for single segments Rahul Bhansali
2026-06-11 14:20 ` [PATCH v2 06/22] net/cnxk: reserve memory for lookup mem at probe Rahul Bhansali
2026-06-11 14:20 ` [PATCH v2 07/22] drivers: add support for devargs skip size Rahul Bhansali
2026-06-11 14:20 ` [PATCH v2 08/22] net/cnxk: update inbound SA pkind for " Rahul Bhansali
2026-06-11 14:20 ` [PATCH v2 09/22] common/cnxk: fix cnxk xstats names Rahul Bhansali
2026-06-11 14:20 ` [PATCH v2 10/22] common/cnxk: fix event type for soft expiry Rahul Bhansali
2026-06-11 14:20 ` [PATCH v2 11/22] net/cnxk: enable CPT CQ by default for inline IPsec Rahul Bhansali
2026-06-11 14:20 ` [PATCH v2 12/22] net/cnxk: fix unsigned integer underflow in LSO calculation Rahul Bhansali
2026-06-11 14:20 ` [PATCH v2 13/22] net/cnxk: derive ethdev from SA for inbound CPT CQ events Rahul Bhansali
2026-06-11 14:20 ` [PATCH v2 14/22] net/cnxk: fix bitwise operand size mismatch in link mode Rahul Bhansali
2026-06-11 14:20 ` [PATCH v2 15/22] common/cnxk: add cipher key length check in key set Rahul Bhansali
2026-06-11 14:20 ` [PATCH v2 16/22] common/cnxk: fix Klocwork static analysis issues Rahul Bhansali
2026-06-11 14:20 ` [PATCH v2 17/22] common/cnxk: add auth key len check in inbound SA Rahul Bhansali
2026-06-11 14:20 ` [PATCH v2 18/22] common/cnxk: add FEC configuration support Rahul Bhansali
2026-06-11 14:20 ` [PATCH v2 19/22] net/cnxk: add FEC get set and capability ops Rahul Bhansali
2026-06-11 14:20 ` [PATCH v2 20/22] event/cnxk: fix Klocwork static analysis issues Rahul Bhansali
2026-06-11 14:20 ` [PATCH v2 21/22] crypto/cnxk: enforce DES/3DES cipher key length Rahul Bhansali
2026-06-11 14:20 ` [PATCH v2 22/22] common/cnxk: fix TM link config selection in debug dump Rahul Bhansali
2026-06-11 15:26 ` [PATCH v2 01/22] net/cnxk: update mbuf next field for multi segment Stephen Hemminger
2026-06-11 17:23 ` [PATCH 01/17] " Stephen Hemminger
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