From: Joshua Washington <joshwash@google.com>
To: Joshua Washington <joshwash@google.com>
Cc: dev@dpdk.org, Mark Blasko <blasko@google.com>
Subject: [PATCH 2/8] net/gve: rename doorbell BAR variable to be more generic
Date: Fri, 2 Oct 2026 19:51:34 -0700 [thread overview]
Message-ID: <20261003025142.1930363-3-joshwash@google.com> (raw)
In-Reply-To: <20261003025142.1930363-1-joshwash@google.com>
From: Mark Blasko <blasko@google.com>
Rename db_bar2 to db_bar in struct gve_priv and update queue doorbell
references across the driver. The doorbells will be in BAR 0 in GVE
Mailbox mode.
Signed-off-by: Mark Blasko <blasko@google.com>
Signed-off-by: Joshua Washington <joshwash@google.com>
---
drivers/net/gve/gve_ethdev.c | 2 +-
drivers/net/gve/gve_ethdev.h | 2 +-
drivers/net/gve/gve_rx.c | 4 ++--
drivers/net/gve/gve_rx_dqo.c | 4 ++--
drivers/net/gve/gve_tx.c | 4 ++--
drivers/net/gve/gve_tx_dqo.c | 4 ++--
6 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/net/gve/gve_ethdev.c b/drivers/net/gve/gve_ethdev.c
index 6704cc40b3..9cfdd03b9d 100644
--- a/drivers/net/gve/gve_ethdev.c
+++ b/drivers/net/gve/gve_ethdev.c
@@ -1717,7 +1717,7 @@ gve_dev_init(struct rte_eth_dev *eth_dev)
gve_write_version(®_bar->driver_version);
priv->reg_bar0 = reg_bar;
- priv->db_bar2 = db_bar;
+ priv->db_bar = db_bar;
priv->pci_dev = pci_dev;
priv->state_flags = 0x0;
diff --git a/drivers/net/gve/gve_ethdev.h b/drivers/net/gve/gve_ethdev.h
index f57e81dbc9..ef54b75c32 100644
--- a/drivers/net/gve/gve_ethdev.h
+++ b/drivers/net/gve/gve_ethdev.h
@@ -353,7 +353,7 @@ struct gve_priv {
uint32_t num_ntfy_blks; /* spilt between TX and RX so must be even */
struct gve_registers __iomem *reg_bar0; /* see gve_register.h */
- rte_be32_t __iomem *db_bar2; /* "array" of doorbells */
+ rte_be32_t __iomem *db_bar; /* "array" of doorbells */
struct rte_pci_device *pci_dev;
/* Admin queue - see gve_adminq.h*/
diff --git a/drivers/net/gve/gve_rx.c b/drivers/net/gve/gve_rx.c
index 2f542c7a66..ac2d174c67 100644
--- a/drivers/net/gve/gve_rx.c
+++ b/drivers/net/gve/gve_rx.c
@@ -349,7 +349,7 @@ gve_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_id,
rxq->is_gqi_qpl = hw->queue_format == GVE_GQI_QPL_FORMAT;
rxq->mpool = pool;
rxq->hw = hw;
- rxq->ntfy_addr = &hw->db_bar2[rte_be_to_cpu_32(hw->irq_dbs[rxq->ntfy_id].id)];
+ rxq->ntfy_addr = &hw->db_bar[rte_be_to_cpu_32(hw->irq_dbs[rxq->ntfy_id].id)];
mbuf_len =
rte_pktmbuf_data_room_size(rxq->mpool) - RTE_PKTMBUF_HEADROOM;
@@ -483,7 +483,7 @@ gve_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
rxq = dev->data->rx_queues[rx_queue_id];
- rxq->qrx_tail = &hw->db_bar2[rte_be_to_cpu_32(rxq->qres->db_index)];
+ rxq->qrx_tail = &hw->db_bar[rte_be_to_cpu_32(rxq->qres->db_index)];
rte_write32(rte_cpu_to_be_32(GVE_IRQ_MASK), rxq->ntfy_addr);
diff --git a/drivers/net/gve/gve_rx_dqo.c b/drivers/net/gve/gve_rx_dqo.c
index 81d7cacaf6..1fbe875954 100644
--- a/drivers/net/gve/gve_rx_dqo.c
+++ b/drivers/net/gve/gve_rx_dqo.c
@@ -370,7 +370,7 @@ gve_rx_queue_setup_dqo(struct rte_eth_dev *dev, uint16_t queue_id,
rxq->mpool = pool;
rxq->hw = hw;
- rxq->ntfy_addr = &hw->db_bar2[rte_be_to_cpu_32(hw->irq_dbs[rxq->ntfy_id].id)];
+ rxq->ntfy_addr = &hw->db_bar[rte_be_to_cpu_32(hw->irq_dbs[rxq->ntfy_id].id)];
mbuf_len =
rte_pktmbuf_data_room_size(rxq->mpool) - RTE_PKTMBUF_HEADROOM;
@@ -519,7 +519,7 @@ gve_rx_queue_start_dqo(struct rte_eth_dev *dev, uint16_t rx_queue_id)
rxq = dev->data->rx_queues[rx_queue_id];
- rxq->qrx_tail = &hw->db_bar2[rte_be_to_cpu_32(rxq->qres->db_index)];
+ rxq->qrx_tail = &hw->db_bar[rte_be_to_cpu_32(rxq->qres->db_index)];
rte_write32(rte_cpu_to_le_32(GVE_NO_INT_MODE_DQO |
GVE_ITR_NO_UPDATE_DQO),
diff --git a/drivers/net/gve/gve_tx.c b/drivers/net/gve/gve_tx.c
index 333e82b141..6398191b0a 100644
--- a/drivers/net/gve/gve_tx.c
+++ b/drivers/net/gve/gve_tx.c
@@ -606,7 +606,7 @@ gve_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_id, uint16_t nb_desc,
txq->ntfy_id = queue_id;
txq->is_gqi_qpl = hw->queue_format == GVE_GQI_QPL_FORMAT;
txq->hw = hw;
- txq->ntfy_addr = &hw->db_bar2[rte_be_to_cpu_32(hw->irq_dbs[txq->ntfy_id].id)];
+ txq->ntfy_addr = &hw->db_bar[rte_be_to_cpu_32(hw->irq_dbs[txq->ntfy_id].id)];
/* Allocate software ring */
txq->sw_ring = rte_zmalloc_socket("gve tx sw ring",
@@ -694,7 +694,7 @@ gve_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
txq = dev->data->tx_queues[tx_queue_id];
- txq->qtx_tail = &hw->db_bar2[rte_be_to_cpu_32(txq->qres->db_index)];
+ txq->qtx_tail = &hw->db_bar[rte_be_to_cpu_32(txq->qres->db_index)];
txq->qtx_head =
&hw->cnt_array[rte_be_to_cpu_32(txq->qres->counter_index)];
diff --git a/drivers/net/gve/gve_tx_dqo.c b/drivers/net/gve/gve_tx_dqo.c
index a44a20b139..fe8b883208 100644
--- a/drivers/net/gve/gve_tx_dqo.c
+++ b/drivers/net/gve/gve_tx_dqo.c
@@ -495,7 +495,7 @@ gve_tx_queue_setup_dqo(struct rte_eth_dev *dev, uint16_t queue_id,
txq->port_id = dev->data->port_id;
txq->ntfy_id = queue_id;
txq->hw = hw;
- txq->ntfy_addr = &hw->db_bar2[rte_be_to_cpu_32(hw->irq_dbs[txq->ntfy_id].id)];
+ txq->ntfy_addr = &hw->db_bar[rte_be_to_cpu_32(hw->irq_dbs[txq->ntfy_id].id)];
/* Allocate software ring */
sw_size = nb_desc;
@@ -575,7 +575,7 @@ gve_tx_queue_start_dqo(struct rte_eth_dev *dev, uint16_t tx_queue_id)
txq = dev->data->tx_queues[tx_queue_id];
- txq->qtx_tail = &hw->db_bar2[rte_be_to_cpu_32(txq->qres->db_index)];
+ txq->qtx_tail = &hw->db_bar[rte_be_to_cpu_32(txq->qres->db_index)];
txq->qtx_head =
&hw->cnt_array[rte_be_to_cpu_32(txq->qres->counter_index)];
--
2.56.0.rc1.315.gc6ed9934b7-goog
next prev parent reply other threads:[~2026-10-03 2:52 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-03 2:51 [PATCH 0/8] gve: precursor control plane changes before bare-metal support Joshua Washington
2026-10-03 2:51 ` [PATCH 1/8] net/gve: refactor ethdev for control ops interface Joshua Washington
2026-10-03 2:51 ` Joshua Washington [this message]
2026-10-03 2:51 ` [PATCH 3/8] net/gve: split default queue counts into Tx and Rx Joshua Washington
2026-10-03 2:51 ` [PATCH 4/8] net/gve: clean Tx queue directly in dqo Joshua Washington
2026-10-03 2:51 ` [PATCH 5/8] net/gve: update RSS config just after successful programming Joshua Washington
2026-10-03 2:51 ` [PATCH 6/8] net/gve: add RSS cache boolean flag Joshua Washington
2026-10-03 2:51 ` [PATCH 7/8] net/gve: fix RSS config memory leak on close Joshua Washington
2026-10-03 2:51 ` [PATCH 8/8] net/gve: refactor timestamp support to clock read type Joshua Washington
2026-10-03 16:29 ` [PATCH 0/8] gve: precursor control plane changes before bare-metal support Stephen Hemminger
2026-10-05 19:39 ` [PATCH v2 " Joshua Washington
2026-10-05 19:39 ` [PATCH v2 1/8] net/gve: refactor ethdev for control ops interface Joshua Washington
2026-10-05 19:39 ` [PATCH v2 2/8] net/gve: rename doorbell BAR variable to be more generic Joshua Washington
2026-10-05 19:39 ` [PATCH v2 3/8] net/gve: split default queue counts into Tx and Rx Joshua Washington
2026-10-05 19:39 ` [PATCH v2 4/8] net/gve: clean Tx queue directly in dqo Joshua Washington
2026-10-05 19:39 ` [PATCH v2 5/8] net/gve: update RSS config just after successful programming Joshua Washington
2026-10-05 19:39 ` [PATCH v2 6/8] net/gve: add RSS cache boolean flag Joshua Washington
2026-10-05 19:39 ` [PATCH v2 7/8] net/gve: fix RSS config memory leak on close Joshua Washington
2026-10-05 19:39 ` [PATCH v2 8/8] net/gve: refactor timestamp support to clock read type Joshua Washington
2026-10-06 14:19 ` [PATCH v2 0/8] gve: precursor control plane changes before bare-metal support Stephen Hemminger
2026-10-06 15:10 ` Stephen Hemminger
2026-10-07 20:11 ` Joshua Washington
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