From: Joshua Washington <joshwash@google.com>
To: Potnuri Bharat Teja <bharat@chelsio.com>
Cc: dev@dpdk.org, Joshua Washington <joshwash@google.com>
Subject: [PATCH v4 10/15] net/cxgbe: use common division round up macro
Date: Mon, 5 Oct 2026 19:30:46 -0700 [thread overview]
Message-ID: <20261006023053.2572501-11-joshwash@google.com> (raw)
In-Reply-To: <20261006023053.2572501-1-joshwash@google.com>
The RTE_DIV_ROUND_UP in rte_common.h makes DIV_ROUND_UP redundant.
Signed-off-by: Joshua Washington <joshwash@google.com>
Reviewed-by: Potnuri Bharat Teja <bharat@chelsio.com>
---
Changes in v3:
- Leave call sites in base/ alone and map DIV_ROUND_UP to
RTE_DIV_ROUND_UP in cxgbe_compat.h.
---
drivers/net/cxgbe/cxgbe_compat.h | 2 +-
drivers/net/cxgbe/cxgbe_filter.c | 6 +++---
drivers/net/cxgbe/cxgbe_ofld.h | 4 ++--
drivers/net/cxgbe/sge.c | 14 +++++++-------
4 files changed, 13 insertions(+), 13 deletions(-)
diff --git a/drivers/net/cxgbe/cxgbe_compat.h b/drivers/net/cxgbe/cxgbe_compat.h
index e74d476f6d..8c03a07fde 100644
--- a/drivers/net/cxgbe/cxgbe_compat.h
+++ b/drivers/net/cxgbe/cxgbe_compat.h
@@ -166,7 +166,7 @@ typedef uint64_t dma_addr_t;
typedef char *caddr_t;
#endif
-#define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))
+#define DIV_ROUND_UP(n, d) RTE_DIV_ROUND_UP(n, d)
#define DELAY(x) rte_delay_us(x)
#define udelay(x) DELAY(x)
#define msleep(x) DELAY(1000 * (x))
diff --git a/drivers/net/cxgbe/cxgbe_filter.c b/drivers/net/cxgbe/cxgbe_filter.c
index 5a7efe7a73..83f86a747a 100644
--- a/drivers/net/cxgbe/cxgbe_filter.c
+++ b/drivers/net/cxgbe/cxgbe_filter.c
@@ -219,7 +219,7 @@ static inline void mk_set_tcb_field_ulp(struct filter_entry *f,
txpkt->cmd_dest = cpu_to_be32(V_ULPTX_CMD(ULP_TX_PKT) |
V_ULP_TXPKT_DEST(0));
- txpkt->len = cpu_to_be32(DIV_ROUND_UP(sizeof(*req), 16));
+ txpkt->len = cpu_to_be32(RTE_DIV_ROUND_UP(sizeof(*req), 16));
sc->cmd_more = cpu_to_be32(V_ULPTX_CMD(ULP_TX_SC_IMM));
sc->len = cpu_to_be32(sizeof(*req) - sizeof(struct work_request_hdr));
OPCODE_TID(req) = cpu_to_be32(MK_OPCODE_TID(CPL_SET_TCB_FIELD, f->tid));
@@ -371,7 +371,7 @@ static void mk_abort_req_ulp(struct cpl_abort_req *abort_req,
txpkt->cmd_dest = cpu_to_be32(V_ULPTX_CMD(ULP_TX_PKT) |
V_ULP_TXPKT_DEST(0));
- txpkt->len = cpu_to_be32(DIV_ROUND_UP(sizeof(*abort_req), 16));
+ txpkt->len = cpu_to_be32(RTE_DIV_ROUND_UP(sizeof(*abort_req), 16));
sc->cmd_more = cpu_to_be32(V_ULPTX_CMD(ULP_TX_SC_IMM));
sc->len = cpu_to_be32(sizeof(*abort_req) -
sizeof(struct work_request_hdr));
@@ -395,7 +395,7 @@ static void mk_abort_rpl_ulp(struct cpl_abort_rpl *abort_rpl,
txpkt->cmd_dest = cpu_to_be32(V_ULPTX_CMD(ULP_TX_PKT) |
V_ULP_TXPKT_DEST(0));
- txpkt->len = cpu_to_be32(DIV_ROUND_UP(sizeof(*abort_rpl), 16));
+ txpkt->len = cpu_to_be32(RTE_DIV_ROUND_UP(sizeof(*abort_rpl), 16));
sc->cmd_more = cpu_to_be32(V_ULPTX_CMD(ULP_TX_SC_IMM));
sc->len = cpu_to_be32(sizeof(*abort_rpl) -
sizeof(struct work_request_hdr));
diff --git a/drivers/net/cxgbe/cxgbe_ofld.h b/drivers/net/cxgbe/cxgbe_ofld.h
index fd1e7d8002..ef56eef426 100644
--- a/drivers/net/cxgbe/cxgbe_ofld.h
+++ b/drivers/net/cxgbe/cxgbe_ofld.h
@@ -14,7 +14,7 @@
(w)->wr.wr_hi = cpu_to_be32(V_FW_WR_OP(FW_TP_WR) | \
V_FW_WR_IMMDLEN(sizeof(*w) - sizeof(w->wr))); \
(w)->wr.wr_mid = cpu_to_be32( \
- V_FW_WR_LEN16(DIV_ROUND_UP(sizeof(*w), 16)) | \
+ V_FW_WR_LEN16(RTE_DIV_ROUND_UP(sizeof(*w), 16)) | \
V_FW_WR_FLOWID(tid)); \
(w)->wr.wr_lo = cpu_to_be64(0); \
} while (0)
@@ -27,7 +27,7 @@
#define INIT_ULPTX_WR(w, wrlen, atomic, tid) do { \
(w)->wr.wr_hi = cpu_to_be32(V_FW_WR_OP(FW_ULPTX_WR) | \
V_FW_WR_ATOMIC(atomic)); \
- (w)->wr.wr_mid = cpu_to_be32(V_FW_WR_LEN16(DIV_ROUND_UP(wrlen, 16)) | \
+ (w)->wr.wr_mid = cpu_to_be32(V_FW_WR_LEN16(RTE_DIV_ROUND_UP(wrlen, 16)) | \
V_FW_WR_FLOWID(tid)); \
(w)->wr.wr_lo = cpu_to_be64(0); \
} while (0)
diff --git a/drivers/net/cxgbe/sge.c b/drivers/net/cxgbe/sge.c
index e9d45f24c4..eb25d80e33 100644
--- a/drivers/net/cxgbe/sge.c
+++ b/drivers/net/cxgbe/sge.c
@@ -459,7 +459,7 @@ static inline unsigned int sgl_len(unsigned int n)
*/
static inline unsigned int flits_to_desc(unsigned int n)
{
- return DIV_ROUND_UP(n, 8);
+ return RTE_DIV_ROUND_UP(n, 8);
}
/**
@@ -505,7 +505,7 @@ static inline unsigned int calc_tx_flits(const struct rte_mbuf *m,
hdrlen = is_eth_imm(m);
if (hdrlen)
- return DIV_ROUND_UP(m->pkt_len + hdrlen, sizeof(__be64));
+ return RTE_DIV_ROUND_UP(m->pkt_len + hdrlen, sizeof(__be64));
/*
* Otherwise, we're going to have to construct a Scatter gather list
@@ -779,7 +779,7 @@ static inline void ship_tx_pkt_coalesce_wr(struct adapter *adap,
wr = (void *)&q->desc[q->pidx];
vmwr = (void *)&q->desc[q->pidx];
- wr_mid = V_FW_WR_LEN16(DIV_ROUND_UP(q->coalesce.flits, 2));
+ wr_mid = V_FW_WR_LEN16(RTE_DIV_ROUND_UP(q->coalesce.flits, 2));
ndesc = flits_to_desc(q->coalesce.flits);
wr->equiq_to_len16 = htonl(wr_mid);
wr->plen = cpu_to_be16(q->coalesce.len);
@@ -866,7 +866,7 @@ static inline int should_tx_packet_coalesce(struct sge_eth_txq *txq,
/* If coalescing is on, the mbuf is added to a pkts WR */
if (q->coalesce.idx) {
- ndesc = DIV_ROUND_UP(q->coalesce.flits + flits, 8);
+ ndesc = RTE_DIV_ROUND_UP(q->coalesce.flits + flits, 8);
credits = txq_avail(q) - ndesc;
if (unlikely(wraps_around(q, ndesc)))
@@ -950,7 +950,7 @@ static inline int tx_do_packet_coalesce(struct sge_eth_txq *txq,
mc->cmd_dest = htonl(V_ULPTX_CMD(4) | V_ULP_TXPKT_DEST(0) |
V_ULP_TXPKT_FID(adap->sge.fw_evtq.cntxt_id) |
F_ULP_TXPKT_RO);
- mc->len = htonl(DIV_ROUND_UP(flits, 2));
+ mc->len = htonl(RTE_DIV_ROUND_UP(flits, 2));
sc_imm = (struct ulptx_idata *)(mc + 1);
sc_imm->cmd_more = htonl(V_ULPTX_CMD(ULP_TX_SC_IMM) |
F_ULP_TX_SC_MORE);
@@ -1116,7 +1116,7 @@ int t4_eth_xmit(struct sge_eth_txq *txq, struct rte_mbuf *mbuf,
goto out_free;
}
- wr_mid = V_FW_WR_LEN16(DIV_ROUND_UP(flits, 2));
+ wr_mid = V_FW_WR_LEN16(RTE_DIV_ROUND_UP(flits, 2));
if (Q_IDXDIFF(&txq->q, equeidx) >= 64) {
txq->q.equeidx = txq->q.pidx;
wr_mid |= F_FW_WR_EQUEQ;
@@ -1322,7 +1322,7 @@ static int ctrl_xmit(struct sge_ctrl_txq *q, struct rte_mbuf *mbuf)
}
reclaim_completed_tx_imm(&q->q);
- ndesc = DIV_ROUND_UP(mbuf->pkt_len, sizeof(struct tx_desc));
+ ndesc = RTE_DIV_ROUND_UP(mbuf->pkt_len, sizeof(struct tx_desc));
t4_os_lock(&q->ctrlq_lock);
q->full = txq_avail(&q->q) < ndesc ? 1 : 0;
--
2.56.0.rc1.315.gc6ed9934b7-goog
next prev parent reply other threads:[~2026-10-06 2:31 UTC|newest]
Thread overview: 69+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-12 22:30 [PATCH] eal: introduce division round up macro Joshua Washington
2026-08-13 1:29 ` Stephen Hemminger
2026-08-13 17:22 ` [PATCH v2 00/14] Introduce RTE_DIV_ROUND_UP Joshua Washington
2026-08-13 17:22 ` [PATCH v2 01/14] eal: introduce division round up macro Joshua Washington
2026-08-13 17:22 ` [PATCH v2 02/14] net/i40e: use common " Joshua Washington
2026-08-13 17:22 ` [PATCH v2 03/14] net/idpf: " Joshua Washington
2026-08-13 17:22 ` [PATCH v2 04/14] net/ice: " Joshua Washington
2026-08-13 17:22 ` [PATCH v2 05/14] net/qede: " Joshua Washington
2026-08-13 17:22 ` [PATCH v2 06/14] net/rnp: " Joshua Washington
2026-08-13 17:22 ` [PATCH v2 07/14] net/hns3: " Joshua Washington
2026-08-13 17:22 ` [PATCH v2 08/14] net/hinic: " Joshua Washington
2026-08-13 17:22 ` [PATCH v2 09/14] net/bnx2x: " Joshua Washington
2026-08-13 17:22 ` [PATCH v2 10/14] net/cxgbe: " Joshua Washington
2026-08-13 17:22 ` [PATCH v2 11/14] net/ena: " Joshua Washington
2026-08-13 17:22 ` [PATCH v2 12/14] raw/ifpga/base: " Joshua Washington
2026-08-13 17:22 ` [PATCH v2 13/14] drivers: " Joshua Washington
2026-08-13 17:22 ` [PATCH v2 14/14] app/procinfo: " Joshua Washington
2026-08-15 15:32 ` [PATCH v2 00/14] Introduce RTE_DIV_ROUND_UP Stephen Hemminger
2026-09-22 0:36 ` Stephen Hemminger
2026-09-23 1:07 ` [PATCH v3 00/16] " Joshua Washington
2026-09-23 1:07 ` [PATCH v3 01/16] eal: introduce division round up macro Joshua Washington
2026-09-23 7:29 ` Bruce Richardson
2026-09-24 7:47 ` fengchengwen
2026-09-23 1:07 ` [PATCH v3 02/16] net/i40e: use common " Joshua Washington
2026-09-23 7:30 ` Bruce Richardson
2026-09-23 7:35 ` Bruce Richardson
2026-09-29 22:44 ` Joshua Washington
2026-09-30 7:31 ` Bruce Richardson
2026-09-23 1:07 ` [PATCH v3 03/16] net/idpf: " Joshua Washington
2026-09-23 7:31 ` Bruce Richardson
2026-09-23 1:07 ` [PATCH v3 04/16] net/ice: " Joshua Washington
2026-09-23 7:31 ` Bruce Richardson
2026-09-23 1:07 ` [PATCH v3 05/16] net/qede: " Joshua Washington
2026-09-23 1:07 ` [PATCH v3 06/16] net/rnp: " Joshua Washington
2026-09-23 1:07 ` [PATCH v3 07/16] net/hns3: " Joshua Washington
2026-09-24 7:48 ` fengchengwen
2026-09-23 1:07 ` [PATCH v3 08/16] net/hinic: " Joshua Washington
2026-09-23 1:07 ` [PATCH v3 09/16] net/bnx2x: " Joshua Washington
2026-09-23 1:07 ` [PATCH v3 10/16] net/cxgbe: " Joshua Washington
2026-09-23 1:07 ` [PATCH v3 11/16] net/ena: " Joshua Washington
2026-09-23 1:07 ` [PATCH v3 12/16] raw/ifpga/base: " Joshua Washington
2026-09-23 1:07 ` [PATCH v3 13/16] net/nfp: " Joshua Washington
2026-09-23 1:07 ` [PATCH v3 14/16] app/procinfo: " Joshua Washington
2026-09-24 7:49 ` fengchengwen
2026-09-23 1:07 ` [PATCH v3 15/16] app/test: " Joshua Washington
2026-09-23 7:36 ` Bruce Richardson
2026-09-24 7:51 ` fengchengwen
2026-09-23 1:07 ` [PATCH v3 16/16] app/test-compress-perf: " Joshua Washington
2026-09-23 7:36 ` Bruce Richardson
2026-09-24 7:51 ` fengchengwen
2026-09-23 17:32 ` [PATCH v3 00/16] Introduce RTE_DIV_ROUND_UP Stephen Hemminger
2026-10-06 2:30 ` [PATCH v4 00/15] " Joshua Washington
2026-10-06 2:30 ` [PATCH v4 01/15] eal: introduce division round up macro Joshua Washington
2026-10-06 2:30 ` [PATCH v4 02/15] net/i40e: use common " Joshua Washington
2026-10-06 2:30 ` [PATCH v4 03/15] net/idpf: " Joshua Washington
2026-10-06 2:30 ` [PATCH v4 04/15] net/ice: " Joshua Washington
2026-10-06 2:30 ` [PATCH v4 05/15] net/qede: " Joshua Washington
2026-10-06 2:30 ` [PATCH v4 06/15] net/rnp: " Joshua Washington
2026-10-06 2:30 ` [PATCH v4 07/15] net/hns3: " Joshua Washington
2026-10-06 2:30 ` [PATCH v4 08/15] net/hinic: " Joshua Washington
2026-10-06 2:30 ` [PATCH v4 09/15] net/bnx2x: " Joshua Washington
2026-10-06 2:30 ` Joshua Washington [this message]
2026-10-06 2:30 ` [PATCH v4 11/15] net/ena: " Joshua Washington
2026-10-06 2:30 ` [PATCH v4 12/15] net/nfp: " Joshua Washington
2026-10-06 2:30 ` [PATCH v4 13/15] app/procinfo: " Joshua Washington
2026-10-06 2:30 ` [PATCH v4 14/15] app/test: " Joshua Washington
2026-10-06 2:30 ` [PATCH v4 15/15] app/test-compress-perf: " Joshua Washington
2026-10-06 16:38 ` [PATCH v4 00/15] Introduce RTE_DIV_ROUND_UP Stephen Hemminger
2026-10-07 20:21 ` Thomas Monjalon
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