[PATCH] eal/x86: fix LZCNT CPU feature bit

[PATCH] eal/x86: fix LZCNT CPU feature bit

[Yonghao Li]

LZCNT support is enumerated by CPUID.80000001H:ECX[5]. The current
definition checks ECX bit 4, which identifies CR8 legacy mode on AMD
processors and is reserved on Intel processors. As a result,
RTE_CPUFLAG_LZCNT can be reported incorrectly.

Check ECX bit 5 instead.

Fixes: af75078fece3 ("first public release")
Cc: stable@dpdk.org
Signed-off-by: Yonghao Li <cruselee1@live.cn>
---
 .mailmap                   | 1 +
 lib/eal/x86/rte_cpuflags.c | 2 +-
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/.mailmap b/.mailmap
index fcb3d1bb3f..fad671fbe9 100644
--- a/.mailmap
+++ b/.mailmap
@@ -1933,6 +1933,7 @@ Yong Wang <wang.yong19@zte.com.cn> <yongwang@vmware.com>
 Yong Xu <yong.xu@corigine.com>
 Yong Zhang <zhang.yong25@zte.com.cn>
 Yongfeng Wang <mannywang@tencent.com>
+Yonghao Li <cruselee1@live.cn>
 Yongji Xie <xieyongji@baidu.com>
 Yongjie Gu <yongjiex.gu@intel.com>
 Yongping Zhang <yongping.zhang@broadcom.com>
diff --git a/lib/eal/x86/rte_cpuflags.c b/lib/eal/x86/rte_cpuflags.c
index 5d1f352e04..80b71a3ce0 100644
--- a/lib/eal/x86/rte_cpuflags.c
+++ b/lib/eal/x86/rte_cpuflags.c
@@ -137,7 +137,7 @@ struct feature_entry rte_cpu_feature_table[] = {
 	FEAT_DEF(AVX512VP2INTERSECT, 0x00000007, 0, RTE_REG_EDX,  8)
 
 	FEAT_DEF(LAHF_SAHF, 0x80000001, 0, RTE_REG_ECX,  0)
-	FEAT_DEF(LZCNT, 0x80000001, 0, RTE_REG_ECX,  4)
+	FEAT_DEF(LZCNT, 0x80000001, 0, RTE_REG_ECX,  5)
 	FEAT_DEF(MONITORX, 0x80000001, 0, RTE_REG_ECX,  29)
 
 	FEAT_DEF(SYSCALL, 0x80000001, 0, RTE_REG_EDX, 11)
-- 
2.43.0

Re: [PATCH] eal/x86: fix LZCNT CPU feature bit

[David Marchand]

On Fri, 28 Aug 2026 at 22:33, Yonghao Li <cruselee1@live.cn> wrote:
>
> LZCNT support is enumerated by CPUID.80000001H:ECX[5]. The current
> definition checks ECX bit 4, which identifies CR8 legacy mode on AMD
> processors and is reserved on Intel processors. As a result,
> RTE_CPUFLAG_LZCNT can be reported incorrectly.
>
> Check ECX bit 5 instead.
>
> Fixes: af75078fece3 ("first public release")
> Cc: stable@dpdk.org
> Signed-off-by: Yonghao Li <cruselee1@live.cn>

This looks correct to me.
Acked-by: David Marchand <david.marchand@redhat.com>

Bruce, can I use a second pair of eyes?


-- 
David Marchand

Re: [PATCH] eal/x86: fix LZCNT CPU feature bit

[Bruce Richardson]

On Fri, Aug 28, 2026 at 09:32:52PM +0100, Yonghao Li wrote:
> LZCNT support is enumerated by CPUID.80000001H:ECX[5]. The current
> definition checks ECX bit 4, which identifies CR8 legacy mode on AMD
> processors and is reserved on Intel processors. As a result,
> RTE_CPUFLAG_LZCNT can be reported incorrectly.
> 
> Check ECX bit 5 instead.
> 
> Fixes: af75078fece3 ("first public release")
> Cc: stable@dpdk.org
> Signed-off-by: Yonghao Li <cruselee1@live.cn>
> ---
>  .mailmap                   | 1 +
>  lib/eal/x86/rte_cpuflags.c | 2 +-
>  2 files changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/.mailmap b/.mailmap
> index fcb3d1bb3f..fad671fbe9 100644
> --- a/.mailmap
> +++ b/.mailmap
> @@ -1933,6 +1933,7 @@ Yong Wang <wang.yong19@zte.com.cn> <yongwang@vmware.com>
>  Yong Xu <yong.xu@corigine.com>
>  Yong Zhang <zhang.yong25@zte.com.cn>
>  Yongfeng Wang <mannywang@tencent.com>
> +Yonghao Li <cruselee1@live.cn>
>  Yongji Xie <xieyongji@baidu.com>
>  Yongjie Gu <yongjiex.gu@intel.com>
>  Yongping Zhang <yongping.zhang@broadcom.com>
> diff --git a/lib/eal/x86/rte_cpuflags.c b/lib/eal/x86/rte_cpuflags.c
> index 5d1f352e04..80b71a3ce0 100644
> --- a/lib/eal/x86/rte_cpuflags.c
> +++ b/lib/eal/x86/rte_cpuflags.c
> @@ -137,7 +137,7 @@ struct feature_entry rte_cpu_feature_table[] = {
>  	FEAT_DEF(AVX512VP2INTERSECT, 0x00000007, 0, RTE_REG_EDX,  8)
>  
>  	FEAT_DEF(LAHF_SAHF, 0x80000001, 0, RTE_REG_ECX,  0)
> -	FEAT_DEF(LZCNT, 0x80000001, 0, RTE_REG_ECX,  4)
> +	FEAT_DEF(LZCNT, 0x80000001, 0, RTE_REG_ECX,  5)
>  	FEAT_DEF(MONITORX, 0x80000001, 0, RTE_REG_ECX,  29)
>  

Confirmed by checking Table 21-90 in the Intel SDM Vol 1 docs. Thanks for
catching this.

Acked-by: Bruce Richardson <bruce.richardson@intel.com>