From: Clint Taylor <clinton.a.taylor@intel.com>
To: Rodrigo Vivi <rodrigo.vivi@intel.com>, dri-devel@lists.freedesktop.org
Cc: mesa-dev@lists.freedesktop.org, intel-gfx@lists.freedesktop.org,
Anusha Srivatsa <anusha.srivatsa@intel.com>
Subject: Re: [PATCH 2/4] intel: Add Cannonlake PCI IDs for Y-skus.
Date: Thu, 29 Jun 2017 15:16:35 -0700 [thread overview]
Message-ID: <08073bb1-2c98-fb72-e277-146fe1e7b36d@intel.com> (raw)
In-Reply-To: <1498772058-902-2-git-send-email-rodrigo.vivi@intel.com>
Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com>
-Clint
On 06/29/2017 02:34 PM, Rodrigo Vivi wrote:
> By the Spec all CNL Y skus are 2+2, i.e. GT2.
>
> This is a copy of merged i915's
> commit 95578277cbdb ("drm/i915/cnl: Add Cannonlake PCI IDs for Y-skus.")
>
> v2: Add kernel commit id for reference.
>
> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Cc: Clinton Taylor <clinton.a.taylor@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> intel/intel_chipset.h | 16 +++++++++++++++-
> 1 file changed, 15 insertions(+), 1 deletion(-)
>
> diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h
> index e6b49d7..37579c6 100644
> --- a/intel/intel_chipset.h
> +++ b/intel/intel_chipset.h
> @@ -237,6 +237,12 @@
> #define PCI_CHIP_CANNONLAKE_U_GT2_1 0x5A5A
> #define PCI_CHIP_CANNONLAKE_U_GT2_2 0x5A42
> #define PCI_CHIP_CANNONLAKE_U_GT2_3 0x5A4A
> +#define PCI_CHIP_CANNONLAKE_Y_GT2_0 0x5A51
> +#define PCI_CHIP_CANNONLAKE_Y_GT2_1 0x5A59
> +#define PCI_CHIP_CANNONLAKE_Y_GT2_2 0x5A41
> +#define PCI_CHIP_CANNONLAKE_Y_GT2_3 0x5A49
> +#define PCI_CHIP_CANNONLAKE_Y_GT2_4 0x5A71
> +#define PCI_CHIP_CANNONLAKE_Y_GT2_5 0x5A79
>
> #define IS_MOBILE(devid) ((devid) == PCI_CHIP_I855_GM || \
> (devid) == PCI_CHIP_I915_GM || \
> @@ -501,12 +507,20 @@
> IS_GEN8(dev) || \
> IS_GEN9(dev))
>
> +#define IS_CNL_Y(devid) ((devid) == PCI_CHIP_CANNONLAKE_Y_GT2_0 || \
> + (devid) == PCI_CHIP_CANNONLAKE_Y_GT2_1 || \
> + (devid) == PCI_CHIP_CANNONLAKE_Y_GT2_2 || \
> + (devid) == PCI_CHIP_CANNONLAKE_Y_GT2_3 || \
> + (devid) == PCI_CHIP_CANNONLAKE_Y_GT2_4 || \
> + (devid) == PCI_CHIP_CANNONLAKE_Y_GT2_5)
> +
> #define IS_CNL_U(devid) ((devid) == PCI_CHIP_CANNONLAKE_U_GT2_0 || \
> (devid) == PCI_CHIP_CANNONLAKE_U_GT2_1 || \
> (devid) == PCI_CHIP_CANNONLAKE_U_GT2_2 || \
> (devid) == PCI_CHIP_CANNONLAKE_U_GT2_3)
>
> -#define IS_CANNONLAKE(devid) (IS_CNL_U(devid))
> +#define IS_CANNONLAKE(devid) (IS_CNL_U(devid) || \
> + IS_CNL_Y(devid))
>
> #define IS_GEN10(devid) (IS_CANNONLAKE(devid))
>
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next prev parent reply other threads:[~2017-06-29 22:16 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-06-29 21:34 [PATCH 1/4] intel: Add Cannonlake PCI IDs for U-skus Rodrigo Vivi
2017-06-29 21:34 ` [PATCH 2/4] intel: Add Cannonlake PCI IDs for Y-skus Rodrigo Vivi
2017-06-29 22:16 ` Clint Taylor [this message]
2017-06-30 15:37 ` [Mesa-dev] " Rodrigo Vivi
2017-06-29 21:34 ` [PATCH 3/4] intel/gen10: Add missed gen10 stuff Rodrigo Vivi
2017-06-29 21:34 ` [PATCH 4/4] intel: add GEN10 to IS_9XX Rodrigo Vivi
2017-06-29 22:15 ` [PATCH 1/4] intel: Add Cannonlake PCI IDs for U-skus Clint Taylor
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