* [PATCH 2/4] intel: Add Cannonlake PCI IDs for Y-skus.
2017-06-29 21:34 [PATCH 1/4] intel: Add Cannonlake PCI IDs for U-skus Rodrigo Vivi
@ 2017-06-29 21:34 ` Rodrigo Vivi
2017-06-29 22:16 ` Clint Taylor
2017-06-29 21:34 ` [PATCH 3/4] intel/gen10: Add missed gen10 stuff Rodrigo Vivi
` (2 subsequent siblings)
3 siblings, 1 reply; 7+ messages in thread
From: Rodrigo Vivi @ 2017-06-29 21:34 UTC (permalink / raw)
To: dri-devel
Cc: Clinton Taylor, mesa-dev, intel-gfx, Anusha Srivatsa,
Rodrigo Vivi
By the Spec all CNL Y skus are 2+2, i.e. GT2.
This is a copy of merged i915's
commit 95578277cbdb ("drm/i915/cnl: Add Cannonlake PCI IDs for Y-skus.")
v2: Add kernel commit id for reference.
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: Clinton Taylor <clinton.a.taylor@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
intel/intel_chipset.h | 16 +++++++++++++++-
1 file changed, 15 insertions(+), 1 deletion(-)
diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h
index e6b49d7..37579c6 100644
--- a/intel/intel_chipset.h
+++ b/intel/intel_chipset.h
@@ -237,6 +237,12 @@
#define PCI_CHIP_CANNONLAKE_U_GT2_1 0x5A5A
#define PCI_CHIP_CANNONLAKE_U_GT2_2 0x5A42
#define PCI_CHIP_CANNONLAKE_U_GT2_3 0x5A4A
+#define PCI_CHIP_CANNONLAKE_Y_GT2_0 0x5A51
+#define PCI_CHIP_CANNONLAKE_Y_GT2_1 0x5A59
+#define PCI_CHIP_CANNONLAKE_Y_GT2_2 0x5A41
+#define PCI_CHIP_CANNONLAKE_Y_GT2_3 0x5A49
+#define PCI_CHIP_CANNONLAKE_Y_GT2_4 0x5A71
+#define PCI_CHIP_CANNONLAKE_Y_GT2_5 0x5A79
#define IS_MOBILE(devid) ((devid) == PCI_CHIP_I855_GM || \
(devid) == PCI_CHIP_I915_GM || \
@@ -501,12 +507,20 @@
IS_GEN8(dev) || \
IS_GEN9(dev))
+#define IS_CNL_Y(devid) ((devid) == PCI_CHIP_CANNONLAKE_Y_GT2_0 || \
+ (devid) == PCI_CHIP_CANNONLAKE_Y_GT2_1 || \
+ (devid) == PCI_CHIP_CANNONLAKE_Y_GT2_2 || \
+ (devid) == PCI_CHIP_CANNONLAKE_Y_GT2_3 || \
+ (devid) == PCI_CHIP_CANNONLAKE_Y_GT2_4 || \
+ (devid) == PCI_CHIP_CANNONLAKE_Y_GT2_5)
+
#define IS_CNL_U(devid) ((devid) == PCI_CHIP_CANNONLAKE_U_GT2_0 || \
(devid) == PCI_CHIP_CANNONLAKE_U_GT2_1 || \
(devid) == PCI_CHIP_CANNONLAKE_U_GT2_2 || \
(devid) == PCI_CHIP_CANNONLAKE_U_GT2_3)
-#define IS_CANNONLAKE(devid) (IS_CNL_U(devid))
+#define IS_CANNONLAKE(devid) (IS_CNL_U(devid) || \
+ IS_CNL_Y(devid))
#define IS_GEN10(devid) (IS_CANNONLAKE(devid))
--
1.9.1
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https://lists.freedesktop.org/mailman/listinfo/mesa-dev
^ permalink raw reply related [flat|nested] 7+ messages in thread* Re: [PATCH 2/4] intel: Add Cannonlake PCI IDs for Y-skus.
2017-06-29 21:34 ` [PATCH 2/4] intel: Add Cannonlake PCI IDs for Y-skus Rodrigo Vivi
@ 2017-06-29 22:16 ` Clint Taylor
2017-06-30 15:37 ` [Mesa-dev] " Rodrigo Vivi
0 siblings, 1 reply; 7+ messages in thread
From: Clint Taylor @ 2017-06-29 22:16 UTC (permalink / raw)
To: Rodrigo Vivi, dri-devel; +Cc: mesa-dev, intel-gfx, Anusha Srivatsa
Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com>
-Clint
On 06/29/2017 02:34 PM, Rodrigo Vivi wrote:
> By the Spec all CNL Y skus are 2+2, i.e. GT2.
>
> This is a copy of merged i915's
> commit 95578277cbdb ("drm/i915/cnl: Add Cannonlake PCI IDs for Y-skus.")
>
> v2: Add kernel commit id for reference.
>
> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Cc: Clinton Taylor <clinton.a.taylor@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> intel/intel_chipset.h | 16 +++++++++++++++-
> 1 file changed, 15 insertions(+), 1 deletion(-)
>
> diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h
> index e6b49d7..37579c6 100644
> --- a/intel/intel_chipset.h
> +++ b/intel/intel_chipset.h
> @@ -237,6 +237,12 @@
> #define PCI_CHIP_CANNONLAKE_U_GT2_1 0x5A5A
> #define PCI_CHIP_CANNONLAKE_U_GT2_2 0x5A42
> #define PCI_CHIP_CANNONLAKE_U_GT2_3 0x5A4A
> +#define PCI_CHIP_CANNONLAKE_Y_GT2_0 0x5A51
> +#define PCI_CHIP_CANNONLAKE_Y_GT2_1 0x5A59
> +#define PCI_CHIP_CANNONLAKE_Y_GT2_2 0x5A41
> +#define PCI_CHIP_CANNONLAKE_Y_GT2_3 0x5A49
> +#define PCI_CHIP_CANNONLAKE_Y_GT2_4 0x5A71
> +#define PCI_CHIP_CANNONLAKE_Y_GT2_5 0x5A79
>
> #define IS_MOBILE(devid) ((devid) == PCI_CHIP_I855_GM || \
> (devid) == PCI_CHIP_I915_GM || \
> @@ -501,12 +507,20 @@
> IS_GEN8(dev) || \
> IS_GEN9(dev))
>
> +#define IS_CNL_Y(devid) ((devid) == PCI_CHIP_CANNONLAKE_Y_GT2_0 || \
> + (devid) == PCI_CHIP_CANNONLAKE_Y_GT2_1 || \
> + (devid) == PCI_CHIP_CANNONLAKE_Y_GT2_2 || \
> + (devid) == PCI_CHIP_CANNONLAKE_Y_GT2_3 || \
> + (devid) == PCI_CHIP_CANNONLAKE_Y_GT2_4 || \
> + (devid) == PCI_CHIP_CANNONLAKE_Y_GT2_5)
> +
> #define IS_CNL_U(devid) ((devid) == PCI_CHIP_CANNONLAKE_U_GT2_0 || \
> (devid) == PCI_CHIP_CANNONLAKE_U_GT2_1 || \
> (devid) == PCI_CHIP_CANNONLAKE_U_GT2_2 || \
> (devid) == PCI_CHIP_CANNONLAKE_U_GT2_3)
>
> -#define IS_CANNONLAKE(devid) (IS_CNL_U(devid))
> +#define IS_CANNONLAKE(devid) (IS_CNL_U(devid) || \
> + IS_CNL_Y(devid))
>
> #define IS_GEN10(devid) (IS_CANNONLAKE(devid))
>
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https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 7+ messages in thread* Re: [Mesa-dev] [PATCH 2/4] intel: Add Cannonlake PCI IDs for Y-skus.
2017-06-29 22:16 ` Clint Taylor
@ 2017-06-30 15:37 ` Rodrigo Vivi
0 siblings, 0 replies; 7+ messages in thread
From: Rodrigo Vivi @ 2017-06-30 15:37 UTC (permalink / raw)
To: Clint Taylor; +Cc: mesa-dev, intel-gfx, DRI mailing list, Rodrigo Vivi
series pushed to libdrm. Thanks for the review.
On Thu, Jun 29, 2017 at 3:16 PM, Clint Taylor
<clinton.a.taylor@intel.com> wrote:
> Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com>
>
> -Clint
>
>
>
>
> On 06/29/2017 02:34 PM, Rodrigo Vivi wrote:
>>
>> By the Spec all CNL Y skus are 2+2, i.e. GT2.
>>
>> This is a copy of merged i915's
>> commit 95578277cbdb ("drm/i915/cnl: Add Cannonlake PCI IDs for Y-skus.")
>>
>> v2: Add kernel commit id for reference.
>>
>> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
>> Cc: Clinton Taylor <clinton.a.taylor@intel.com>
>> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>> ---
>> intel/intel_chipset.h | 16 +++++++++++++++-
>> 1 file changed, 15 insertions(+), 1 deletion(-)
>>
>> diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h
>> index e6b49d7..37579c6 100644
>> --- a/intel/intel_chipset.h
>> +++ b/intel/intel_chipset.h
>> @@ -237,6 +237,12 @@
>> #define PCI_CHIP_CANNONLAKE_U_GT2_1 0x5A5A
>> #define PCI_CHIP_CANNONLAKE_U_GT2_2 0x5A42
>> #define PCI_CHIP_CANNONLAKE_U_GT2_3 0x5A4A
>> +#define PCI_CHIP_CANNONLAKE_Y_GT2_0 0x5A51
>> +#define PCI_CHIP_CANNONLAKE_Y_GT2_1 0x5A59
>> +#define PCI_CHIP_CANNONLAKE_Y_GT2_2 0x5A41
>> +#define PCI_CHIP_CANNONLAKE_Y_GT2_3 0x5A49
>> +#define PCI_CHIP_CANNONLAKE_Y_GT2_4 0x5A71
>> +#define PCI_CHIP_CANNONLAKE_Y_GT2_5 0x5A79
>> #define IS_MOBILE(devid) ((devid) == PCI_CHIP_I855_GM || \
>> (devid) == PCI_CHIP_I915_GM || \
>> @@ -501,12 +507,20 @@
>> IS_GEN8(dev) || \
>> IS_GEN9(dev))
>> +#define IS_CNL_Y(devid) ((devid) ==
>> PCI_CHIP_CANNONLAKE_Y_GT2_0 || \
>> + (devid) == PCI_CHIP_CANNONLAKE_Y_GT2_1 ||
>> \
>> + (devid) == PCI_CHIP_CANNONLAKE_Y_GT2_2 ||
>> \
>> + (devid) == PCI_CHIP_CANNONLAKE_Y_GT2_3 ||
>> \
>> + (devid) == PCI_CHIP_CANNONLAKE_Y_GT2_4 ||
>> \
>> + (devid) == PCI_CHIP_CANNONLAKE_Y_GT2_5)
>> +
>> #define IS_CNL_U(devid) ((devid) ==
>> PCI_CHIP_CANNONLAKE_U_GT2_0 || \
>> (devid) == PCI_CHIP_CANNONLAKE_U_GT2_1 ||
>> \
>> (devid) == PCI_CHIP_CANNONLAKE_U_GT2_2 ||
>> \
>> (devid) == PCI_CHIP_CANNONLAKE_U_GT2_3)
>> -#define IS_CANNONLAKE(devid) (IS_CNL_U(devid))
>> +#define IS_CANNONLAKE(devid) (IS_CNL_U(devid) || \
>> + IS_CNL_Y(devid))
>> #define IS_GEN10(devid) (IS_CANNONLAKE(devid))
>>
>
>
> _______________________________________________
> mesa-dev mailing list
> mesa-dev@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/mesa-dev
--
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH 3/4] intel/gen10: Add missed gen10 stuff
2017-06-29 21:34 [PATCH 1/4] intel: Add Cannonlake PCI IDs for U-skus Rodrigo Vivi
2017-06-29 21:34 ` [PATCH 2/4] intel: Add Cannonlake PCI IDs for Y-skus Rodrigo Vivi
@ 2017-06-29 21:34 ` Rodrigo Vivi
2017-06-29 21:34 ` [PATCH 4/4] intel: add GEN10 to IS_9XX Rodrigo Vivi
2017-06-29 22:15 ` [PATCH 1/4] intel: Add Cannonlake PCI IDs for U-skus Clint Taylor
3 siblings, 0 replies; 7+ messages in thread
From: Rodrigo Vivi @ 2017-06-29 21:34 UTC (permalink / raw)
To: dri-devel; +Cc: mesa-dev, intel-gfx, Ben Widawsky, Ben Widawsky
From: Ben Widawsky <ben@bwidawsk.net>
This got lost on rebase, I believe
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
---
intel/intel_bufmgr_gem.c | 2 ++
intel/intel_decode.c | 4 +++-
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c
index 45a26da..71f140f 100644
--- a/intel/intel_bufmgr_gem.c
+++ b/intel/intel_bufmgr_gem.c
@@ -3662,6 +3662,8 @@ drm_intel_bufmgr_gem_init(int fd, int batch_size)
bufmgr_gem->gen = 8;
else if (IS_GEN9(bufmgr_gem->pci_device))
bufmgr_gem->gen = 9;
+ else if (IS_GEN10(bufmgr_gem->pci_device))
+ bufmgr_gem->gen = 10;
else {
free(bufmgr_gem);
bufmgr_gem = NULL;
diff --git a/intel/intel_decode.c b/intel/intel_decode.c
index 2721ffd..3a81500 100644
--- a/intel/intel_decode.c
+++ b/intel/intel_decode.c
@@ -3827,7 +3827,9 @@ drm_intel_decode_context_alloc(uint32_t devid)
ctx->devid = devid;
ctx->out = stdout;
- if (IS_GEN9(devid))
+ if (IS_GEN10(devid))
+ ctx->gen = 10;
+ else if (IS_GEN9(devid))
ctx->gen = 9;
else if (IS_GEN8(devid))
ctx->gen = 8;
--
1.9.1
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^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH 4/4] intel: add GEN10 to IS_9XX.
2017-06-29 21:34 [PATCH 1/4] intel: Add Cannonlake PCI IDs for U-skus Rodrigo Vivi
2017-06-29 21:34 ` [PATCH 2/4] intel: Add Cannonlake PCI IDs for Y-skus Rodrigo Vivi
2017-06-29 21:34 ` [PATCH 3/4] intel/gen10: Add missed gen10 stuff Rodrigo Vivi
@ 2017-06-29 21:34 ` Rodrigo Vivi
2017-06-29 22:15 ` [PATCH 1/4] intel: Add Cannonlake PCI IDs for U-skus Clint Taylor
3 siblings, 0 replies; 7+ messages in thread
From: Rodrigo Vivi @ 2017-06-29 21:34 UTC (permalink / raw)
To: dri-devel; +Cc: mesa-dev, intel-gfx, Paulo Zanoni
From: Paulo Zanoni <paulo.r.zanoni@intel.com>
As far as I understand, IS_9XX should return true for it.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
intel/intel_chipset.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h
index 37579c6..770d21f 100644
--- a/intel/intel_chipset.h
+++ b/intel/intel_chipset.h
@@ -505,7 +505,8 @@
IS_GEN6(dev) || \
IS_GEN7(dev) || \
IS_GEN8(dev) || \
- IS_GEN9(dev))
+ IS_GEN9(dev) || \
+ IS_GEN10(dev))
#define IS_CNL_Y(devid) ((devid) == PCI_CHIP_CANNONLAKE_Y_GT2_0 || \
(devid) == PCI_CHIP_CANNONLAKE_Y_GT2_1 || \
--
1.9.1
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH 1/4] intel: Add Cannonlake PCI IDs for U-skus.
2017-06-29 21:34 [PATCH 1/4] intel: Add Cannonlake PCI IDs for U-skus Rodrigo Vivi
` (2 preceding siblings ...)
2017-06-29 21:34 ` [PATCH 4/4] intel: add GEN10 to IS_9XX Rodrigo Vivi
@ 2017-06-29 22:15 ` Clint Taylor
3 siblings, 0 replies; 7+ messages in thread
From: Clint Taylor @ 2017-06-29 22:15 UTC (permalink / raw)
To: Rodrigo Vivi, dri-devel; +Cc: mesa-dev, intel-gfx, Anusha Srivatsa
Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com>
-Clint
On 06/29/2017 02:34 PM, Rodrigo Vivi wrote:
> Platform enabling and its power-on are organized in different
> skus (U x Y x S x H, etc). So instead of organizing it in
> GT1 x GT2 x GT3 let's also use the platform sku.
>
> This is a copy of merged i915's
> commit e918d79a5d0a ("drm/i915/cnl: Add Cannonlake PCI IDs for U-skus.")
>
> v2: Remove PCI IDs for SKU not mentioned in spec.
> v3: Add kernel commit id for reference.
>
> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Cc: Clinton Taylor <clinton.a.taylor@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> intel/intel_chipset.h | 13 +++++++++++++
> 1 file changed, 13 insertions(+)
>
> diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h
> index 891b50f..e6b49d7 100644
> --- a/intel/intel_chipset.h
> +++ b/intel/intel_chipset.h
> @@ -233,6 +233,11 @@
> #define PCI_CHIP_COFFEELAKE_U_GT3_3 0x3EA7
> #define PCI_CHIP_COFFEELAKE_U_GT3_4 0x3EA8
>
> +#define PCI_CHIP_CANNONLAKE_U_GT2_0 0x5A52
> +#define PCI_CHIP_CANNONLAKE_U_GT2_1 0x5A5A
> +#define PCI_CHIP_CANNONLAKE_U_GT2_2 0x5A42
> +#define PCI_CHIP_CANNONLAKE_U_GT2_3 0x5A4A
> +
> #define IS_MOBILE(devid) ((devid) == PCI_CHIP_I855_GM || \
> (devid) == PCI_CHIP_I915_GM || \
> (devid) == PCI_CHIP_I945_GM || \
> @@ -496,5 +501,13 @@
> IS_GEN8(dev) || \
> IS_GEN9(dev))
>
> +#define IS_CNL_U(devid) ((devid) == PCI_CHIP_CANNONLAKE_U_GT2_0 || \
> + (devid) == PCI_CHIP_CANNONLAKE_U_GT2_1 || \
> + (devid) == PCI_CHIP_CANNONLAKE_U_GT2_2 || \
> + (devid) == PCI_CHIP_CANNONLAKE_U_GT2_3)
> +
> +#define IS_CANNONLAKE(devid) (IS_CNL_U(devid))
> +
> +#define IS_GEN10(devid) (IS_CANNONLAKE(devid))
>
> #endif /* _INTEL_CHIPSET_H */
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^ permalink raw reply [flat|nested] 7+ messages in thread