From: Chris Wilson <chris@chris-wilson.co.uk>
To: Intel Graphics Development <intel-gfx@lists.freedesktop.org>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>,
stable@kernel.org,
DRI Development <dri-devel@lists.freedesktop.org>
Subject: Re: [PATCH] drm/i915: properly compute dp dithering for user-created modes
Date: Tue, 10 Apr 2012 09:14:32 +0100 [thread overview]
Message-ID: <1334045675_341262@CP5-2952> (raw)
In-Reply-To: <1334043199-21493-1-git-send-email-daniel.vetter@ffwll.ch>
On Tue, 10 Apr 2012 09:33:19 +0200, Daniel Vetter <daniel.vetter@ffwll.ch> wrote:
> We've only computed whether we need to fall back to 6bpc due to dp
> link bandwidth constrains in mode_valid, but not mode_fixup. Under
> various circumstances X likes to create new modes which then lack
> proper 6bpc flags (if required), resulting in mode_fixup failures and
> ultimately black screens.
>
> This is hopefully fixes the last regression fallout of the dp
> bandwidth fixes.
Based on my reading, this still leaves the issue of depth > 24 modes as
the upper bandwidth required is calculated on the presumption of
depth == 24, but the divider set to the fb depth in the normal case.
> The likely culprit for this regression is
>
> commit 3d794f87238f74d80e78a7611c7fbde8a54c85c2
> Author: Keith Packard <keithp@keithp.com>
> Date: Wed Jan 25 08:16:25 2012 -0800
>
> drm/i915: Force explicit bpp selection for intel_dp_link_required
>
> Reported-and-tested-by: Brice Goglin <Brice.Goglin@ens-lyon.org>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=48170
> Cc: stable@kernel.org
> Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> ---
> drivers/gpu/drm/i915/intel_dp.c | 49 +++++++++++++++++++++++++++-----------
> 1 files changed, 35 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 110552f..065c26d 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -219,14 +219,38 @@ intel_dp_max_data_rate(int max_link_clock, int max_lanes)
> return (max_link_clock * max_lanes * 8) / 10;
> }
>
> +static bool
> +intel_dp_adjust_dithering(struct intel_dp *intel_dp,
> + struct drm_display_mode *mode,
> + struct drm_display_mode *adjusted_mode)
> +{
> + int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp));
> + int max_lanes = intel_dp_max_lane_count(intel_dp);
> + int max_rate, mode_rate;
> +
> + mode_rate = intel_dp_link_required(mode->clock, 24);
> + max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
> +
> + if (mode_rate > max_rate) {
> + mode_rate = intel_dp_link_required(mode->clock, 18);
Cut'n'paste bad whitespace.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
next prev parent reply other threads:[~2012-04-10 8:14 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-04-10 7:33 [PATCH] drm/i915: properly compute dp dithering for user-created modes Daniel Vetter
2012-04-10 8:14 ` Chris Wilson [this message]
2012-04-10 8:36 ` Daniel Vetter
2012-04-10 8:42 ` Daniel Vetter
2012-04-10 13:46 ` Adam Jackson
2012-04-10 17:23 ` Daniel Vetter
2012-04-10 17:26 ` [Intel-gfx] " Keith Packard
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