* [next][PATCH 1/3] drm/radeon/hdmi: separate evergreen code
2012-05-06 15:29 [next][PATCH 0/3] drm/radeon/hdmi: separate Evergreen, update modesetting Rafał Miłecki
@ 2012-05-06 15:29 ` Rafał Miłecki
2012-05-06 15:29 ` [next][PATCH 2/3] drm/radeon/hdmi: update modesetting Rafał Miłecki
2012-05-06 15:29 ` [next][PATCH 3/3] drm/radeon/hdmi: fix some coding style Rafał Miłecki
2 siblings, 0 replies; 9+ messages in thread
From: Rafał Miłecki @ 2012-05-06 15:29 UTC (permalink / raw)
To: Dave Airlie, dri-devel; +Cc: Christian König
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
---
drivers/gpu/drm/radeon/Makefile | 5 +-
drivers/gpu/drm/radeon/atombios_encoders.c | 5 +-
drivers/gpu/drm/radeon/evergreen_hdmi.c | 187 ++++++++++++++++++++++++++++
drivers/gpu/drm/radeon/r600_hdmi.c | 9 +--
drivers/gpu/drm/radeon/radeon.h | 8 ++
5 files changed, 203 insertions(+), 11 deletions(-)
create mode 100644 drivers/gpu/drm/radeon/evergreen_hdmi.c
diff --git a/drivers/gpu/drm/radeon/Makefile b/drivers/gpu/drm/radeon/Makefile
index 9d83729..1efb6eb 100644
--- a/drivers/gpu/drm/radeon/Makefile
+++ b/drivers/gpu/drm/radeon/Makefile
@@ -70,8 +70,9 @@ radeon-y += radeon_device.o radeon_asic.o radeon_kms.o \
r200.o radeon_legacy_tv.o r600_cs.o r600_blit.o r600_blit_shaders.o \
r600_blit_kms.o radeon_pm.o atombios_dp.o r600_audio.o r600_hdmi.o \
evergreen.o evergreen_cs.o evergreen_blit_shaders.o evergreen_blit_kms.o \
- radeon_trace_points.o ni.o cayman_blit_shaders.o atombios_encoders.o \
- radeon_semaphore.o radeon_sa.o atombios_i2c.o si.o si_blit_shaders.o
+ evergreen_hdmi.o radeon_trace_points.o ni.o cayman_blit_shaders.o \
+ atombios_encoders.o radeon_semaphore.o radeon_sa.o atombios_i2c.o si.o \
+ si_blit_shaders.o
radeon-$(CONFIG_COMPAT) += radeon_ioc32.o
radeon-$(CONFIG_VGA_SWITCHEROO) += radeon_atpx_handler.o
diff --git a/drivers/gpu/drm/radeon/atombios_encoders.c b/drivers/gpu/drm/radeon/atombios_encoders.c
index 2d39f99..1ed0ff5 100644
--- a/drivers/gpu/drm/radeon/atombios_encoders.c
+++ b/drivers/gpu/drm/radeon/atombios_encoders.c
@@ -1926,7 +1926,10 @@ radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
r600_hdmi_enable(encoder);
- r600_hdmi_setmode(encoder, adjusted_mode);
+ if (ASIC_IS_DCE4(rdev))
+ evergreen_hdmi_setmode(encoder, adjusted_mode);
+ else
+ r600_hdmi_setmode(encoder, adjusted_mode);
}
}
diff --git a/drivers/gpu/drm/radeon/evergreen_hdmi.c b/drivers/gpu/drm/radeon/evergreen_hdmi.c
new file mode 100644
index 0000000..d3d00b5
--- /dev/null
+++ b/drivers/gpu/drm/radeon/evergreen_hdmi.c
@@ -0,0 +1,187 @@
+/*
+ * Copyright 2008 Advanced Micro Devices, Inc.
+ * Copyright 2008 Red Hat Inc.
+ * Copyright 2009 Christian König.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Christian König
+ * Rafał Miłecki
+ */
+#include "drmP.h"
+#include "radeon_drm.h"
+#include "radeon.h"
+#include "radeon_asic.h"
+#include "evergreend.h"
+#include "atom.h"
+
+/*
+ * update the N and CTS parameters for a given pixel clock rate
+ */
+static void evergreen_hdmi_update_ACR(struct drm_encoder *encoder, uint32_t clock)
+{
+ struct drm_device *dev = encoder->dev;
+ struct radeon_device *rdev = dev->dev_private;
+ struct radeon_hdmi_acr acr = r600_hdmi_acr(clock);
+ uint32_t offset = to_radeon_encoder(encoder)->hdmi_offset;
+
+ WREG32(HDMI_ACR_32_0 + offset, HDMI_ACR_CTS_32(acr.cts_32khz));
+ WREG32(HDMI_ACR_32_1 + offset, acr.n_32khz);
+
+ WREG32(HDMI_ACR_44_0 + offset, HDMI_ACR_CTS_44(acr.cts_44_1khz));
+ WREG32(HDMI_ACR_44_1 + offset, acr.n_44_1khz);
+
+ WREG32(HDMI_ACR_48_0 + offset, HDMI_ACR_CTS_48(acr.cts_48khz));
+ WREG32(HDMI_ACR_48_1 + offset, acr.n_48khz);
+}
+
+/*
+ * calculate the crc for a given info frame
+ */
+static void evergreen_hdmi_infoframe_checksum(uint8_t packetType,
+ uint8_t versionNumber,
+ uint8_t length,
+ uint8_t *frame)
+{
+ int i;
+ frame[0] = packetType + versionNumber + length;
+ for (i = 1; i <= length; i++)
+ frame[0] += frame[i];
+ frame[0] = 0x100 - frame[0];
+}
+
+/*
+ * build a HDMI Video Info Frame
+ */
+static void evergreen_hdmi_videoinfoframe(
+ struct drm_encoder *encoder,
+ uint8_t color_format,
+ int active_information_present,
+ uint8_t active_format_aspect_ratio,
+ uint8_t scan_information,
+ uint8_t colorimetry,
+ uint8_t ex_colorimetry,
+ uint8_t quantization,
+ int ITC,
+ uint8_t picture_aspect_ratio,
+ uint8_t video_format_identification,
+ uint8_t pixel_repetition,
+ uint8_t non_uniform_picture_scaling,
+ uint8_t bar_info_data_valid,
+ uint16_t top_bar,
+ uint16_t bottom_bar,
+ uint16_t left_bar,
+ uint16_t right_bar
+)
+{
+ struct drm_device *dev = encoder->dev;
+ struct radeon_device *rdev = dev->dev_private;
+ uint32_t offset = to_radeon_encoder(encoder)->hdmi_offset;
+
+ uint8_t frame[14];
+
+ frame[0x0] = 0;
+ frame[0x1] =
+ (scan_information & 0x3) |
+ ((bar_info_data_valid & 0x3) << 2) |
+ ((active_information_present & 0x1) << 4) |
+ ((color_format & 0x3) << 5);
+ frame[0x2] =
+ (active_format_aspect_ratio & 0xF) |
+ ((picture_aspect_ratio & 0x3) << 4) |
+ ((colorimetry & 0x3) << 6);
+ frame[0x3] =
+ (non_uniform_picture_scaling & 0x3) |
+ ((quantization & 0x3) << 2) |
+ ((ex_colorimetry & 0x7) << 4) |
+ ((ITC & 0x1) << 7);
+ frame[0x4] = (video_format_identification & 0x7F);
+ frame[0x5] = (pixel_repetition & 0xF);
+ frame[0x6] = (top_bar & 0xFF);
+ frame[0x7] = (top_bar >> 8);
+ frame[0x8] = (bottom_bar & 0xFF);
+ frame[0x9] = (bottom_bar >> 8);
+ frame[0xA] = (left_bar & 0xFF);
+ frame[0xB] = (left_bar >> 8);
+ frame[0xC] = (right_bar & 0xFF);
+ frame[0xD] = (right_bar >> 8);
+
+ evergreen_hdmi_infoframe_checksum(0x82, 0x02, 0x0D, frame);
+ /* Our header values (type, version, length) should be alright, Intel
+ * is using the same. Checksum function also seems to be OK, it works
+ * fine for audio infoframe. However calculated value is always lower
+ * by 2 in comparison to fglrx. It breaks displaying anything in case
+ * of TVs that strictly check the checksum. Hack it manually here to
+ * workaround this issue. */
+ frame[0x0] += 2;
+
+ WREG32(AFMT_AVI_INFO0 + offset,
+ frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
+ WREG32(AFMT_AVI_INFO1 + offset,
+ frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
+ WREG32(AFMT_AVI_INFO2 + offset,
+ frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
+ WREG32(AFMT_AVI_INFO3 + offset,
+ frame[0xC] | (frame[0xD] << 8));
+}
+
+/*
+ * update the info frames with the data from the current display mode
+ */
+void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode)
+{
+ struct drm_device *dev = encoder->dev;
+ struct radeon_device *rdev = dev->dev_private;
+ uint32_t offset = to_radeon_encoder(encoder)->hdmi_offset;
+
+ if (ASIC_IS_DCE5(rdev))
+ return;
+
+ if (!to_radeon_encoder(encoder)->hdmi_enabled)
+ return;
+
+ r600_audio_set_clock(encoder, mode->clock);
+
+ WREG32(AFMT_AUDIO_CRC_CONTROL + offset, 0x1000);
+ WREG32(HDMI_GC + offset, 0x0);
+
+ /* Send audio packets */
+ WREG32_P(AFMT_AUDIO_PACKET_CONTROL + offset,
+ AFMT_AUDIO_SAMPLE_SEND, ~AFMT_AUDIO_SAMPLE_SEND);
+
+ WREG32(HDMI_ACR_PACKET_CONTROL + offset, 0x1000);
+
+ evergreen_hdmi_update_ACR(encoder, mode->clock);
+
+ WREG32(HDMI_INFOFRAME_CONTROL0 + offset, 0x13);
+
+ WREG32(HDMI_INFOFRAME_CONTROL1 + offset, 0x202);
+
+ evergreen_hdmi_videoinfoframe(encoder, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0);
+
+ /* it's unknown what these bits do excatly, but it's indeed quite useful for debugging */
+ WREG32(AFMT_RAMP_CONTROL0 + offset, 0x00FFFFFF);
+ WREG32(AFMT_RAMP_CONTROL1 + offset, 0x007FFFFF);
+ WREG32(AFMT_RAMP_CONTROL2 + offset, 0x00000001);
+ WREG32(AFMT_RAMP_CONTROL3 + offset, 0x00000001);
+
+ /* audio packets per line, does anyone know how to calc this ? */
+ WREG32_P(AFMT_AUDIO_PACKET_CONTROL + offset, 0x00040000, ~0x001F0000);
+}
diff --git a/drivers/gpu/drm/radeon/r600_hdmi.c b/drivers/gpu/drm/radeon/r600_hdmi.c
index 0319619..5a2305e 100644
--- a/drivers/gpu/drm/radeon/r600_hdmi.c
+++ b/drivers/gpu/drm/radeon/r600_hdmi.c
@@ -328,10 +328,7 @@ void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mod
WREG32(HDMI0_GC + offset, 0x0);
/* Send audio packets */
- if (ASIC_IS_DCE4(rdev))
- WREG32_P(0x74fc + offset,
- AFMT_AUDIO_SAMPLE_SEND, ~AFMT_AUDIO_SAMPLE_SEND);
- else if (ASIC_IS_DCE32(rdev))
+ if (ASIC_IS_DCE32(rdev))
WREG32_P(AFMT_AUDIO_PACKET_CONTROL + offset,
AFMT_AUDIO_SAMPLE_SEND, ~AFMT_AUDIO_SAMPLE_SEND);
else
@@ -458,10 +455,6 @@ static void r600_hdmi_assign_block(struct drm_encoder *encoder)
return;
}
radeon_encoder->hdmi_offset = eg_offsets[dig->dig_encoder];
- /* Temp hack for Evergreen until we split r600_hdmi.c
- * Evergreen first block is 0x7030 instead of 0x7400.
- */
- radeon_encoder->hdmi_offset -= 0x3d0;
} else if (ASIC_IS_DCE3(rdev)) {
radeon_encoder->hdmi_offset = dig->dig_encoder ?
DCE3_HDMI_OFFSET1 : DCE3_HDMI_OFFSET0;
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 71779c8..a7ae4ca 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -1874,10 +1874,18 @@ struct radeon_hdmi_acr {
};
+extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock);
+
extern void r600_hdmi_enable(struct drm_encoder *encoder);
extern void r600_hdmi_disable(struct drm_encoder *encoder);
extern void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
+/*
+ * evergreen functions used by radeon_encoder.c
+ */
+
+extern void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
+
extern int ni_init_microcode(struct radeon_device *rdev);
extern int ni_mc_load_microcode(struct radeon_device *rdev);
--
1.7.7
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 9+ messages in thread* [next][PATCH 2/3] drm/radeon/hdmi: update modesetting
2012-05-06 15:29 [next][PATCH 0/3] drm/radeon/hdmi: separate Evergreen, update modesetting Rafał Miłecki
2012-05-06 15:29 ` [next][PATCH 1/3] drm/radeon/hdmi: separate evergreen code Rafał Miłecki
@ 2012-05-06 15:29 ` Rafał Miłecki
2012-05-26 8:22 ` Rafał Miłecki
2012-05-06 15:29 ` [next][PATCH 3/3] drm/radeon/hdmi: fix some coding style Rafał Miłecki
2 siblings, 1 reply; 9+ messages in thread
From: Rafał Miłecki @ 2012-05-06 15:29 UTC (permalink / raw)
To: Dave Airlie, dri-devel; +Cc: Christian König
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
---
drivers/gpu/drm/radeon/evergreen_hdmi.c | 43 ++++++++++++++++++------
drivers/gpu/drm/radeon/r600_hdmi.c | 53 ++++++++++++++++++++++---------
2 files changed, 70 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/radeon/evergreen_hdmi.c b/drivers/gpu/drm/radeon/evergreen_hdmi.c
index d3d00b5..9037bff 100644
--- a/drivers/gpu/drm/radeon/evergreen_hdmi.c
+++ b/drivers/gpu/drm/radeon/evergreen_hdmi.c
@@ -158,30 +158,51 @@ void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode
r600_audio_set_clock(encoder, mode->clock);
+ WREG32(HDMI_VBI_PACKET_CONTROL + offset,
+ HDMI_NULL_SEND); /* send null packets when required */
+
WREG32(AFMT_AUDIO_CRC_CONTROL + offset, 0x1000);
- WREG32(HDMI_GC + offset, 0x0);
- /* Send audio packets */
- WREG32_P(AFMT_AUDIO_PACKET_CONTROL + offset,
- AFMT_AUDIO_SAMPLE_SEND, ~AFMT_AUDIO_SAMPLE_SEND);
+ WREG32(HDMI_AUDIO_PACKET_CONTROL + offset,
+ HDMI_AUDIO_DELAY_EN(1) | /* set the default audio delay */
+ HDMI_AUDIO_PACKETS_PER_LINE(3)); /* should be suffient for all audio modes and small enough for all hblanks */
- WREG32(HDMI_ACR_PACKET_CONTROL + offset, 0x1000);
+ WREG32(AFMT_AUDIO_PACKET_CONTROL + offset,
+ AFMT_AUDIO_SAMPLE_SEND | /* send audio packets */
+ AFMT_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */
- evergreen_hdmi_update_ACR(encoder, mode->clock);
+ WREG32(HDMI_ACR_PACKET_CONTROL + offset,
+ HDMI_ACR_AUTO_SEND | /* allow hw to sent ACR packets when required */
+ HDMI_ACR_SOURCE); /* select SW CTS value */
+
+ WREG32(HDMI_VBI_PACKET_CONTROL + offset,
+ HDMI_NULL_SEND | /* send null packets when required */
+ HDMI_GC_SEND | /* send general control packets */
+ HDMI_GC_CONT); /* send general control packets every frame */
+
+ WREG32(HDMI_INFOFRAME_CONTROL0 + offset,
+ HDMI_AVI_INFO_SEND | /* enable AVI info frames */
+ HDMI_AVI_INFO_CONT | /* send AVI info frames every frame/field */
+ HDMI_AUDIO_INFO_SEND | /* enable audio info frames (frames won't be set until audio is enabled) */
+ HDMI_AUDIO_INFO_CONT); /* required for audio info values to be updated */
+
+ WREG32(AFMT_INFOFRAME_CONTROL0 + offset,
+ AFMT_AUDIO_INFO_UPDATE); /* required for audio info values to be updated */
- WREG32(HDMI_INFOFRAME_CONTROL0 + offset, 0x13);
+ WREG32(HDMI_INFOFRAME_CONTROL1 + offset,
+ HDMI_AVI_INFO_LINE(2) | /* anything other than 0 */
+ HDMI_AUDIO_INFO_LINE(2)); /* anything other than 0 */
- WREG32(HDMI_INFOFRAME_CONTROL1 + offset, 0x202);
+ WREG32(HDMI_GC + offset, 0); /* unset HDMI_GC_AVMUTE */
evergreen_hdmi_videoinfoframe(encoder, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0);
+ evergreen_hdmi_update_ACR(encoder, mode->clock);
+
/* it's unknown what these bits do excatly, but it's indeed quite useful for debugging */
WREG32(AFMT_RAMP_CONTROL0 + offset, 0x00FFFFFF);
WREG32(AFMT_RAMP_CONTROL1 + offset, 0x007FFFFF);
WREG32(AFMT_RAMP_CONTROL2 + offset, 0x00000001);
WREG32(AFMT_RAMP_CONTROL3 + offset, 0x00000001);
-
- /* audio packets per line, does anyone know how to calc this ? */
- WREG32_P(AFMT_AUDIO_PACKET_CONTROL + offset, 0x00040000, ~0x001F0000);
}
diff --git a/drivers/gpu/drm/radeon/r600_hdmi.c b/drivers/gpu/drm/radeon/r600_hdmi.c
index 5a2305e..30e616a 100644
--- a/drivers/gpu/drm/radeon/r600_hdmi.c
+++ b/drivers/gpu/drm/radeon/r600_hdmi.c
@@ -324,28 +324,54 @@ void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mod
r600_audio_set_clock(encoder, mode->clock);
+ WREG32(HDMI0_VBI_PACKET_CONTROL + offset,
+ HDMI0_NULL_SEND); /* send null packets when required */
+
WREG32(HDMI0_AUDIO_CRC_CONTROL + offset, 0x1000);
- WREG32(HDMI0_GC + offset, 0x0);
- /* Send audio packets */
- if (ASIC_IS_DCE32(rdev))
- WREG32_P(AFMT_AUDIO_PACKET_CONTROL + offset,
- AFMT_AUDIO_SAMPLE_SEND, ~AFMT_AUDIO_SAMPLE_SEND);
- else
- WREG32_P(HDMI0_AUDIO_PACKET_CONTROL + offset,
- HDMI0_AUDIO_SAMPLE_SEND, ~HDMI0_AUDIO_SAMPLE_SEND);
+ if (ASIC_IS_DCE32(rdev)) {
+ WREG32(HDMI0_AUDIO_PACKET_CONTROL + offset,
+ HDMI0_AUDIO_DELAY_EN(1) | /* default audio delay */
+ HDMI0_AUDIO_PACKETS_PER_LINE(3)); /* should be suffient for all audio modes and small enough for all hblanks */
+ WREG32(AFMT_AUDIO_PACKET_CONTROL + offset,
+ AFMT_AUDIO_SAMPLE_SEND | /* send audio packets */
+ AFMT_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */
+ } else {
+ WREG32(HDMI0_AUDIO_PACKET_CONTROL + offset,
+ HDMI0_AUDIO_SAMPLE_SEND | /* send audio packets */
+ HDMI0_AUDIO_DELAY_EN(1) | /* default audio delay */
+ HDMI0_AUDIO_SEND_MAX_PACKETS | /* send NULL packets if no audio is available */
+ HDMI0_AUDIO_PACKETS_PER_LINE(3) | /* should be suffient for all audio modes and small enough for all hblanks */
+ HDMI0_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */
+ }
- WREG32(HDMI0_ACR_PACKET_CONTROL + offset, 0x1000);
+ WREG32(HDMI0_ACR_PACKET_CONTROL + offset,
+ HDMI0_ACR_AUTO_SEND | /* allow hw to sent ACR packets when required */
+ HDMI0_ACR_SOURCE); /* select SW CTS value */
- r600_hdmi_update_ACR(encoder, mode->clock);
+ WREG32(HDMI0_VBI_PACKET_CONTROL + offset,
+ HDMI0_NULL_SEND | /* send null packets when required */
+ HDMI0_GC_SEND | /* send general control packets */
+ HDMI0_GC_CONT); /* send general control packets every frame */
- WREG32(HDMI0_INFOFRAME_CONTROL0 + offset, 0x13);
+ /* TODO: HDMI0_AUDIO_INFO_UPDATE */
+ WREG32(HDMI0_INFOFRAME_CONTROL0 + offset,
+ HDMI0_AVI_INFO_SEND | /* enable AVI info frames */
+ HDMI0_AVI_INFO_CONT | /* send AVI info frames every frame/field */
+ HDMI0_AUDIO_INFO_SEND | /* enable audio info frames (frames won't be set until audio is enabled) */
+ HDMI0_AUDIO_INFO_CONT); /* send audio info frames every frame/field */
- WREG32(HDMI0_INFOFRAME_CONTROL1 + offset, 0x202);
+ WREG32(HDMI0_INFOFRAME_CONTROL1 + offset,
+ HDMI0_AVI_INFO_LINE(2) | /* anything other than 0 */
+ HDMI0_AUDIO_INFO_LINE(2)); /* anything other than 0 */
+
+ WREG32(HDMI0_GC + offset, 0); /* unset HDMI0_GC_AVMUTE */
r600_hdmi_videoinfoframe(encoder, RGB, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
+ r600_hdmi_update_ACR(encoder, mode->clock);
+
/* it's unknown what these bits do excatly, but it's indeed quite useful for debugging */
WREG32(HDMI0_RAMP_CONTROL0 + offset, 0x00FFFFFF);
WREG32(HDMI0_RAMP_CONTROL1 + offset, 0x007FFFFF);
@@ -353,9 +379,6 @@ void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mod
WREG32(HDMI0_RAMP_CONTROL3 + offset, 0x00000001);
r600_hdmi_audio_workaround(encoder);
-
- /* audio packets per line, does anyone know how to calc this ? */
- WREG32_P(HDMI0_AUDIO_PACKET_CONTROL + offset, 0x00040000, ~0x001F0000);
}
/*
--
1.7.7
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dri-devel@lists.freedesktop.org
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^ permalink raw reply related [flat|nested] 9+ messages in thread* Re: [next][PATCH 2/3] drm/radeon/hdmi: update modesetting
2012-05-06 15:29 ` [next][PATCH 2/3] drm/radeon/hdmi: update modesetting Rafał Miłecki
@ 2012-05-26 8:22 ` Rafał Miłecki
2012-05-26 15:19 ` Rafał Miłecki
0 siblings, 1 reply; 9+ messages in thread
From: Rafał Miłecki @ 2012-05-26 8:22 UTC (permalink / raw)
To: Alex Deucher, Dave Airlie, dri-devel
2012/5/6 Rafał Miłecki <zajec5@gmail.com>:
> + WREG32(HDMI0_AUDIO_PACKET_CONTROL + offset,
> + HDMI0_AUDIO_SAMPLE_SEND | /* send audio packets */
> + HDMI0_AUDIO_DELAY_EN(1) | /* default audio delay */
> + HDMI0_AUDIO_SEND_MAX_PACKETS | /* send NULL packets if no audio is available */
> + HDMI0_AUDIO_PACKETS_PER_LINE(3) | /* should be suffient for all audio modes and small enough for all hblanks */
> + HDMI0_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */
Alex, I've problem with the above code. I've arrived to my parent's
house and I noticed audio doesn't work anymore with Onkyo TX-SR605.
The problem is caused by:
HDMI0_AUDIO_SEND_MAX_PACKETS
Setting this bit doesn't seem to be problem for my Denon 1912, so I
didn't notice that earlier. Before the rewrite modesetting we weren't
set that bit, so it's actually a regression for my case with Onkyo.
Can you say something more about this bit? My only solution is to just
don't set it, but maybe there's a better one?
--
Rafał
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^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [next][PATCH 2/3] drm/radeon/hdmi: update modesetting
2012-05-26 8:22 ` Rafał Miłecki
@ 2012-05-26 15:19 ` Rafał Miłecki
2012-05-26 21:40 ` Rafał Miłecki
0 siblings, 1 reply; 9+ messages in thread
From: Rafał Miłecki @ 2012-05-26 15:19 UTC (permalink / raw)
To: Alex Deucher, Dave Airlie, dri-devel
2012/5/26 Rafał Miłecki <zajec5@gmail.com>:
> 2012/5/6 Rafał Miłecki <zajec5@gmail.com>:
>> + WREG32(HDMI0_AUDIO_PACKET_CONTROL + offset,
>> + HDMI0_AUDIO_SAMPLE_SEND | /* send audio packets */
>> + HDMI0_AUDIO_DELAY_EN(1) | /* default audio delay */
>> + HDMI0_AUDIO_SEND_MAX_PACKETS | /* send NULL packets if no audio is available */
>> + HDMI0_AUDIO_PACKETS_PER_LINE(3) | /* should be suffient for all audio modes and small enough for all hblanks */
>> + HDMI0_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */
>
> Alex, I've problem with the above code. I've arrived to my parent's
> house and I noticed audio doesn't work anymore with Onkyo TX-SR605.
> The problem is caused by:
> HDMI0_AUDIO_SEND_MAX_PACKETS
>
> Setting this bit doesn't seem to be problem for my Denon 1912, so I
> didn't notice that earlier. Before the rewrite modesetting we weren't
> set that bit, so it's actually a regression for my case with Onkyo.
>
> Can you say something more about this bit? My only solution is to just
> don't set it, but maybe there's a better one?
The same happens when I connect my RV620 directly to the TV (not using
Onkyo between as audio receiver). My TV is Sony BRAVIA KDL-52X3500.
Setting bit HDMI0_AUDIO_SEND_MAX_PACKETS also causes no audio in TV.
--
Rafał
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^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [next][PATCH 2/3] drm/radeon/hdmi: update modesetting
2012-05-26 15:19 ` Rafał Miłecki
@ 2012-05-26 21:40 ` Rafał Miłecki
2012-05-27 15:30 ` Alex Deucher
0 siblings, 1 reply; 9+ messages in thread
From: Rafał Miłecki @ 2012-05-26 21:40 UTC (permalink / raw)
To: Alex Deucher, Dave Airlie, dri-devel
2012/5/26 Rafał Miłecki <zajec5@gmail.com>:
> 2012/5/26 Rafał Miłecki <zajec5@gmail.com>:
>> 2012/5/6 Rafał Miłecki <zajec5@gmail.com>:
>>> + WREG32(HDMI0_AUDIO_PACKET_CONTROL + offset,
>>> + HDMI0_AUDIO_SAMPLE_SEND | /* send audio packets */
>>> + HDMI0_AUDIO_DELAY_EN(1) | /* default audio delay */
>>> + HDMI0_AUDIO_SEND_MAX_PACKETS | /* send NULL packets if no audio is available */
>>> + HDMI0_AUDIO_PACKETS_PER_LINE(3) | /* should be suffient for all audio modes and small enough for all hblanks */
>>> + HDMI0_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */
>>
>> Alex, I've problem with the above code. I've arrived to my parent's
>> house and I noticed audio doesn't work anymore with Onkyo TX-SR605.
>> The problem is caused by:
>> HDMI0_AUDIO_SEND_MAX_PACKETS
>>
>> Setting this bit doesn't seem to be problem for my Denon 1912, so I
>> didn't notice that earlier. Before the rewrite modesetting we weren't
>> set that bit, so it's actually a regression for my case with Onkyo.
>>
>> Can you say something more about this bit? My only solution is to just
>> don't set it, but maybe there's a better one?
>
> The same happens when I connect my RV620 directly to the TV (not using
> Onkyo between as audio receiver). My TV is Sony BRAVIA KDL-52X3500.
> Setting bit HDMI0_AUDIO_SEND_MAX_PACKETS also causes no audio in TV.
Last e-mail for today (well, it's only 25 minutes left here ;) ). I've
decided to give fglrx a chance (12.4).
1) RV620 connected directly to Sony BRAVIA KDL-52X3500
[ 234.399] (WW) fglrx(0): Incorrect HDMI dongle found, HDMI audio disabled.
I couldn't play anything.
2) RV620 connected to Onkyo TX-SR605
Audio playing, but fglrx set 0x7408 to:
0x10020011
so it seems fglrx isn't using
HDMI0_AUDIO_SEND_MAX_PACKETS == 0x100
Setting that bit while using fglrx broke audio.
I did one more test with a different TV: Sony BRAVIA KDL-40S40xx. The
results are the same. fglrx sets 0x7408 to: 0x10020011 (so
HDMI0_AUDIO_SEND_MAX_PACKETS is not set). Setting that bit manually
(while using fglrx) breaks audio.
It just seems to me we shouldn't set that bit at all...
--
Rafał
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^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [next][PATCH 2/3] drm/radeon/hdmi: update modesetting
2012-05-26 21:40 ` Rafał Miłecki
@ 2012-05-27 15:30 ` Alex Deucher
2012-05-27 18:50 ` Rafał Miłecki
0 siblings, 1 reply; 9+ messages in thread
From: Alex Deucher @ 2012-05-27 15:30 UTC (permalink / raw)
To: Rafał Miłecki; +Cc: dri-devel
On Sat, May 26, 2012 at 5:40 PM, Rafał Miłecki <zajec5@gmail.com> wrote:
> 2012/5/26 Rafał Miłecki <zajec5@gmail.com>:
>> 2012/5/26 Rafał Miłecki <zajec5@gmail.com>:
>>> 2012/5/6 Rafał Miłecki <zajec5@gmail.com>:
>>>> + WREG32(HDMI0_AUDIO_PACKET_CONTROL + offset,
>>>> + HDMI0_AUDIO_SAMPLE_SEND | /* send audio packets */
>>>> + HDMI0_AUDIO_DELAY_EN(1) | /* default audio delay */
>>>> + HDMI0_AUDIO_SEND_MAX_PACKETS | /* send NULL packets if no audio is available */
>>>> + HDMI0_AUDIO_PACKETS_PER_LINE(3) | /* should be suffient for all audio modes and small enough for all hblanks */
>>>> + HDMI0_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */
>>>
>>> Alex, I've problem with the above code. I've arrived to my parent's
>>> house and I noticed audio doesn't work anymore with Onkyo TX-SR605.
>>> The problem is caused by:
>>> HDMI0_AUDIO_SEND_MAX_PACKETS
>>>
>>> Setting this bit doesn't seem to be problem for my Denon 1912, so I
>>> didn't notice that earlier. Before the rewrite modesetting we weren't
>>> set that bit, so it's actually a regression for my case with Onkyo.
>>>
>>> Can you say something more about this bit? My only solution is to just
>>> don't set it, but maybe there's a better one?
>>
>> The same happens when I connect my RV620 directly to the TV (not using
>> Onkyo between as audio receiver). My TV is Sony BRAVIA KDL-52X3500.
>> Setting bit HDMI0_AUDIO_SEND_MAX_PACKETS also causes no audio in TV.
>
> Last e-mail for today (well, it's only 25 minutes left here ;) ). I've
> decided to give fglrx a chance (12.4).
>
> 1) RV620 connected directly to Sony BRAVIA KDL-52X3500
> [ 234.399] (WW) fglrx(0): Incorrect HDMI dongle found, HDMI audio disabled.
> I couldn't play anything.
>
> 2) RV620 connected to Onkyo TX-SR605
> Audio playing, but fglrx set 0x7408 to:
> 0x10020011
> so it seems fglrx isn't using
> HDMI0_AUDIO_SEND_MAX_PACKETS == 0x100
> Setting that bit while using fglrx broke audio.
>
>
> I did one more test with a different TV: Sony BRAVIA KDL-40S40xx. The
> results are the same. fglrx sets 0x7408 to: 0x10020011 (so
> HDMI0_AUDIO_SEND_MAX_PACKETS is not set). Setting that bit manually
> (while using fglrx) breaks audio.
>
>
> It just seems to me we shouldn't set that bit at all...
If it breaks things, might as well not set it. I only set it because
some of the documents said it needed to be set. That bit causes the
hw to send null packets if audio data is not available. Maybe some
receivers don't deal well with null packets. Might as well disable it
for now and I can ask the display guys more about it next week.
Alex
>
> --
> Rafał
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [next][PATCH 2/3] drm/radeon/hdmi: update modesetting
2012-05-27 15:30 ` Alex Deucher
@ 2012-05-27 18:50 ` Rafał Miłecki
0 siblings, 0 replies; 9+ messages in thread
From: Rafał Miłecki @ 2012-05-27 18:50 UTC (permalink / raw)
To: Alex Deucher; +Cc: dri-devel
2012/5/27 Alex Deucher <alexdeucher@gmail.com>:
> On Sat, May 26, 2012 at 5:40 PM, Rafał Miłecki <zajec5@gmail.com> wrote:
>> 2012/5/26 Rafał Miłecki <zajec5@gmail.com>:
>>> 2012/5/26 Rafał Miłecki <zajec5@gmail.com>:
>>>> 2012/5/6 Rafał Miłecki <zajec5@gmail.com>:
>>>>> + WREG32(HDMI0_AUDIO_PACKET_CONTROL + offset,
>>>>> + HDMI0_AUDIO_SAMPLE_SEND | /* send audio packets */
>>>>> + HDMI0_AUDIO_DELAY_EN(1) | /* default audio delay */
>>>>> + HDMI0_AUDIO_SEND_MAX_PACKETS | /* send NULL packets if no audio is available */
>>>>> + HDMI0_AUDIO_PACKETS_PER_LINE(3) | /* should be suffient for all audio modes and small enough for all hblanks */
>>>>> + HDMI0_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */
>>>>
>>>> Alex, I've problem with the above code. I've arrived to my parent's
>>>> house and I noticed audio doesn't work anymore with Onkyo TX-SR605.
>>>> The problem is caused by:
>>>> HDMI0_AUDIO_SEND_MAX_PACKETS
>>>>
>>>> Setting this bit doesn't seem to be problem for my Denon 1912, so I
>>>> didn't notice that earlier. Before the rewrite modesetting we weren't
>>>> set that bit, so it's actually a regression for my case with Onkyo.
>>>>
>>>> Can you say something more about this bit? My only solution is to just
>>>> don't set it, but maybe there's a better one?
>>>
>>> The same happens when I connect my RV620 directly to the TV (not using
>>> Onkyo between as audio receiver). My TV is Sony BRAVIA KDL-52X3500.
>>> Setting bit HDMI0_AUDIO_SEND_MAX_PACKETS also causes no audio in TV.
>>
>> Last e-mail for today (well, it's only 25 minutes left here ;) ). I've
>> decided to give fglrx a chance (12.4).
>>
>> 1) RV620 connected directly to Sony BRAVIA KDL-52X3500
>> [ 234.399] (WW) fglrx(0): Incorrect HDMI dongle found, HDMI audio disabled.
>> I couldn't play anything.
>>
>> 2) RV620 connected to Onkyo TX-SR605
>> Audio playing, but fglrx set 0x7408 to:
>> 0x10020011
>> so it seems fglrx isn't using
>> HDMI0_AUDIO_SEND_MAX_PACKETS == 0x100
>> Setting that bit while using fglrx broke audio.
>>
>>
>> I did one more test with a different TV: Sony BRAVIA KDL-40S40xx. The
>> results are the same. fglrx sets 0x7408 to: 0x10020011 (so
>> HDMI0_AUDIO_SEND_MAX_PACKETS is not set). Setting that bit manually
>> (while using fglrx) breaks audio.
>>
>>
>> It just seems to me we shouldn't set that bit at all...
>
> If it breaks things, might as well not set it. I only set it because
> some of the documents said it needed to be set. That bit causes the
> hw to send null packets if audio data is not available. Maybe some
> receivers don't deal well with null packets. Might as well disable it
> for now and I can ask the display guys more about it next week.
Thanks for answer. It seems this bit works somehow differently than
your docs says.
I could understand NULL packets breaking display when not playing
audio. However this bit broke audio totally, even when feeding GPU
with audio, my receivers still couldn't play anything.
I've just arrived my home and tested my home configuration: Denon 1912
+ Sony UE55D7000. This set handles audio correctly even when setting
HDMI0_AUDIO_SEND_MAX_PACKETS. However dumping regs while using fglrx
has showed this bit is not being set (by fglrx).
So there isn't any magical detection of HDMI0_AUDIO_SEND_MAX_PACKETS
receiver-acceptance in fglrx code. fglrx just doesn't set
HDMI0_AUDIO_SEND_MAX_PACKETS no matter if this would work with the
attached receivers. Maybe fglrx programmers detected problem with that
bit/feature and disabled it, ignoring specs at this single point.
--
Rafał
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^ permalink raw reply [flat|nested] 9+ messages in thread
* [next][PATCH 3/3] drm/radeon/hdmi: fix some coding style
2012-05-06 15:29 [next][PATCH 0/3] drm/radeon/hdmi: separate Evergreen, update modesetting Rafał Miłecki
2012-05-06 15:29 ` [next][PATCH 1/3] drm/radeon/hdmi: separate evergreen code Rafał Miłecki
2012-05-06 15:29 ` [next][PATCH 2/3] drm/radeon/hdmi: update modesetting Rafał Miłecki
@ 2012-05-06 15:29 ` Rafał Miłecki
2 siblings, 0 replies; 9+ messages in thread
From: Rafał Miłecki @ 2012-05-06 15:29 UTC (permalink / raw)
To: Dave Airlie, dri-devel; +Cc: Christian König
Use defined macros by the way.
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
---
drivers/gpu/drm/radeon/r600_hdmi.c | 47 ++++++++++++++++++++++++-----------
1 files changed, 32 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/radeon/r600_hdmi.c b/drivers/gpu/drm/radeon/r600_hdmi.c
index 30e616a..c308432 100644
--- a/drivers/gpu/drm/radeon/r600_hdmi.c
+++ b/drivers/gpu/drm/radeon/r600_hdmi.c
@@ -417,34 +417,51 @@ void r600_hdmi_update_audio_settings(struct drm_encoder *encoder)
if (status_bits & AUDIO_STATUS_EMPHASIS)
iec |= 1 << 3;
- iec |= category_code << 8;
+ iec |= HDMI0_60958_CS_CATEGORY_CODE(category_code);
switch (rate) {
- case 32000: iec |= 0x3 << 24; break;
- case 44100: iec |= 0x0 << 24; break;
- case 88200: iec |= 0x8 << 24; break;
- case 176400: iec |= 0xc << 24; break;
- case 48000: iec |= 0x2 << 24; break;
- case 96000: iec |= 0xa << 24; break;
- case 192000: iec |= 0xe << 24; break;
+ case 32000:
+ iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0x3);
+ break;
+ case 44100:
+ iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0x0);
+ break;
+ case 48000:
+ iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0x2);
+ break;
+ case 88200:
+ iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0x8);
+ break;
+ case 96000:
+ iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0xa);
+ break;
+ case 176400:
+ iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0xc);
+ break;
+ case 192000:
+ iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0xe);
+ break;
}
WREG32(HDMI0_60958_0 + offset, iec);
iec = 0;
switch (bps) {
- case 16: iec |= 0x2; break;
- case 20: iec |= 0x3; break;
- case 24: iec |= 0xb; break;
+ case 16:
+ iec |= HDMI0_60958_CS_WORD_LENGTH(0x2);
+ break;
+ case 20:
+ iec |= HDMI0_60958_CS_WORD_LENGTH(0x3);
+ break;
+ case 24:
+ iec |= HDMI0_60958_CS_WORD_LENGTH(0xb);
+ break;
}
if (status_bits & AUDIO_STATUS_V)
iec |= 0x5 << 16;
-
WREG32_P(HDMI0_60958_1 + offset, iec, ~0x5000f);
- /* 0x021 or 0x031 sets the audio frame length */
- WREG32(HDMI0_VBI_PACKET_CONTROL + offset, 0x31);
- r600_hdmi_audioinfoframe(encoder, channels-1, 0, 0, 0, 0, 0, 0, 0);
+ r600_hdmi_audioinfoframe(encoder, channels - 1, 0, 0, 0, 0, 0, 0, 0);
r600_hdmi_audio_workaround(encoder);
}
--
1.7.7
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^ permalink raw reply related [flat|nested] 9+ messages in thread