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From: Thierry Reding <thierry.reding@gmail.com>
To: dri-devel@lists.freedesktop.org
Cc: linux-tegra@vger.kernel.org
Subject: [PATCH 07/14] gpu: host1x: mipi: Preserve the contents of MIPI_CAL_CTRL
Date: Mon, 13 Oct 2014 12:21:48 +0200	[thread overview]
Message-ID: <1413195715-4719-7-git-send-email-thierry.reding@gmail.com> (raw)
In-Reply-To: <1413195715-4719-1-git-send-email-thierry.reding@gmail.com>

From: Sean Paul <seanpaul@chromium.org>

By paving the CTRL reg value, the current code changes MIPI_CAL_PRESCALE
("Auto-cal calibration step prescale") from 1us to 0.1us (val=0). In the
description for PHY's noise filter (MIPI_CAL_NOISE_FLT), the TRM states
that if the value of the prescale is 0 (or 0.1us), the filter should be
set between 2-5. However, the current code sets it to 0.

For now, let's keep the prescale and filter values as-is, which is most
likely the power-on-reset values of 0x2 and 0xa, respectively.

Signed-off-by: Sean Paul <seanpaul@chromium.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
 drivers/gpu/host1x/mipi.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/host1x/mipi.c b/drivers/gpu/host1x/mipi.c
index a3e215a0116f..0d8c3ae8db6a 100644
--- a/drivers/gpu/host1x/mipi.c
+++ b/drivers/gpu/host1x/mipi.c
@@ -208,7 +208,9 @@ int tegra_mipi_calibrate(struct tegra_mipi_device *device)
 		tegra_mipi_writel(device->mipi, value, modules[i].reg);
 	}
 
-	tegra_mipi_writel(device->mipi, MIPI_CAL_CTRL_START, MIPI_CAL_CTRL);
+	value = tegra_mipi_readl(device->mipi, MIPI_CAL_CTRL);
+	value |= MIPI_CAL_CTRL_START;
+	tegra_mipi_writel(device->mipi, value, MIPI_CAL_CTRL);
 
 	err = tegra_mipi_wait(device->mipi);
 
-- 
2.1.2

  parent reply	other threads:[~2014-10-13 10:22 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-10-13 10:21 [PATCH 01/14] gpu: host1x: Use struct host1x_bo pointers in traces Thierry Reding
     [not found] ` <1413195715-4719-1-git-send-email-thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2014-10-13 10:21   ` [PATCH 02/14] gpu: host1x: Make mapped field of push buffers void * Thierry Reding
2014-10-13 10:21   ` [PATCH 06/14] gpu: host1x: mipi: Registers are 32 bits wide Thierry Reding
2014-10-13 10:21   ` [PATCH 11/14] drm/tegra: Do not enable output on .mode_set() Thierry Reding
2014-10-13 10:21 ` [PATCH 03/14] gpu: host1x: Fix typo in comment Thierry Reding
2014-10-13 10:21 ` [PATCH 04/14] gpu: host1x: Print address/offset pairs consistently Thierry Reding
2014-10-13 10:21 ` [PATCH 05/14] gpu: host1x: Make gather offsets unsigned Thierry Reding
2014-10-13 10:21 ` Thierry Reding [this message]
2014-10-13 10:21 ` [PATCH 08/14] gpu: host1x: mipi: Calibrate clock lanes Thierry Reding
2014-10-13 10:21 ` [PATCH 09/14] gpu: host1x: mipi: Set MIPI_CAL_BIAS_PAD_CFG1 register Thierry Reding
2014-10-13 10:21 ` [PATCH 10/14] drm/tegra: dc: Add powergate support Thierry Reding
2014-10-13 10:21 ` [PATCH 12/14] drm/tegra: dsi: Make FIFO depths host parameters Thierry Reding
2014-10-13 10:21 ` [PATCH 13/14] drm/tegra: dsi: Add ganged mode support Thierry Reding
     [not found]   ` <1413195715-4719-13-git-send-email-thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2014-10-14 14:51     ` Sean Paul
2014-10-13 10:21 ` [PATCH 14/14] drm/tegra: dsi: Set up PHY_TIMING & BTA_TIMING registers earlier Thierry Reding

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