From: Thierry Reding <thierry.reding@gmail.com>
To: dri-devel@lists.freedesktop.org
Cc: linux-tegra@vger.kernel.org
Subject: [PATCH 09/14] gpu: host1x: mipi: Set MIPI_CAL_BIAS_PAD_CFG1 register
Date: Mon, 13 Oct 2014 12:21:50 +0200 [thread overview]
Message-ID: <1413195715-4719-9-git-send-email-thierry.reding@gmail.com> (raw)
In-Reply-To: <1413195715-4719-1-git-send-email-thierry.reding@gmail.com>
From: Sean Paul <seanpaul@chromium.org>
During calibration, sets the "internal reference level for drive pull-
down" to the value specified in the Tegra TRM.
Signed-off-by: Sean Paul <seanpaul@chromium.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
drivers/gpu/host1x/mipi.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/host1x/mipi.c b/drivers/gpu/host1x/mipi.c
index 22e20c2399c5..fbc6ee6ca337 100644
--- a/drivers/gpu/host1x/mipi.c
+++ b/drivers/gpu/host1x/mipi.c
@@ -72,6 +72,7 @@
#define MIPI_CAL_BIAS_PAD_E_VCLAMP_REF (1 << 0)
#define MIPI_CAL_BIAS_PAD_CFG1 0x17
+#define MIPI_CAL_BIAS_PAD_DRV_DN_REF(x) (((x) & 0x7) << 16)
#define MIPI_CAL_BIAS_PAD_CFG2 0x18
#define MIPI_CAL_BIAS_PAD_PDVREG (1 << 1)
@@ -203,6 +204,9 @@ int tegra_mipi_calibrate(struct tegra_mipi_device *device)
value |= MIPI_CAL_BIAS_PAD_E_VCLAMP_REF;
tegra_mipi_writel(device->mipi, value, MIPI_CAL_BIAS_PAD_CFG0);
+ tegra_mipi_writel(device->mipi, MIPI_CAL_BIAS_PAD_DRV_DN_REF(2),
+ MIPI_CAL_BIAS_PAD_CFG1);
+
value = tegra_mipi_readl(device->mipi, MIPI_CAL_BIAS_PAD_CFG2);
value &= ~MIPI_CAL_BIAS_PAD_PDVREG;
tegra_mipi_writel(device->mipi, value, MIPI_CAL_BIAS_PAD_CFG2);
--
2.1.2
next prev parent reply other threads:[~2014-10-13 10:22 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-10-13 10:21 [PATCH 01/14] gpu: host1x: Use struct host1x_bo pointers in traces Thierry Reding
2014-10-13 10:21 ` [PATCH 03/14] gpu: host1x: Fix typo in comment Thierry Reding
2014-10-13 10:21 ` [PATCH 04/14] gpu: host1x: Print address/offset pairs consistently Thierry Reding
2014-10-13 10:21 ` [PATCH 05/14] gpu: host1x: Make gather offsets unsigned Thierry Reding
[not found] ` <1413195715-4719-1-git-send-email-thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2014-10-13 10:21 ` [PATCH 02/14] gpu: host1x: Make mapped field of push buffers void * Thierry Reding
2014-10-13 10:21 ` [PATCH 06/14] gpu: host1x: mipi: Registers are 32 bits wide Thierry Reding
2014-10-13 10:21 ` [PATCH 11/14] drm/tegra: Do not enable output on .mode_set() Thierry Reding
2014-10-13 10:21 ` [PATCH 07/14] gpu: host1x: mipi: Preserve the contents of MIPI_CAL_CTRL Thierry Reding
2014-10-13 10:21 ` [PATCH 08/14] gpu: host1x: mipi: Calibrate clock lanes Thierry Reding
2014-10-13 10:21 ` Thierry Reding [this message]
2014-10-13 10:21 ` [PATCH 10/14] drm/tegra: dc: Add powergate support Thierry Reding
2014-10-13 10:21 ` [PATCH 12/14] drm/tegra: dsi: Make FIFO depths host parameters Thierry Reding
2014-10-13 10:21 ` [PATCH 13/14] drm/tegra: dsi: Add ganged mode support Thierry Reding
[not found] ` <1413195715-4719-13-git-send-email-thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2014-10-14 14:51 ` Sean Paul
2014-10-13 10:21 ` [PATCH 14/14] drm/tegra: dsi: Set up PHY_TIMING & BTA_TIMING registers earlier Thierry Reding
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