* [PATCH 2/2] drm/amdgpu: start using engine_id for encoders.
2016-04-14 4:41 [PATCH 1/2] drm/amdgpu: drop CV/TV bits in atombios_encoders Dave Airlie
@ 2016-04-14 4:41 ` Dave Airlie
0 siblings, 0 replies; 2+ messages in thread
From: Dave Airlie @ 2016-04-14 4:41 UTC (permalink / raw)
To: dri-devel
From: Dave Airlie <airlied@redhat.com>
This moves dig_encoder up a level and starts consistently using
engine_id in its place for all the digital and dac engines.
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
.../drm/amd/amdgpu/amdgpu_grph_object_id_helpers.c | 37 +++++++
drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 3 +-
drivers/gpu/drm/amd/amdgpu/atombios_encoders.c | 108 +++------------------
drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 30 +++---
drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 30 +++---
drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 31 +++---
6 files changed, 107 insertions(+), 132 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_grph_object_id_helpers.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_grph_object_id_helpers.c
index 122dfdb..32f0e3f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_grph_object_id_helpers.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_grph_object_id_helpers.c
@@ -310,3 +310,40 @@ uint8_t amdgpu_encoder_object_to_atom(struct graphics_object_id object_id)
enum encoder_id enc_id = display_graphics_object_id_get_encoder_id(object_id);
return amdgpu_encoder_id_to_atom(enc_id);
}
+
+bool amdgpu_engine_id_to_atom_encoder(enum engine_id engine, uint8_t *atom_encoder_id)
+{
+ uint8_t encoder_id = 0;
+ switch (engine) {
+ case ENGINE_ID_DIGA:
+ encoder_id = ASIC_INT_DIG1_ENCODER_ID;
+ break;
+ case ENGINE_ID_DIGB:
+ encoder_id = ASIC_INT_DIG2_ENCODER_ID;
+ break;
+ case ENGINE_ID_DIGC:
+ encoder_id = ASIC_INT_DIG3_ENCODER_ID;
+ break;
+ case ENGINE_ID_DIGD:
+ encoder_id = ASIC_INT_DIG4_ENCODER_ID;
+ break;
+ case ENGINE_ID_DIGE:
+ encoder_id = ASIC_INT_DIG5_ENCODER_ID;
+ break;
+ case ENGINE_ID_DIGF:
+ encoder_id = ASIC_INT_DIG6_ENCODER_ID;
+ break;
+ case ENGINE_ID_DIGG:
+ encoder_id = ASIC_INT_DIG7_ENCODER_ID;
+ break;
+ case ENCODER_ID_INTERNAL_KLDSCP_DAC1:
+ encoder_id = ASIC_INT_DAC1_ENCODER_ID;
+ break;
+ case ENCODER_ID_INTERNAL_KLDSCP_DAC2:
+ encoder_id = ASIC_INT_DAC2_ENCODER_ID;
+ default:
+ return false;
+ }
+ *atom_encoder_id = encoder_id;
+ return true;
+}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
index 5624c81..cb7a4f9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
@@ -416,7 +416,6 @@ struct amdgpu_encoder_atom_dig {
bool linkb;
/* atom dig */
bool coherent_mode;
- int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB, etc. */
/* atom lvds/edp */
uint32_t lcd_misc;
uint16_t panel_pwr_delay;
@@ -446,6 +445,7 @@ struct amdgpu_encoder {
int audio_polling_active;
bool is_ext_encoder;
u16 caps;
+ enum engine_id engine_id; /* -1 disabled, 0 DIGA, 1 DIGB, etc. */
};
struct amdgpu_connector_atom_dig {
@@ -596,4 +596,5 @@ extern const struct drm_mode_config_funcs amdgpu_mode_funcs;
struct graphics_object_id amdgpu_object_id_from_bios_object_id(uint32_t bios_object_id);
uint8_t amdgpu_encoder_object_to_atom(struct graphics_object_id object_id);
uint8_t amdgpu_encoder_id_to_atom(enum encoder_id id);
+bool amdgpu_engine_id_to_atom_encoder(enum engine_id engine, uint8_t *atom_encoder_id);
#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c b/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c
index 37c498b..ff24826 100644
--- a/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c
+++ b/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c
@@ -520,7 +520,7 @@ amdgpu_atombios_encoder_setup_dig_encoder(struct drm_encoder *encoder,
}
/* no dig encoder assigned */
- if (dig->dig_encoder == -1)
+ if (amdgpu_encoder->engine_id == ENGINE_ID_UNKNOWN)
return;
memset(&args, 0, sizeof(args));
@@ -585,7 +585,7 @@ amdgpu_atombios_encoder_setup_dig_encoder(struct drm_encoder *encoder,
if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode) && (dp_clock == 270000))
args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
- args.v3.acConfig.ucDigSel = dig->dig_encoder;
+ args.v3.acConfig.ucDigSel = amdgpu_encoder->engine_id;
args.v3.ucBitPerColor = amdgpu_atombios_encoder_get_bpc(encoder);
break;
case 4:
@@ -613,7 +613,7 @@ amdgpu_atombios_encoder_setup_dig_encoder(struct drm_encoder *encoder,
else
args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_1_62GHZ;
}
- args.v4.acConfig.ucDigSel = dig->dig_encoder;
+ args.v4.acConfig.ucDigSel = amdgpu_encoder->engine_id;
args.v4.ucBitPerColor = amdgpu_atombios_encoder_get_bpc(encoder);
if (hpd_id == AMDGPU_HPD_NONE)
args.v4.ucHPD_ID = 0;
@@ -660,7 +660,7 @@ amdgpu_atombios_encoder_setup_dig_transmitter(struct drm_encoder *encoder, int a
int dp_lane_count = 0;
int connector_object_id = 0;
int igp_lane_info = 0;
- int dig_encoder = dig->dig_encoder;
+ enum engine_id engine = amdgpu_encoder->engine_id;
int hpd_id = AMDGPU_HPD_NONE;
enum encoder_id enc_id = display_graphics_object_id_get_encoder_id(amdgpu_encoder->encoder_object_id);
@@ -669,7 +669,7 @@ amdgpu_atombios_encoder_setup_dig_transmitter(struct drm_encoder *encoder, int a
/* just needed to avoid bailing in the encoder check. the encoder
* isn't used for init
*/
- dig_encoder = 0;
+ engine = ENGINE_ID_DIGA;
} else
connector = amdgpu_get_connector_for_encoder(encoder);
@@ -690,7 +690,7 @@ amdgpu_atombios_encoder_setup_dig_transmitter(struct drm_encoder *encoder, int a
}
/* no dig encoder assigned */
- if (dig_encoder == -1)
+ if (engine == ENGINE_ID_UNKNOWN)
return;
if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(encoder)))
@@ -736,7 +736,7 @@ amdgpu_atombios_encoder_setup_dig_transmitter(struct drm_encoder *encoder, int a
args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
- if (dig_encoder)
+ if (engine)
args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
else
args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
@@ -791,7 +791,7 @@ amdgpu_atombios_encoder_setup_dig_transmitter(struct drm_encoder *encoder, int a
args.v2.usPixelClock = cpu_to_le16(amdgpu_encoder->pixel_clock / 10);
}
- args.v2.acConfig.ucEncoderSel = dig_encoder;
+ args.v2.acConfig.ucEncoderSel = engine;
if (dig->linkb)
args.v2.acConfig.ucLinkSel = 1;
@@ -844,7 +844,7 @@ amdgpu_atombios_encoder_setup_dig_transmitter(struct drm_encoder *encoder, int a
if (dig->linkb)
args.v3.acConfig.ucLinkSel = 1;
- if (dig_encoder & 1)
+ if (engine & 1)
args.v3.acConfig.ucEncoderSel = 1;
/* Select the PLL for the PHY
@@ -905,7 +905,7 @@ amdgpu_atombios_encoder_setup_dig_transmitter(struct drm_encoder *encoder, int a
if (dig->linkb)
args.v4.acConfig.ucLinkSel = 1;
- if (dig_encoder & 1)
+ if (engine & 1)
args.v4.acConfig.ucEncoderSel = 1;
/* Select the PLL for the PHY
@@ -1000,7 +1000,7 @@ amdgpu_atombios_encoder_setup_dig_transmitter(struct drm_encoder *encoder, int a
args.v5.asConfig.ucHPDSel = 0;
else
args.v5.asConfig.ucHPDSel = hpd_id + 1;
- args.v5.ucDigEncoderSel = 1 << dig_encoder;
+ args.v5.ucDigEncoderSel = 1 << engine;
args.v5.ucDPLaneSet = lane_set;
break;
default:
@@ -1305,7 +1305,6 @@ amdgpu_atombios_encoder_set_crtc_source(struct drm_encoder *encoder)
union crtc_source_param args;
int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
uint8_t frev, crev;
- struct amdgpu_encoder_atom_dig *dig;
enum encoder_id enc_id = display_graphics_object_id_get_encoder_id(amdgpu_encoder->encoder_object_id);
enum controller_id controller_id = display_graphics_object_id_get_controller_id(amdgpu_crtc->crtc_object_id);
memset(&args, 0, sizeof(args));
@@ -1362,46 +1361,9 @@ amdgpu_atombios_encoder_set_crtc_source(struct drm_encoder *encoder)
} else {
args.v2.ucEncodeMode = amdgpu_atombios_encoder_get_encoder_mode(encoder);
}
- switch (enc_id) {
- case ENCODER_ID_INTERNAL_UNIPHY:
- case ENCODER_ID_INTERNAL_UNIPHY1:
- case ENCODER_ID_INTERNAL_UNIPHY2:
- case ENCODER_ID_INTERNAL_UNIPHY3:
- case ENCODER_ID_INTERNAL_KLDSCP_LVTMA:
- dig = amdgpu_encoder->enc_priv;
- switch (dig->dig_encoder) {
- case 0:
- args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
- break;
- case 1:
- args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
- break;
- case 2:
- args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID;
- break;
- case 3:
- args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID;
- break;
- case 4:
- args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID;
- break;
- case 5:
- args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID;
- break;
- case 6:
- args.v2.ucEncoderID = ASIC_INT_DIG7_ENCODER_ID;
- break;
- }
- break;
- case ENCODER_ID_INTERNAL_KLDSCP_DAC1:
- args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID;
- break;
- case ENCODER_ID_INTERNAL_KLDSCP_DAC2:
- args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID;
- break;
- default:
+
+ if (!amdgpu_engine_id_to_atom_encoder(amdgpu_encoder->engine_id, &args.v2.ucEncoderID))
return;
- }
break;
case 3:
args.v3.ucCRTC = controller_id;
@@ -1420,46 +1382,9 @@ amdgpu_atombios_encoder_set_crtc_source(struct drm_encoder *encoder)
args.v2.ucEncodeMode = amdgpu_atombios_encoder_get_encoder_mode(encoder);
}
args.v3.ucDstBpc = amdgpu_atombios_encoder_get_bpc(encoder);
- switch (enc_id) {
- case ENCODER_ID_INTERNAL_UNIPHY:
- case ENCODER_ID_INTERNAL_UNIPHY1:
- case ENCODER_ID_INTERNAL_UNIPHY2:
- case ENCODER_ID_INTERNAL_UNIPHY3:
- case ENCODER_ID_INTERNAL_KLDSCP_LVTMA:
- dig = amdgpu_encoder->enc_priv;
- switch (dig->dig_encoder) {
- case 0:
- args.v3.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
- break;
- case 1:
- args.v3.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
- break;
- case 2:
- args.v3.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID;
- break;
- case 3:
- args.v3.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID;
- break;
- case 4:
- args.v3.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID;
- break;
- case 5:
- args.v3.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID;
- break;
- case 6:
- args.v3.ucEncoderID = ASIC_INT_DIG7_ENCODER_ID;
- break;
- }
- break;
- case ENCODER_ID_INTERNAL_KLDSCP_DAC1:
- args.v3.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID;
- break;
- case ENCODER_ID_INTERNAL_KLDSCP_DAC2:
- args.v3.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID;
- break;
- default:
- break;
- }
+
+ if (!amdgpu_engine_id_to_atom_encoder(amdgpu_encoder->engine_id, &args.v3.ucEncoderID))
+ return;
break;
}
break;
@@ -1951,7 +1876,6 @@ amdgpu_atombios_encoder_get_dig_info(struct amdgpu_encoder *amdgpu_encoder)
/* coherent mode by default */
dig->coherent_mode = true;
- dig->dig_encoder = -1;
if (encoder_enum == ENUM_ID_2)
dig->linkb = true;
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
index e2b22bf..71b30b5 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
@@ -2385,7 +2385,7 @@ static void dce_v10_0_crtc_load_lut(struct drm_crtc *crtc)
WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
}
-static int dce_v10_0_pick_dig_encoder(struct drm_encoder *encoder)
+static enum engine_id dce_v10_0_pick_engine(struct drm_encoder *encoder)
{
struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
@@ -2394,24 +2394,29 @@ static int dce_v10_0_pick_dig_encoder(struct drm_encoder *encoder)
switch (enc_id) {
case ENCODER_ID_INTERNAL_UNIPHY:
if (dig->linkb)
- return 1;
+ return ENGINE_ID_DIGB;
else
- return 0;
+ return ENGINE_ID_DIGA;
break;
case ENCODER_ID_INTERNAL_UNIPHY1:
if (dig->linkb)
- return 3;
+ return ENGINE_ID_DIGD;
else
- return 2; break;
+ return ENGINE_ID_DIGC;
+ break;
case ENCODER_ID_INTERNAL_UNIPHY2:
if (dig->linkb)
- return 5;
+ return ENGINE_ID_DIGF;
else
- return 4;
+ return ENGINE_ID_DIGE;
break;
case ENCODER_ID_INTERNAL_UNIPHY3:
- return 6;
+ return ENGINE_ID_DIGG;
break;
+ case ENCODER_ID_INTERNAL_KLDSCP_DAC1:
+ return ENGINE_ID_DACA;
+ case ENCODER_ID_INTERNAL_KLDSCP_DAC2:
+ return ENGINE_ID_DACB;
default:
DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_object_id.id);
return 0;
@@ -3546,15 +3551,15 @@ static void dce_v10_0_encoder_prepare(struct drm_encoder *encoder)
struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
+ amdgpu_encoder->engine_id = dce_v10_0_pick_engine(encoder);
if ((amdgpu_encoder->active_device &
(ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
(amdgpu_encoder_get_dp_bridge_encoder_id(encoder) !=
ENCODER_ID_UNKNOWN)) {
struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
if (dig) {
- dig->dig_encoder = dce_v10_0_pick_dig_encoder(encoder);
if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT)
- dig->afmt = adev->mode_info.afmt[dig->dig_encoder];
+ dig->afmt = adev->mode_info.afmt[amdgpu_encoder->engine_id];
}
}
@@ -3592,16 +3597,14 @@ static void dce_v10_0_encoder_commit(struct drm_encoder *encoder)
static void dce_v10_0_encoder_disable(struct drm_encoder *encoder)
{
struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
- struct amdgpu_encoder_atom_dig *dig;
amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
if (amdgpu_atombios_encoder_is_digital(encoder)) {
if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
dce_v10_0_afmt_enable(encoder, false);
- dig = amdgpu_encoder->enc_priv;
- dig->dig_encoder = -1;
}
+ amdgpu_encoder->engine_id = ENGINE_ID_UNKNOWN;
amdgpu_encoder->active_device = 0;
}
@@ -3727,6 +3730,7 @@ static void dce_v10_0_encoder_add(struct amdgpu_device *adev,
amdgpu_encoder->underscan_type = UNDERSCAN_OFF;
amdgpu_encoder->is_ext_encoder = false;
amdgpu_encoder->caps = caps;
+ amdgpu_encoder->engine_id = ENGINE_ID_UNKNOWN;
switch (encoder_object_id.id) {
case ENCODER_ID_INTERNAL_KLDSCP_DAC1:
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
index a231679..20db7a3 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
@@ -2311,7 +2311,7 @@ static void dce_v11_0_crtc_load_lut(struct drm_crtc *crtc)
WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
}
-static int dce_v11_0_pick_dig_encoder(struct drm_encoder *encoder)
+static enum engine_id dce_v11_0_pick_engine(struct drm_encoder *encoder)
{
struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
@@ -2320,25 +2320,29 @@ static int dce_v11_0_pick_dig_encoder(struct drm_encoder *encoder)
switch (enc_id) {
case ENCODER_ID_INTERNAL_UNIPHY:
if (dig->linkb)
- return 1;
+ return ENGINE_ID_DIGB;
else
- return 0;
+ return ENGINE_ID_DIGA;
break;
case ENCODER_ID_INTERNAL_UNIPHY1:
if (dig->linkb)
- return 3;
+ return ENGINE_ID_DIGD;
else
- return 2;
+ return ENGINE_ID_DIGC;
break;
case ENCODER_ID_INTERNAL_UNIPHY2:
if (dig->linkb)
- return 5;
+ return ENGINE_ID_DIGF;
else
- return 4;
+ return ENGINE_ID_DIGE;
break;
case ENCODER_ID_INTERNAL_UNIPHY3:
- return 6;
+ return ENGINE_ID_DIGG;
break;
+ case ENCODER_ID_INTERNAL_KLDSCP_DAC1:
+ return ENGINE_ID_DACA;
+ case ENCODER_ID_INTERNAL_KLDSCP_DAC2:
+ return ENGINE_ID_DACB;
default:
DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_object_id.id);
return 0;
@@ -3488,15 +3492,16 @@ static void dce_v11_0_encoder_prepare(struct drm_encoder *encoder)
struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
+ amdgpu_encoder->engine_id = dce_v11_0_pick_engine(encoder);
+
if ((amdgpu_encoder->active_device &
(ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
(amdgpu_encoder_get_dp_bridge_encoder_id(encoder) !=
ENCODER_ID_UNKNOWN)) {
struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
if (dig) {
- dig->dig_encoder = dce_v11_0_pick_dig_encoder(encoder);
if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT)
- dig->afmt = adev->mode_info.afmt[dig->dig_encoder];
+ dig->afmt = adev->mode_info.afmt[amdgpu_encoder->engine_id];
}
}
@@ -3534,16 +3539,14 @@ static void dce_v11_0_encoder_commit(struct drm_encoder *encoder)
static void dce_v11_0_encoder_disable(struct drm_encoder *encoder)
{
struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
- struct amdgpu_encoder_atom_dig *dig;
amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
if (amdgpu_atombios_encoder_is_digital(encoder)) {
if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
dce_v11_0_afmt_enable(encoder, false);
- dig = amdgpu_encoder->enc_priv;
- dig->dig_encoder = -1;
}
+ amdgpu_encoder->engine_id = ENGINE_ID_UNKNOWN;
amdgpu_encoder->active_device = 0;
}
@@ -3669,6 +3672,7 @@ static void dce_v11_0_encoder_add(struct amdgpu_device *adev,
amdgpu_encoder->underscan_type = UNDERSCAN_OFF;
amdgpu_encoder->is_ext_encoder = false;
amdgpu_encoder->caps = caps;
+ amdgpu_encoder->engine_id = ENGINE_ID_UNKNOWN;
switch (encoder_object_id.id) {
case ENCODER_ID_INTERNAL_KLDSCP_DAC1:
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
index 6a53cde..9e48a7a 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
@@ -2286,33 +2286,38 @@ static void dce_v8_0_crtc_load_lut(struct drm_crtc *crtc)
ALPHA_CONTROL__CURSOR_ALPHA_BLND_ENA_MASK);
}
-static int dce_v8_0_pick_dig_encoder(struct drm_encoder *encoder)
+static enum engine_id dce_v8_0_pick_engine(struct drm_encoder *encoder)
{
struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
enum encoder_id enc_id = display_graphics_object_id_get_encoder_id(amdgpu_encoder->encoder_object_id);
+
switch (enc_id) {
case ENCODER_ID_INTERNAL_UNIPHY:
if (dig->linkb)
- return 1;
+ return ENGINE_ID_DIGB;
else
- return 0;
+ return ENGINE_ID_DIGA;
break;
case ENCODER_ID_INTERNAL_UNIPHY1:
if (dig->linkb)
- return 3;
+ return ENGINE_ID_DIGD;
else
- return 2;
+ return ENGINE_ID_DIGC;
break;
case ENCODER_ID_INTERNAL_UNIPHY2:
if (dig->linkb)
- return 5;
+ return ENGINE_ID_DIGF;
else
- return 4;
+ return ENGINE_ID_DIGE;
break;
case ENCODER_ID_INTERNAL_UNIPHY3:
- return 6;
+ return ENGINE_ID_DIGG;
break;
+ case ENCODER_ID_INTERNAL_KLDSCP_DAC1:
+ return ENGINE_ID_DACA;
+ case ENCODER_ID_INTERNAL_KLDSCP_DAC2:
+ return ENGINE_ID_DACB;
default:
DRM_ERROR("invalid encoder_id: 0x%x\n", enc_id);
return 0;
@@ -3476,15 +3481,16 @@ static void dce_v8_0_encoder_prepare(struct drm_encoder *encoder)
struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
+ amdgpu_encoder->engine_id = dce_v8_0_pick_engine(encoder);
+
if ((amdgpu_encoder->active_device &
(ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
(amdgpu_encoder_get_dp_bridge_encoder_id(encoder) !=
ENCODER_ID_UNKNOWN)) {
struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
if (dig) {
- dig->dig_encoder = dce_v8_0_pick_dig_encoder(encoder);
if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT)
- dig->afmt = adev->mode_info.afmt[dig->dig_encoder];
+ dig->afmt = adev->mode_info.afmt[amdgpu_encoder->engine_id];
}
}
@@ -3522,16 +3528,14 @@ static void dce_v8_0_encoder_commit(struct drm_encoder *encoder)
static void dce_v8_0_encoder_disable(struct drm_encoder *encoder)
{
struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
- struct amdgpu_encoder_atom_dig *dig;
amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
if (amdgpu_atombios_encoder_is_digital(encoder)) {
if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
dce_v8_0_afmt_enable(encoder, false);
- dig = amdgpu_encoder->enc_priv;
- dig->dig_encoder = -1;
}
+ amdgpu_encoder->engine_id = ENGINE_ID_UNKNOWN;
amdgpu_encoder->active_device = 0;
}
@@ -3656,6 +3660,7 @@ static void dce_v8_0_encoder_add(struct amdgpu_device *adev,
amdgpu_encoder->underscan_type = UNDERSCAN_OFF;
amdgpu_encoder->is_ext_encoder = false;
amdgpu_encoder->caps = caps;
+ amdgpu_encoder->engine_id = ENGINE_ID_UNKNOWN;
switch (encoder_object_id.id) {
case ENCODER_ID_INTERNAL_KLDSCP_DAC1:
--
2.5.5
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 2+ messages in thread