* [PATCH 1/3] drm/dp: Add definition for Display Control DPCD Registers capability size
[not found] <1461669918-4851-1-git-send-email-yetundex.adebisi@intel.com>
@ 2016-04-26 11:25 ` Yetunde Adebisi
0 siblings, 0 replies; 5+ messages in thread
From: Yetunde Adebisi @ 2016-04-26 11:25 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula, isg-gms, dri-devel
This is used when reading Display Control capability Registers on the sink
device.
cc: Jani Nikula <jani.nikula@intel.com>
cc: dri-devel@lists.freedesktop.org
Signed-off-by: Yetunde Adebisi <yetundex.adebisi@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
---
include/drm/drm_dp_helper.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 1252108..92d9a52 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -621,6 +621,7 @@ u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SI
#define DP_BRANCH_OUI_HEADER_SIZE 0xc
#define DP_RECEIVER_CAP_SIZE 0xf
#define EDP_PSR_RECEIVER_CAP_SIZE 2
+#define EDP_DISPLAY_CTL_CAP_SIZE 3
void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
--
1.9.3
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 5+ messages in thread
[parent not found: <1459865452-9138-1-git-send-email-yetundex.adebisi@intel.com>]
* [PATCH 1/3] drm/dp: Add definition for Display Control DPCD Registers capability size
[not found] <1459865452-9138-1-git-send-email-yetundex.adebisi@intel.com>
@ 2016-04-05 14:10 ` Yetunde Adebisi
0 siblings, 0 replies; 5+ messages in thread
From: Yetunde Adebisi @ 2016-04-05 14:10 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
This is used when reading Display Control capability Registers on the sink
device.
cc: dri-devel@lists.freedesktop.org
Signed-off-by: Yetunde Adebisi <yetundex.adebisi@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
---
include/drm/drm_dp_helper.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 1252108..92d9a52 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -621,6 +621,7 @@ u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SI
#define DP_BRANCH_OUI_HEADER_SIZE 0xc
#define DP_RECEIVER_CAP_SIZE 0xf
#define EDP_PSR_RECEIVER_CAP_SIZE 2
+#define EDP_DISPLAY_CTL_CAP_SIZE 3
void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
--
1.9.3
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 5+ messages in thread
[parent not found: <1459864227-8155-1-git-send-email-yetundex.adebisi@intel.com>]
* [PATCH 1/3] drm/dp: Add definition for Display Control DPCD Registers capability size
[not found] <1459864227-8155-1-git-send-email-yetundex.adebisi@intel.com>
@ 2016-04-05 13:50 ` Yetunde Adebisi
0 siblings, 0 replies; 5+ messages in thread
From: Yetunde Adebisi @ 2016-04-05 13:50 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula, isg-gms, dri-devel
This is used when reading Display Control capability Registers on the sink
device.
cc: Jani Nikula <jani.nikula@intel.com>
cc: dri-devel@lists.freedesktop.org
Signed-off-by: Yetunde Adebisi <yetundex.adebisi@intel.com>
---
include/drm/drm_dp_helper.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 1252108..92d9a52 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -621,6 +621,7 @@ u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SI
#define DP_BRANCH_OUI_HEADER_SIZE 0xc
#define DP_RECEIVER_CAP_SIZE 0xf
#define EDP_PSR_RECEIVER_CAP_SIZE 2
+#define EDP_DISPLAY_CTL_CAP_SIZE 3
void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
--
1.9.3
_______________________________________________
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dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 5+ messages in thread
[parent not found: <1459348041-28165-1-git-send-email-yetundex.adebisi@intel.com>]
* [PATCH 1/3] drm/dp: Add definition for Display Control DPCD Registers capability size
[not found] <1459348041-28165-1-git-send-email-yetundex.adebisi@intel.com>
@ 2016-03-30 14:27 ` Yetunde Adebisi
2016-03-31 7:04 ` Jani Nikula
0 siblings, 1 reply; 5+ messages in thread
From: Yetunde Adebisi @ 2016-03-30 14:27 UTC (permalink / raw)
To: intel-gfx; +Cc: Yetunde Adebisi, Jani Nikula, isg-gms, dri-devel
This is used when reading Display Control capability Registers on the sink
device.
cc: Jani Nikula <jani.nikula@intel.com>
cc: dri-devel@lists.freedesktop.org
Signed-off-by: Yetunde Adebisi <yetundex.adebisi@intel.com>
---
include/drm/drm_dp_helper.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 1252108..92d9a52 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -621,6 +621,7 @@ u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SI
#define DP_BRANCH_OUI_HEADER_SIZE 0xc
#define DP_RECEIVER_CAP_SIZE 0xf
#define EDP_PSR_RECEIVER_CAP_SIZE 2
+#define EDP_DISPLAY_CTL_CAP_SIZE 3
void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
--
1.9.3
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 5+ messages in thread* Re: [PATCH 1/3] drm/dp: Add definition for Display Control DPCD Registers capability size
2016-03-30 14:27 ` Yetunde Adebisi
@ 2016-03-31 7:04 ` Jani Nikula
0 siblings, 0 replies; 5+ messages in thread
From: Jani Nikula @ 2016-03-31 7:04 UTC (permalink / raw)
To: intel-gfx; +Cc: Yetunde Adebisi, isg-gms, dri-devel
On Wed, 30 Mar 2016, Yetunde Adebisi <yetundex.adebisi@intel.com> wrote:
> This is used when reading Display Control capability Registers on the sink
> device.
>
> cc: Jani Nikula <jani.nikula@intel.com>
> cc: dri-devel@lists.freedesktop.org
> Signed-off-by: Yetunde Adebisi <yetundex.adebisi@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> include/drm/drm_dp_helper.h | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> index 1252108..92d9a52 100644
> --- a/include/drm/drm_dp_helper.h
> +++ b/include/drm/drm_dp_helper.h
> @@ -621,6 +621,7 @@ u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SI
> #define DP_BRANCH_OUI_HEADER_SIZE 0xc
> #define DP_RECEIVER_CAP_SIZE 0xf
> #define EDP_PSR_RECEIVER_CAP_SIZE 2
> +#define EDP_DISPLAY_CTL_CAP_SIZE 3
>
> void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
> void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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2016-04-26 11:25 ` [PATCH 1/3] drm/dp: Add definition for Display Control DPCD Registers capability size Yetunde Adebisi
[not found] <1459865452-9138-1-git-send-email-yetundex.adebisi@intel.com>
2016-04-05 14:10 ` Yetunde Adebisi
[not found] <1459864227-8155-1-git-send-email-yetundex.adebisi@intel.com>
2016-04-05 13:50 ` Yetunde Adebisi
[not found] <1459348041-28165-1-git-send-email-yetundex.adebisi@intel.com>
2016-03-30 14:27 ` Yetunde Adebisi
2016-03-31 7:04 ` Jani Nikula
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