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From: Alex Deucher <alexdeucher@gmail.com>
To: dri-devel@lists.freedesktop.org
Cc: Alex Deucher <alexander.deucher@amd.com>
Subject: [PATCH] drm/amdgpu/gfx: add proper CG flags for fiji
Date: Mon,  2 May 2016 16:00:21 -0400	[thread overview]
Message-ID: <1462219259-29806-9-git-send-email-alexander.deucher@amd.com> (raw)
In-Reply-To: <1462219259-29806-1-git-send-email-alexander.deucher@amd.com>

We were already enabling these CG features, this uses
the standard interface for doing so.

Acked-by: Tom St Denis <tom.stdenis@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 82 ++++++++++++++++++++---------------
 drivers/gpu/drm/amd/amdgpu/vi.c       |  9 +++-
 2 files changed, 56 insertions(+), 35 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 842e4ad..4adccd1 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -4282,7 +4282,7 @@ static int gfx_v8_0_set_powergating_state(void *handle,
 }
 
 static void fiji_send_serdes_cmd(struct amdgpu_device *adev,
-		uint32_t reg_addr, uint32_t cmd)
+				     uint32_t reg_addr, uint32_t cmd)
 {
 	uint32_t data;
 
@@ -4312,23 +4312,29 @@ static void fiji_send_serdes_cmd(struct amdgpu_device *adev,
 }
 
 static void fiji_update_medium_grain_clock_gating(struct amdgpu_device *adev,
-		bool enable)
+						  bool enable)
 {
 	uint32_t temp, data;
 
 	/* It is disabled by HW by default */
-	if (enable) {
-		/* 1 - RLC memory Light sleep */
-		temp = data = RREG32(mmRLC_MEM_SLP_CNTL);
-		data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
-		if (temp != data)
-			WREG32(mmRLC_MEM_SLP_CNTL, data);
+	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
+		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
+			if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) {
+				/* 1 - RLC memory Light sleep */
+				temp = data = RREG32(mmRLC_MEM_SLP_CNTL);
+				data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
+				if (temp != data)
+					WREG32(mmRLC_MEM_SLP_CNTL, data);
+			}
 
-		/* 2 - CP memory Light sleep */
-		temp = data = RREG32(mmCP_MEM_SLP_CNTL);
-		data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
-		if (temp != data)
-			WREG32(mmCP_MEM_SLP_CNTL, data);
+			if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
+				/* 2 - CP memory Light sleep */
+				temp = data = RREG32(mmCP_MEM_SLP_CNTL);
+				data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
+				if (temp != data)
+					WREG32(mmCP_MEM_SLP_CNTL, data);
+			}
+		}
 
 		/* 3 - RLC_CGTT_MGCG_OVERRIDE */
 		temp = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
@@ -4346,17 +4352,21 @@ static void fiji_update_medium_grain_clock_gating(struct amdgpu_device *adev,
 		/* 5 - clear mgcg override */
 		fiji_send_serdes_cmd(adev, BPM_REG_MGCG_OVERRIDE, CLE_BPM_SERDES_CMD);
 
-		/* 6 - Enable CGTS(Tree Shade) MGCG /MGLS */
-		temp = data = RREG32(mmCGTS_SM_CTRL_REG);
-		data &= ~(CGTS_SM_CTRL_REG__SM_MODE_MASK);
-		data |= (0x2 << CGTS_SM_CTRL_REG__SM_MODE__SHIFT);
-		data |= CGTS_SM_CTRL_REG__SM_MODE_ENABLE_MASK;
-		data &= ~CGTS_SM_CTRL_REG__OVERRIDE_MASK;
-		data &= ~CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK;
-		data |= CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN_MASK;
-		data |= (0x96 << CGTS_SM_CTRL_REG__ON_MONITOR_ADD__SHIFT);
-		if (temp != data)
-			WREG32(mmCGTS_SM_CTRL_REG, data);
+		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGTS) {
+			/* 6 - Enable CGTS(Tree Shade) MGCG /MGLS */
+			temp = data = RREG32(mmCGTS_SM_CTRL_REG);
+			data &= ~(CGTS_SM_CTRL_REG__SM_MODE_MASK);
+			data |= (0x2 << CGTS_SM_CTRL_REG__SM_MODE__SHIFT);
+			data |= CGTS_SM_CTRL_REG__SM_MODE_ENABLE_MASK;
+			data &= ~CGTS_SM_CTRL_REG__OVERRIDE_MASK;
+			if ((adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) &&
+			    (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGTS_LS))
+				data &= ~CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK;
+			data |= CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN_MASK;
+			data |= (0x96 << CGTS_SM_CTRL_REG__ON_MONITOR_ADD__SHIFT);
+			if (temp != data)
+				WREG32(mmCGTS_SM_CTRL_REG, data);
+		}
 		udelay(50);
 
 		/* 7 - wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
@@ -4406,13 +4416,13 @@ static void fiji_update_medium_grain_clock_gating(struct amdgpu_device *adev,
 }
 
 static void fiji_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
-		bool enable)
+						  bool enable)
 {
 	uint32_t temp, temp1, data, data1;
 
 	temp = data = RREG32(mmRLC_CGCG_CGLS_CTRL);
 
-	if (enable) {
+	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
 		/* 1 enable cntx_empty_int_enable/cntx_busy_int_enable/
 		 * Cmp_busy/GFX_Idle interrupts
 		 */
@@ -4438,14 +4448,18 @@ static void fiji_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
 		/* 5 - enable cgcg */
 		data |= RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
 
-		/* enable cgls*/
-		data |= RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
+		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) {
+			/* enable cgls*/
+			data |= RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
 
-		temp1 = data1 =	RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
-		data1 &= ~RLC_CGTT_MGCG_OVERRIDE__CGLS_MASK;
+			temp1 = data1 =	RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
+			data1 &= ~RLC_CGTT_MGCG_OVERRIDE__CGLS_MASK;
 
-		if (temp1 != data1)
-			WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data1);
+			if (temp1 != data1)
+				WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data1);
+		} else {
+			data &= ~RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
+		}
 
 		if (temp != data)
 			WREG32(mmRLC_CGCG_CGLS_CTRL, data);
@@ -4480,13 +4494,13 @@ static void fiji_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
 
 		/* disable cgcg, cgls should be disabled too. */
 		data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK |
-				RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
+			  RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
 		if (temp != data)
 			WREG32(mmRLC_CGCG_CGLS_CTRL, data);
 	}
 }
 static int fiji_update_gfx_clock_gating(struct amdgpu_device *adev,
-		bool enable)
+					bool enable)
 {
 	if (enable) {
 		/* CGCG/CGLS should be enabled after MGCG/MGLS/TS(CG/LS)
diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
index 3964790..8d9b03f 100644
--- a/drivers/gpu/drm/amd/amdgpu/vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
@@ -1076,7 +1076,14 @@ static int vi_common_early_init(void *handle)
 		adev->external_rev_id = 0x1;
 		break;
 	case CHIP_FIJI:
-		adev->cg_flags = 0;
+		adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
+			AMD_CG_SUPPORT_GFX_MGLS |
+			AMD_CG_SUPPORT_GFX_RLC_LS |
+			AMD_CG_SUPPORT_GFX_CP_LS |
+			AMD_CG_SUPPORT_GFX_CGTS |
+			AMD_CG_SUPPORT_GFX_CGTS_LS |
+			AMD_CG_SUPPORT_GFX_CGCG |
+			AMD_CG_SUPPORT_GFX_CGLS;
 		adev->pg_flags = 0;
 		adev->external_rev_id = adev->rev_id + 0x3c;
 		break;
-- 
2.5.5

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  parent reply	other threads:[~2016-05-02 20:01 UTC|newest]

Thread overview: 47+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-05-02 20:00 Misc amdgpu patches Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amdgpu/dce11: fix vertical bars appear on monitor Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amd/amdgpu: Add SW clock gating support to UVD 5 and 6 Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amd/amdgpu: Enable clockgating for UVD5 on Tonga Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amd/amdgpu: Enable clockgating in UVD6 for Stoney Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amd/powerplay: use min_clock_in_sr for deep sleep feature Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amdgpu: Set PFLIP_SUBMITTED for crtc after address update Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amdgpu: add new CG flag for ROM clockgating Alex Deucher
2016-05-02 20:00 ` Alex Deucher [this message]
2016-05-02 20:00 ` [PATCH] drm/amdgpu/sdma: add proper CG flags for fiji Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amdgpu/common: " Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amdgpu/gmc: " Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amdgpu/gfx8: rename send_serdes_cmd Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amdgpu/gfx: adjust gfx_v8_0_send_serdes_cmd for ST Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amdgpu: add a new set of rlc function pointers Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amdgpu/gfx: rework fiji cg functions so they can be shared Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amdgpu: enable gfx clockgating for CZ Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amdgpu: enable gfx clockgating for ST (v2) Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amdgpu/vi: rename fiji cg functions Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amdgpu: enable gmc clockgating for CZ Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amdgpu: enable gmc clockgating for ST Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amdgpu/sdma: rename fiji cg functions Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amdgpu: enable sdma clockgating on CZ Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amdgpu: enable sdma clockgating on ST Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amdgpu: add ELM/BAF DCE11 configs (v2) Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amdgpu: add ELM/BAF support to dce_v11_0_pick_pll (v2) Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amd/powerplay: enable some feature for baffin/ellesmere. (v2) Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amd/powerplay: add fan control mode interface for baffin Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amd/powerplay: parameter updates according to SMC Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amd/powerplay: fix issue that get wrong reference clock value Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amd/powerplay: Fix a bug for enabling ACDC gpio interrupt Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amd/powerplay: update vce power gate state for baffin Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amdgpu: fix memory leak in CGS (FW info) Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amd/powerplay: return 0 when interface not implement on some asic Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amd/powerplay: fix some initialize error on polaris10 Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amd/powerplay: fix bug dpm can't work when resume back on Polaris Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amd/powerplay: fix fan speed percent setting error on Polaris10 Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amd/powerplay: add dpm force multiple levels on cz/tonga/fiji/polaris (v2) Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amd/powerplay: revise caching the soft pptable and add it's size Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amd/powerplay: revise reading/writing pptable on Fiji Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amd/powerplay: revise reading/writing pptable on Tonga Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amd/powerplay: revise reading/writing pptable on Polaris10 Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amd/amdgpu: Drop print_status callbacks Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amd/amdgpu: Add debugfs entries for smc/didt/pcie Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/powerplay: add missing clockgating callback for tonga Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amdgpu/fiji: set UVD CG state when enabling UVD DPM (v2) Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amdgpu/uvd6: add bypass support for fiji (v3) Alex Deucher

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