From: Alex Deucher <alexdeucher@gmail.com>
To: dri-devel@lists.freedesktop.org
Cc: Alex Deucher <alexander.deucher@amd.com>,
Vitaly Prosyak <vitaly.prosyak@amd.com>
Subject: [PATCH] drm/amdgpu/dce11: fix vertical bars appear on monitor
Date: Mon, 2 May 2016 16:00:14 -0400 [thread overview]
Message-ID: <1462219259-29806-2-git-send-email-alexander.deucher@amd.com> (raw)
In-Reply-To: <1462219259-29806-1-git-send-email-alexander.deucher@amd.com>
From: Vitaly Prosyak <vitaly.prosyak@amd.com>
Fixed mc stop and resume hardware programming sequence.
Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 65 +++-------------------------------
1 file changed, 5 insertions(+), 60 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
index e9ccc6b..89aab0a 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
@@ -565,35 +565,14 @@ static void dce_v11_0_stop_mc_access(struct amdgpu_device *adev,
crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),
CRTC_CONTROL, CRTC_MASTER_EN);
if (crtc_enabled) {
-#if 0
- u32 frame_count;
- int j;
-
+#if 1
save->crtc_enabled[i] = true;
tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]);
if (REG_GET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN) == 0) {
- amdgpu_display_vblank_wait(adev, i);
- WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
+ /*it is correct only for RGB ; black is 0*/
+ WREG32(mmCRTC_BLANK_DATA_COLOR + crtc_offsets[i], 0);
tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 1);
WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
- WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
- }
- /* wait for the next frame */
- frame_count = amdgpu_display_vblank_get_counter(adev, i);
- for (j = 0; j < adev->usec_timeout; j++) {
- if (amdgpu_display_vblank_get_counter(adev, i) != frame_count)
- break;
- udelay(1);
- }
- tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]);
- if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK) == 0) {
- tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 1);
- WREG32(mmGRPH_UPDATE + crtc_offsets[i], tmp);
- }
- tmp = RREG32(mmCRTC_MASTER_UPDATE_LOCK + crtc_offsets[i]);
- if (REG_GET_FIELD(tmp, CRTC_MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK) == 0) {
- tmp = REG_SET_FIELD(tmp, CRTC_MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK, 1);
- WREG32(mmCRTC_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
}
#else
/* XXX this is a hack to avoid strange behavior with EFI on certain systems */
@@ -614,54 +593,20 @@ static void dce_v11_0_stop_mc_access(struct amdgpu_device *adev,
static void dce_v11_0_resume_mc_access(struct amdgpu_device *adev,
struct amdgpu_mode_mc_save *save)
{
- u32 tmp, frame_count;
- int i, j;
+ u32 tmp;
+ int i;
/* update crtc base addresses */
for (i = 0; i < adev->mode_info.num_crtc; i++) {
WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
upper_32_bits(adev->mc.vram_start));
- WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
- upper_32_bits(adev->mc.vram_start));
WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i],
(u32)adev->mc.vram_start);
- WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i],
- (u32)adev->mc.vram_start);
if (save->crtc_enabled[i]) {
- tmp = RREG32(mmCRTC_MASTER_UPDATE_MODE + crtc_offsets[i]);
- if (REG_GET_FIELD(tmp, CRTC_MASTER_UPDATE_MODE, MASTER_UPDATE_MODE) != 3) {
- tmp = REG_SET_FIELD(tmp, CRTC_MASTER_UPDATE_MODE, MASTER_UPDATE_MODE, 3);
- WREG32(mmCRTC_MASTER_UPDATE_MODE + crtc_offsets[i], tmp);
- }
- tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]);
- if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK)) {
- tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 0);
- WREG32(mmGRPH_UPDATE + crtc_offsets[i], tmp);
- }
- tmp = RREG32(mmCRTC_MASTER_UPDATE_LOCK + crtc_offsets[i]);
- if (REG_GET_FIELD(tmp, CRTC_MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK)) {
- tmp = REG_SET_FIELD(tmp, CRTC_MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK, 0);
- WREG32(mmCRTC_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
- }
- for (j = 0; j < adev->usec_timeout; j++) {
- tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]);
- if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_SURFACE_UPDATE_PENDING) == 0)
- break;
- udelay(1);
- }
tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]);
tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 0);
- WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
- WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
- /* wait for the next frame */
- frame_count = amdgpu_display_vblank_get_counter(adev, i);
- for (j = 0; j < adev->usec_timeout; j++) {
- if (amdgpu_display_vblank_get_counter(adev, i) != frame_count)
- break;
- udelay(1);
- }
}
}
--
2.5.5
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next prev parent reply other threads:[~2016-05-02 20:01 UTC|newest]
Thread overview: 47+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-05-02 20:00 Misc amdgpu patches Alex Deucher
2016-05-02 20:00 ` Alex Deucher [this message]
2016-05-02 20:00 ` [PATCH] drm/amd/amdgpu: Add SW clock gating support to UVD 5 and 6 Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amd/amdgpu: Enable clockgating for UVD5 on Tonga Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amd/amdgpu: Enable clockgating in UVD6 for Stoney Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amd/powerplay: use min_clock_in_sr for deep sleep feature Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amdgpu: Set PFLIP_SUBMITTED for crtc after address update Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amdgpu: add new CG flag for ROM clockgating Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amdgpu/gfx: add proper CG flags for fiji Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amdgpu/sdma: " Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amdgpu/common: " Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amdgpu/gmc: " Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amdgpu/gfx8: rename send_serdes_cmd Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amdgpu/gfx: adjust gfx_v8_0_send_serdes_cmd for ST Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amdgpu: add a new set of rlc function pointers Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amdgpu/gfx: rework fiji cg functions so they can be shared Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amdgpu: enable gfx clockgating for CZ Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amdgpu: enable gfx clockgating for ST (v2) Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amdgpu/vi: rename fiji cg functions Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amdgpu: enable gmc clockgating for CZ Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amdgpu: enable gmc clockgating for ST Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amdgpu/sdma: rename fiji cg functions Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amdgpu: enable sdma clockgating on CZ Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amdgpu: enable sdma clockgating on ST Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amdgpu: add ELM/BAF DCE11 configs (v2) Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amdgpu: add ELM/BAF support to dce_v11_0_pick_pll (v2) Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amd/powerplay: enable some feature for baffin/ellesmere. (v2) Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amd/powerplay: add fan control mode interface for baffin Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amd/powerplay: parameter updates according to SMC Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amd/powerplay: fix issue that get wrong reference clock value Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amd/powerplay: Fix a bug for enabling ACDC gpio interrupt Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amd/powerplay: update vce power gate state for baffin Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amdgpu: fix memory leak in CGS (FW info) Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amd/powerplay: return 0 when interface not implement on some asic Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amd/powerplay: fix some initialize error on polaris10 Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amd/powerplay: fix bug dpm can't work when resume back on Polaris Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amd/powerplay: fix fan speed percent setting error on Polaris10 Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amd/powerplay: add dpm force multiple levels on cz/tonga/fiji/polaris (v2) Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amd/powerplay: revise caching the soft pptable and add it's size Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amd/powerplay: revise reading/writing pptable on Fiji Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amd/powerplay: revise reading/writing pptable on Tonga Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amd/powerplay: revise reading/writing pptable on Polaris10 Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amd/amdgpu: Drop print_status callbacks Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amd/amdgpu: Add debugfs entries for smc/didt/pcie Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/powerplay: add missing clockgating callback for tonga Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amdgpu/fiji: set UVD CG state when enabling UVD DPM (v2) Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amdgpu/uvd6: add bypass support for fiji (v3) Alex Deucher
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