* Misc amdgpu patches
@ 2016-05-02 20:00 Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amdgpu/dce11: fix vertical bars appear on monitor Alex Deucher
` (45 more replies)
0 siblings, 46 replies; 47+ messages in thread
From: Alex Deucher @ 2016-05-02 20:00 UTC (permalink / raw)
To: dri-devel; +Cc: Alex Deucher
This is just a bunch of patches that I've been carrying in my -wip tree for a
while. Some are minor updates to previous versions I've sent out.
- Fixes to non-DAL modesetting code for Polaris
- Clockgating fixes and enablement
- Misc powerplay bug fixes
- Misc bug fixes and cleanups
I meant to send these out last week, but time got away from me.
Alex
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* [PATCH] drm/amdgpu/dce11: fix vertical bars appear on monitor
2016-05-02 20:00 Misc amdgpu patches Alex Deucher
@ 2016-05-02 20:00 ` Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amd/amdgpu: Add SW clock gating support to UVD 5 and 6 Alex Deucher
` (44 subsequent siblings)
45 siblings, 0 replies; 47+ messages in thread
From: Alex Deucher @ 2016-05-02 20:00 UTC (permalink / raw)
To: dri-devel; +Cc: Alex Deucher, Vitaly Prosyak
From: Vitaly Prosyak <vitaly.prosyak@amd.com>
Fixed mc stop and resume hardware programming sequence.
Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 65 +++-------------------------------
1 file changed, 5 insertions(+), 60 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
index e9ccc6b..89aab0a 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
@@ -565,35 +565,14 @@ static void dce_v11_0_stop_mc_access(struct amdgpu_device *adev,
crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),
CRTC_CONTROL, CRTC_MASTER_EN);
if (crtc_enabled) {
-#if 0
- u32 frame_count;
- int j;
-
+#if 1
save->crtc_enabled[i] = true;
tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]);
if (REG_GET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN) == 0) {
- amdgpu_display_vblank_wait(adev, i);
- WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
+ /*it is correct only for RGB ; black is 0*/
+ WREG32(mmCRTC_BLANK_DATA_COLOR + crtc_offsets[i], 0);
tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 1);
WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
- WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
- }
- /* wait for the next frame */
- frame_count = amdgpu_display_vblank_get_counter(adev, i);
- for (j = 0; j < adev->usec_timeout; j++) {
- if (amdgpu_display_vblank_get_counter(adev, i) != frame_count)
- break;
- udelay(1);
- }
- tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]);
- if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK) == 0) {
- tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 1);
- WREG32(mmGRPH_UPDATE + crtc_offsets[i], tmp);
- }
- tmp = RREG32(mmCRTC_MASTER_UPDATE_LOCK + crtc_offsets[i]);
- if (REG_GET_FIELD(tmp, CRTC_MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK) == 0) {
- tmp = REG_SET_FIELD(tmp, CRTC_MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK, 1);
- WREG32(mmCRTC_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
}
#else
/* XXX this is a hack to avoid strange behavior with EFI on certain systems */
@@ -614,54 +593,20 @@ static void dce_v11_0_stop_mc_access(struct amdgpu_device *adev,
static void dce_v11_0_resume_mc_access(struct amdgpu_device *adev,
struct amdgpu_mode_mc_save *save)
{
- u32 tmp, frame_count;
- int i, j;
+ u32 tmp;
+ int i;
/* update crtc base addresses */
for (i = 0; i < adev->mode_info.num_crtc; i++) {
WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
upper_32_bits(adev->mc.vram_start));
- WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
- upper_32_bits(adev->mc.vram_start));
WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i],
(u32)adev->mc.vram_start);
- WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i],
- (u32)adev->mc.vram_start);
if (save->crtc_enabled[i]) {
- tmp = RREG32(mmCRTC_MASTER_UPDATE_MODE + crtc_offsets[i]);
- if (REG_GET_FIELD(tmp, CRTC_MASTER_UPDATE_MODE, MASTER_UPDATE_MODE) != 3) {
- tmp = REG_SET_FIELD(tmp, CRTC_MASTER_UPDATE_MODE, MASTER_UPDATE_MODE, 3);
- WREG32(mmCRTC_MASTER_UPDATE_MODE + crtc_offsets[i], tmp);
- }
- tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]);
- if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK)) {
- tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 0);
- WREG32(mmGRPH_UPDATE + crtc_offsets[i], tmp);
- }
- tmp = RREG32(mmCRTC_MASTER_UPDATE_LOCK + crtc_offsets[i]);
- if (REG_GET_FIELD(tmp, CRTC_MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK)) {
- tmp = REG_SET_FIELD(tmp, CRTC_MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK, 0);
- WREG32(mmCRTC_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
- }
- for (j = 0; j < adev->usec_timeout; j++) {
- tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]);
- if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_SURFACE_UPDATE_PENDING) == 0)
- break;
- udelay(1);
- }
tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]);
tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 0);
- WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
- WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
- /* wait for the next frame */
- frame_count = amdgpu_display_vblank_get_counter(adev, i);
- for (j = 0; j < adev->usec_timeout; j++) {
- if (amdgpu_display_vblank_get_counter(adev, i) != frame_count)
- break;
- udelay(1);
- }
}
}
--
2.5.5
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^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH] drm/amd/amdgpu: Add SW clock gating support to UVD 5 and 6
2016-05-02 20:00 Misc amdgpu patches Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amdgpu/dce11: fix vertical bars appear on monitor Alex Deucher
@ 2016-05-02 20:00 ` Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amd/amdgpu: Enable clockgating for UVD5 on Tonga Alex Deucher
` (43 subsequent siblings)
45 siblings, 0 replies; 47+ messages in thread
From: Alex Deucher @ 2016-05-02 20:00 UTC (permalink / raw)
To: dri-devel; +Cc: Tom St Denis, Alex Deucher
From: Tom St Denis <tom.stdenis@amd.com>
This patch adds support for software clock gating to UVD 5
and UVD 6 blocks with a preliminary commented out hardware
gating routine.
Currently hardware gating does not work so it's not activated.
Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c | 115 ++++++++++++++
drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 281 ++++++++++++++--------------------
2 files changed, 232 insertions(+), 164 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
index 16476d8..de459c8 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
@@ -31,6 +31,7 @@
#include "uvd/uvd_5_0_sh_mask.h"
#include "oss/oss_2_0_d.h"
#include "oss/oss_2_0_sh_mask.h"
+#include "vi.h"
static void uvd_v5_0_set_ring_funcs(struct amdgpu_device *adev);
static void uvd_v5_0_set_irq_funcs(struct amdgpu_device *adev);
@@ -754,14 +755,128 @@ static int uvd_v5_0_process_interrupt(struct amdgpu_device *adev,
return 0;
}
+static void uvd_v5_0_set_sw_clock_gating(struct amdgpu_device *adev)
+{
+ uint32_t data, data1, data2, suvd_flags;
+
+ data = RREG32(mmUVD_CGC_CTRL);
+ data1 = RREG32(mmUVD_SUVD_CGC_GATE);
+ data2 = RREG32(mmUVD_SUVD_CGC_CTRL);
+
+ data &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK |
+ UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK);
+
+ suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK |
+ UVD_SUVD_CGC_GATE__SIT_MASK |
+ UVD_SUVD_CGC_GATE__SMP_MASK |
+ UVD_SUVD_CGC_GATE__SCM_MASK |
+ UVD_SUVD_CGC_GATE__SDB_MASK;
+
+ data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK |
+ (1 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_GATE_DLY_TIMER)) |
+ (4 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_OFF_DELAY));
+
+ data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK |
+ UVD_CGC_CTRL__UDEC_CM_MODE_MASK |
+ UVD_CGC_CTRL__UDEC_IT_MODE_MASK |
+ UVD_CGC_CTRL__UDEC_DB_MODE_MASK |
+ UVD_CGC_CTRL__UDEC_MP_MODE_MASK |
+ UVD_CGC_CTRL__SYS_MODE_MASK |
+ UVD_CGC_CTRL__UDEC_MODE_MASK |
+ UVD_CGC_CTRL__MPEG2_MODE_MASK |
+ UVD_CGC_CTRL__REGS_MODE_MASK |
+ UVD_CGC_CTRL__RBC_MODE_MASK |
+ UVD_CGC_CTRL__LMI_MC_MODE_MASK |
+ UVD_CGC_CTRL__LMI_UMC_MODE_MASK |
+ UVD_CGC_CTRL__IDCT_MODE_MASK |
+ UVD_CGC_CTRL__MPRD_MODE_MASK |
+ UVD_CGC_CTRL__MPC_MODE_MASK |
+ UVD_CGC_CTRL__LBSI_MODE_MASK |
+ UVD_CGC_CTRL__LRBBM_MODE_MASK |
+ UVD_CGC_CTRL__WCB_MODE_MASK |
+ UVD_CGC_CTRL__VCPU_MODE_MASK |
+ UVD_CGC_CTRL__JPEG_MODE_MASK |
+ UVD_CGC_CTRL__SCPU_MODE_MASK);
+ data2 &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK |
+ UVD_SUVD_CGC_CTRL__SIT_MODE_MASK |
+ UVD_SUVD_CGC_CTRL__SMP_MODE_MASK |
+ UVD_SUVD_CGC_CTRL__SCM_MODE_MASK |
+ UVD_SUVD_CGC_CTRL__SDB_MODE_MASK);
+ data1 |= suvd_flags;
+
+ WREG32(mmUVD_CGC_CTRL, data);
+ WREG32(mmUVD_CGC_GATE, 0);
+ WREG32(mmUVD_SUVD_CGC_GATE, data1);
+ WREG32(mmUVD_SUVD_CGC_CTRL, data2);
+}
+
+#if 0
+static void uvd_v5_0_set_hw_clock_gating(struct amdgpu_device *adev)
+{
+ uint32_t data, data1, cgc_flags, suvd_flags;
+
+ data = RREG32(mmUVD_CGC_GATE);
+ data1 = RREG32(mmUVD_SUVD_CGC_GATE);
+
+ cgc_flags = UVD_CGC_GATE__SYS_MASK |
+ UVD_CGC_GATE__UDEC_MASK |
+ UVD_CGC_GATE__MPEG2_MASK |
+ UVD_CGC_GATE__RBC_MASK |
+ UVD_CGC_GATE__LMI_MC_MASK |
+ UVD_CGC_GATE__IDCT_MASK |
+ UVD_CGC_GATE__MPRD_MASK |
+ UVD_CGC_GATE__MPC_MASK |
+ UVD_CGC_GATE__LBSI_MASK |
+ UVD_CGC_GATE__LRBBM_MASK |
+ UVD_CGC_GATE__UDEC_RE_MASK |
+ UVD_CGC_GATE__UDEC_CM_MASK |
+ UVD_CGC_GATE__UDEC_IT_MASK |
+ UVD_CGC_GATE__UDEC_DB_MASK |
+ UVD_CGC_GATE__UDEC_MP_MASK |
+ UVD_CGC_GATE__WCB_MASK |
+ UVD_CGC_GATE__VCPU_MASK |
+ UVD_CGC_GATE__SCPU_MASK;
+
+ suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK |
+ UVD_SUVD_CGC_GATE__SIT_MASK |
+ UVD_SUVD_CGC_GATE__SMP_MASK |
+ UVD_SUVD_CGC_GATE__SCM_MASK |
+ UVD_SUVD_CGC_GATE__SDB_MASK;
+
+ data |= cgc_flags;
+ data1 |= suvd_flags;
+
+ WREG32(mmUVD_CGC_GATE, data);
+ WREG32(mmUVD_SUVD_CGC_GATE, data1);
+}
+#endif
+
static int uvd_v5_0_set_clockgating_state(void *handle,
enum amd_clockgating_state state)
{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
+ static int curstate = -1;
if (!(adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG))
return 0;
+ if (curstate == state)
+ return 0;
+
+ curstate = state;
+ if (enable) {
+ /* disable HW gating and enable Sw gating */
+ uvd_v5_0_set_sw_clock_gating(adev);
+ } else {
+ /* wait for STATUS to clear */
+ if (uvd_v5_0_wait_for_idle(handle))
+ return -EBUSY;
+
+ /* enable HW gates because UVD is idle */
+/* uvd_v5_0_set_hw_clock_gating(adev); */
+ }
+
return 0;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
index d493791..372d70a 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
@@ -31,11 +31,13 @@
#include "uvd/uvd_6_0_sh_mask.h"
#include "oss/oss_2_0_d.h"
#include "oss/oss_2_0_sh_mask.h"
+#include "vi.h"
static void uvd_v6_0_set_ring_funcs(struct amdgpu_device *adev);
static void uvd_v6_0_set_irq_funcs(struct amdgpu_device *adev);
static int uvd_v6_0_start(struct amdgpu_device *adev);
static void uvd_v6_0_stop(struct amdgpu_device *adev);
+static void uvd_v6_0_set_sw_clock_gating(struct amdgpu_device *adev);
/**
* uvd_v6_0_ring_get_rptr - get read pointer
@@ -284,6 +286,7 @@ static void uvd_v6_0_mc_resume(struct amdgpu_device *adev)
WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
}
+#if 0
static void cz_set_uvd_clock_gating_branches(struct amdgpu_device *adev,
bool enable)
{
@@ -360,157 +363,7 @@ static void cz_set_uvd_clock_gating_branches(struct amdgpu_device *adev,
WREG32(mmUVD_CGC_GATE, data);
WREG32(mmUVD_SUVD_CGC_GATE, data1);
}
-
-static void tonga_set_uvd_clock_gating_branches(struct amdgpu_device *adev,
- bool enable)
-{
- u32 data, data1;
-
- data = RREG32(mmUVD_CGC_GATE);
- data1 = RREG32(mmUVD_SUVD_CGC_GATE);
- if (enable) {
- data |= UVD_CGC_GATE__SYS_MASK |
- UVD_CGC_GATE__UDEC_MASK |
- UVD_CGC_GATE__MPEG2_MASK |
- UVD_CGC_GATE__RBC_MASK |
- UVD_CGC_GATE__LMI_MC_MASK |
- UVD_CGC_GATE__IDCT_MASK |
- UVD_CGC_GATE__MPRD_MASK |
- UVD_CGC_GATE__MPC_MASK |
- UVD_CGC_GATE__LBSI_MASK |
- UVD_CGC_GATE__LRBBM_MASK |
- UVD_CGC_GATE__UDEC_RE_MASK |
- UVD_CGC_GATE__UDEC_CM_MASK |
- UVD_CGC_GATE__UDEC_IT_MASK |
- UVD_CGC_GATE__UDEC_DB_MASK |
- UVD_CGC_GATE__UDEC_MP_MASK |
- UVD_CGC_GATE__WCB_MASK |
- UVD_CGC_GATE__VCPU_MASK |
- UVD_CGC_GATE__SCPU_MASK;
- data1 |= UVD_SUVD_CGC_GATE__SRE_MASK |
- UVD_SUVD_CGC_GATE__SIT_MASK |
- UVD_SUVD_CGC_GATE__SMP_MASK |
- UVD_SUVD_CGC_GATE__SCM_MASK |
- UVD_SUVD_CGC_GATE__SDB_MASK;
- } else {
- data &= ~(UVD_CGC_GATE__SYS_MASK |
- UVD_CGC_GATE__UDEC_MASK |
- UVD_CGC_GATE__MPEG2_MASK |
- UVD_CGC_GATE__RBC_MASK |
- UVD_CGC_GATE__LMI_MC_MASK |
- UVD_CGC_GATE__LMI_UMC_MASK |
- UVD_CGC_GATE__IDCT_MASK |
- UVD_CGC_GATE__MPRD_MASK |
- UVD_CGC_GATE__MPC_MASK |
- UVD_CGC_GATE__LBSI_MASK |
- UVD_CGC_GATE__LRBBM_MASK |
- UVD_CGC_GATE__UDEC_RE_MASK |
- UVD_CGC_GATE__UDEC_CM_MASK |
- UVD_CGC_GATE__UDEC_IT_MASK |
- UVD_CGC_GATE__UDEC_DB_MASK |
- UVD_CGC_GATE__UDEC_MP_MASK |
- UVD_CGC_GATE__WCB_MASK |
- UVD_CGC_GATE__VCPU_MASK |
- UVD_CGC_GATE__SCPU_MASK);
- data1 &= ~(UVD_SUVD_CGC_GATE__SRE_MASK |
- UVD_SUVD_CGC_GATE__SIT_MASK |
- UVD_SUVD_CGC_GATE__SMP_MASK |
- UVD_SUVD_CGC_GATE__SCM_MASK |
- UVD_SUVD_CGC_GATE__SDB_MASK);
- }
- WREG32(mmUVD_CGC_GATE, data);
- WREG32(mmUVD_SUVD_CGC_GATE, data1);
-}
-
-static void uvd_v6_0_set_uvd_dynamic_clock_mode(struct amdgpu_device *adev,
- bool swmode)
-{
- u32 data, data1 = 0, data2;
-
- /* Always un-gate UVD REGS bit */
- data = RREG32(mmUVD_CGC_GATE);
- data &= ~(UVD_CGC_GATE__REGS_MASK);
- WREG32(mmUVD_CGC_GATE, data);
-
- data = RREG32(mmUVD_CGC_CTRL);
- data &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK |
- UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK);
- data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK |
- 1 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_GATE_DLY_TIMER) |
- 4 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_OFF_DELAY);
-
- data2 = RREG32(mmUVD_SUVD_CGC_CTRL);
- if (swmode) {
- data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK |
- UVD_CGC_CTRL__UDEC_CM_MODE_MASK |
- UVD_CGC_CTRL__UDEC_IT_MODE_MASK |
- UVD_CGC_CTRL__UDEC_DB_MODE_MASK |
- UVD_CGC_CTRL__UDEC_MP_MODE_MASK |
- UVD_CGC_CTRL__SYS_MODE_MASK |
- UVD_CGC_CTRL__UDEC_MODE_MASK |
- UVD_CGC_CTRL__MPEG2_MODE_MASK |
- UVD_CGC_CTRL__REGS_MODE_MASK |
- UVD_CGC_CTRL__RBC_MODE_MASK |
- UVD_CGC_CTRL__LMI_MC_MODE_MASK |
- UVD_CGC_CTRL__LMI_UMC_MODE_MASK |
- UVD_CGC_CTRL__IDCT_MODE_MASK |
- UVD_CGC_CTRL__MPRD_MODE_MASK |
- UVD_CGC_CTRL__MPC_MODE_MASK |
- UVD_CGC_CTRL__LBSI_MODE_MASK |
- UVD_CGC_CTRL__LRBBM_MODE_MASK |
- UVD_CGC_CTRL__WCB_MODE_MASK |
- UVD_CGC_CTRL__VCPU_MODE_MASK |
- UVD_CGC_CTRL__JPEG_MODE_MASK |
- UVD_CGC_CTRL__SCPU_MODE_MASK);
- data1 |= UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN_MASK |
- UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN_MASK;
- data1 &= ~UVD_CGC_CTRL2__GATER_DIV_ID_MASK;
- data1 |= 7 << REG_FIELD_SHIFT(UVD_CGC_CTRL2, GATER_DIV_ID);
- data2 &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK |
- UVD_SUVD_CGC_CTRL__SIT_MODE_MASK |
- UVD_SUVD_CGC_CTRL__SMP_MODE_MASK |
- UVD_SUVD_CGC_CTRL__SCM_MODE_MASK |
- UVD_SUVD_CGC_CTRL__SDB_MODE_MASK);
- } else {
- data |= UVD_CGC_CTRL__UDEC_RE_MODE_MASK |
- UVD_CGC_CTRL__UDEC_CM_MODE_MASK |
- UVD_CGC_CTRL__UDEC_IT_MODE_MASK |
- UVD_CGC_CTRL__UDEC_DB_MODE_MASK |
- UVD_CGC_CTRL__UDEC_MP_MODE_MASK |
- UVD_CGC_CTRL__SYS_MODE_MASK |
- UVD_CGC_CTRL__UDEC_MODE_MASK |
- UVD_CGC_CTRL__MPEG2_MODE_MASK |
- UVD_CGC_CTRL__REGS_MODE_MASK |
- UVD_CGC_CTRL__RBC_MODE_MASK |
- UVD_CGC_CTRL__LMI_MC_MODE_MASK |
- UVD_CGC_CTRL__LMI_UMC_MODE_MASK |
- UVD_CGC_CTRL__IDCT_MODE_MASK |
- UVD_CGC_CTRL__MPRD_MODE_MASK |
- UVD_CGC_CTRL__MPC_MODE_MASK |
- UVD_CGC_CTRL__LBSI_MODE_MASK |
- UVD_CGC_CTRL__LRBBM_MODE_MASK |
- UVD_CGC_CTRL__WCB_MODE_MASK |
- UVD_CGC_CTRL__VCPU_MODE_MASK |
- UVD_CGC_CTRL__SCPU_MODE_MASK;
- data2 |= UVD_SUVD_CGC_CTRL__SRE_MODE_MASK |
- UVD_SUVD_CGC_CTRL__SIT_MODE_MASK |
- UVD_SUVD_CGC_CTRL__SMP_MODE_MASK |
- UVD_SUVD_CGC_CTRL__SCM_MODE_MASK |
- UVD_SUVD_CGC_CTRL__SDB_MODE_MASK;
- }
- WREG32(mmUVD_CGC_CTRL, data);
- WREG32(mmUVD_SUVD_CGC_CTRL, data2);
-
- data = RREG32_UVD_CTX(ixUVD_CGC_CTRL2);
- data &= ~(REG_FIELD_MASK(UVD_CGC_CTRL2, DYN_OCLK_RAMP_EN) |
- REG_FIELD_MASK(UVD_CGC_CTRL2, DYN_RCLK_RAMP_EN) |
- REG_FIELD_MASK(UVD_CGC_CTRL2, GATER_DIV_ID));
- data1 &= (REG_FIELD_MASK(UVD_CGC_CTRL2, DYN_OCLK_RAMP_EN) |
- REG_FIELD_MASK(UVD_CGC_CTRL2, DYN_RCLK_RAMP_EN) |
- REG_FIELD_MASK(UVD_CGC_CTRL2, GATER_DIV_ID));
- data |= data1;
- WREG32_UVD_CTX(ixUVD_CGC_CTRL2, data);
-}
+#endif
/**
* uvd_v6_0_start - start UVD block
@@ -538,11 +391,7 @@ static int uvd_v6_0_start(struct amdgpu_device *adev)
/* Set dynamic clock gating in S/W control mode */
if (adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG) {
- if (adev->flags & AMD_IS_APU)
- cz_set_uvd_clock_gating_branches(adev, false);
- else
- tonga_set_uvd_clock_gating_branches(adev, false);
- uvd_v6_0_set_uvd_dynamic_clock_mode(adev, true);
+ uvd_v6_0_set_sw_clock_gating(adev);
} else {
/* disable clock gating */
uint32_t data = RREG32(mmUVD_CGC_CTRL);
@@ -978,25 +827,129 @@ static int uvd_v6_0_process_interrupt(struct amdgpu_device *adev,
return 0;
}
+static void uvd_v6_0_set_sw_clock_gating(struct amdgpu_device *adev)
+{
+ uint32_t data, data1, data2, suvd_flags;
+
+ data = RREG32(mmUVD_CGC_CTRL);
+ data1 = RREG32(mmUVD_SUVD_CGC_GATE);
+ data2 = RREG32(mmUVD_SUVD_CGC_CTRL);
+
+ data &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK |
+ UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK);
+
+ suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK |
+ UVD_SUVD_CGC_GATE__SIT_MASK |
+ UVD_SUVD_CGC_GATE__SMP_MASK |
+ UVD_SUVD_CGC_GATE__SCM_MASK |
+ UVD_SUVD_CGC_GATE__SDB_MASK;
+
+ data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK |
+ (1 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_GATE_DLY_TIMER)) |
+ (4 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_OFF_DELAY));
+
+ data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK |
+ UVD_CGC_CTRL__UDEC_CM_MODE_MASK |
+ UVD_CGC_CTRL__UDEC_IT_MODE_MASK |
+ UVD_CGC_CTRL__UDEC_DB_MODE_MASK |
+ UVD_CGC_CTRL__UDEC_MP_MODE_MASK |
+ UVD_CGC_CTRL__SYS_MODE_MASK |
+ UVD_CGC_CTRL__UDEC_MODE_MASK |
+ UVD_CGC_CTRL__MPEG2_MODE_MASK |
+ UVD_CGC_CTRL__REGS_MODE_MASK |
+ UVD_CGC_CTRL__RBC_MODE_MASK |
+ UVD_CGC_CTRL__LMI_MC_MODE_MASK |
+ UVD_CGC_CTRL__LMI_UMC_MODE_MASK |
+ UVD_CGC_CTRL__IDCT_MODE_MASK |
+ UVD_CGC_CTRL__MPRD_MODE_MASK |
+ UVD_CGC_CTRL__MPC_MODE_MASK |
+ UVD_CGC_CTRL__LBSI_MODE_MASK |
+ UVD_CGC_CTRL__LRBBM_MODE_MASK |
+ UVD_CGC_CTRL__WCB_MODE_MASK |
+ UVD_CGC_CTRL__VCPU_MODE_MASK |
+ UVD_CGC_CTRL__JPEG_MODE_MASK |
+ UVD_CGC_CTRL__SCPU_MODE_MASK |
+ UVD_CGC_CTRL__JPEG2_MODE_MASK);
+ data2 &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK |
+ UVD_SUVD_CGC_CTRL__SIT_MODE_MASK |
+ UVD_SUVD_CGC_CTRL__SMP_MODE_MASK |
+ UVD_SUVD_CGC_CTRL__SCM_MODE_MASK |
+ UVD_SUVD_CGC_CTRL__SDB_MODE_MASK);
+ data1 |= suvd_flags;
+
+ WREG32(mmUVD_CGC_CTRL, data);
+ WREG32(mmUVD_CGC_GATE, 0);
+ WREG32(mmUVD_SUVD_CGC_GATE, data1);
+ WREG32(mmUVD_SUVD_CGC_CTRL, data2);
+}
+
+#if 0
+static void uvd_v6_0_set_hw_clock_gating(struct amdgpu_device *adev)
+{
+ uint32_t data, data1, cgc_flags, suvd_flags;
+
+ data = RREG32(mmUVD_CGC_GATE);
+ data1 = RREG32(mmUVD_SUVD_CGC_GATE);
+
+ cgc_flags = UVD_CGC_GATE__SYS_MASK |
+ UVD_CGC_GATE__UDEC_MASK |
+ UVD_CGC_GATE__MPEG2_MASK |
+ UVD_CGC_GATE__RBC_MASK |
+ UVD_CGC_GATE__LMI_MC_MASK |
+ UVD_CGC_GATE__IDCT_MASK |
+ UVD_CGC_GATE__MPRD_MASK |
+ UVD_CGC_GATE__MPC_MASK |
+ UVD_CGC_GATE__LBSI_MASK |
+ UVD_CGC_GATE__LRBBM_MASK |
+ UVD_CGC_GATE__UDEC_RE_MASK |
+ UVD_CGC_GATE__UDEC_CM_MASK |
+ UVD_CGC_GATE__UDEC_IT_MASK |
+ UVD_CGC_GATE__UDEC_DB_MASK |
+ UVD_CGC_GATE__UDEC_MP_MASK |
+ UVD_CGC_GATE__WCB_MASK |
+ UVD_CGC_GATE__VCPU_MASK |
+ UVD_CGC_GATE__SCPU_MASK |
+ UVD_CGC_GATE__JPEG_MASK |
+ UVD_CGC_GATE__JPEG2_MASK;
+
+ suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK |
+ UVD_SUVD_CGC_GATE__SIT_MASK |
+ UVD_SUVD_CGC_GATE__SMP_MASK |
+ UVD_SUVD_CGC_GATE__SCM_MASK |
+ UVD_SUVD_CGC_GATE__SDB_MASK;
+
+ data |= cgc_flags;
+ data1 |= suvd_flags;
+
+ WREG32(mmUVD_CGC_GATE, data);
+ WREG32(mmUVD_SUVD_CGC_GATE, data1);
+}
+#endif
+
static int uvd_v6_0_set_clockgating_state(void *handle,
enum amd_clockgating_state state)
{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
+ static int curstate = -1;
if (!(adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG))
return 0;
+ if (curstate == state)
+ return 0;
+
+ curstate = state;
if (enable) {
- if (adev->flags & AMD_IS_APU)
- cz_set_uvd_clock_gating_branches(adev, enable);
- else
- tonga_set_uvd_clock_gating_branches(adev, enable);
- uvd_v6_0_set_uvd_dynamic_clock_mode(adev, true);
+ /* disable HW gating and enable Sw gating */
+ uvd_v6_0_set_sw_clock_gating(adev);
} else {
- uint32_t data = RREG32(mmUVD_CGC_CTRL);
- data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
- WREG32(mmUVD_CGC_CTRL, data);
+ /* wait for STATUS to clear */
+ if (uvd_v6_0_wait_for_idle(handle))
+ return -EBUSY;
+
+ /* enable HW gates because UVD is idle */
+/* uvd_v6_0_set_hw_clock_gating(adev); */
}
return 0;
--
2.5.5
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^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH] drm/amd/amdgpu: Enable clockgating for UVD5 on Tonga
2016-05-02 20:00 Misc amdgpu patches Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amdgpu/dce11: fix vertical bars appear on monitor Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amd/amdgpu: Add SW clock gating support to UVD 5 and 6 Alex Deucher
@ 2016-05-02 20:00 ` Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amd/amdgpu: Enable clockgating in UVD6 for Stoney Alex Deucher
` (42 subsequent siblings)
45 siblings, 0 replies; 47+ messages in thread
From: Alex Deucher @ 2016-05-02 20:00 UTC (permalink / raw)
To: dri-devel; +Cc: Tom St Denis, Alex Deucher
From: Tom St Denis <tom.stdenis@amd.com>
This patch enables clock gating for the UVD5 block with
Tonga.
Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/vi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
index a145556..5c39470 100644
--- a/drivers/gpu/drm/amd/amdgpu/vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
@@ -1081,7 +1081,7 @@ static int vi_common_early_init(void *handle)
adev->external_rev_id = adev->rev_id + 0x3c;
break;
case CHIP_TONGA:
- adev->cg_flags = 0;
+ adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG;
adev->pg_flags = 0;
adev->external_rev_id = adev->rev_id + 0x14;
break;
--
2.5.5
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^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH] drm/amd/amdgpu: Enable clockgating in UVD6 for Stoney
2016-05-02 20:00 Misc amdgpu patches Alex Deucher
` (2 preceding siblings ...)
2016-05-02 20:00 ` [PATCH] drm/amd/amdgpu: Enable clockgating for UVD5 on Tonga Alex Deucher
@ 2016-05-02 20:00 ` Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amd/powerplay: use min_clock_in_sr for deep sleep feature Alex Deucher
` (41 subsequent siblings)
45 siblings, 0 replies; 47+ messages in thread
From: Alex Deucher @ 2016-05-02 20:00 UTC (permalink / raw)
To: dri-devel; +Cc: Tom St Denis, Alex Deucher
From: Tom St Denis <tom.stdenis@amd.com>
This patch enables clockgating for the UVD6 block in Stoney.
Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/vi.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
index 5c39470..3964790 100644
--- a/drivers/gpu/drm/amd/amdgpu/vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
@@ -1086,11 +1086,15 @@ static int vi_common_early_init(void *handle)
adev->external_rev_id = adev->rev_id + 0x14;
break;
case CHIP_CARRIZO:
- case CHIP_STONEY:
adev->cg_flags = 0;
adev->pg_flags = 0;
adev->external_rev_id = adev->rev_id + 0x1;
break;
+ case CHIP_STONEY:
+ adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG;
+ adev->pg_flags = 0;
+ adev->external_rev_id = adev->rev_id + 0x1;
+ break;
default:
/* FIXME: not supported yet */
return -EINVAL;
--
2.5.5
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^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH] drm/amd/powerplay: use min_clock_in_sr for deep sleep feature.
2016-05-02 20:00 Misc amdgpu patches Alex Deucher
` (3 preceding siblings ...)
2016-05-02 20:00 ` [PATCH] drm/amd/amdgpu: Enable clockgating in UVD6 for Stoney Alex Deucher
@ 2016-05-02 20:00 ` Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amdgpu: Set PFLIP_SUBMITTED for crtc after address update Alex Deucher
` (40 subsequent siblings)
45 siblings, 0 replies; 47+ messages in thread
From: Alex Deucher @ 2016-05-02 20:00 UTC (permalink / raw)
To: dri-devel; +Cc: Alex Deucher, Rex Zhu
From: Rex Zhu <Rex.Zhu@amd.com>
This comes from the display handling code.
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c | 50 ++++++++++++++----------
1 file changed, 30 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
index 89f31bc..025a3ed 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
@@ -1885,6 +1885,23 @@ static int fiji_get_dependency_volt_by_clk(struct pp_hwmgr *hwmgr,
return 0;
}
+
+static uint8_t fiji_get_sleep_divider_id_from_clock(struct pp_hwmgr *hwmgr,
+ uint32_t clock, uint32_t clock_insr)
+{
+ uint8_t i;
+ uint32_t temp;
+ uint32_t min = clock_insr > 2500 ? clock_insr : 2500;
+
+ PP_ASSERT_WITH_CODE((clock >= min), "Engine clock can't satisfy stutter requirement!", return 0);
+ for (i = FIJI_MAX_DEEPSLEEP_DIVIDER_ID; ; i--) {
+ temp = clock / (1UL << i);
+
+ if (temp >= min || i == 0)
+ break;
+ }
+ return i;
+}
/**
* Populates single SMC SCLK structure using the provided engine clock
*
@@ -1928,17 +1945,13 @@ static int fiji_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
threshold = clock * data->fast_watermark_threshold / 100;
- /*
- * TODO: get minimum clocks from dal configaration
- * PECI_GetMinClockSettings(hwmgr->pPECI, &minClocks);
- */
- /* data->DisplayTiming.minClockInSR = minClocks.engineClockInSR; */
- /* get level->DeepSleepDivId
- if (phm_cap_enabled(hwmgr->platformDescriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep))
- {
- level->DeepSleepDivId = PhwFiji_GetSleepDividerIdFromClock(hwmgr, clock, minClocks.engineClockInSR);
- } */
+ data->display_timing.min_clock_in_sr = hwmgr->display_config.min_core_set_clock_in_sr;
+
+ if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep))
+ level->DeepSleepDivId = fiji_get_sleep_divider_id_from_clock(hwmgr, clock,
+ hwmgr->display_config.min_core_set_clock_in_sr);
+
/* Default to slow, highest DPM level will be
* set to PPSMC_DISPLAY_WATERMARK_LOW later.
@@ -4066,7 +4079,6 @@ static int fiji_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, cons
struct fiji_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table);
uint32_t mclk = fiji_ps->performance_levels
[fiji_ps->performance_level_count - 1].memory_clock;
- struct PP_Clocks min_clocks = {0};
uint32_t i;
struct cgs_display_info info = {0};
@@ -4080,10 +4092,8 @@ static int fiji_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, cons
if (i >= sclk_table->count)
data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
else {
- /* TODO: Check SCLK in DAL's minimum clocks
- * in case DeepSleep divider update is required.
- */
- if(data->display_timing.min_clock_in_sr != min_clocks.engineClockInSR)
+ if(data->display_timing.min_clock_in_sr !=
+ hwmgr->display_config.min_core_set_clock_in_sr)
data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_SCLK;
}
@@ -5252,12 +5262,12 @@ bool fiji_check_smc_update_required_for_display_configuration(struct pp_hwmgr *h
if (data->display_timing.num_existing_displays != info.display_count)
is_update_required = true;
-/* TO DO NEED TO GET DEEP SLEEP CLOCK FROM DAL
- if (phm_cap_enabled(hwmgr->hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) {
- cgs_get_min_clock_settings(hwmgr->device, &min_clocks);
- if(min_clocks.engineClockInSR != data->display_timing.minClockInSR)
+
+ if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) {
+ if(hwmgr->display_config.min_core_set_clock_in_sr != data->display_timing.min_clock_in_sr)
is_update_required = true;
-*/
+ }
+
return is_update_required;
}
--
2.5.5
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^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH] drm/amdgpu: Set PFLIP_SUBMITTED for crtc after address update
2016-05-02 20:00 Misc amdgpu patches Alex Deucher
` (4 preceding siblings ...)
2016-05-02 20:00 ` [PATCH] drm/amd/powerplay: use min_clock_in_sr for deep sleep feature Alex Deucher
@ 2016-05-02 20:00 ` Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amdgpu: add new CG flag for ROM clockgating Alex Deucher
` (39 subsequent siblings)
45 siblings, 0 replies; 47+ messages in thread
From: Alex Deucher @ 2016-05-02 20:00 UTC (permalink / raw)
To: dri-devel; +Cc: Alex Deucher, Andrey Grodzovsky
From: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
Also add some pflip debug prints.
This change allows us to wait on pflip status until the new surface address
is actually submitted to the register.
This reverts ed3020e923240829dcdfd3343f6e91dc02c63775
drm/amdgpu: Move MMIO flip out of spinlocked region
The original change assumed DAL will aquire locks inside DAL
implemetion of page_flip callback which eventaully didn't happen.
This moves the flip before status update which makes sense for the
non-DAL code pathes as well.
Signed-off-by: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 14 +++++++++++---
1 file changed, 11 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
index 3fb405b..0535095 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
@@ -131,12 +131,17 @@ static void amdgpu_flip_work_func(struct work_struct *__work)
vblank->framedur_ns / 1000,
vblank->linedur_ns / 1000, stat, vpos, hpos);
- /* set the flip status */
+ /* Do the flip (mmio) */
+ adev->mode_info.funcs->page_flip(adev, work->crtc_id, work->base);
+
+ /* Set the flip status */
amdgpuCrtc->pflip_status = AMDGPU_FLIP_SUBMITTED;
spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
- /* Do the flip (mmio) */
- adev->mode_info.funcs->page_flip(adev, work->crtc_id, work->base);
+
+ DRM_DEBUG_DRIVER("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_SUBMITTED, work: %p,\n",
+ amdgpuCrtc->crtc_id, amdgpuCrtc, work);
+
}
/*
@@ -252,6 +257,9 @@ int amdgpu_crtc_page_flip(struct drm_crtc *crtc,
amdgpu_crtc->pflip_status = AMDGPU_FLIP_PENDING;
amdgpu_crtc->pflip_works = work;
+
+ DRM_DEBUG_DRIVER("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_PENDING, work: %p,\n",
+ amdgpu_crtc->crtc_id, amdgpu_crtc, work);
/* update crtc fb */
crtc->primary->fb = fb;
spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
--
2.5.5
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https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH] drm/amdgpu: add new CG flag for ROM clockgating
2016-05-02 20:00 Misc amdgpu patches Alex Deucher
` (5 preceding siblings ...)
2016-05-02 20:00 ` [PATCH] drm/amdgpu: Set PFLIP_SUBMITTED for crtc after address update Alex Deucher
@ 2016-05-02 20:00 ` Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amdgpu/gfx: add proper CG flags for fiji Alex Deucher
` (38 subsequent siblings)
45 siblings, 0 replies; 47+ messages in thread
From: Alex Deucher @ 2016-05-02 20:00 UTC (permalink / raw)
To: dri-devel; +Cc: Alex Deucher
Acked-by: Tom St Denis <tom.stdenis@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/include/amd_shared.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/include/amd_shared.h b/drivers/gpu/drm/amd/include/amd_shared.h
index 04e4090..f8afe53 100644
--- a/drivers/gpu/drm/amd/include/amd_shared.h
+++ b/drivers/gpu/drm/amd/include/amd_shared.h
@@ -104,6 +104,7 @@ enum amd_powergating_state {
#define AMD_CG_SUPPORT_VCE_MGCG (1 << 14)
#define AMD_CG_SUPPORT_HDP_LS (1 << 15)
#define AMD_CG_SUPPORT_HDP_MGCG (1 << 16)
+#define AMD_CG_SUPPORT_ROM_MGCG (1 << 17)
/* PG flags */
#define AMD_PG_SUPPORT_GFX_PG (1 << 0)
--
2.5.5
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^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH] drm/amdgpu/gfx: add proper CG flags for fiji
2016-05-02 20:00 Misc amdgpu patches Alex Deucher
` (6 preceding siblings ...)
2016-05-02 20:00 ` [PATCH] drm/amdgpu: add new CG flag for ROM clockgating Alex Deucher
@ 2016-05-02 20:00 ` Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amdgpu/sdma: " Alex Deucher
` (37 subsequent siblings)
45 siblings, 0 replies; 47+ messages in thread
From: Alex Deucher @ 2016-05-02 20:00 UTC (permalink / raw)
To: dri-devel; +Cc: Alex Deucher
We were already enabling these CG features, this uses
the standard interface for doing so.
Acked-by: Tom St Denis <tom.stdenis@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 82 ++++++++++++++++++++---------------
drivers/gpu/drm/amd/amdgpu/vi.c | 9 +++-
2 files changed, 56 insertions(+), 35 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 842e4ad..4adccd1 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -4282,7 +4282,7 @@ static int gfx_v8_0_set_powergating_state(void *handle,
}
static void fiji_send_serdes_cmd(struct amdgpu_device *adev,
- uint32_t reg_addr, uint32_t cmd)
+ uint32_t reg_addr, uint32_t cmd)
{
uint32_t data;
@@ -4312,23 +4312,29 @@ static void fiji_send_serdes_cmd(struct amdgpu_device *adev,
}
static void fiji_update_medium_grain_clock_gating(struct amdgpu_device *adev,
- bool enable)
+ bool enable)
{
uint32_t temp, data;
/* It is disabled by HW by default */
- if (enable) {
- /* 1 - RLC memory Light sleep */
- temp = data = RREG32(mmRLC_MEM_SLP_CNTL);
- data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
- if (temp != data)
- WREG32(mmRLC_MEM_SLP_CNTL, data);
+ if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
+ if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
+ if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) {
+ /* 1 - RLC memory Light sleep */
+ temp = data = RREG32(mmRLC_MEM_SLP_CNTL);
+ data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
+ if (temp != data)
+ WREG32(mmRLC_MEM_SLP_CNTL, data);
+ }
- /* 2 - CP memory Light sleep */
- temp = data = RREG32(mmCP_MEM_SLP_CNTL);
- data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
- if (temp != data)
- WREG32(mmCP_MEM_SLP_CNTL, data);
+ if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
+ /* 2 - CP memory Light sleep */
+ temp = data = RREG32(mmCP_MEM_SLP_CNTL);
+ data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
+ if (temp != data)
+ WREG32(mmCP_MEM_SLP_CNTL, data);
+ }
+ }
/* 3 - RLC_CGTT_MGCG_OVERRIDE */
temp = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
@@ -4346,17 +4352,21 @@ static void fiji_update_medium_grain_clock_gating(struct amdgpu_device *adev,
/* 5 - clear mgcg override */
fiji_send_serdes_cmd(adev, BPM_REG_MGCG_OVERRIDE, CLE_BPM_SERDES_CMD);
- /* 6 - Enable CGTS(Tree Shade) MGCG /MGLS */
- temp = data = RREG32(mmCGTS_SM_CTRL_REG);
- data &= ~(CGTS_SM_CTRL_REG__SM_MODE_MASK);
- data |= (0x2 << CGTS_SM_CTRL_REG__SM_MODE__SHIFT);
- data |= CGTS_SM_CTRL_REG__SM_MODE_ENABLE_MASK;
- data &= ~CGTS_SM_CTRL_REG__OVERRIDE_MASK;
- data &= ~CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK;
- data |= CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN_MASK;
- data |= (0x96 << CGTS_SM_CTRL_REG__ON_MONITOR_ADD__SHIFT);
- if (temp != data)
- WREG32(mmCGTS_SM_CTRL_REG, data);
+ if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGTS) {
+ /* 6 - Enable CGTS(Tree Shade) MGCG /MGLS */
+ temp = data = RREG32(mmCGTS_SM_CTRL_REG);
+ data &= ~(CGTS_SM_CTRL_REG__SM_MODE_MASK);
+ data |= (0x2 << CGTS_SM_CTRL_REG__SM_MODE__SHIFT);
+ data |= CGTS_SM_CTRL_REG__SM_MODE_ENABLE_MASK;
+ data &= ~CGTS_SM_CTRL_REG__OVERRIDE_MASK;
+ if ((adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) &&
+ (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGTS_LS))
+ data &= ~CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK;
+ data |= CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN_MASK;
+ data |= (0x96 << CGTS_SM_CTRL_REG__ON_MONITOR_ADD__SHIFT);
+ if (temp != data)
+ WREG32(mmCGTS_SM_CTRL_REG, data);
+ }
udelay(50);
/* 7 - wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
@@ -4406,13 +4416,13 @@ static void fiji_update_medium_grain_clock_gating(struct amdgpu_device *adev,
}
static void fiji_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
- bool enable)
+ bool enable)
{
uint32_t temp, temp1, data, data1;
temp = data = RREG32(mmRLC_CGCG_CGLS_CTRL);
- if (enable) {
+ if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
/* 1 enable cntx_empty_int_enable/cntx_busy_int_enable/
* Cmp_busy/GFX_Idle interrupts
*/
@@ -4438,14 +4448,18 @@ static void fiji_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
/* 5 - enable cgcg */
data |= RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
- /* enable cgls*/
- data |= RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
+ if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) {
+ /* enable cgls*/
+ data |= RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
- temp1 = data1 = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
- data1 &= ~RLC_CGTT_MGCG_OVERRIDE__CGLS_MASK;
+ temp1 = data1 = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
+ data1 &= ~RLC_CGTT_MGCG_OVERRIDE__CGLS_MASK;
- if (temp1 != data1)
- WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data1);
+ if (temp1 != data1)
+ WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data1);
+ } else {
+ data &= ~RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
+ }
if (temp != data)
WREG32(mmRLC_CGCG_CGLS_CTRL, data);
@@ -4480,13 +4494,13 @@ static void fiji_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
/* disable cgcg, cgls should be disabled too. */
data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK |
- RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
+ RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
if (temp != data)
WREG32(mmRLC_CGCG_CGLS_CTRL, data);
}
}
static int fiji_update_gfx_clock_gating(struct amdgpu_device *adev,
- bool enable)
+ bool enable)
{
if (enable) {
/* CGCG/CGLS should be enabled after MGCG/MGLS/TS(CG/LS)
diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
index 3964790..8d9b03f 100644
--- a/drivers/gpu/drm/amd/amdgpu/vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
@@ -1076,7 +1076,14 @@ static int vi_common_early_init(void *handle)
adev->external_rev_id = 0x1;
break;
case CHIP_FIJI:
- adev->cg_flags = 0;
+ adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
+ AMD_CG_SUPPORT_GFX_MGLS |
+ AMD_CG_SUPPORT_GFX_RLC_LS |
+ AMD_CG_SUPPORT_GFX_CP_LS |
+ AMD_CG_SUPPORT_GFX_CGTS |
+ AMD_CG_SUPPORT_GFX_CGTS_LS |
+ AMD_CG_SUPPORT_GFX_CGCG |
+ AMD_CG_SUPPORT_GFX_CGLS;
adev->pg_flags = 0;
adev->external_rev_id = adev->rev_id + 0x3c;
break;
--
2.5.5
_______________________________________________
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dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH] drm/amdgpu/sdma: add proper CG flags for fiji
2016-05-02 20:00 Misc amdgpu patches Alex Deucher
` (7 preceding siblings ...)
2016-05-02 20:00 ` [PATCH] drm/amdgpu/gfx: add proper CG flags for fiji Alex Deucher
@ 2016-05-02 20:00 ` Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amdgpu/common: " Alex Deucher
` (36 subsequent siblings)
45 siblings, 0 replies; 47+ messages in thread
From: Alex Deucher @ 2016-05-02 20:00 UTC (permalink / raw)
To: dri-devel; +Cc: Alex Deucher
We were already enabling these CG features, this uses
the standard interface for doing so.
Acked-by: Tom St Denis <tom.stdenis@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/vi.c | 4 +++-
2 files changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
index a78f13e..739365d 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
@@ -1464,7 +1464,7 @@ static void fiji_update_sdma_medium_grain_clock_gating(
{
uint32_t temp, data;
- if (enable) {
+ if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
temp = data = RREG32(mmSDMA0_CLK_CTRL);
data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
@@ -1524,7 +1524,7 @@ static void fiji_update_sdma_medium_grain_light_sleep(
{
uint32_t temp, data;
- if (enable) {
+ if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
temp = data = RREG32(mmSDMA0_POWER_CNTL);
data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
index 8d9b03f..5759504 100644
--- a/drivers/gpu/drm/amd/amdgpu/vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
@@ -1083,7 +1083,9 @@ static int vi_common_early_init(void *handle)
AMD_CG_SUPPORT_GFX_CGTS |
AMD_CG_SUPPORT_GFX_CGTS_LS |
AMD_CG_SUPPORT_GFX_CGCG |
- AMD_CG_SUPPORT_GFX_CGLS;
+ AMD_CG_SUPPORT_GFX_CGLS |
+ AMD_CG_SUPPORT_SDMA_MGCG |
+ AMD_CG_SUPPORT_SDMA_LS;
adev->pg_flags = 0;
adev->external_rev_id = adev->rev_id + 0x3c;
break;
--
2.5.5
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dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH] drm/amdgpu/common: add proper CG flags for fiji
2016-05-02 20:00 Misc amdgpu patches Alex Deucher
` (8 preceding siblings ...)
2016-05-02 20:00 ` [PATCH] drm/amdgpu/sdma: " Alex Deucher
@ 2016-05-02 20:00 ` Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amdgpu/gmc: " Alex Deucher
` (35 subsequent siblings)
45 siblings, 0 replies; 47+ messages in thread
From: Alex Deucher @ 2016-05-02 20:00 UTC (permalink / raw)
To: dri-devel; +Cc: Alex Deucher
We were already enabling these CG features, this uses
the standard interface for doing so.
Acked-by: Tom St Denis <tom.stdenis@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/vi.c | 22 +++++++++++++---------
1 file changed, 13 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
index 5759504..ea9edf4 100644
--- a/drivers/gpu/drm/amd/amdgpu/vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
@@ -1085,7 +1085,11 @@ static int vi_common_early_init(void *handle)
AMD_CG_SUPPORT_GFX_CGCG |
AMD_CG_SUPPORT_GFX_CGLS |
AMD_CG_SUPPORT_SDMA_MGCG |
- AMD_CG_SUPPORT_SDMA_LS;
+ AMD_CG_SUPPORT_SDMA_LS |
+ AMD_CG_SUPPORT_BIF_LS |
+ AMD_CG_SUPPORT_HDP_MGCG |
+ AMD_CG_SUPPORT_HDP_LS |
+ AMD_CG_SUPPORT_ROM_MGCG;
adev->pg_flags = 0;
adev->external_rev_id = adev->rev_id + 0x3c;
break;
@@ -1188,13 +1192,13 @@ static int vi_common_soft_reset(void *handle)
}
static void fiji_update_bif_medium_grain_light_sleep(struct amdgpu_device *adev,
- bool enable)
+ bool enable)
{
uint32_t temp, data;
temp = data = RREG32_PCIE(ixPCIE_CNTL2);
- if (enable)
+ if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS))
data |= PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
PCIE_CNTL2__MST_MEM_LS_EN_MASK |
PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK;
@@ -1208,13 +1212,13 @@ static void fiji_update_bif_medium_grain_light_sleep(struct amdgpu_device *adev,
}
static void fiji_update_hdp_medium_grain_clock_gating(struct amdgpu_device *adev,
- bool enable)
+ bool enable)
{
uint32_t temp, data;
temp = data = RREG32(mmHDP_HOST_PATH_CNTL);
- if (enable)
+ if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG))
data &= ~HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS_MASK;
else
data |= HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS_MASK;
@@ -1230,7 +1234,7 @@ static void fiji_update_hdp_light_sleep(struct amdgpu_device *adev,
temp = data = RREG32(mmHDP_MEM_POWER_LS);
- if (enable)
+ if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
data |= HDP_MEM_POWER_LS__LS_ENABLE_MASK;
else
data &= ~HDP_MEM_POWER_LS__LS_ENABLE_MASK;
@@ -1240,13 +1244,13 @@ static void fiji_update_hdp_light_sleep(struct amdgpu_device *adev,
}
static void fiji_update_rom_medium_grain_clock_gating(struct amdgpu_device *adev,
- bool enable)
+ bool enable)
{
uint32_t temp, data;
temp = data = RREG32_SMC(ixCGTT_ROM_CLK_CTRL0);
- if (enable)
+ if (enable && (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG))
data &= ~(CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK);
else
@@ -1258,7 +1262,7 @@ static void fiji_update_rom_medium_grain_clock_gating(struct amdgpu_device *adev
}
static int vi_common_set_clockgating_state(void *handle,
- enum amd_clockgating_state state)
+ enum amd_clockgating_state state)
{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
--
2.5.5
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dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH] drm/amdgpu/gmc: add proper CG flags for fiji
2016-05-02 20:00 Misc amdgpu patches Alex Deucher
` (9 preceding siblings ...)
2016-05-02 20:00 ` [PATCH] drm/amdgpu/common: " Alex Deucher
@ 2016-05-02 20:00 ` Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amdgpu/gfx8: rename send_serdes_cmd Alex Deucher
` (34 subsequent siblings)
45 siblings, 0 replies; 47+ messages in thread
From: Alex Deucher @ 2016-05-02 20:00 UTC (permalink / raw)
To: dri-devel; +Cc: Alex Deucher
We were already enabling these CG features, this uses
the standard interface for doing so.
Acked-by: Tom St Denis <tom.stdenis@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 8 ++++----
drivers/gpu/drm/amd/amdgpu/vi.c | 4 +++-
2 files changed, 7 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
index 02deb32..1e85b8f 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
@@ -1310,11 +1310,11 @@ static int gmc_v8_0_process_interrupt(struct amdgpu_device *adev,
}
static void fiji_update_mc_medium_grain_clock_gating(struct amdgpu_device *adev,
- bool enable)
+ bool enable)
{
uint32_t data;
- if (enable) {
+ if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) {
data = RREG32(mmMC_HUB_MISC_HUB_CG);
data |= MC_HUB_MISC_HUB_CG__ENABLE_MASK;
WREG32(mmMC_HUB_MISC_HUB_CG, data);
@@ -1390,11 +1390,11 @@ static void fiji_update_mc_medium_grain_clock_gating(struct amdgpu_device *adev,
}
static void fiji_update_mc_light_sleep(struct amdgpu_device *adev,
- bool enable)
+ bool enable)
{
uint32_t data;
- if (enable) {
+ if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS)) {
data = RREG32(mmMC_HUB_MISC_HUB_CG);
data |= MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK;
WREG32(mmMC_HUB_MISC_HUB_CG, data);
diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
index ea9edf4..16b2a29 100644
--- a/drivers/gpu/drm/amd/amdgpu/vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
@@ -1089,7 +1089,9 @@ static int vi_common_early_init(void *handle)
AMD_CG_SUPPORT_BIF_LS |
AMD_CG_SUPPORT_HDP_MGCG |
AMD_CG_SUPPORT_HDP_LS |
- AMD_CG_SUPPORT_ROM_MGCG;
+ AMD_CG_SUPPORT_ROM_MGCG |
+ AMD_CG_SUPPORT_MC_MGCG |
+ AMD_CG_SUPPORT_MC_LS;
adev->pg_flags = 0;
adev->external_rev_id = adev->rev_id + 0x3c;
break;
--
2.5.5
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dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH] drm/amdgpu/gfx8: rename send_serdes_cmd
2016-05-02 20:00 Misc amdgpu patches Alex Deucher
` (10 preceding siblings ...)
2016-05-02 20:00 ` [PATCH] drm/amdgpu/gmc: " Alex Deucher
@ 2016-05-02 20:00 ` Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amdgpu/gfx: adjust gfx_v8_0_send_serdes_cmd for ST Alex Deucher
` (33 subsequent siblings)
45 siblings, 0 replies; 47+ messages in thread
From: Alex Deucher @ 2016-05-02 20:00 UTC (permalink / raw)
To: dri-devel; +Cc: Alex Deucher
So it can be shared with CZ/ST.
Acked-by: Tom St Denis <tom.stdenis@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 4adccd1..7e94a85 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -4281,7 +4281,7 @@ static int gfx_v8_0_set_powergating_state(void *handle,
return 0;
}
-static void fiji_send_serdes_cmd(struct amdgpu_device *adev,
+static void gfx_v8_0_send_serdes_cmd(struct amdgpu_device *adev,
uint32_t reg_addr, uint32_t cmd)
{
uint32_t data;
@@ -4350,7 +4350,7 @@ static void fiji_update_medium_grain_clock_gating(struct amdgpu_device *adev,
gfx_v8_0_wait_for_rlc_serdes(adev);
/* 5 - clear mgcg override */
- fiji_send_serdes_cmd(adev, BPM_REG_MGCG_OVERRIDE, CLE_BPM_SERDES_CMD);
+ gfx_v8_0_send_serdes_cmd(adev, BPM_REG_MGCG_OVERRIDE, CLE_BPM_SERDES_CMD);
if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGTS) {
/* 6 - Enable CGTS(Tree Shade) MGCG /MGLS */
@@ -4406,7 +4406,7 @@ static void fiji_update_medium_grain_clock_gating(struct amdgpu_device *adev,
gfx_v8_0_wait_for_rlc_serdes(adev);
/* 6 - set mgcg override */
- fiji_send_serdes_cmd(adev, BPM_REG_MGCG_OVERRIDE, SET_BPM_SERDES_CMD);
+ gfx_v8_0_send_serdes_cmd(adev, BPM_REG_MGCG_OVERRIDE, SET_BPM_SERDES_CMD);
udelay(50);
@@ -4437,13 +4437,13 @@ static void fiji_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
gfx_v8_0_wait_for_rlc_serdes(adev);
/* 3 - clear cgcg override */
- fiji_send_serdes_cmd(adev, BPM_REG_CGCG_OVERRIDE, CLE_BPM_SERDES_CMD);
+ gfx_v8_0_send_serdes_cmd(adev, BPM_REG_CGCG_OVERRIDE, CLE_BPM_SERDES_CMD);
/* wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
gfx_v8_0_wait_for_rlc_serdes(adev);
/* 4 - write cmd to set CGLS */
- fiji_send_serdes_cmd(adev, BPM_REG_CGLS_EN, SET_BPM_SERDES_CMD);
+ gfx_v8_0_send_serdes_cmd(adev, BPM_REG_CGLS_EN, SET_BPM_SERDES_CMD);
/* 5 - enable cgcg */
data |= RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
@@ -4484,13 +4484,13 @@ static void fiji_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
gfx_v8_0_wait_for_rlc_serdes(adev);
/* write cmd to Set CGCG Overrride */
- fiji_send_serdes_cmd(adev, BPM_REG_CGCG_OVERRIDE, SET_BPM_SERDES_CMD);
+ gfx_v8_0_send_serdes_cmd(adev, BPM_REG_CGCG_OVERRIDE, SET_BPM_SERDES_CMD);
/* wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
gfx_v8_0_wait_for_rlc_serdes(adev);
/* write cmd to Clear CGLS */
- fiji_send_serdes_cmd(adev, BPM_REG_CGLS_EN, CLE_BPM_SERDES_CMD);
+ gfx_v8_0_send_serdes_cmd(adev, BPM_REG_CGLS_EN, CLE_BPM_SERDES_CMD);
/* disable cgcg, cgls should be disabled too. */
data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK |
--
2.5.5
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^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH] drm/amdgpu/gfx: adjust gfx_v8_0_send_serdes_cmd for ST
2016-05-02 20:00 Misc amdgpu patches Alex Deucher
` (11 preceding siblings ...)
2016-05-02 20:00 ` [PATCH] drm/amdgpu/gfx8: rename send_serdes_cmd Alex Deucher
@ 2016-05-02 20:00 ` Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amdgpu: add a new set of rlc function pointers Alex Deucher
` (32 subsequent siblings)
45 siblings, 0 replies; 47+ messages in thread
From: Alex Deucher @ 2016-05-02 20:00 UTC (permalink / raw)
To: dri-devel; +Cc: Alex Deucher
Acked-by: Tom St Denis <tom.stdenis@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 23 +++++++++++++++++------
1 file changed, 17 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 7e94a85..b15162d 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -4292,7 +4292,8 @@ static void gfx_v8_0_send_serdes_cmd(struct amdgpu_device *adev,
WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);
data = RREG32(mmRLC_SERDES_WR_CTRL);
- data &= ~(RLC_SERDES_WR_CTRL__WRITE_COMMAND_MASK |
+ if (adev->asic_type == CHIP_STONEY)
+ data &= ~(RLC_SERDES_WR_CTRL__WRITE_COMMAND_MASK |
RLC_SERDES_WR_CTRL__READ_COMMAND_MASK |
RLC_SERDES_WR_CTRL__P1_SELECT_MASK |
RLC_SERDES_WR_CTRL__P2_SELECT_MASK |
@@ -4300,13 +4301,23 @@ static void gfx_v8_0_send_serdes_cmd(struct amdgpu_device *adev,
RLC_SERDES_WR_CTRL__POWER_DOWN_MASK |
RLC_SERDES_WR_CTRL__POWER_UP_MASK |
RLC_SERDES_WR_CTRL__SHORT_FORMAT_MASK |
- RLC_SERDES_WR_CTRL__BPM_DATA_MASK |
- RLC_SERDES_WR_CTRL__REG_ADDR_MASK |
RLC_SERDES_WR_CTRL__SRBM_OVERRIDE_MASK);
+ else
+ data &= ~(RLC_SERDES_WR_CTRL__WRITE_COMMAND_MASK |
+ RLC_SERDES_WR_CTRL__READ_COMMAND_MASK |
+ RLC_SERDES_WR_CTRL__P1_SELECT_MASK |
+ RLC_SERDES_WR_CTRL__P2_SELECT_MASK |
+ RLC_SERDES_WR_CTRL__RDDATA_RESET_MASK |
+ RLC_SERDES_WR_CTRL__POWER_DOWN_MASK |
+ RLC_SERDES_WR_CTRL__POWER_UP_MASK |
+ RLC_SERDES_WR_CTRL__SHORT_FORMAT_MASK |
+ RLC_SERDES_WR_CTRL__BPM_DATA_MASK |
+ RLC_SERDES_WR_CTRL__REG_ADDR_MASK |
+ RLC_SERDES_WR_CTRL__SRBM_OVERRIDE_MASK);
data |= (RLC_SERDES_WR_CTRL__RSVD_BPM_ADDR_MASK |
- (cmd << RLC_SERDES_WR_CTRL__BPM_DATA__SHIFT) |
- (reg_addr << RLC_SERDES_WR_CTRL__REG_ADDR__SHIFT) |
- (0xff << RLC_SERDES_WR_CTRL__BPM_ADDR__SHIFT));
+ (cmd << RLC_SERDES_WR_CTRL__BPM_DATA__SHIFT) |
+ (reg_addr << RLC_SERDES_WR_CTRL__REG_ADDR__SHIFT) |
+ (0xff << RLC_SERDES_WR_CTRL__BPM_ADDR__SHIFT));
WREG32(mmRLC_SERDES_WR_CTRL, data);
}
--
2.5.5
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^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH] drm/amdgpu: add a new set of rlc function pointers
2016-05-02 20:00 Misc amdgpu patches Alex Deucher
` (12 preceding siblings ...)
2016-05-02 20:00 ` [PATCH] drm/amdgpu/gfx: adjust gfx_v8_0_send_serdes_cmd for ST Alex Deucher
@ 2016-05-02 20:00 ` Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amdgpu/gfx: rework fiji cg functions so they can be shared Alex Deucher
` (31 subsequent siblings)
45 siblings, 0 replies; 47+ messages in thread
From: Alex Deucher @ 2016-05-02 20:00 UTC (permalink / raw)
To: dri-devel; +Cc: Alex Deucher
Different asics tend to have different ways to interact
with the RLC. This just covers enter/exit of safe mode
for updating CG and PG state, but could be extended to
cover other RLC operations in the future if necessary.
Acked-by: Tom St Denis <tom.stdenis@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index a7a53ac..4a2b9a3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1037,6 +1037,11 @@ void amdgpu_bo_list_free(struct amdgpu_bo_list *list);
*/
#include "clearstate_defs.h"
+struct amdgpu_rlc_funcs {
+ void (*enter_safe_mode)(struct amdgpu_device *adev);
+ void (*exit_safe_mode)(struct amdgpu_device *adev);
+};
+
struct amdgpu_rlc {
/* for power gating */
struct amdgpu_bo *save_restore_obj;
@@ -1055,6 +1060,10 @@ struct amdgpu_rlc {
uint64_t cp_table_gpu_addr;
volatile uint32_t *cp_table_ptr;
u32 cp_table_size;
+
+ /* safe mode for updating CG/PG state */
+ bool in_safe_mode;
+ const struct amdgpu_rlc_funcs *funcs;
};
struct amdgpu_mec {
--
2.5.5
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^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH] drm/amdgpu/gfx: rework fiji cg functions so they can be shared
2016-05-02 20:00 Misc amdgpu patches Alex Deucher
` (13 preceding siblings ...)
2016-05-02 20:00 ` [PATCH] drm/amdgpu: add a new set of rlc function pointers Alex Deucher
@ 2016-05-02 20:00 ` Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amdgpu: enable gfx clockgating for CZ Alex Deucher
` (30 subsequent siblings)
45 siblings, 0 replies; 47+ messages in thread
From: Alex Deucher @ 2016-05-02 20:00 UTC (permalink / raw)
To: dri-devel; +Cc: Alex Deucher
They can be shared with other asics with minor modifications.
Acked-by: Tom St Denis <tom.stdenis@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 218 +++++++++++++++++++++++++++++++---
1 file changed, 202 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index b15162d..b2ee49e 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -558,6 +558,7 @@ static const u32 stoney_mgcg_cgcg_init[] =
static void gfx_v8_0_set_ring_funcs(struct amdgpu_device *adev);
static void gfx_v8_0_set_irq_funcs(struct amdgpu_device *adev);
static void gfx_v8_0_set_gds_init(struct amdgpu_device *adev);
+static void gfx_v8_0_set_rlc_funcs(struct amdgpu_device *adev);
static void gfx_v8_0_init_golden_registers(struct amdgpu_device *adev)
{
@@ -4250,6 +4251,7 @@ static int gfx_v8_0_early_init(void *handle)
gfx_v8_0_set_ring_funcs(adev);
gfx_v8_0_set_irq_funcs(adev);
gfx_v8_0_set_gds_init(adev);
+ gfx_v8_0_set_rlc_funcs(adev);
return 0;
}
@@ -4322,11 +4324,166 @@ static void gfx_v8_0_send_serdes_cmd(struct amdgpu_device *adev,
WREG32(mmRLC_SERDES_WR_CTRL, data);
}
-static void fiji_update_medium_grain_clock_gating(struct amdgpu_device *adev,
- bool enable)
+#define MSG_ENTER_RLC_SAFE_MODE 1
+#define MSG_EXIT_RLC_SAFE_MODE 0
+
+#define RLC_GPR_REG2__REQ_MASK 0x00000001
+#define RLC_GPR_REG2__MESSAGE__SHIFT 0x00000001
+#define RLC_GPR_REG2__MESSAGE_MASK 0x0000001e
+
+static void cz_enter_rlc_safe_mode(struct amdgpu_device *adev)
+{
+ u32 data = 0;
+ unsigned i;
+
+ data = RREG32(mmRLC_CNTL);
+ if ((data & RLC_CNTL__RLC_ENABLE_F32_MASK) == 0)
+ return;
+
+ if ((adev->cg_flags & (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_MGCG)) ||
+ (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG | AMD_PG_SUPPORT_GFX_SMG |
+ AMD_PG_SUPPORT_GFX_DMG))) {
+ data |= RLC_GPR_REG2__REQ_MASK;
+ data &= ~RLC_GPR_REG2__MESSAGE_MASK;
+ data |= (MSG_ENTER_RLC_SAFE_MODE << RLC_GPR_REG2__MESSAGE__SHIFT);
+ WREG32(mmRLC_GPR_REG2, data);
+
+ for (i = 0; i < adev->usec_timeout; i++) {
+ if ((RREG32(mmRLC_GPM_STAT) &
+ (RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK |
+ RLC_GPM_STAT__GFX_POWER_STATUS_MASK)) ==
+ (RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK |
+ RLC_GPM_STAT__GFX_POWER_STATUS_MASK))
+ break;
+ udelay(1);
+ }
+
+ for (i = 0; i < adev->usec_timeout; i++) {
+ if ((RREG32(mmRLC_GPR_REG2) & RLC_GPR_REG2__REQ_MASK) == 0)
+ break;
+ udelay(1);
+ }
+ adev->gfx.rlc.in_safe_mode = true;
+ }
+}
+
+static void cz_exit_rlc_safe_mode(struct amdgpu_device *adev)
+{
+ u32 data;
+ unsigned i;
+
+ data = RREG32(mmRLC_CNTL);
+ if ((data & RLC_CNTL__RLC_ENABLE_F32_MASK) == 0)
+ return;
+
+ if ((adev->cg_flags & (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_MGCG)) ||
+ (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG | AMD_PG_SUPPORT_GFX_SMG |
+ AMD_PG_SUPPORT_GFX_DMG))) {
+ data |= RLC_GPR_REG2__REQ_MASK;
+ data &= ~RLC_GPR_REG2__MESSAGE_MASK;
+ data |= (MSG_EXIT_RLC_SAFE_MODE << RLC_GPR_REG2__MESSAGE__SHIFT);
+ WREG32(mmRLC_GPR_REG2, data);
+ adev->gfx.rlc.in_safe_mode = false;
+ }
+
+ for (i = 0; i < adev->usec_timeout; i++) {
+ if ((RREG32(mmRLC_GPR_REG2) & RLC_GPR_REG2__REQ_MASK) == 0)
+ break;
+ udelay(1);
+ }
+}
+
+static void iceland_enter_rlc_safe_mode(struct amdgpu_device *adev)
+{
+ u32 data;
+ unsigned i;
+
+ data = RREG32(mmRLC_CNTL);
+ if (!(data & RLC_CNTL__RLC_ENABLE_F32_MASK))
+ return;
+
+ if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_MGCG)) {
+ data |= RLC_SAFE_MODE__CMD_MASK;
+ data &= ~RLC_SAFE_MODE__MESSAGE_MASK;
+ data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
+ WREG32(mmRLC_SAFE_MODE, data);
+
+ for (i = 0; i < adev->usec_timeout; i++) {
+ if ((RREG32(mmRLC_GPM_STAT) &
+ (RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK |
+ RLC_GPM_STAT__GFX_POWER_STATUS_MASK)) ==
+ (RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK |
+ RLC_GPM_STAT__GFX_POWER_STATUS_MASK))
+ break;
+ udelay(1);
+ }
+
+ for (i = 0; i < adev->usec_timeout; i++) {
+ if ((RREG32(mmRLC_SAFE_MODE) & RLC_SAFE_MODE__CMD_MASK) == 0)
+ break;
+ udelay(1);
+ }
+ adev->gfx.rlc.in_safe_mode = true;
+ }
+}
+
+static void iceland_exit_rlc_safe_mode(struct amdgpu_device *adev)
+{
+ u32 data = 0;
+ unsigned i;
+
+ data = RREG32(mmRLC_CNTL);
+ if (!(data & RLC_CNTL__RLC_ENABLE_F32_MASK))
+ return;
+
+ if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_MGCG)) {
+ if (adev->gfx.rlc.in_safe_mode) {
+ data |= RLC_SAFE_MODE__CMD_MASK;
+ data &= ~RLC_SAFE_MODE__MESSAGE_MASK;
+ WREG32(mmRLC_SAFE_MODE, data);
+ adev->gfx.rlc.in_safe_mode = false;
+ }
+ }
+
+ for (i = 0; i < adev->usec_timeout; i++) {
+ if ((RREG32(mmRLC_SAFE_MODE) & RLC_SAFE_MODE__CMD_MASK) == 0)
+ break;
+ udelay(1);
+ }
+}
+
+static void gfx_v8_0_nop_enter_rlc_safe_mode(struct amdgpu_device *adev)
+{
+ adev->gfx.rlc.in_safe_mode = true;
+}
+
+static void gfx_v8_0_nop_exit_rlc_safe_mode(struct amdgpu_device *adev)
+{
+ adev->gfx.rlc.in_safe_mode = false;
+}
+
+static const struct amdgpu_rlc_funcs cz_rlc_funcs = {
+ .enter_safe_mode = cz_enter_rlc_safe_mode,
+ .exit_safe_mode = cz_exit_rlc_safe_mode
+};
+
+static const struct amdgpu_rlc_funcs iceland_rlc_funcs = {
+ .enter_safe_mode = iceland_enter_rlc_safe_mode,
+ .exit_safe_mode = iceland_exit_rlc_safe_mode
+};
+
+static const struct amdgpu_rlc_funcs gfx_v8_0_nop_rlc_funcs = {
+ .enter_safe_mode = gfx_v8_0_nop_enter_rlc_safe_mode,
+ .exit_safe_mode = gfx_v8_0_nop_exit_rlc_safe_mode
+};
+
+static void gfx_v8_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
+ bool enable)
{
uint32_t temp, data;
+ adev->gfx.rlc.funcs->enter_safe_mode(adev);
+
/* It is disabled by HW by default */
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
@@ -4349,10 +4506,15 @@ static void fiji_update_medium_grain_clock_gating(struct amdgpu_device *adev,
/* 3 - RLC_CGTT_MGCG_OVERRIDE */
temp = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
- data &= ~(RLC_CGTT_MGCG_OVERRIDE__CPF_MASK |
- RLC_CGTT_MGCG_OVERRIDE__RLC_MASK |
- RLC_CGTT_MGCG_OVERRIDE__MGCG_MASK |
- RLC_CGTT_MGCG_OVERRIDE__GRBM_MASK);
+ if (adev->flags & AMD_IS_APU)
+ data &= ~(RLC_CGTT_MGCG_OVERRIDE__CPF_MASK |
+ RLC_CGTT_MGCG_OVERRIDE__RLC_MASK |
+ RLC_CGTT_MGCG_OVERRIDE__MGCG_MASK);
+ else
+ data &= ~(RLC_CGTT_MGCG_OVERRIDE__CPF_MASK |
+ RLC_CGTT_MGCG_OVERRIDE__RLC_MASK |
+ RLC_CGTT_MGCG_OVERRIDE__MGCG_MASK |
+ RLC_CGTT_MGCG_OVERRIDE__GRBM_MASK);
if (temp != data)
WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);
@@ -4424,15 +4586,19 @@ static void fiji_update_medium_grain_clock_gating(struct amdgpu_device *adev,
/* 7- wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
gfx_v8_0_wait_for_rlc_serdes(adev);
}
+
+ adev->gfx.rlc.funcs->exit_safe_mode(adev);
}
-static void fiji_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
- bool enable)
+static void gfx_v8_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
+ bool enable)
{
uint32_t temp, temp1, data, data1;
temp = data = RREG32(mmRLC_CGCG_CGLS_CTRL);
+ adev->gfx.rlc.funcs->enter_safe_mode(adev);
+
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
/* 1 enable cntx_empty_int_enable/cntx_busy_int_enable/
* Cmp_busy/GFX_Idle interrupts
@@ -4509,22 +4675,24 @@ static void fiji_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
if (temp != data)
WREG32(mmRLC_CGCG_CGLS_CTRL, data);
}
+
+ adev->gfx.rlc.funcs->exit_safe_mode(adev);
}
-static int fiji_update_gfx_clock_gating(struct amdgpu_device *adev,
- bool enable)
+static int gfx_v8_0_update_gfx_clock_gating(struct amdgpu_device *adev,
+ bool enable)
{
if (enable) {
/* CGCG/CGLS should be enabled after MGCG/MGLS/TS(CG/LS)
* === MGCG + MGLS + TS(CG/LS) ===
*/
- fiji_update_medium_grain_clock_gating(adev, enable);
- fiji_update_coarse_grain_clock_gating(adev, enable);
+ gfx_v8_0_update_medium_grain_clock_gating(adev, enable);
+ gfx_v8_0_update_coarse_grain_clock_gating(adev, enable);
} else {
/* CGCG/CGLS should be disabled before MGCG/MGLS/TS(CG/LS)
* === CGCG + CGLS ===
*/
- fiji_update_coarse_grain_clock_gating(adev, enable);
- fiji_update_medium_grain_clock_gating(adev, enable);
+ gfx_v8_0_update_coarse_grain_clock_gating(adev, enable);
+ gfx_v8_0_update_medium_grain_clock_gating(adev, enable);
}
return 0;
}
@@ -4536,8 +4704,10 @@ static int gfx_v8_0_set_clockgating_state(void *handle,
switch (adev->asic_type) {
case CHIP_FIJI:
- fiji_update_gfx_clock_gating(adev,
- state == AMD_CG_STATE_GATE ? true : false);
+ case CHIP_CARRIZO:
+ case CHIP_STONEY:
+ gfx_v8_0_update_gfx_clock_gating(adev,
+ state == AMD_CG_STATE_GATE ? true : false);
break;
default:
break;
@@ -5137,6 +5307,22 @@ static void gfx_v8_0_set_irq_funcs(struct amdgpu_device *adev)
adev->gfx.priv_inst_irq.funcs = &gfx_v8_0_priv_inst_irq_funcs;
}
+static void gfx_v8_0_set_rlc_funcs(struct amdgpu_device *adev)
+{
+ switch (adev->asic_type) {
+ case CHIP_TOPAZ:
+ case CHIP_STONEY:
+ adev->gfx.rlc.funcs = &iceland_rlc_funcs;
+ break;
+ case CHIP_CARRIZO:
+ adev->gfx.rlc.funcs = &cz_rlc_funcs;
+ break;
+ default:
+ adev->gfx.rlc.funcs = &gfx_v8_0_nop_rlc_funcs;
+ break;
+ }
+}
+
static void gfx_v8_0_set_gds_init(struct amdgpu_device *adev)
{
/* init asci gds info */
--
2.5.5
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^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH] drm/amdgpu: enable gfx clockgating for CZ
2016-05-02 20:00 Misc amdgpu patches Alex Deucher
` (14 preceding siblings ...)
2016-05-02 20:00 ` [PATCH] drm/amdgpu/gfx: rework fiji cg functions so they can be shared Alex Deucher
@ 2016-05-02 20:00 ` Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amdgpu: enable gfx clockgating for ST (v2) Alex Deucher
` (29 subsequent siblings)
45 siblings, 0 replies; 47+ messages in thread
From: Alex Deucher @ 2016-05-02 20:00 UTC (permalink / raw)
To: dri-devel; +Cc: Alex Deucher
Acked-by: Tom St Denis <tom.stdenis@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/vi.c | 10 +++++++++-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
index 16b2a29..c9c88a5 100644
--- a/drivers/gpu/drm/amd/amdgpu/vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
@@ -1101,7 +1101,15 @@ static int vi_common_early_init(void *handle)
adev->external_rev_id = adev->rev_id + 0x14;
break;
case CHIP_CARRIZO:
- adev->cg_flags = 0;
+ adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
+ AMD_CG_SUPPORT_GFX_MGLS |
+ AMD_CG_SUPPORT_GFX_RLC_LS |
+ AMD_CG_SUPPORT_GFX_CP_LS |
+ AMD_CG_SUPPORT_GFX_CGTS |
+ AMD_CG_SUPPORT_GFX_MGLS |
+ AMD_CG_SUPPORT_GFX_CGTS_LS |
+ AMD_CG_SUPPORT_GFX_CGCG |
+ AMD_CG_SUPPORT_GFX_CGLS;
adev->pg_flags = 0;
adev->external_rev_id = adev->rev_id + 0x1;
break;
--
2.5.5
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH] drm/amdgpu: enable gfx clockgating for ST (v2)
2016-05-02 20:00 Misc amdgpu patches Alex Deucher
` (15 preceding siblings ...)
2016-05-02 20:00 ` [PATCH] drm/amdgpu: enable gfx clockgating for CZ Alex Deucher
@ 2016-05-02 20:00 ` Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amdgpu/vi: rename fiji cg functions Alex Deucher
` (28 subsequent siblings)
45 siblings, 0 replies; 47+ messages in thread
From: Alex Deucher @ 2016-05-02 20:00 UTC (permalink / raw)
To: dri-devel; +Cc: Alex Deucher
v2: just enable MGCG for now since CGCG causes hangs
Acked-by: Tom St Denis <tom.stdenis@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/vi.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
index c9c88a5..2a7d37a 100644
--- a/drivers/gpu/drm/amd/amdgpu/vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
@@ -1114,7 +1114,9 @@ static int vi_common_early_init(void *handle)
adev->external_rev_id = adev->rev_id + 0x1;
break;
case CHIP_STONEY:
- adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG;
+ adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG |
+ AMD_CG_SUPPORT_GFX_MGCG |
+ AMD_CG_SUPPORT_GFX_MGLS;
adev->pg_flags = 0;
adev->external_rev_id = adev->rev_id + 0x1;
break;
--
2.5.5
_______________________________________________
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dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH] drm/amdgpu/vi: rename fiji cg functions
2016-05-02 20:00 Misc amdgpu patches Alex Deucher
` (16 preceding siblings ...)
2016-05-02 20:00 ` [PATCH] drm/amdgpu: enable gfx clockgating for ST (v2) Alex Deucher
@ 2016-05-02 20:00 ` Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amdgpu: enable gmc clockgating for CZ Alex Deucher
` (27 subsequent siblings)
45 siblings, 0 replies; 47+ messages in thread
From: Alex Deucher @ 2016-05-02 20:00 UTC (permalink / raw)
To: dri-devel; +Cc: Alex Deucher
They can be used for other VI parts.
Acked-by: Tom St Denis <tom.stdenis@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/vi.c | 33 +++++++++++++++++++++------------
1 file changed, 21 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
index 2a7d37a..7d03ea1 100644
--- a/drivers/gpu/drm/amd/amdgpu/vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
@@ -1203,8 +1203,8 @@ static int vi_common_soft_reset(void *handle)
return 0;
}
-static void fiji_update_bif_medium_grain_light_sleep(struct amdgpu_device *adev,
- bool enable)
+static void vi_update_bif_medium_grain_light_sleep(struct amdgpu_device *adev,
+ bool enable)
{
uint32_t temp, data;
@@ -1223,8 +1223,8 @@ static void fiji_update_bif_medium_grain_light_sleep(struct amdgpu_device *adev,
WREG32_PCIE(ixPCIE_CNTL2, data);
}
-static void fiji_update_hdp_medium_grain_clock_gating(struct amdgpu_device *adev,
- bool enable)
+static void vi_update_hdp_medium_grain_clock_gating(struct amdgpu_device *adev,
+ bool enable)
{
uint32_t temp, data;
@@ -1239,8 +1239,8 @@ static void fiji_update_hdp_medium_grain_clock_gating(struct amdgpu_device *adev
WREG32(mmHDP_HOST_PATH_CNTL, data);
}
-static void fiji_update_hdp_light_sleep(struct amdgpu_device *adev,
- bool enable)
+static void vi_update_hdp_light_sleep(struct amdgpu_device *adev,
+ bool enable)
{
uint32_t temp, data;
@@ -1255,8 +1255,8 @@ static void fiji_update_hdp_light_sleep(struct amdgpu_device *adev,
WREG32(mmHDP_MEM_POWER_LS, data);
}
-static void fiji_update_rom_medium_grain_clock_gating(struct amdgpu_device *adev,
- bool enable)
+static void vi_update_rom_medium_grain_clock_gating(struct amdgpu_device *adev,
+ bool enable)
{
uint32_t temp, data;
@@ -1280,13 +1280,22 @@ static int vi_common_set_clockgating_state(void *handle,
switch (adev->asic_type) {
case CHIP_FIJI:
- fiji_update_bif_medium_grain_light_sleep(adev,
+ vi_update_bif_medium_grain_light_sleep(adev,
state == AMD_CG_STATE_GATE ? true : false);
- fiji_update_hdp_medium_grain_clock_gating(adev,
+ vi_update_hdp_medium_grain_clock_gating(adev,
state == AMD_CG_STATE_GATE ? true : false);
- fiji_update_hdp_light_sleep(adev,
+ vi_update_hdp_light_sleep(adev,
state == AMD_CG_STATE_GATE ? true : false);
- fiji_update_rom_medium_grain_clock_gating(adev,
+ vi_update_rom_medium_grain_clock_gating(adev,
+ state == AMD_CG_STATE_GATE ? true : false);
+ break;
+ case CHIP_CARRIZO:
+ case CHIP_STONEY:
+ vi_update_bif_medium_grain_light_sleep(adev,
+ state == AMD_CG_STATE_GATE ? true : false);
+ vi_update_hdp_medium_grain_clock_gating(adev,
+ state == AMD_CG_STATE_GATE ? true : false);
+ vi_update_hdp_light_sleep(adev,
state == AMD_CG_STATE_GATE ? true : false);
break;
default:
--
2.5.5
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https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH] drm/amdgpu: enable gmc clockgating for CZ
2016-05-02 20:00 Misc amdgpu patches Alex Deucher
` (17 preceding siblings ...)
2016-05-02 20:00 ` [PATCH] drm/amdgpu/vi: rename fiji cg functions Alex Deucher
@ 2016-05-02 20:00 ` Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amdgpu: enable gmc clockgating for ST Alex Deucher
` (26 subsequent siblings)
45 siblings, 0 replies; 47+ messages in thread
From: Alex Deucher @ 2016-05-02 20:00 UTC (permalink / raw)
To: dri-devel; +Cc: Alex Deucher
Acked-by: Tom St Denis <tom.stdenis@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/vi.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
index 7d03ea1..0e9d3821 100644
--- a/drivers/gpu/drm/amd/amdgpu/vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
@@ -1109,7 +1109,10 @@ static int vi_common_early_init(void *handle)
AMD_CG_SUPPORT_GFX_MGLS |
AMD_CG_SUPPORT_GFX_CGTS_LS |
AMD_CG_SUPPORT_GFX_CGCG |
- AMD_CG_SUPPORT_GFX_CGLS;
+ AMD_CG_SUPPORT_GFX_CGLS |
+ AMD_CG_SUPPORT_BIF_LS |
+ AMD_CG_SUPPORT_HDP_MGCG |
+ AMD_CG_SUPPORT_HDP_LS;
adev->pg_flags = 0;
adev->external_rev_id = adev->rev_id + 0x1;
break;
--
2.5.5
_______________________________________________
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dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH] drm/amdgpu: enable gmc clockgating for ST
2016-05-02 20:00 Misc amdgpu patches Alex Deucher
` (18 preceding siblings ...)
2016-05-02 20:00 ` [PATCH] drm/amdgpu: enable gmc clockgating for CZ Alex Deucher
@ 2016-05-02 20:00 ` Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amdgpu/sdma: rename fiji cg functions Alex Deucher
` (25 subsequent siblings)
45 siblings, 0 replies; 47+ messages in thread
From: Alex Deucher @ 2016-05-02 20:00 UTC (permalink / raw)
To: dri-devel; +Cc: Alex Deucher
Acked-by: Tom St Denis <tom.stdenis@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/vi.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
index 0e9d3821..a330d70 100644
--- a/drivers/gpu/drm/amd/amdgpu/vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
@@ -1119,7 +1119,10 @@ static int vi_common_early_init(void *handle)
case CHIP_STONEY:
adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG |
AMD_CG_SUPPORT_GFX_MGCG |
- AMD_CG_SUPPORT_GFX_MGLS;
+ AMD_CG_SUPPORT_GFX_MGLS |
+ AMD_CG_SUPPORT_BIF_LS |
+ AMD_CG_SUPPORT_HDP_MGCG |
+ AMD_CG_SUPPORT_HDP_LS;
adev->pg_flags = 0;
adev->external_rev_id = adev->rev_id + 0x1;
break;
--
2.5.5
_______________________________________________
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dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH] drm/amdgpu/sdma: rename fiji cg functions
2016-05-02 20:00 Misc amdgpu patches Alex Deucher
` (19 preceding siblings ...)
2016-05-02 20:00 ` [PATCH] drm/amdgpu: enable gmc clockgating for ST Alex Deucher
@ 2016-05-02 20:00 ` Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amdgpu: enable sdma clockgating on CZ Alex Deucher
` (24 subsequent siblings)
45 siblings, 0 replies; 47+ messages in thread
From: Alex Deucher @ 2016-05-02 20:00 UTC (permalink / raw)
To: dri-devel; +Cc: Alex Deucher
They care common for all sdma 3.0 parts
Acked-by: Tom St Denis <tom.stdenis@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 104 +++++++++++++--------------------
1 file changed, 39 insertions(+), 65 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
index 739365d..dc29a20b 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
@@ -1458,40 +1458,31 @@ static int sdma_v3_0_process_illegal_inst_irq(struct amdgpu_device *adev,
return 0;
}
-static void fiji_update_sdma_medium_grain_clock_gating(
+static void sdma_v3_0_update_sdma_medium_grain_clock_gating(
struct amdgpu_device *adev,
bool enable)
{
uint32_t temp, data;
+ int i;
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
- temp = data = RREG32(mmSDMA0_CLK_CTRL);
- data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
- SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
- SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
- SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
- SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
- SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
- SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
- SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
- if (data != temp)
- WREG32(mmSDMA0_CLK_CTRL, data);
-
- temp = data = RREG32(mmSDMA1_CLK_CTRL);
- data &= ~(SDMA1_CLK_CTRL__SOFT_OVERRIDE7_MASK |
- SDMA1_CLK_CTRL__SOFT_OVERRIDE6_MASK |
- SDMA1_CLK_CTRL__SOFT_OVERRIDE5_MASK |
- SDMA1_CLK_CTRL__SOFT_OVERRIDE4_MASK |
- SDMA1_CLK_CTRL__SOFT_OVERRIDE3_MASK |
- SDMA1_CLK_CTRL__SOFT_OVERRIDE2_MASK |
- SDMA1_CLK_CTRL__SOFT_OVERRIDE1_MASK |
- SDMA1_CLK_CTRL__SOFT_OVERRIDE0_MASK);
-
- if (data != temp)
- WREG32(mmSDMA1_CLK_CTRL, data);
+ for (i = 0; i < adev->sdma.num_instances; i++) {
+ temp = data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i]);
+ data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
+ SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
+ SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
+ SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
+ SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
+ SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
+ SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
+ SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
+ if (data != temp)
+ WREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i], data);
+ }
} else {
- temp = data = RREG32(mmSDMA0_CLK_CTRL);
- data |= SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
+ for (i = 0; i < adev->sdma.num_instances; i++) {
+ temp = data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i]);
+ data |= SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
@@ -1500,54 +1491,35 @@ static void fiji_update_sdma_medium_grain_clock_gating(
SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK;
- if (data != temp)
- WREG32(mmSDMA0_CLK_CTRL, data);
-
- temp = data = RREG32(mmSDMA1_CLK_CTRL);
- data |= SDMA1_CLK_CTRL__SOFT_OVERRIDE7_MASK |
- SDMA1_CLK_CTRL__SOFT_OVERRIDE6_MASK |
- SDMA1_CLK_CTRL__SOFT_OVERRIDE5_MASK |
- SDMA1_CLK_CTRL__SOFT_OVERRIDE4_MASK |
- SDMA1_CLK_CTRL__SOFT_OVERRIDE3_MASK |
- SDMA1_CLK_CTRL__SOFT_OVERRIDE2_MASK |
- SDMA1_CLK_CTRL__SOFT_OVERRIDE1_MASK |
- SDMA1_CLK_CTRL__SOFT_OVERRIDE0_MASK;
-
- if (data != temp)
- WREG32(mmSDMA1_CLK_CTRL, data);
+ if (data != temp)
+ WREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i], data);
+ }
}
}
-static void fiji_update_sdma_medium_grain_light_sleep(
+static void sdma_v3_0_update_sdma_medium_grain_light_sleep(
struct amdgpu_device *adev,
bool enable)
{
uint32_t temp, data;
+ int i;
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
- temp = data = RREG32(mmSDMA0_POWER_CNTL);
- data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
-
- if (temp != data)
- WREG32(mmSDMA0_POWER_CNTL, data);
-
- temp = data = RREG32(mmSDMA1_POWER_CNTL);
- data |= SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
+ for (i = 0; i < adev->sdma.num_instances; i++) {
+ temp = data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i]);
+ data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
- if (temp != data)
- WREG32(mmSDMA1_POWER_CNTL, data);
+ if (temp != data)
+ WREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i], data);
+ }
} else {
- temp = data = RREG32(mmSDMA0_POWER_CNTL);
- data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
-
- if (temp != data)
- WREG32(mmSDMA0_POWER_CNTL, data);
-
- temp = data = RREG32(mmSDMA1_POWER_CNTL);
- data &= ~SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
+ for (i = 0; i < adev->sdma.num_instances; i++) {
+ temp = data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i]);
+ data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
- if (temp != data)
- WREG32(mmSDMA1_POWER_CNTL, data);
+ if (temp != data)
+ WREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i], data);
+ }
}
}
@@ -1558,9 +1530,11 @@ static int sdma_v3_0_set_clockgating_state(void *handle,
switch (adev->asic_type) {
case CHIP_FIJI:
- fiji_update_sdma_medium_grain_clock_gating(adev,
+ case CHIP_CARRIZO:
+ case CHIP_STONEY:
+ sdma_v3_0_update_sdma_medium_grain_clock_gating(adev,
state == AMD_CG_STATE_GATE ? true : false);
- fiji_update_sdma_medium_grain_light_sleep(adev,
+ sdma_v3_0_update_sdma_medium_grain_light_sleep(adev,
state == AMD_CG_STATE_GATE ? true : false);
break;
default:
--
2.5.5
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https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH] drm/amdgpu: enable sdma clockgating on CZ
2016-05-02 20:00 Misc amdgpu patches Alex Deucher
` (20 preceding siblings ...)
2016-05-02 20:00 ` [PATCH] drm/amdgpu/sdma: rename fiji cg functions Alex Deucher
@ 2016-05-02 20:00 ` Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amdgpu: enable sdma clockgating on ST Alex Deucher
` (23 subsequent siblings)
45 siblings, 0 replies; 47+ messages in thread
From: Alex Deucher @ 2016-05-02 20:00 UTC (permalink / raw)
To: dri-devel; +Cc: Alex Deucher
Acked-by: Tom St Denis <tom.stdenis@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/vi.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
index a330d70..83f890a 100644
--- a/drivers/gpu/drm/amd/amdgpu/vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
@@ -1112,7 +1112,9 @@ static int vi_common_early_init(void *handle)
AMD_CG_SUPPORT_GFX_CGLS |
AMD_CG_SUPPORT_BIF_LS |
AMD_CG_SUPPORT_HDP_MGCG |
- AMD_CG_SUPPORT_HDP_LS;
+ AMD_CG_SUPPORT_HDP_LS |
+ AMD_CG_SUPPORT_SDMA_MGCG |
+ AMD_CG_SUPPORT_SDMA_LS;
adev->pg_flags = 0;
adev->external_rev_id = adev->rev_id + 0x1;
break;
--
2.5.5
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https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH] drm/amdgpu: enable sdma clockgating on ST
2016-05-02 20:00 Misc amdgpu patches Alex Deucher
` (21 preceding siblings ...)
2016-05-02 20:00 ` [PATCH] drm/amdgpu: enable sdma clockgating on CZ Alex Deucher
@ 2016-05-02 20:00 ` Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amdgpu: add ELM/BAF DCE11 configs (v2) Alex Deucher
` (22 subsequent siblings)
45 siblings, 0 replies; 47+ messages in thread
From: Alex Deucher @ 2016-05-02 20:00 UTC (permalink / raw)
To: dri-devel; +Cc: Alex Deucher
Acked-by: Tom St Denis <tom.stdenis@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/vi.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
index 83f890a..ddbb63a 100644
--- a/drivers/gpu/drm/amd/amdgpu/vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
@@ -1124,7 +1124,9 @@ static int vi_common_early_init(void *handle)
AMD_CG_SUPPORT_GFX_MGLS |
AMD_CG_SUPPORT_BIF_LS |
AMD_CG_SUPPORT_HDP_MGCG |
- AMD_CG_SUPPORT_HDP_LS;
+ AMD_CG_SUPPORT_HDP_LS |
+ AMD_CG_SUPPORT_SDMA_MGCG |
+ AMD_CG_SUPPORT_SDMA_LS;
adev->pg_flags = 0;
adev->external_rev_id = adev->rev_id + 0x1;
break;
--
2.5.5
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https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH] drm/amdgpu: add ELM/BAF DCE11 configs (v2)
2016-05-02 20:00 Misc amdgpu patches Alex Deucher
` (22 preceding siblings ...)
2016-05-02 20:00 ` [PATCH] drm/amdgpu: enable sdma clockgating on ST Alex Deucher
@ 2016-05-02 20:00 ` Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amdgpu: add ELM/BAF support to dce_v11_0_pick_pll (v2) Alex Deucher
` (21 subsequent siblings)
45 siblings, 0 replies; 47+ messages in thread
From: Alex Deucher @ 2016-05-02 20:00 UTC (permalink / raw)
To: dri-devel; +Cc: Alex Deucher
Add support for the display configuration on elm/baf.
v2: add missing Stoney case
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
---
drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 25 ++++++++++++++++++++++++-
1 file changed, 24 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
index 89aab0a..613cc98 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
@@ -1580,7 +1580,20 @@ static int dce_v11_0_audio_init(struct amdgpu_device *adev)
adev->mode_info.audio.enabled = true;
- adev->mode_info.audio.num_pins = 7;
+ switch (adev->asic_type) {
+ case CHIP_CARRIZO:
+ case CHIP_STONEY:
+ adev->mode_info.audio.num_pins = 7;
+ break;
+ case CHIP_ELLESMERE:
+ adev->mode_info.audio.num_pins = 8;
+ break;
+ case CHIP_BAFFIN:
+ adev->mode_info.audio.num_pins = 6;
+ break;
+ default:
+ return -EINVAL;
+ }
for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
adev->mode_info.audio.pin[i].channels = -1;
@@ -2900,6 +2913,16 @@ static int dce_v11_0_early_init(void *handle)
adev->mode_info.num_hpd = 6;
adev->mode_info.num_dig = 9;
break;
+ case CHIP_ELLESMERE:
+ adev->mode_info.num_crtc = 6;
+ adev->mode_info.num_hpd = 6;
+ adev->mode_info.num_dig = 6;
+ break;
+ case CHIP_BAFFIN:
+ adev->mode_info.num_crtc = 5;
+ adev->mode_info.num_hpd = 5;
+ adev->mode_info.num_dig = 5;
+ break;
default:
/* FIXME: not supported yet */
return -EINVAL;
--
2.5.5
_______________________________________________
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dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH] drm/amdgpu: add ELM/BAF support to dce_v11_0_pick_pll (v2)
2016-05-02 20:00 Misc amdgpu patches Alex Deucher
` (23 preceding siblings ...)
2016-05-02 20:00 ` [PATCH] drm/amdgpu: add ELM/BAF DCE11 configs (v2) Alex Deucher
@ 2016-05-02 20:00 ` Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amd/powerplay: enable some feature for baffin/ellesmere. (v2) Alex Deucher
` (20 subsequent siblings)
45 siblings, 0 replies; 47+ messages in thread
From: Alex Deucher @ 2016-05-02 20:00 UTC (permalink / raw)
To: dri-devel; +Cc: Alex Deucher
New PLL scheme on ELM/BAF.
v2: squash in pll fix. Plls are part of the phys.
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
---
drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 38 ++++++++++++++++++++++++++++++++++
1 file changed, 38 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
index 613cc98..d1a0a55 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
@@ -2385,6 +2385,44 @@ static u32 dce_v11_0_pick_pll(struct drm_crtc *crtc)
u32 pll_in_use;
int pll;
+ if ((adev->asic_type == CHIP_ELLESMERE) ||
+ (adev->asic_type == CHIP_BAFFIN)) {
+ struct amdgpu_encoder *amdgpu_encoder =
+ to_amdgpu_encoder(amdgpu_crtc->encoder);
+ struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
+
+ if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder)))
+ return ATOM_DP_DTO;
+ /* use the same PPLL for all monitors with the same clock */
+ pll = amdgpu_pll_get_shared_nondp_ppll(crtc);
+ if (pll != ATOM_PPLL_INVALID)
+ return pll;
+
+ switch (amdgpu_encoder->encoder_id) {
+ case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
+ if (dig->linkb)
+ return ATOM_COMBOPHY_PLL1;
+ else
+ return ATOM_COMBOPHY_PLL0;
+ break;
+ case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
+ if (dig->linkb)
+ return ATOM_COMBOPHY_PLL3;
+ else
+ return ATOM_COMBOPHY_PLL2;
+ break;
+ case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
+ if (dig->linkb)
+ return ATOM_COMBOPHY_PLL5;
+ else
+ return ATOM_COMBOPHY_PLL4;
+ break;
+ default:
+ DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id);
+ return ATOM_PPLL_INVALID;
+ }
+ }
+
if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) {
if (adev->clock.dp_extclk)
/* skip PPLL programming if using ext clock */
--
2.5.5
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https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH] drm/amd/powerplay: enable some feature for baffin/ellesmere. (v2)
2016-05-02 20:00 Misc amdgpu patches Alex Deucher
` (24 preceding siblings ...)
2016-05-02 20:00 ` [PATCH] drm/amdgpu: add ELM/BAF support to dce_v11_0_pick_pll (v2) Alex Deucher
@ 2016-05-02 20:00 ` Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amd/powerplay: add fan control mode interface for baffin Alex Deucher
` (19 subsequent siblings)
45 siblings, 0 replies; 47+ messages in thread
From: Alex Deucher @ 2016-05-02 20:00 UTC (permalink / raw)
To: dri-devel; +Cc: Alex Deucher, Rex Zhu
From: Rex Zhu <Rex.Zhu@amd.com>
Sync up with internal updates.
v2: squash in:
drm/amd/powerplay: set revert flag for enable thermal protect.
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c | 2 +-
.../gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c | 94 +++++++++++++++++++---
2 files changed, 83 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
index 55a006d..dc836d3 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
@@ -3377,7 +3377,7 @@ static void fiji_set_dpm_event_sources(struct pp_hwmgr *hwmgr,
DPM_EVENT_SRC, src);
PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
THERMAL_PROTECTION_DIS,
- phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
+ !phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_ThermalController));
} else
PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
index 8a90a56..85a3341 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
@@ -2395,7 +2395,7 @@ static void polaris10_set_dpm_event_sources(struct pp_hwmgr *hwmgr, uint32_t sou
DPM_EVENT_SRC, src);
PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
THERMAL_PROTECTION_DIS,
- phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
+ !phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_ThermalController));
} else
PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
@@ -2562,6 +2562,9 @@ int polaris10_set_features_platform_caps(struct pp_hwmgr *hwmgr)
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_SclkDeepSleep);
+ phm_cap_set(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_DynamicPatchPowerState);
+
if (data->mvdd_control == POLARIS10_VOLTAGE_CONTROL_NONE)
phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_EnableMVDDControl);
@@ -2580,6 +2583,9 @@ int polaris10_set_features_platform_caps(struct pp_hwmgr *hwmgr)
PHM_PlatformCaps_DynamicPowerManagement);
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_UnTabledHardwareInterface);
+
+ phm_cap_set(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_TablelessHardwareInterface);
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
@@ -2596,10 +2602,6 @@ int polaris10_set_features_platform_caps(struct pp_hwmgr *hwmgr)
/* power tune caps Assume disabled */
phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_PowerContainment);
- phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_CAC);
- phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_SQRamping);
phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_DBRamping);
@@ -2608,6 +2610,22 @@ int polaris10_set_features_platform_caps(struct pp_hwmgr *hwmgr)
phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_TCPRamping);
+ phm_cap_set(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_PowerContainment);
+ phm_cap_set(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_CAC);
+
+ phm_cap_set(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_RegulatorHot);
+
+ phm_cap_set(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_AutomaticDCTransition);
+
+ phm_cap_set(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_ODFuzzyFanControlSupport);
+
+ phm_cap_set(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_FanSpeedInTableIsRPM);
if (hwmgr->chip_id == CHIP_POLARIS11)
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_SPLLShutdownSupport);
@@ -2890,6 +2908,11 @@ static int polaris10_set_private_data_based_on_pptable(struct pp_hwmgr *hwmgr)
table_info->max_clock_voltage_on_ac.vddci =
allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].vddci;
+ hwmgr->dyn_state.max_clock_voltage_on_ac.sclk = table_info->max_clock_voltage_on_ac.sclk;
+ hwmgr->dyn_state.max_clock_voltage_on_ac.mclk = table_info->max_clock_voltage_on_ac.mclk;
+ hwmgr->dyn_state.max_clock_voltage_on_ac.vddc = table_info->max_clock_voltage_on_ac.vddc;
+ hwmgr->dyn_state.max_clock_voltage_on_ac.vddci =table_info->max_clock_voltage_on_ac.vddci;
+
return 0;
}
@@ -2899,6 +2922,8 @@ int polaris10_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
struct pp_atomctrl_gpio_pin_assignment gpio_pin_assignment;
uint32_t temp_reg;
int result;
+ struct phm_ppt_v1_information *table_info =
+ (struct phm_ppt_v1_information *)(hwmgr->pptable);
data->dll_default_on = false;
data->sram_end = SMC_RAM_END;
@@ -2937,9 +2962,6 @@ int polaris10_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2))
data->voltage_control = POLARIS10_VOLTAGE_CONTROL_BY_SVID2;
- phm_cap_set(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_DynamicPatchPowerState);
-
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_EnableMVDDControl)) {
if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
@@ -2987,10 +3009,7 @@ int polaris10_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
POLARIS10_MAX_HARDWARE_POWERLEVELS;
hwmgr->platform_descriptor.hardwarePerformanceLevels = 2;
hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50;
- hwmgr->platform_descriptor.vbiosInterruptId = 0x20000400; /* IRQ_SOURCE1_SW_INT */
-/* The true clock step depends on the frequency, typically 4.5 or 9 MHz. Here we use 5. */
- hwmgr->platform_descriptor.clockStep.engineClock = 500;
- hwmgr->platform_descriptor.clockStep.memoryClock = 500;
+
if (atomctrl_get_pp_assign_pin(hwmgr, VDDC_PCC_GPIO_PINID, &gpio_pin_assignment)) {
temp_reg = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCNB_PWRMGT_CNTL);
@@ -3019,6 +3038,52 @@ int polaris10_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCNB_PWRMGT_CNTL, temp_reg);
}
+ if (table_info->cac_dtp_table->usDefaultTargetOperatingTemp != 0 &&
+ hwmgr->thermal_controller.advanceFanControlParameters.ucFanControlMode) {
+ hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMMinLimit =
+ (uint16_t)hwmgr->thermal_controller.advanceFanControlParameters.ucMinimumPWMLimit;
+
+ hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMMaxLimit =
+ (uint16_t)hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanPWM;
+
+ hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMStep = 1;
+
+ hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMMaxLimit = 100;
+
+ hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMMinLimit =
+ (uint16_t)hwmgr->thermal_controller.advanceFanControlParameters.ucMinimumPWMLimit;
+
+ hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMStep = 1;
+
+ table_info->cac_dtp_table->usDefaultTargetOperatingTemp = (table_info->cac_dtp_table->usDefaultTargetOperatingTemp >= 50) ?
+ (table_info->cac_dtp_table->usDefaultTargetOperatingTemp -50) : 0;
+
+ table_info->cac_dtp_table->usOperatingTempMaxLimit = table_info->cac_dtp_table->usDefaultTargetOperatingTemp;
+ table_info->cac_dtp_table->usOperatingTempStep = 1;
+ table_info->cac_dtp_table->usOperatingTempHyst = 1;
+
+ hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanPWM =
+ hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanPWM;
+
+ hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanRPM =
+ hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanRPM;
+
+ hwmgr->dyn_state.cac_dtp_table->usOperatingTempMinLimit =
+ table_info->cac_dtp_table->usOperatingTempMinLimit;
+
+ hwmgr->dyn_state.cac_dtp_table->usOperatingTempMaxLimit =
+ table_info->cac_dtp_table->usOperatingTempMaxLimit;
+
+ hwmgr->dyn_state.cac_dtp_table->usDefaultTargetOperatingTemp =
+ table_info->cac_dtp_table->usDefaultTargetOperatingTemp;
+
+ hwmgr->dyn_state.cac_dtp_table->usOperatingTempStep =
+ table_info->cac_dtp_table->usOperatingTempStep;
+
+ hwmgr->dyn_state.cac_dtp_table->usTargetOperatingTemp =
+ table_info->cac_dtp_table->usTargetOperatingTemp;
+ }
+
sys_info.size = sizeof(struct cgs_system_info);
sys_info.info_id = CGS_SYSTEM_INFO_PCIE_GEN_INFO;
result = cgs_query_system_info(hwmgr->device, &sys_info);
@@ -3035,6 +3100,11 @@ int polaris10_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
data->pcie_lane_cap = 0x2f0000;
else
data->pcie_lane_cap = (uint32_t)sys_info.value;
+
+ hwmgr->platform_descriptor.vbiosInterruptId = 0x20000400; /* IRQ_SOURCE1_SW_INT */
+/* The true clock step depends on the frequency, typically 4.5 or 9 MHz. Here we use 5. */
+ hwmgr->platform_descriptor.clockStep.engineClock = 500;
+ hwmgr->platform_descriptor.clockStep.memoryClock = 500;
} else {
/* Ignore return value in here, we are cleaning up a mess. */
polaris10_hwmgr_backend_fini(hwmgr);
--
2.5.5
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dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH] drm/amd/powerplay: add fan control mode interface for baffin
2016-05-02 20:00 Misc amdgpu patches Alex Deucher
` (25 preceding siblings ...)
2016-05-02 20:00 ` [PATCH] drm/amd/powerplay: enable some feature for baffin/ellesmere. (v2) Alex Deucher
@ 2016-05-02 20:00 ` Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amd/powerplay: parameter updates according to SMC Alex Deucher
` (18 subsequent siblings)
45 siblings, 0 replies; 47+ messages in thread
From: Alex Deucher @ 2016-05-02 20:00 UTC (permalink / raw)
To: dri-devel; +Cc: Alex Deucher, Rex Zhu
From: Rex Zhu <Rex.Zhu@amd.com>
Add interface for manual fan control.
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
.../gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c | 26 ++++++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
index 85a3341..fd29c56 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
@@ -4871,6 +4871,30 @@ static int polaris10_print_clock_levels(struct pp_hwmgr *hwmgr,
return size;
}
+static int polaris10_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
+{
+ if (mode) {
+ /* stop auto-manage */
+ if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_MicrocodeFanControl))
+ polaris10_fan_ctrl_stop_smc_fan_control(hwmgr);
+ polaris10_fan_ctrl_set_static_mode(hwmgr, mode);
+ } else
+ /* restart auto-manage */
+ polaris10_fan_ctrl_reset_fan_speed_to_default(hwmgr);
+
+ return 0;
+}
+
+static int polaris10_get_fan_control_mode(struct pp_hwmgr *hwmgr)
+{
+ if (hwmgr->fan_ctrl_is_in_default_mode)
+ return hwmgr->fan_ctrl_default_mode;
+ else
+ return PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
+ CG_FDO_CTRL2, FDO_PWM_MODE);
+}
+
static const struct pp_hwmgr_func polaris10_hwmgr_funcs = {
.backend_init = &polaris10_hwmgr_backend_init,
.backend_fini = &polaris10_hwmgr_backend_fini,
@@ -4907,6 +4931,8 @@ static const struct pp_hwmgr_func polaris10_hwmgr_funcs = {
.register_internal_thermal_interrupt = polaris10_register_internal_thermal_interrupt,
.check_smc_update_required_for_display_configuration = polaris10_check_smc_update_required_for_display_configuration,
.check_states_equal = polaris10_check_states_equal,
+ .set_fan_control_mode = polaris10_set_fan_control_mode,
+ .get_fan_control_mode = polaris10_get_fan_control_mode,
.get_pp_table = polaris10_get_pp_table,
.set_pp_table = polaris10_set_pp_table,
.force_clock_level = polaris10_force_clock_level,
--
2.5.5
_______________________________________________
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dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH] drm/amd/powerplay: parameter updates according to SMC.
2016-05-02 20:00 Misc amdgpu patches Alex Deucher
` (26 preceding siblings ...)
2016-05-02 20:00 ` [PATCH] drm/amd/powerplay: add fan control mode interface for baffin Alex Deucher
@ 2016-05-02 20:00 ` Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amd/powerplay: fix issue that get wrong reference clock value Alex Deucher
` (17 subsequent siblings)
45 siblings, 0 replies; 47+ messages in thread
From: Alex Deucher @ 2016-05-02 20:00 UTC (permalink / raw)
To: dri-devel; +Cc: Alex Deucher, Rex Zhu
From: Rex Zhu <Rex.Zhu@amd.com>
Update to latest changes for SMC team.
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
.../drm/amd/powerplay/hwmgr/polaris10_powertune.c | 32 ++++++++++++----------
drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h | 10 +++----
2 files changed, 22 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c
index 4d97326..02bcedc 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c
@@ -57,6 +57,13 @@ void polaris10_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr)
}
+static uint16_t scale_fan_gain_settings(uint16_t raw_setting)
+{
+ uint32_t tmp;
+ tmp = raw_setting * 4096 / 100;
+ return (uint16_t)tmp;
+}
+
int polaris10_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr)
{
struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
@@ -65,6 +72,8 @@ int polaris10_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr)
struct phm_ppt_v1_information *table_info =
(struct phm_ppt_v1_information *)(hwmgr->pptable);
struct phm_cac_tdp_table *cac_dtp_table = table_info->cac_dtp_table;
+ struct pp_advance_fan_control_parameters *fan_table=
+ &hwmgr->thermal_controller.advanceFanControlParameters;
int i, j, k;
uint16_t *pdef1;
uint16_t *pdef2;
@@ -75,15 +84,16 @@ int polaris10_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr)
PP_ASSERT_WITH_CODE(cac_dtp_table->usTargetOperatingTemp <= 255,
"Target Operating Temp is out of Range!",
);
-/* This is the same value as TemperatureLimitHigh except it is integer with no fraction bit. */
- dpm_table->GpuTjMax = (uint8_t)(cac_dtp_table->usTargetOperatingTemp);
-/* HW request to hard code this value to 8 which is 0.5C */
- dpm_table->GpuTjHyst = 8;
+ dpm_table->TemperatureLimitEdge = PP_HOST_TO_SMC_US(
+ cac_dtp_table->usTargetOperatingTemp * 256);
+ dpm_table->TemperatureLimitHotspot = PP_HOST_TO_SMC_US(
+ cac_dtp_table->usTemperatureLimitHotspot * 256);
+ dpm_table->FanGainEdge = PP_HOST_TO_SMC_US(
+ scale_fan_gain_settings(fan_table->usFanGainEdge));
+ dpm_table->FanGainHotspot = PP_HOST_TO_SMC_US(
+ scale_fan_gain_settings(fan_table->usFanGainHotspot));
- dpm_table->DTEAmbientTempBase = defaults->DTEAmbientTempBase;
- dpm_table->DTETjOffset = (uint8_t)(data->dte_tj_offset);
- dpm_table->BAPM_TEMP_GRADIENT = PP_HOST_TO_SMC_UL(defaults->BAPM_TEMP_GRADIENT);
pdef1 = defaults->BAPMTI_R;
pdef2 = defaults->BAPMTI_RC;
@@ -330,14 +340,6 @@ int polaris10_enable_power_containment(struct pp_hwmgr *hwmgr)
data->power_containment_features = 0;
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_PowerContainment)) {
- if (data->enable_dte_feature) {
- smc_result = smum_send_msg_to_smc(hwmgr->smumgr,
- (uint16_t)(PPSMC_MSG_EnableDTE));
- PP_ASSERT_WITH_CODE((0 == smc_result),
- "Failed to enable DTE in SMC.", result = -1;);
- if (0 == smc_result)
- data->power_containment_features |= POWERCONTAINMENT_FEATURE_DTE;
- }
if (data->enable_tdc_limit_feature) {
smc_result = smum_send_msg_to_smc(hwmgr->smumgr,
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h b/drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h
index f6a7591..0dfe823 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h
@@ -323,14 +323,14 @@ struct SMU74_Discrete_DpmTable {
uint16_t BAPMTI_R[SMU74_DTE_ITERATIONS][SMU74_DTE_SOURCES][SMU74_DTE_SINKS];
uint16_t BAPMTI_RC[SMU74_DTE_ITERATIONS][SMU74_DTE_SOURCES][SMU74_DTE_SINKS];
- uint8_t DTEAmbientTempBase;
- uint8_t DTETjOffset;
- uint8_t GpuTjMax;
- uint8_t GpuTjHyst;
+ uint16_t TemperatureLimitEdge;
+ uint16_t TemperatureLimitHotspot;
+
uint16_t BootVddc;
uint16_t BootVddci;
- uint32_t BAPM_TEMP_GRADIENT;
+ uint16_t FanGainEdge;
+ uint16_t FanGainHotspot;
uint32_t LowSclkInterruptThreshold;
uint32_t VddGfxReChkWait;
--
2.5.5
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^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH] drm/amd/powerplay: fix issue that get wrong reference clock value.
2016-05-02 20:00 Misc amdgpu patches Alex Deucher
` (27 preceding siblings ...)
2016-05-02 20:00 ` [PATCH] drm/amd/powerplay: parameter updates according to SMC Alex Deucher
@ 2016-05-02 20:00 ` Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amd/powerplay: Fix a bug for enabling ACDC gpio interrupt Alex Deucher
` (16 subsequent siblings)
45 siblings, 0 replies; 47+ messages in thread
From: Alex Deucher @ 2016-05-02 20:00 UTC (permalink / raw)
To: dri-devel; +Cc: Alex Deucher, Rex Zhu
From: Rex Zhu <Rex.Zhu@amd.com>
use wrong parameter to compute the reference clock.
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
index 3bed991..0242e34 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
@@ -5893,7 +5893,7 @@ uint32_t tonga_get_xclk(struct pp_hwmgr *hwmgr)
if (!fw_info)
return 0;
- reference_clock = le16_to_cpu(fw_info->usMinPixelClockPLL_Output);
+ reference_clock = le16_to_cpu(fw_info->usReferenceClock);
divide = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_CLKPIN_CNTL, XTALIN_DIVIDE);
--
2.5.5
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^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH] drm/amd/powerplay: Fix a bug for enabling ACDC gpio interrupt
2016-05-02 20:00 Misc amdgpu patches Alex Deucher
` (28 preceding siblings ...)
2016-05-02 20:00 ` [PATCH] drm/amd/powerplay: fix issue that get wrong reference clock value Alex Deucher
@ 2016-05-02 20:00 ` Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amd/powerplay: update vce power gate state for baffin Alex Deucher
` (15 subsequent siblings)
45 siblings, 0 replies; 47+ messages in thread
From: Alex Deucher @ 2016-05-02 20:00 UTC (permalink / raw)
To: dri-devel; +Cc: Eric Huang, Alex Deucher, Eric Yang
From: Eric Huang <JinHuiEric.Huang@amd.com>
Only enable it if it's supported rather than unconitionally.
Signed-off-by: Eric Yang <eric.yang2@amd.com>
Reviewed-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c | 11 +++++++----
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
index fd29c56..045c7ef 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
@@ -2354,10 +2354,13 @@ static int polaris10_start_dpm(struct pp_hwmgr *hwmgr)
return -1);
}
- PP_ASSERT_WITH_CODE((0 == smum_send_msg_to_smc(hwmgr->smumgr,
- PPSMC_MSG_EnableACDCGPIOInterrupt)),
- "Failed to enable AC DC GPIO Interrupt!",
- );
+ if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
+ PHM_PlatformCaps_Falcon_QuickTransition)) {
+ PP_ASSERT_WITH_CODE((0 == smum_send_msg_to_smc(hwmgr->smumgr,
+ PPSMC_MSG_EnableACDCGPIOInterrupt)),
+ "Failed to enable AC DC GPIO Interrupt!",
+ );
+ }
return 0;
}
--
2.5.5
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^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH] drm/amd/powerplay: update vce power gate state for baffin.
2016-05-02 20:00 Misc amdgpu patches Alex Deucher
` (29 preceding siblings ...)
2016-05-02 20:00 ` [PATCH] drm/amd/powerplay: Fix a bug for enabling ACDC gpio interrupt Alex Deucher
@ 2016-05-02 20:00 ` Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amdgpu: fix memory leak in CGS (FW info) Alex Deucher
` (14 subsequent siblings)
45 siblings, 0 replies; 47+ messages in thread
From: Alex Deucher @ 2016-05-02 20:00 UTC (permalink / raw)
To: dri-devel; +Cc: Alex Deucher, Rex Zhu
From: Rex Zhu <Rex.Zhu@amd.com>
Forgot to save the current gate state so we don't know
what the current state is if we try and gate/ungate the
block.
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_clockpowergating.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_clockpowergating.c b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_clockpowergating.c
index e362ddb..8f142a7 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_clockpowergating.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_clockpowergating.c
@@ -123,6 +123,8 @@ int polaris10_phm_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate)
if (data->vce_power_gated == bgate)
return 0;
+ data->vce_power_gated = bgate;
+
if (bgate)
polaris10_phm_powerdown_vce(hwmgr);
else
--
2.5.5
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https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH] drm/amdgpu: fix memory leak in CGS (FW info)
2016-05-02 20:00 Misc amdgpu patches Alex Deucher
` (30 preceding siblings ...)
2016-05-02 20:00 ` [PATCH] drm/amd/powerplay: update vce power gate state for baffin Alex Deucher
@ 2016-05-02 20:00 ` Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amd/powerplay: return 0 when interface not implement on some asic Alex Deucher
` (13 subsequent siblings)
45 siblings, 0 replies; 47+ messages in thread
From: Alex Deucher @ 2016-05-02 20:00 UTC (permalink / raw)
To: dri-devel; +Cc: Mykola Lysenko
From: Mykola Lysenko <Mykola.Lysenko@amd.com>
Previously requested FW pointer should not be
overwritten on a subsequent call.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Mykola Lysenko <Mykola.Lysenko@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c | 70 +++++++++++++++++----------------
1 file changed, 36 insertions(+), 34 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
index 837cdd2..490464e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
@@ -735,42 +735,44 @@ static int amdgpu_cgs_get_firmware_info(struct cgs_device *cgs_device,
const uint8_t *src;
const struct smc_firmware_header_v1_0 *hdr;
- switch (adev->asic_type) {
- case CHIP_TONGA:
- strcpy(fw_name, "amdgpu/tonga_smc.bin");
- break;
- case CHIP_FIJI:
- strcpy(fw_name, "amdgpu/fiji_smc.bin");
- break;
- case CHIP_POLARIS11:
- if (type == CGS_UCODE_ID_SMU)
- strcpy(fw_name, "amdgpu/polaris11_smc.bin");
- else if (type == CGS_UCODE_ID_SMU_SK)
- strcpy(fw_name, "amdgpu/polaris11_smc_sk.bin");
- break;
- case CHIP_POLARIS10:
- if (type == CGS_UCODE_ID_SMU)
- strcpy(fw_name, "amdgpu/polaris10_smc.bin");
- else if (type == CGS_UCODE_ID_SMU_SK)
- strcpy(fw_name, "amdgpu/polaris10_smc_sk.bin");
- break;
- default:
- DRM_ERROR("SMC firmware not supported\n");
- return -EINVAL;
- }
+ if (!adev->pm.fw) {
+ switch (adev->asic_type) {
+ case CHIP_TONGA:
+ strcpy(fw_name, "amdgpu/tonga_smc.bin");
+ break;
+ case CHIP_FIJI:
+ strcpy(fw_name, "amdgpu/fiji_smc.bin");
+ break;
+ case CHIP_POLARIS11:
+ if (type == CGS_UCODE_ID_SMU)
+ strcpy(fw_name, "amdgpu/polaris11_smc.bin");
+ else if (type == CGS_UCODE_ID_SMU_SK)
+ strcpy(fw_name, "amdgpu/polaris11_smc_sk.bin");
+ break;
+ case CHIP_POLARIS10:
+ if (type == CGS_UCODE_ID_SMU)
+ strcpy(fw_name, "amdgpu/polaris10_smc.bin");
+ else if (type == CGS_UCODE_ID_SMU_SK)
+ strcpy(fw_name, "amdgpu/polaris10_smc_sk.bin");
+ break;
+ default:
+ DRM_ERROR("SMC firmware not supported\n");
+ return -EINVAL;
+ }
- err = request_firmware(&adev->pm.fw, fw_name, adev->dev);
- if (err) {
- DRM_ERROR("Failed to request firmware\n");
- return err;
- }
+ err = request_firmware(&adev->pm.fw, fw_name, adev->dev);
+ if (err) {
+ DRM_ERROR("Failed to request firmware\n");
+ return err;
+ }
- err = amdgpu_ucode_validate(adev->pm.fw);
- if (err) {
- DRM_ERROR("Failed to load firmware \"%s\"", fw_name);
- release_firmware(adev->pm.fw);
- adev->pm.fw = NULL;
- return err;
+ err = amdgpu_ucode_validate(adev->pm.fw);
+ if (err) {
+ DRM_ERROR("Failed to load firmware \"%s\"", fw_name);
+ release_firmware(adev->pm.fw);
+ adev->pm.fw = NULL;
+ return err;
+ }
}
hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
--
2.5.5
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dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH] drm/amd/powerplay: return 0 when interface not implement on some asic.
2016-05-02 20:00 Misc amdgpu patches Alex Deucher
` (31 preceding siblings ...)
2016-05-02 20:00 ` [PATCH] drm/amdgpu: fix memory leak in CGS (FW info) Alex Deucher
@ 2016-05-02 20:00 ` Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amd/powerplay: fix some initialize error on polaris10 Alex Deucher
` (12 subsequent siblings)
45 siblings, 0 replies; 47+ messages in thread
From: Alex Deucher @ 2016-05-02 20:00 UTC (permalink / raw)
To: dri-devel; +Cc: Alex Deucher, Rex Zhu
From: Rex Zhu <Rex.Zhu@amd.com>
Don't fail if certain optional interface callbacks are missing.
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 169 +++++++++++++++++---------
1 file changed, 113 insertions(+), 56 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
index 32a6a6f..ce8d9bf 100644
--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
@@ -37,6 +37,12 @@
return -EINVAL; \
} while (0)
+#define PP_CHECK_HW(hwmgr) \
+ do { \
+ if ((hwmgr) == NULL || (hwmgr)->hwmgr_func == NULL) \
+ return -EINVAL; \
+ } while (0)
+
static int pp_early_init(void *handle)
{
return 0;
@@ -54,8 +60,9 @@ static int pp_sw_init(void *handle)
pp_handle = (struct pp_instance *)handle;
hwmgr = pp_handle->hwmgr;
- if (hwmgr == NULL || hwmgr->pptable_func == NULL ||
- hwmgr->hwmgr_func == NULL ||
+ PP_CHECK_HW(hwmgr);
+
+ if (hwmgr->pptable_func == NULL ||
hwmgr->pptable_func->pptable_init == NULL ||
hwmgr->hwmgr_func->backend_init == NULL)
return -EINVAL;
@@ -66,9 +73,9 @@ static int pp_sw_init(void *handle)
ret = hwmgr->hwmgr_func->backend_init(hwmgr);
if (ret)
- printk("amdgpu: powerplay initialization failed\n");
+ printk(KERN_ERR "amdgpu: powerplay initialization failed\n");
else
- printk("amdgpu: powerplay initialized\n");
+ printk(KERN_INFO "amdgpu: powerplay initialized\n");
return ret;
}
@@ -85,8 +92,9 @@ static int pp_sw_fini(void *handle)
pp_handle = (struct pp_instance *)handle;
hwmgr = pp_handle->hwmgr;
- if (hwmgr != NULL || hwmgr->hwmgr_func != NULL ||
- hwmgr->hwmgr_func->backend_fini != NULL)
+ PP_CHECK_HW(hwmgr);
+
+ if (hwmgr->hwmgr_func->backend_fini != NULL)
ret = hwmgr->hwmgr_func->backend_fini(hwmgr);
return ret;
@@ -188,11 +196,12 @@ static int pp_set_clockgating_state(void *handle,
hwmgr = ((struct pp_instance *)handle)->hwmgr;
- if (hwmgr == NULL || hwmgr->hwmgr_func == NULL)
- return -EINVAL;
+ PP_CHECK_HW(hwmgr);
- if (hwmgr->hwmgr_func->update_clock_gatings == NULL)
+ if (hwmgr->hwmgr_func->update_clock_gatings == NULL) {
+ printk(KERN_INFO "%s was not implemented.\n", __func__);
return 0;
+ }
if (state == AMD_CG_STATE_UNGATE)
pp_state = 0;
@@ -276,9 +285,12 @@ static int pp_set_powergating_state(void *handle,
hwmgr = ((struct pp_instance *)handle)->hwmgr;
- if (hwmgr == NULL || hwmgr->hwmgr_func == NULL ||
- hwmgr->hwmgr_func->enable_per_cu_power_gating == NULL)
- return -EINVAL;
+ PP_CHECK_HW(hwmgr);
+
+ if (hwmgr->hwmgr_func->enable_per_cu_power_gating == NULL) {
+ printk(KERN_INFO "%s was not implemented.\n", __func__);
+ return 0;
+ }
/* Enable/disable GFX per cu powergating through SMU */
return hwmgr->hwmgr_func->enable_per_cu_power_gating(hwmgr,
@@ -371,9 +383,12 @@ static int pp_dpm_force_performance_level(void *handle,
hwmgr = pp_handle->hwmgr;
- if (hwmgr == NULL || hwmgr->hwmgr_func == NULL ||
- hwmgr->hwmgr_func->force_dpm_level == NULL)
- return -EINVAL;
+ PP_CHECK_HW(hwmgr);
+
+ if (hwmgr->hwmgr_func->force_dpm_level == NULL) {
+ printk(KERN_INFO "%s was not implemented.\n", __func__);
+ return 0;
+ }
hwmgr->hwmgr_func->force_dpm_level(hwmgr, level);
@@ -405,9 +420,12 @@ static int pp_dpm_get_sclk(void *handle, bool low)
hwmgr = ((struct pp_instance *)handle)->hwmgr;
- if (hwmgr == NULL || hwmgr->hwmgr_func == NULL ||
- hwmgr->hwmgr_func->get_sclk == NULL)
- return -EINVAL;
+ PP_CHECK_HW(hwmgr);
+
+ if (hwmgr->hwmgr_func->get_sclk == NULL) {
+ printk(KERN_INFO "%s was not implemented.\n", __func__);
+ return 0;
+ }
return hwmgr->hwmgr_func->get_sclk(hwmgr, low);
}
@@ -421,9 +439,12 @@ static int pp_dpm_get_mclk(void *handle, bool low)
hwmgr = ((struct pp_instance *)handle)->hwmgr;
- if (hwmgr == NULL || hwmgr->hwmgr_func == NULL ||
- hwmgr->hwmgr_func->get_mclk == NULL)
- return -EINVAL;
+ PP_CHECK_HW(hwmgr);
+
+ if (hwmgr->hwmgr_func->get_mclk == NULL) {
+ printk(KERN_INFO "%s was not implemented.\n", __func__);
+ return 0;
+ }
return hwmgr->hwmgr_func->get_mclk(hwmgr, low);
}
@@ -437,9 +458,12 @@ static int pp_dpm_powergate_vce(void *handle, bool gate)
hwmgr = ((struct pp_instance *)handle)->hwmgr;
- if (hwmgr == NULL || hwmgr->hwmgr_func == NULL ||
- hwmgr->hwmgr_func->powergate_vce == NULL)
- return -EINVAL;
+ PP_CHECK_HW(hwmgr);
+
+ if (hwmgr->hwmgr_func->powergate_vce == NULL) {
+ printk(KERN_INFO "%s was not implemented.\n", __func__);
+ return 0;
+ }
return hwmgr->hwmgr_func->powergate_vce(hwmgr, gate);
}
@@ -453,9 +477,12 @@ static int pp_dpm_powergate_uvd(void *handle, bool gate)
hwmgr = ((struct pp_instance *)handle)->hwmgr;
- if (hwmgr == NULL || hwmgr->hwmgr_func == NULL ||
- hwmgr->hwmgr_func->powergate_uvd == NULL)
- return -EINVAL;
+ PP_CHECK_HW(hwmgr);
+
+ if (hwmgr->hwmgr_func->powergate_uvd == NULL) {
+ printk(KERN_INFO "%s was not implemented.\n", __func__);
+ return 0;
+ }
return hwmgr->hwmgr_func->powergate_uvd(hwmgr, gate);
}
@@ -551,9 +578,13 @@ pp_debugfs_print_current_performance_level(void *handle,
hwmgr = ((struct pp_instance *)handle)->hwmgr;
- if (hwmgr == NULL || hwmgr->hwmgr_func == NULL ||
- hwmgr->hwmgr_func->print_current_perforce_level == NULL)
+ if (hwmgr == NULL || hwmgr->hwmgr_func == NULL)
+ return;
+
+ if (hwmgr->hwmgr_func->print_current_perforce_level == NULL) {
+ printk(KERN_INFO "%s was not implemented.\n", __func__);
return;
+ }
hwmgr->hwmgr_func->print_current_perforce_level(hwmgr, m);
}
@@ -567,9 +598,12 @@ static int pp_dpm_set_fan_control_mode(void *handle, uint32_t mode)
hwmgr = ((struct pp_instance *)handle)->hwmgr;
- if (hwmgr == NULL || hwmgr->hwmgr_func == NULL ||
- hwmgr->hwmgr_func->set_fan_control_mode == NULL)
- return -EINVAL;
+ PP_CHECK_HW(hwmgr);
+
+ if (hwmgr->hwmgr_func->set_fan_control_mode == NULL) {
+ printk(KERN_INFO "%s was not implemented.\n", __func__);
+ return 0;
+ }
return hwmgr->hwmgr_func->set_fan_control_mode(hwmgr, mode);
}
@@ -583,9 +617,12 @@ static int pp_dpm_get_fan_control_mode(void *handle)
hwmgr = ((struct pp_instance *)handle)->hwmgr;
- if (hwmgr == NULL || hwmgr->hwmgr_func == NULL ||
- hwmgr->hwmgr_func->get_fan_control_mode == NULL)
- return -EINVAL;
+ PP_CHECK_HW(hwmgr);
+
+ if (hwmgr->hwmgr_func->get_fan_control_mode == NULL) {
+ printk(KERN_INFO "%s was not implemented.\n", __func__);
+ return 0;
+ }
return hwmgr->hwmgr_func->get_fan_control_mode(hwmgr);
}
@@ -599,9 +636,12 @@ static int pp_dpm_set_fan_speed_percent(void *handle, uint32_t percent)
hwmgr = ((struct pp_instance *)handle)->hwmgr;
- if (hwmgr == NULL || hwmgr->hwmgr_func == NULL ||
- hwmgr->hwmgr_func->set_fan_speed_percent == NULL)
- return -EINVAL;
+ PP_CHECK_HW(hwmgr);
+
+ if (hwmgr->hwmgr_func->set_fan_speed_percent == NULL) {
+ printk(KERN_INFO "%s was not implemented.\n", __func__);
+ return 0;
+ }
return hwmgr->hwmgr_func->set_fan_speed_percent(hwmgr, percent);
}
@@ -615,9 +655,12 @@ static int pp_dpm_get_fan_speed_percent(void *handle, uint32_t *speed)
hwmgr = ((struct pp_instance *)handle)->hwmgr;
- if (hwmgr == NULL || hwmgr->hwmgr_func == NULL ||
- hwmgr->hwmgr_func->get_fan_speed_percent == NULL)
- return -EINVAL;
+ PP_CHECK_HW(hwmgr);
+
+ if (hwmgr->hwmgr_func->get_fan_speed_percent == NULL) {
+ printk(KERN_INFO "%s was not implemented.\n", __func__);
+ return 0;
+ }
return hwmgr->hwmgr_func->get_fan_speed_percent(hwmgr, speed);
}
@@ -631,9 +674,12 @@ static int pp_dpm_get_temperature(void *handle)
hwmgr = ((struct pp_instance *)handle)->hwmgr;
- if (hwmgr == NULL || hwmgr->hwmgr_func == NULL ||
- hwmgr->hwmgr_func->get_temperature == NULL)
- return -EINVAL;
+ PP_CHECK_HW(hwmgr);
+
+ if (hwmgr->hwmgr_func->get_temperature == NULL) {
+ printk(KERN_INFO "%s was not implemented.\n", __func__);
+ return 0;
+ }
return hwmgr->hwmgr_func->get_temperature(hwmgr);
}
@@ -687,9 +733,12 @@ static int pp_dpm_get_pp_table(void *handle, char **table)
hwmgr = ((struct pp_instance *)handle)->hwmgr;
- if (hwmgr == NULL || hwmgr->hwmgr_func == NULL ||
- hwmgr->hwmgr_func->get_pp_table == NULL)
- return -EINVAL;
+ PP_CHECK_HW(hwmgr);
+
+ if (hwmgr->hwmgr_func->get_pp_table == NULL) {
+ printk(KERN_INFO "%s was not implemented.\n", __func__);
+ return 0;
+ }
return hwmgr->hwmgr_func->get_pp_table(hwmgr, table);
}
@@ -703,9 +752,12 @@ static int pp_dpm_set_pp_table(void *handle, const char *buf, size_t size)
hwmgr = ((struct pp_instance *)handle)->hwmgr;
- if (hwmgr == NULL || hwmgr->hwmgr_func == NULL ||
- hwmgr->hwmgr_func->set_pp_table == NULL)
- return -EINVAL;
+ PP_CHECK_HW(hwmgr);
+
+ if (hwmgr->hwmgr_func->set_pp_table == NULL) {
+ printk(KERN_INFO "%s was not implemented.\n", __func__);
+ return 0;
+ }
return hwmgr->hwmgr_func->set_pp_table(hwmgr, buf, size);
}
@@ -720,9 +772,12 @@ static int pp_dpm_force_clock_level(void *handle,
hwmgr = ((struct pp_instance *)handle)->hwmgr;
- if (hwmgr == NULL || hwmgr->hwmgr_func == NULL ||
- hwmgr->hwmgr_func->force_clock_level == NULL)
- return -EINVAL;
+ PP_CHECK_HW(hwmgr);
+
+ if (hwmgr->hwmgr_func->force_clock_level == NULL) {
+ printk(KERN_INFO "%s was not implemented.\n", __func__);
+ return 0;
+ }
return hwmgr->hwmgr_func->force_clock_level(hwmgr, type, level);
}
@@ -737,10 +792,12 @@ static int pp_dpm_print_clock_levels(void *handle,
hwmgr = ((struct pp_instance *)handle)->hwmgr;
- if (hwmgr == NULL || hwmgr->hwmgr_func == NULL ||
- hwmgr->hwmgr_func->print_clock_levels == NULL)
- return -EINVAL;
+ PP_CHECK_HW(hwmgr);
+ if (hwmgr->hwmgr_func->print_clock_levels == NULL) {
+ printk(KERN_INFO "%s was not implemented.\n", __func__);
+ return 0;
+ }
return hwmgr->hwmgr_func->print_clock_levels(hwmgr, type, buf);
}
--
2.5.5
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^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH] drm/amd/powerplay: fix some initialize error on polaris10.
2016-05-02 20:00 Misc amdgpu patches Alex Deucher
` (32 preceding siblings ...)
2016-05-02 20:00 ` [PATCH] drm/amd/powerplay: return 0 when interface not implement on some asic Alex Deucher
@ 2016-05-02 20:00 ` Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amd/powerplay: fix bug dpm can't work when resume back on Polaris Alex Deucher
` (11 subsequent siblings)
45 siblings, 0 replies; 47+ messages in thread
From: Alex Deucher @ 2016-05-02 20:00 UTC (permalink / raw)
To: dri-devel; +Cc: Alex Deucher, Rex Zhu
From: Rex Zhu <Rex.Zhu@amd.com>
1. don't enable SclkThrottleLowNotification, it's not supported.
2. Set missing mclk_dpm0_activity_target
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c | 5 +----
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
index 045c7ef..c3e9aca 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
@@ -2600,9 +2600,6 @@ int polaris10_set_features_platform_caps(struct pp_hwmgr *hwmgr)
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_DynamicUVDState);
- phm_cap_set(hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_SclkThrottleLowNotification);
-
/* power tune caps Assume disabled */
phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_SQRamping);
@@ -2930,7 +2927,7 @@ int polaris10_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
data->dll_default_on = false;
data->sram_end = SMC_RAM_END;
-
+ data->mclk_dpm0_activity_target = 0xa;
data->disable_dpm_mask = 0xFF;
data->static_screen_threshold = PPPOLARIS10_STATICSCREENTHRESHOLD_DFLT;
data->static_screen_threshold_unit = PPPOLARIS10_STATICSCREENTHRESHOLD_DFLT;
--
2.5.5
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^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH] drm/amd/powerplay: fix bug dpm can't work when resume back on Polaris
2016-05-02 20:00 Misc amdgpu patches Alex Deucher
` (33 preceding siblings ...)
2016-05-02 20:00 ` [PATCH] drm/amd/powerplay: fix some initialize error on polaris10 Alex Deucher
@ 2016-05-02 20:00 ` Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amd/powerplay: fix fan speed percent setting error on Polaris10 Alex Deucher
` (10 subsequent siblings)
45 siblings, 0 replies; 47+ messages in thread
From: Alex Deucher @ 2016-05-02 20:00 UTC (permalink / raw)
To: dri-devel; +Cc: Eric Huang, Alex Deucher, Rex Zhu
From: Eric Huang <JinHuiEric.Huang@amd.com>
Need to initialize the values to 0 since they get or'ed with additional
values. If the initialization is missing, on resume, they may end up
with a combination of stale data and new data.
Fixes dpm on resume.
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
index c3e9aca..2ab3bb2 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
@@ -1565,6 +1565,7 @@ static int polaris10_populate_smc_vce_level(struct pp_hwmgr *hwmgr,
for (count = 0; count < table->VceLevelCount; count++) {
table->VceLevel[count].Frequency = mm_table->entries[count].eclk;
+ table->VceLevel[count].MinVoltage = 0;
table->VceLevel[count].MinVoltage |=
(mm_table->entries[count].vddc * VOLTAGE_SCALE) << VDDC_SHIFT;
table->VceLevel[count].MinVoltage |=
@@ -1604,6 +1605,7 @@ static int polaris10_populate_smc_samu_level(struct pp_hwmgr *hwmgr,
for (count = 0; count < table->SamuLevelCount; count++) {
/* not sure whether we need evclk or not */
+ table->SamuLevel[count].MinVoltage = 0;
table->SamuLevel[count].Frequency = mm_table->entries[count].samclock;
table->SamuLevel[count].MinVoltage |= (mm_table->entries[count].vddc *
VOLTAGE_SCALE) << VDDC_SHIFT;
@@ -1696,6 +1698,7 @@ static int polaris10_populate_smc_uvd_level(struct pp_hwmgr *hwmgr,
table->UvdBootLevel = 0;
for (count = 0; count < table->UvdLevelCount; count++) {
+ table->UvdLevel[count].MinVoltage = 0;
table->UvdLevel[count].VclkFrequency = mm_table->entries[count].vclk;
table->UvdLevel[count].DclkFrequency = mm_table->entries[count].dclk;
table->UvdLevel[count].MinVoltage |= (mm_table->entries[count].vddc *
@@ -2011,6 +2014,7 @@ static int polaris10_init_smc_table(struct pp_hwmgr *hwmgr)
if (POLARIS10_VOLTAGE_CONTROL_NONE != data->voltage_control)
polaris10_populate_smc_voltage_tables(hwmgr, table);
+ table->SystemFlags = 0;
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_AutomaticDCTransition))
table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
@@ -2104,6 +2108,7 @@ static int polaris10_init_smc_table(struct pp_hwmgr *hwmgr)
table->MemoryThermThrottleEnable = 1;
table->PCIeBootLinkLevel = 0;
table->PCIeGenInterval = 1;
+ table->VRConfig = 0;
result = polaris10_populate_vr_config(hwmgr, table);
PP_ASSERT_WITH_CODE(0 == result,
--
2.5.5
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https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH] drm/amd/powerplay: fix fan speed percent setting error on Polaris10
2016-05-02 20:00 Misc amdgpu patches Alex Deucher
` (34 preceding siblings ...)
2016-05-02 20:00 ` [PATCH] drm/amd/powerplay: fix bug dpm can't work when resume back on Polaris Alex Deucher
@ 2016-05-02 20:00 ` Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amd/powerplay: add dpm force multiple levels on cz/tonga/fiji/polaris (v2) Alex Deucher
` (9 subsequent siblings)
45 siblings, 0 replies; 47+ messages in thread
From: Alex Deucher @ 2016-05-02 20:00 UTC (permalink / raw)
To: dri-devel; +Cc: Eric Huang, Alex Deucher
From: Eric Huang <JinHuiEric.Huang@amd.com>
The logic was reversed.
Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_thermal.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_thermal.c b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_thermal.c
index d2f553d..d39c89b 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_thermal.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_thermal.c
@@ -220,8 +220,8 @@ int polaris10_fan_ctrl_set_fan_speed_percent(struct pp_hwmgr *hwmgr,
if (duty100 == 0)
return -EINVAL;
- tmp64 = (uint64_t)speed * 100;
- do_div(tmp64, duty100);
+ tmp64 = (uint64_t)speed * duty100;
+ do_div(tmp64, 100);
duty = (uint32_t)tmp64;
PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
--
2.5.5
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https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH] drm/amd/powerplay: add dpm force multiple levels on cz/tonga/fiji/polaris (v2)
2016-05-02 20:00 Misc amdgpu patches Alex Deucher
` (35 preceding siblings ...)
2016-05-02 20:00 ` [PATCH] drm/amd/powerplay: fix fan speed percent setting error on Polaris10 Alex Deucher
@ 2016-05-02 20:00 ` Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amd/powerplay: revise caching the soft pptable and add it's size Alex Deucher
` (8 subsequent siblings)
45 siblings, 0 replies; 47+ messages in thread
From: Alex Deucher @ 2016-05-02 20:00 UTC (permalink / raw)
To: dri-devel; +Cc: Eric Huang, Alex Deucher
From: Eric Huang <JinHuiEric.Huang@amd.com>
Allows you to force multiple levels rather than just one via the new
sysfs interrface.
v2: squash in:
drm/amd/powerplay: ensure clock level set by user is valid.
From Rex.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 51 +++++++++++++++-------
drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 4 +-
drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c | 6 +--
drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c | 18 ++++++--
.../gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c | 16 +++++--
drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c | 16 +++++--
drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h | 2 +-
drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 2 +-
8 files changed, 81 insertions(+), 34 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index 6d44d4a..589b36e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -362,16 +362,23 @@ static ssize_t amdgpu_set_pp_dpm_sclk(struct device *dev,
struct amdgpu_device *adev = ddev->dev_private;
int ret;
long level;
+ uint32_t i, mask = 0;
+ char sub_str[2];
- ret = kstrtol(buf, 0, &level);
+ for (i = 0; i < strlen(buf) - 1; i++) {
+ sub_str[0] = *(buf + i);
+ sub_str[1] = '\0';
+ ret = kstrtol(sub_str, 0, &level);
- if (ret) {
- count = -EINVAL;
- goto fail;
+ if (ret) {
+ count = -EINVAL;
+ goto fail;
+ }
+ mask |= 1 << level;
}
if (adev->pp_enabled)
- amdgpu_dpm_force_clock_level(adev, PP_SCLK, level);
+ amdgpu_dpm_force_clock_level(adev, PP_SCLK, mask);
fail:
return count;
}
@@ -399,16 +406,23 @@ static ssize_t amdgpu_set_pp_dpm_mclk(struct device *dev,
struct amdgpu_device *adev = ddev->dev_private;
int ret;
long level;
+ uint32_t i, mask = 0;
+ char sub_str[2];
- ret = kstrtol(buf, 0, &level);
+ for (i = 0; i < strlen(buf) - 1; i++) {
+ sub_str[0] = *(buf + i);
+ sub_str[1] = '\0';
+ ret = kstrtol(sub_str, 0, &level);
- if (ret) {
- count = -EINVAL;
- goto fail;
+ if (ret) {
+ count = -EINVAL;
+ goto fail;
+ }
+ mask |= 1 << level;
}
if (adev->pp_enabled)
- amdgpu_dpm_force_clock_level(adev, PP_MCLK, level);
+ amdgpu_dpm_force_clock_level(adev, PP_MCLK, mask);
fail:
return count;
}
@@ -436,16 +450,23 @@ static ssize_t amdgpu_set_pp_dpm_pcie(struct device *dev,
struct amdgpu_device *adev = ddev->dev_private;
int ret;
long level;
+ uint32_t i, mask = 0;
+ char sub_str[2];
- ret = kstrtol(buf, 0, &level);
+ for (i = 0; i < strlen(buf) - 1; i++) {
+ sub_str[0] = *(buf + i);
+ sub_str[1] = '\0';
+ ret = kstrtol(sub_str, 0, &level);
- if (ret) {
- count = -EINVAL;
- goto fail;
+ if (ret) {
+ count = -EINVAL;
+ goto fail;
+ }
+ mask |= 1 << level;
}
if (adev->pp_enabled)
- amdgpu_dpm_force_clock_level(adev, PP_PCIE, level);
+ amdgpu_dpm_force_clock_level(adev, PP_PCIE, mask);
fail:
return count;
}
diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
index ce8d9bf..0527ae3 100644
--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
@@ -763,7 +763,7 @@ static int pp_dpm_set_pp_table(void *handle, const char *buf, size_t size)
}
static int pp_dpm_force_clock_level(void *handle,
- enum pp_clock_type type, int level)
+ enum pp_clock_type type, uint32_t mask)
{
struct pp_hwmgr *hwmgr;
@@ -779,7 +779,7 @@ static int pp_dpm_force_clock_level(void *handle,
return 0;
}
- return hwmgr->hwmgr_func->force_clock_level(hwmgr, type, level);
+ return hwmgr->hwmgr_func->force_clock_level(hwmgr, type, mask);
}
static int pp_dpm_print_clock_levels(void *handle,
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
index 648394f..1f14c47 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
@@ -1729,7 +1729,7 @@ static int cz_get_dal_power_level(struct pp_hwmgr *hwmgr,
}
static int cz_force_clock_level(struct pp_hwmgr *hwmgr,
- enum pp_clock_type type, int level)
+ enum pp_clock_type type, uint32_t mask)
{
if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
return -EINVAL;
@@ -1738,10 +1738,10 @@ static int cz_force_clock_level(struct pp_hwmgr *hwmgr,
case PP_SCLK:
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
PPSMC_MSG_SetSclkSoftMin,
- (1 << level));
+ mask);
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
PPSMC_MSG_SetSclkSoftMax,
- (1 << level));
+ mask);
break;
default:
break;
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
index dc836d3..f8d49f1 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
@@ -5113,7 +5113,7 @@ static int fiji_set_pp_table(struct pp_hwmgr *hwmgr, const char *buf, size_t siz
}
static int fiji_force_clock_level(struct pp_hwmgr *hwmgr,
- enum pp_clock_type type, int level)
+ enum pp_clock_type type, uint32_t mask)
{
struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
@@ -5125,20 +5125,30 @@ static int fiji_force_clock_level(struct pp_hwmgr *hwmgr,
if (!data->sclk_dpm_key_disabled)
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
PPSMC_MSG_SCLKDPM_SetEnabledMask,
- (1 << level));
+ data->dpm_level_enable_mask.sclk_dpm_enable_mask & mask);
break;
+
case PP_MCLK:
if (!data->mclk_dpm_key_disabled)
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
PPSMC_MSG_MCLKDPM_SetEnabledMask,
- (1 << level));
+ data->dpm_level_enable_mask.mclk_dpm_enable_mask & mask);
break;
+
case PP_PCIE:
+ {
+ uint32_t tmp = mask & data->dpm_level_enable_mask.pcie_dpm_enable_mask;
+ uint32_t level = 0;
+
+ while (tmp >>= 1)
+ level++;
+
if (!data->pcie_dpm_key_disabled)
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
PPSMC_MSG_PCIeDPM_ForceLevel,
- (1 << level));
+ level);
break;
+ }
default:
break;
}
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
index 2ab3bb2..79192c3 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
@@ -4767,7 +4767,7 @@ static int polaris10_set_pp_table(struct pp_hwmgr *hwmgr, const char *buf, size_
}
static int polaris10_force_clock_level(struct pp_hwmgr *hwmgr,
- enum pp_clock_type type, int level)
+ enum pp_clock_type type, uint32_t mask)
{
struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
@@ -4779,20 +4779,28 @@ static int polaris10_force_clock_level(struct pp_hwmgr *hwmgr,
if (!data->sclk_dpm_key_disabled)
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
PPSMC_MSG_SCLKDPM_SetEnabledMask,
- (1 << level));
+ data->dpm_level_enable_mask.sclk_dpm_enable_mask & mask);
break;
case PP_MCLK:
if (!data->mclk_dpm_key_disabled)
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
PPSMC_MSG_MCLKDPM_SetEnabledMask,
- (1 << level));
+ data->dpm_level_enable_mask.mclk_dpm_enable_mask & mask);
break;
case PP_PCIE:
+ {
+ uint32_t tmp = mask & data->dpm_level_enable_mask.pcie_dpm_enable_mask;
+ uint32_t level = 0;
+
+ while (tmp >>= 1)
+ level++;
+
if (!data->pcie_dpm_key_disabled)
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
PPSMC_MSG_PCIeDPM_ForceLevel,
- (1 << level));
+ level);
break;
+ }
default:
break;
}
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
index 0242e34..9040225 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
@@ -6075,7 +6075,7 @@ static int tonga_set_pp_table(struct pp_hwmgr *hwmgr, const char *buf, size_t si
}
static int tonga_force_clock_level(struct pp_hwmgr *hwmgr,
- enum pp_clock_type type, int level)
+ enum pp_clock_type type, uint32_t mask)
{
struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
@@ -6087,20 +6087,28 @@ static int tonga_force_clock_level(struct pp_hwmgr *hwmgr,
if (!data->sclk_dpm_key_disabled)
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
PPSMC_MSG_SCLKDPM_SetEnabledMask,
- (1 << level));
+ data->dpm_level_enable_mask.sclk_dpm_enable_mask & mask);
break;
case PP_MCLK:
if (!data->mclk_dpm_key_disabled)
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
PPSMC_MSG_MCLKDPM_SetEnabledMask,
- (1 << level));
+ data->dpm_level_enable_mask.mclk_dpm_enable_mask & mask);
break;
case PP_PCIE:
+ {
+ uint32_t tmp = mask & data->dpm_level_enable_mask.pcie_dpm_enable_mask;
+ uint32_t level = 0;
+
+ while (tmp >>= 1)
+ level++;
+
if (!data->pcie_dpm_key_disabled)
smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
PPSMC_MSG_PCIeDPM_ForceLevel,
- (1 << level));
+ level);
break;
+ }
default:
break;
}
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h b/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h
index e5f2ee7..50b367d 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h
@@ -340,7 +340,7 @@ struct amd_powerplay_funcs {
int (*get_pp_num_states)(void *handle, struct pp_states_info *data);
int (*get_pp_table)(void *handle, char **table);
int (*set_pp_table)(void *handle, const char *buf, size_t size);
- int (*force_clock_level)(void *handle, enum pp_clock_type type, int level);
+ int (*force_clock_level)(void *handle, enum pp_clock_type type, uint32_t mask);
int (*print_clock_levels)(void *handle, enum pp_clock_type type, char *buf);
};
diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
index 12285a9..b1a9ae5 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
@@ -335,7 +335,7 @@ struct pp_hwmgr_func {
int (*power_off_asic)(struct pp_hwmgr *hwmgr);
int (*get_pp_table)(struct pp_hwmgr *hwmgr, char **table);
int (*set_pp_table)(struct pp_hwmgr *hwmgr, const char *buf, size_t size);
- int (*force_clock_level)(struct pp_hwmgr *hwmgr, enum pp_clock_type type, int level);
+ int (*force_clock_level)(struct pp_hwmgr *hwmgr, enum pp_clock_type type, uint32_t mask);
int (*print_clock_levels)(struct pp_hwmgr *hwmgr, enum pp_clock_type type, char *buf);
int (*enable_per_cu_power_gating)(struct pp_hwmgr *hwmgr, bool enable);
};
--
2.5.5
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH] drm/amd/powerplay: revise caching the soft pptable and add it's size
2016-05-02 20:00 Misc amdgpu patches Alex Deucher
` (36 preceding siblings ...)
2016-05-02 20:00 ` [PATCH] drm/amd/powerplay: add dpm force multiple levels on cz/tonga/fiji/polaris (v2) Alex Deucher
@ 2016-05-02 20:00 ` Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amd/powerplay: revise reading/writing pptable on Fiji Alex Deucher
` (7 subsequent siblings)
45 siblings, 0 replies; 47+ messages in thread
From: Alex Deucher @ 2016-05-02 20:00 UTC (permalink / raw)
To: dri-devel; +Cc: Eric Huang, Alex Deucher
From: Eric Huang <JinHuiEric.Huang@amd.com>
This fixes a bug in the pptable access interface that could lead to
a crash. Check the pointer before using it.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
.../gpu/drm/amd/powerplay/hwmgr/tonga_processpptables.c | 15 +++++++++------
drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 1 +
2 files changed, 10 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_processpptables.c b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_processpptables.c
index 96a2787..10e3630 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_processpptables.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_processpptables.c
@@ -138,12 +138,15 @@ const void *get_powerplay_table(struct pp_hwmgr *hwmgr)
u16 size;
u8 frev, crev;
- void *table_address;
-
- table_address = (ATOM_Tonga_POWERPLAYTABLE *)
- cgs_atom_get_data_table(hwmgr->device, index, &size, &frev, &crev);
-
- hwmgr->soft_pp_table = table_address; /*Cache the result in RAM.*/
+ void *table_address = (void *)hwmgr->soft_pp_table;
+
+ if (!table_address) {
+ table_address = (ATOM_Tonga_POWERPLAYTABLE *)
+ cgs_atom_get_data_table(hwmgr->device,
+ index, &size, &frev, &crev);
+ hwmgr->soft_pp_table = table_address; /*Cache the result in RAM.*/
+ hwmgr->soft_pp_table_size = size;
+ }
return table_address;
}
diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
index b1a9ae5..c96e5b1 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
@@ -577,6 +577,7 @@ struct pp_hwmgr {
void *device;
struct pp_smumgr *smumgr;
const void *soft_pp_table;
+ uint32_t soft_pp_table_size;
bool need_pp_table_upload;
enum amd_dpm_forced_level dpm_level;
bool block_hw_access;
--
2.5.5
_______________________________________________
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dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH] drm/amd/powerplay: revise reading/writing pptable on Fiji
2016-05-02 20:00 Misc amdgpu patches Alex Deucher
` (37 preceding siblings ...)
2016-05-02 20:00 ` [PATCH] drm/amd/powerplay: revise caching the soft pptable and add it's size Alex Deucher
@ 2016-05-02 20:00 ` Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amd/powerplay: revise reading/writing pptable on Tonga Alex Deucher
` (6 subsequent siblings)
45 siblings, 0 replies; 47+ messages in thread
From: Alex Deucher @ 2016-05-02 20:00 UTC (permalink / raw)
To: dri-devel; +Cc: Eric Huang, Alex Deucher
From: Eric Huang <JinHuiEric.Huang@amd.com>
Change the way we store pptables in the driver to better
facilitate eventual runtime updates for debugging.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c | 40 ++++++++++++++++++++----
drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.h | 4 ++-
2 files changed, 37 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
index f8d49f1..55e877c 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
@@ -579,6 +579,18 @@ static int fiji_patch_boot_state(struct pp_hwmgr *hwmgr,
return 0;
}
+static int fiji_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
+{
+ struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
+
+ if (data->soft_pp_table) {
+ kfree(data->soft_pp_table);
+ data->soft_pp_table = NULL;
+ }
+
+ return phm_hwmgr_backend_fini(hwmgr);
+}
+
static int fiji_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
{
struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
@@ -734,7 +746,7 @@ static int fiji_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
data->pcie_lane_cap = (uint32_t)sys_info.value;
} else {
/* Ignore return value in here, we are cleaning up a mess. */
- tonga_hwmgr_backend_fini(hwmgr);
+ fiji_hwmgr_backend_fini(hwmgr);
}
return 0;
@@ -5096,18 +5108,34 @@ static int fiji_get_pp_table(struct pp_hwmgr *hwmgr, char **table)
{
struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
- *table = (char *)&data->smc_state_table;
+ if (!data->soft_pp_table) {
+ data->soft_pp_table = kzalloc(hwmgr->soft_pp_table_size, GFP_KERNEL);
+ if (!data->soft_pp_table)
+ return -ENOMEM;
+ memcpy(data->soft_pp_table, hwmgr->soft_pp_table,
+ hwmgr->soft_pp_table_size);
+ }
+
+ *table = (char *)&data->soft_pp_table;
- return sizeof(struct SMU73_Discrete_DpmTable);
+ return hwmgr->soft_pp_table_size;
}
static int fiji_set_pp_table(struct pp_hwmgr *hwmgr, const char *buf, size_t size)
{
struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
- void *table = (void *)&data->smc_state_table;
+ if (!data->soft_pp_table) {
+ data->soft_pp_table = kzalloc(hwmgr->soft_pp_table_size, GFP_KERNEL);
+ if (!data->soft_pp_table)
+ return -ENOMEM;
+ }
+
+ memcpy(data->soft_pp_table, buf, size);
+
+ hwmgr->soft_pp_table = data->soft_pp_table;
- memcpy(table, buf, size);
+ /* TODO: re-init powerplay to implement modified pptable */
return 0;
}
@@ -5284,7 +5312,7 @@ bool fiji_check_smc_update_required_for_display_configuration(struct pp_hwmgr *h
static const struct pp_hwmgr_func fiji_hwmgr_funcs = {
.backend_init = &fiji_hwmgr_backend_init,
- .backend_fini = &tonga_hwmgr_backend_fini,
+ .backend_fini = &fiji_hwmgr_backend_fini,
.asic_setup = &fiji_setup_asic_task,
.dynamic_state_management_enable = &fiji_enable_dpm_tasks,
.force_dpm_level = &fiji_dpm_force_dpm_level,
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.h
index 4b29d9e..170edf5 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.h
@@ -302,6 +302,9 @@ struct fiji_hwmgr {
bool pg_acp_init;
bool frtc_enabled;
bool frtc_status_changed;
+
+ /* soft pptable for re-uploading into smu */
+ void *soft_pp_table;
};
/* To convert to Q8.8 format for firmware */
@@ -338,7 +341,6 @@ enum Fiji_I2CLineID {
#define FIJI_UNUSED_GPIO_PIN 0x7F
extern int tonga_initializa_dynamic_state_adjustment_rule_settings(struct pp_hwmgr *hwmgr);
-extern int tonga_hwmgr_backend_fini(struct pp_hwmgr *hwmgr);
extern int tonga_get_mc_microcode_version (struct pp_hwmgr *hwmgr);
extern int tonga_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr);
extern int tonga_notify_smc_display_change(struct pp_hwmgr *hwmgr, bool has_display);
--
2.5.5
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dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH] drm/amd/powerplay: revise reading/writing pptable on Tonga
2016-05-02 20:00 Misc amdgpu patches Alex Deucher
` (38 preceding siblings ...)
2016-05-02 20:00 ` [PATCH] drm/amd/powerplay: revise reading/writing pptable on Fiji Alex Deucher
@ 2016-05-02 20:00 ` Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amd/powerplay: revise reading/writing pptable on Polaris10 Alex Deucher
` (5 subsequent siblings)
45 siblings, 0 replies; 47+ messages in thread
From: Alex Deucher @ 2016-05-02 20:00 UTC (permalink / raw)
To: dri-devel; +Cc: Eric Huang, Alex Deucher
From: Eric Huang <JinHuiEric.Huang@amd.com>
Change the way we store pptables in the driver to better
facilitate eventual runtime updates for debugging.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c | 37 +++++++++++++++--------
drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.h | 2 ++
2 files changed, 27 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
index 9040225..28f5c65 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
@@ -4443,17 +4443,14 @@ int tonga_reset_asic_tasks(struct pp_hwmgr *hwmgr)
int tonga_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
{
- if (NULL != hwmgr->dyn_state.vddc_dep_on_dal_pwrl) {
- kfree(hwmgr->dyn_state.vddc_dep_on_dal_pwrl);
- hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL;
- }
+ struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
- if (NULL != hwmgr->backend) {
- kfree(hwmgr->backend);
- hwmgr->backend = NULL;
+ if (data->soft_pp_table) {
+ kfree(data->soft_pp_table);
+ data->soft_pp_table = NULL;
}
- return 0;
+ return phm_hwmgr_backend_fini(hwmgr);
}
/**
@@ -6058,18 +6055,34 @@ static int tonga_get_pp_table(struct pp_hwmgr *hwmgr, char **table)
{
struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
- *table = (char *)&data->smc_state_table;
+ if (!data->soft_pp_table) {
+ data->soft_pp_table = kzalloc(hwmgr->soft_pp_table_size, GFP_KERNEL);
+ if (!data->soft_pp_table)
+ return -ENOMEM;
+ memcpy(data->soft_pp_table, hwmgr->soft_pp_table,
+ hwmgr->soft_pp_table_size);
+ }
+
+ *table = (char *)&data->soft_pp_table;
- return sizeof(struct SMU72_Discrete_DpmTable);
+ return hwmgr->soft_pp_table_size;
}
static int tonga_set_pp_table(struct pp_hwmgr *hwmgr, const char *buf, size_t size)
{
struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
- void *table = (void *)&data->smc_state_table;
+ if (!data->soft_pp_table) {
+ data->soft_pp_table = kzalloc(hwmgr->soft_pp_table_size, GFP_KERNEL);
+ if (!data->soft_pp_table)
+ return -ENOMEM;
+ }
+
+ memcpy(data->soft_pp_table, buf, size);
+
+ hwmgr->soft_pp_table = data->soft_pp_table;
- memcpy(table, buf, size);
+ /* TODO: re-init powerplay to implement modified pptable */
return 0;
}
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.h
index f88d3bb..c6a6b40 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.h
@@ -353,6 +353,8 @@ struct tonga_hwmgr {
bool acp_power_gated; /* 1: gated, 0:not gated */
bool pg_acp_init;
+ /* soft pptable for re-uploading into smu */
+ void *soft_pp_table;
};
typedef struct tonga_hwmgr tonga_hwmgr;
--
2.5.5
_______________________________________________
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dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH] drm/amd/powerplay: revise reading/writing pptable on Polaris10
2016-05-02 20:00 Misc amdgpu patches Alex Deucher
` (39 preceding siblings ...)
2016-05-02 20:00 ` [PATCH] drm/amd/powerplay: revise reading/writing pptable on Tonga Alex Deucher
@ 2016-05-02 20:00 ` Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amd/amdgpu: Drop print_status callbacks Alex Deucher
` (4 subsequent siblings)
45 siblings, 0 replies; 47+ messages in thread
From: Alex Deucher @ 2016-05-02 20:00 UTC (permalink / raw)
To: dri-devel; +Cc: Eric Huang, Alex Deucher
From: Eric Huang <JinHuiEric.Huang@amd.com>
Change the way we store pptables in the driver to better
facilitate eventual runtime updates for debugging.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
.../gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c | 31 +++++++++++++++++++---
.../gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.h | 3 +++
2 files changed, 30 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
index 79192c3..b146ec8 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
@@ -2560,6 +2560,13 @@ int polaris10_reset_asic_tasks(struct pp_hwmgr *hwmgr)
int polaris10_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
{
+ struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
+
+ if (data->soft_pp_table) {
+ kfree(data->soft_pp_table);
+ data->soft_pp_table = NULL;
+ }
+
return phm_hwmgr_backend_fini(hwmgr);
}
@@ -4750,18 +4757,34 @@ static int polaris10_get_pp_table(struct pp_hwmgr *hwmgr, char **table)
{
struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
- *table = (char *)&data->smc_state_table;
+ if (!data->soft_pp_table) {
+ data->soft_pp_table = kzalloc(hwmgr->soft_pp_table_size, GFP_KERNEL);
+ if (!data->soft_pp_table)
+ return -ENOMEM;
+ memcpy(data->soft_pp_table, hwmgr->soft_pp_table,
+ hwmgr->soft_pp_table_size);
+ }
- return sizeof(struct SMU74_Discrete_DpmTable);
+ *table = (char *)&data->soft_pp_table;
+
+ return hwmgr->soft_pp_table_size;
}
static int polaris10_set_pp_table(struct pp_hwmgr *hwmgr, const char *buf, size_t size)
{
struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
- void *table = (void *)&data->smc_state_table;
+ if (!data->soft_pp_table) {
+ data->soft_pp_table = kzalloc(hwmgr->soft_pp_table_size, GFP_KERNEL);
+ if (!data->soft_pp_table)
+ return -ENOMEM;
+ }
+
+ memcpy(data->soft_pp_table, buf, size);
+
+ hwmgr->soft_pp_table = data->soft_pp_table;
- memcpy(table, buf, size);
+ /* TODO: re-init powerplay to implement modified pptable */
return 0;
}
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.h
index 2507404..b022964 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.h
@@ -309,6 +309,9 @@ struct polaris10_hwmgr {
uint32_t up_hyst;
uint32_t disable_dpm_mask;
bool apply_optimized_settings;
+
+ /* soft pptable for re-uploading into smu */
+ void *soft_pp_table;
};
/* To convert to Q8.8 format for firmware */
--
2.5.5
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https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH] drm/amd/amdgpu: Drop print_status callbacks.
2016-05-02 20:00 Misc amdgpu patches Alex Deucher
` (40 preceding siblings ...)
2016-05-02 20:00 ` [PATCH] drm/amd/powerplay: revise reading/writing pptable on Polaris10 Alex Deucher
@ 2016-05-02 20:00 ` Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amd/amdgpu: Add debugfs entries for smc/didt/pcie Alex Deucher
` (3 subsequent siblings)
45 siblings, 0 replies; 47+ messages in thread
From: Alex Deucher @ 2016-05-02 20:00 UTC (permalink / raw)
To: dri-devel; +Cc: Tom St Denis, Alex Deucher
From: Tom St Denis <tom.stdenis@amd.com>
First patch in series to move to user mode
debug tools we're removing the print_status callbacks.
These functions were unused at the moment anyway.
Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c | 8 -
drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c | 10 -
drivers/gpu/drm/amd/amdgpu/ci_dpm.c | 210 ---------------------
drivers/gpu/drm/amd/amdgpu/cik.c | 6 -
drivers/gpu/drm/amd/amdgpu/cik_ih.c | 34 ----
drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 56 ------
drivers/gpu/drm/amd/amdgpu/cz_dpm.c | 1 -
drivers/gpu/drm/amd/amdgpu/cz_ih.c | 34 ----
drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 12 --
drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 12 --
drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 12 --
drivers/gpu/drm/amd/amdgpu/fiji_dpm.c | 1 -
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 253 --------------------------
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 182 ------------------
drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 113 ------------
drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 110 -----------
drivers/gpu/drm/amd/amdgpu/iceland_dpm.c | 1 -
drivers/gpu/drm/amd/amdgpu/iceland_ih.c | 34 ----
drivers/gpu/drm/amd/amdgpu/kv_dpm.c | 57 ------
drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 54 ------
drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 56 ------
drivers/gpu/drm/amd/amdgpu/tonga_dpm.c | 1 -
drivers/gpu/drm/amd/amdgpu/tonga_ih.c | 34 ----
drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c | 112 ------------
drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c | 115 ------------
drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 107 -----------
drivers/gpu/drm/amd/amdgpu/vce_v2_0.c | 70 -------
drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 68 -------
drivers/gpu/drm/amd/amdgpu/vi.c | 6 -
drivers/gpu/drm/amd/include/amd_shared.h | 2 -
drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 5 -
31 files changed, 1776 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
index d6b0bff..da764e1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
@@ -463,13 +463,6 @@ static int acp_soft_reset(void *handle)
return 0;
}
-static void acp_print_status(void *handle)
-{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-
- dev_info(adev->dev, "ACP STATUS\n");
-}
-
static int acp_set_clockgating_state(void *handle,
enum amd_clockgating_state state)
{
@@ -494,7 +487,6 @@ const struct amd_ip_funcs acp_ip_funcs = {
.is_idle = acp_is_idle,
.wait_for_idle = acp_wait_for_idle,
.soft_reset = acp_soft_reset,
- .print_status = acp_print_status,
.set_clockgating_state = acp_set_clockgating_state,
.set_powergating_state = acp_set_powergating_state,
};
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
index f315995..be56595 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
@@ -303,15 +303,6 @@ static int amdgpu_pp_soft_reset(void *handle)
return ret;
}
-static void amdgpu_pp_print_status(void *handle)
-{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-
- if (adev->powerplay.ip_funcs->print_status)
- adev->powerplay.ip_funcs->print_status(
- adev->powerplay.pp_handle);
-}
-
const struct amd_ip_funcs amdgpu_pp_ip_funcs = {
.early_init = amdgpu_pp_early_init,
.late_init = amdgpu_pp_late_init,
@@ -324,7 +315,6 @@ const struct amd_ip_funcs amdgpu_pp_ip_funcs = {
.is_idle = amdgpu_pp_is_idle,
.wait_for_idle = amdgpu_pp_wait_for_idle,
.soft_reset = amdgpu_pp_soft_reset,
- .print_status = amdgpu_pp_print_status,
.set_clockgating_state = amdgpu_pp_set_clockgating_state,
.set_powergating_state = amdgpu_pp_set_powergating_state,
};
diff --git a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
index 1f9109d..90f83b2 100644
--- a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
@@ -6309,215 +6309,6 @@ static int ci_dpm_wait_for_idle(void *handle)
return 0;
}
-static void ci_dpm_print_status(void *handle)
-{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-
- dev_info(adev->dev, "CIK DPM registers\n");
- dev_info(adev->dev, " BIOS_SCRATCH_4=0x%08X\n",
- RREG32(mmBIOS_SCRATCH_4));
- dev_info(adev->dev, " MC_ARB_DRAM_TIMING=0x%08X\n",
- RREG32(mmMC_ARB_DRAM_TIMING));
- dev_info(adev->dev, " MC_ARB_DRAM_TIMING2=0x%08X\n",
- RREG32(mmMC_ARB_DRAM_TIMING2));
- dev_info(adev->dev, " MC_ARB_BURST_TIME=0x%08X\n",
- RREG32(mmMC_ARB_BURST_TIME));
- dev_info(adev->dev, " MC_ARB_DRAM_TIMING_1=0x%08X\n",
- RREG32(mmMC_ARB_DRAM_TIMING_1));
- dev_info(adev->dev, " MC_ARB_DRAM_TIMING2_1=0x%08X\n",
- RREG32(mmMC_ARB_DRAM_TIMING2_1));
- dev_info(adev->dev, " MC_CG_CONFIG=0x%08X\n",
- RREG32(mmMC_CG_CONFIG));
- dev_info(adev->dev, " MC_ARB_CG=0x%08X\n",
- RREG32(mmMC_ARB_CG));
- dev_info(adev->dev, " DIDT_SQ_CTRL0=0x%08X\n",
- RREG32_DIDT(ixDIDT_SQ_CTRL0));
- dev_info(adev->dev, " DIDT_DB_CTRL0=0x%08X\n",
- RREG32_DIDT(ixDIDT_DB_CTRL0));
- dev_info(adev->dev, " DIDT_TD_CTRL0=0x%08X\n",
- RREG32_DIDT(ixDIDT_TD_CTRL0));
- dev_info(adev->dev, " DIDT_TCP_CTRL0=0x%08X\n",
- RREG32_DIDT(ixDIDT_TCP_CTRL0));
- dev_info(adev->dev, " CG_THERMAL_INT=0x%08X\n",
- RREG32_SMC(ixCG_THERMAL_INT));
- dev_info(adev->dev, " CG_THERMAL_CTRL=0x%08X\n",
- RREG32_SMC(ixCG_THERMAL_CTRL));
- dev_info(adev->dev, " GENERAL_PWRMGT=0x%08X\n",
- RREG32_SMC(ixGENERAL_PWRMGT));
- dev_info(adev->dev, " MC_SEQ_CNTL_3=0x%08X\n",
- RREG32(mmMC_SEQ_CNTL_3));
- dev_info(adev->dev, " LCAC_MC0_CNTL=0x%08X\n",
- RREG32_SMC(ixLCAC_MC0_CNTL));
- dev_info(adev->dev, " LCAC_MC1_CNTL=0x%08X\n",
- RREG32_SMC(ixLCAC_MC1_CNTL));
- dev_info(adev->dev, " LCAC_CPL_CNTL=0x%08X\n",
- RREG32_SMC(ixLCAC_CPL_CNTL));
- dev_info(adev->dev, " SCLK_PWRMGT_CNTL=0x%08X\n",
- RREG32_SMC(ixSCLK_PWRMGT_CNTL));
- dev_info(adev->dev, " BIF_LNCNT_RESET=0x%08X\n",
- RREG32(mmBIF_LNCNT_RESET));
- dev_info(adev->dev, " FIRMWARE_FLAGS=0x%08X\n",
- RREG32_SMC(ixFIRMWARE_FLAGS));
- dev_info(adev->dev, " CG_SPLL_FUNC_CNTL=0x%08X\n",
- RREG32_SMC(ixCG_SPLL_FUNC_CNTL));
- dev_info(adev->dev, " CG_SPLL_FUNC_CNTL_2=0x%08X\n",
- RREG32_SMC(ixCG_SPLL_FUNC_CNTL_2));
- dev_info(adev->dev, " CG_SPLL_FUNC_CNTL_3=0x%08X\n",
- RREG32_SMC(ixCG_SPLL_FUNC_CNTL_3));
- dev_info(adev->dev, " CG_SPLL_FUNC_CNTL_4=0x%08X\n",
- RREG32_SMC(ixCG_SPLL_FUNC_CNTL_4));
- dev_info(adev->dev, " CG_SPLL_SPREAD_SPECTRUM=0x%08X\n",
- RREG32_SMC(ixCG_SPLL_SPREAD_SPECTRUM));
- dev_info(adev->dev, " CG_SPLL_SPREAD_SPECTRUM_2=0x%08X\n",
- RREG32_SMC(ixCG_SPLL_SPREAD_SPECTRUM_2));
- dev_info(adev->dev, " DLL_CNTL=0x%08X\n",
- RREG32(mmDLL_CNTL));
- dev_info(adev->dev, " MCLK_PWRMGT_CNTL=0x%08X\n",
- RREG32(mmMCLK_PWRMGT_CNTL));
- dev_info(adev->dev, " MPLL_AD_FUNC_CNTL=0x%08X\n",
- RREG32(mmMPLL_AD_FUNC_CNTL));
- dev_info(adev->dev, " MPLL_DQ_FUNC_CNTL=0x%08X\n",
- RREG32(mmMPLL_DQ_FUNC_CNTL));
- dev_info(adev->dev, " MPLL_FUNC_CNTL=0x%08X\n",
- RREG32(mmMPLL_FUNC_CNTL));
- dev_info(adev->dev, " MPLL_FUNC_CNTL_1=0x%08X\n",
- RREG32(mmMPLL_FUNC_CNTL_1));
- dev_info(adev->dev, " MPLL_FUNC_CNTL_2=0x%08X\n",
- RREG32(mmMPLL_FUNC_CNTL_2));
- dev_info(adev->dev, " MPLL_SS1=0x%08X\n",
- RREG32(mmMPLL_SS1));
- dev_info(adev->dev, " MPLL_SS2=0x%08X\n",
- RREG32(mmMPLL_SS2));
- dev_info(adev->dev, " CG_DISPLAY_GAP_CNTL=0x%08X\n",
- RREG32_SMC(ixCG_DISPLAY_GAP_CNTL));
- dev_info(adev->dev, " CG_DISPLAY_GAP_CNTL2=0x%08X\n",
- RREG32_SMC(ixCG_DISPLAY_GAP_CNTL2));
- dev_info(adev->dev, " CG_STATIC_SCREEN_PARAMETER=0x%08X\n",
- RREG32_SMC(ixCG_STATIC_SCREEN_PARAMETER));
- dev_info(adev->dev, " CG_FREQ_TRAN_VOTING_0=0x%08X\n",
- RREG32_SMC(ixCG_FREQ_TRAN_VOTING_0));
- dev_info(adev->dev, " CG_FREQ_TRAN_VOTING_1=0x%08X\n",
- RREG32_SMC(ixCG_FREQ_TRAN_VOTING_1));
- dev_info(adev->dev, " CG_FREQ_TRAN_VOTING_2=0x%08X\n",
- RREG32_SMC(ixCG_FREQ_TRAN_VOTING_2));
- dev_info(adev->dev, " CG_FREQ_TRAN_VOTING_3=0x%08X\n",
- RREG32_SMC(ixCG_FREQ_TRAN_VOTING_3));
- dev_info(adev->dev, " CG_FREQ_TRAN_VOTING_4=0x%08X\n",
- RREG32_SMC(ixCG_FREQ_TRAN_VOTING_4));
- dev_info(adev->dev, " CG_FREQ_TRAN_VOTING_5=0x%08X\n",
- RREG32_SMC(ixCG_FREQ_TRAN_VOTING_5));
- dev_info(adev->dev, " CG_FREQ_TRAN_VOTING_6=0x%08X\n",
- RREG32_SMC(ixCG_FREQ_TRAN_VOTING_6));
- dev_info(adev->dev, " CG_FREQ_TRAN_VOTING_7=0x%08X\n",
- RREG32_SMC(ixCG_FREQ_TRAN_VOTING_7));
- dev_info(adev->dev, " RCU_UC_EVENTS=0x%08X\n",
- RREG32_SMC(ixRCU_UC_EVENTS));
- dev_info(adev->dev, " DPM_TABLE_475=0x%08X\n",
- RREG32_SMC(ixDPM_TABLE_475));
- dev_info(adev->dev, " MC_SEQ_RAS_TIMING_LP=0x%08X\n",
- RREG32(mmMC_SEQ_RAS_TIMING_LP));
- dev_info(adev->dev, " MC_SEQ_RAS_TIMING=0x%08X\n",
- RREG32(mmMC_SEQ_RAS_TIMING));
- dev_info(adev->dev, " MC_SEQ_CAS_TIMING_LP=0x%08X\n",
- RREG32(mmMC_SEQ_CAS_TIMING_LP));
- dev_info(adev->dev, " MC_SEQ_CAS_TIMING=0x%08X\n",
- RREG32(mmMC_SEQ_CAS_TIMING));
- dev_info(adev->dev, " MC_SEQ_DLL_STBY_LP=0x%08X\n",
- RREG32(mmMC_SEQ_DLL_STBY_LP));
- dev_info(adev->dev, " MC_SEQ_DLL_STBY=0x%08X\n",
- RREG32(mmMC_SEQ_DLL_STBY));
- dev_info(adev->dev, " MC_SEQ_G5PDX_CMD0_LP=0x%08X\n",
- RREG32(mmMC_SEQ_G5PDX_CMD0_LP));
- dev_info(adev->dev, " MC_SEQ_G5PDX_CMD0=0x%08X\n",
- RREG32(mmMC_SEQ_G5PDX_CMD0));
- dev_info(adev->dev, " MC_SEQ_G5PDX_CMD1_LP=0x%08X\n",
- RREG32(mmMC_SEQ_G5PDX_CMD1_LP));
- dev_info(adev->dev, " MC_SEQ_G5PDX_CMD1=0x%08X\n",
- RREG32(mmMC_SEQ_G5PDX_CMD1));
- dev_info(adev->dev, " MC_SEQ_G5PDX_CTRL_LP=0x%08X\n",
- RREG32(mmMC_SEQ_G5PDX_CTRL_LP));
- dev_info(adev->dev, " MC_SEQ_G5PDX_CTRL=0x%08X\n",
- RREG32(mmMC_SEQ_G5PDX_CTRL));
- dev_info(adev->dev, " MC_SEQ_PMG_DVS_CMD_LP=0x%08X\n",
- RREG32(mmMC_SEQ_PMG_DVS_CMD_LP));
- dev_info(adev->dev, " MC_SEQ_PMG_DVS_CMD=0x%08X\n",
- RREG32(mmMC_SEQ_PMG_DVS_CMD));
- dev_info(adev->dev, " MC_SEQ_PMG_DVS_CTL_LP=0x%08X\n",
- RREG32(mmMC_SEQ_PMG_DVS_CTL_LP));
- dev_info(adev->dev, " MC_SEQ_PMG_DVS_CTL=0x%08X\n",
- RREG32(mmMC_SEQ_PMG_DVS_CTL));
- dev_info(adev->dev, " MC_SEQ_MISC_TIMING_LP=0x%08X\n",
- RREG32(mmMC_SEQ_MISC_TIMING_LP));
- dev_info(adev->dev, " MC_SEQ_MISC_TIMING=0x%08X\n",
- RREG32(mmMC_SEQ_MISC_TIMING));
- dev_info(adev->dev, " MC_SEQ_MISC_TIMING2_LP=0x%08X\n",
- RREG32(mmMC_SEQ_MISC_TIMING2_LP));
- dev_info(adev->dev, " MC_SEQ_MISC_TIMING2=0x%08X\n",
- RREG32(mmMC_SEQ_MISC_TIMING2));
- dev_info(adev->dev, " MC_SEQ_PMG_CMD_EMRS_LP=0x%08X\n",
- RREG32(mmMC_SEQ_PMG_CMD_EMRS_LP));
- dev_info(adev->dev, " MC_PMG_CMD_EMRS=0x%08X\n",
- RREG32(mmMC_PMG_CMD_EMRS));
- dev_info(adev->dev, " MC_SEQ_PMG_CMD_MRS_LP=0x%08X\n",
- RREG32(mmMC_SEQ_PMG_CMD_MRS_LP));
- dev_info(adev->dev, " MC_PMG_CMD_MRS=0x%08X\n",
- RREG32(mmMC_PMG_CMD_MRS));
- dev_info(adev->dev, " MC_SEQ_PMG_CMD_MRS1_LP=0x%08X\n",
- RREG32(mmMC_SEQ_PMG_CMD_MRS1_LP));
- dev_info(adev->dev, " MC_PMG_CMD_MRS1=0x%08X\n",
- RREG32(mmMC_PMG_CMD_MRS1));
- dev_info(adev->dev, " MC_SEQ_WR_CTL_D0_LP=0x%08X\n",
- RREG32(mmMC_SEQ_WR_CTL_D0_LP));
- dev_info(adev->dev, " MC_SEQ_WR_CTL_D0=0x%08X\n",
- RREG32(mmMC_SEQ_WR_CTL_D0));
- dev_info(adev->dev, " MC_SEQ_WR_CTL_D1_LP=0x%08X\n",
- RREG32(mmMC_SEQ_WR_CTL_D1_LP));
- dev_info(adev->dev, " MC_SEQ_WR_CTL_D1=0x%08X\n",
- RREG32(mmMC_SEQ_WR_CTL_D1));
- dev_info(adev->dev, " MC_SEQ_RD_CTL_D0_LP=0x%08X\n",
- RREG32(mmMC_SEQ_RD_CTL_D0_LP));
- dev_info(adev->dev, " MC_SEQ_RD_CTL_D0=0x%08X\n",
- RREG32(mmMC_SEQ_RD_CTL_D0));
- dev_info(adev->dev, " MC_SEQ_RD_CTL_D1_LP=0x%08X\n",
- RREG32(mmMC_SEQ_RD_CTL_D1_LP));
- dev_info(adev->dev, " MC_SEQ_RD_CTL_D1=0x%08X\n",
- RREG32(mmMC_SEQ_RD_CTL_D1));
- dev_info(adev->dev, " MC_SEQ_PMG_TIMING_LP=0x%08X\n",
- RREG32(mmMC_SEQ_PMG_TIMING_LP));
- dev_info(adev->dev, " MC_SEQ_PMG_TIMING=0x%08X\n",
- RREG32(mmMC_SEQ_PMG_TIMING));
- dev_info(adev->dev, " MC_SEQ_PMG_CMD_MRS2_LP=0x%08X\n",
- RREG32(mmMC_SEQ_PMG_CMD_MRS2_LP));
- dev_info(adev->dev, " MC_PMG_CMD_MRS2=0x%08X\n",
- RREG32(mmMC_PMG_CMD_MRS2));
- dev_info(adev->dev, " MC_SEQ_WR_CTL_2_LP=0x%08X\n",
- RREG32(mmMC_SEQ_WR_CTL_2_LP));
- dev_info(adev->dev, " MC_SEQ_WR_CTL_2=0x%08X\n",
- RREG32(mmMC_SEQ_WR_CTL_2));
- dev_info(adev->dev, " PCIE_LC_SPEED_CNTL=0x%08X\n",
- RREG32_PCIE(ixPCIE_LC_SPEED_CNTL));
- dev_info(adev->dev, " PCIE_LC_LINK_WIDTH_CNTL=0x%08X\n",
- RREG32_PCIE(ixPCIE_LC_LINK_WIDTH_CNTL));
- dev_info(adev->dev, " SMC_IND_INDEX_0=0x%08X\n",
- RREG32(mmSMC_IND_INDEX_0));
- dev_info(adev->dev, " SMC_IND_DATA_0=0x%08X\n",
- RREG32(mmSMC_IND_DATA_0));
- dev_info(adev->dev, " SMC_IND_ACCESS_CNTL=0x%08X\n",
- RREG32(mmSMC_IND_ACCESS_CNTL));
- dev_info(adev->dev, " SMC_RESP_0=0x%08X\n",
- RREG32(mmSMC_RESP_0));
- dev_info(adev->dev, " SMC_MESSAGE_0=0x%08X\n",
- RREG32(mmSMC_MESSAGE_0));
- dev_info(adev->dev, " SMC_SYSCON_RESET_CNTL=0x%08X\n",
- RREG32_SMC(ixSMC_SYSCON_RESET_CNTL));
- dev_info(adev->dev, " SMC_SYSCON_CLOCK_CNTL_0=0x%08X\n",
- RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0));
- dev_info(adev->dev, " SMC_SYSCON_MISC_CNTL=0x%08X\n",
- RREG32_SMC(ixSMC_SYSCON_MISC_CNTL));
- dev_info(adev->dev, " SMC_PC_C=0x%08X\n",
- RREG32_SMC(ixSMC_PC_C));
-}
-
static int ci_dpm_soft_reset(void *handle)
{
return 0;
@@ -6625,7 +6416,6 @@ const struct amd_ip_funcs ci_dpm_ip_funcs = {
.is_idle = ci_dpm_is_idle,
.wait_for_idle = ci_dpm_wait_for_idle,
.soft_reset = ci_dpm_soft_reset,
- .print_status = ci_dpm_print_status,
.set_clockgating_state = ci_dpm_set_clockgating_state,
.set_powergating_state = ci_dpm_set_powergating_state,
};
diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c
index 009598b..c6127d6 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik.c
@@ -2214,11 +2214,6 @@ static int cik_common_wait_for_idle(void *handle)
return 0;
}
-static void cik_common_print_status(void *handle)
-{
-
-}
-
static int cik_common_soft_reset(void *handle)
{
/* XXX hard reset?? */
@@ -2249,7 +2244,6 @@ const struct amd_ip_funcs cik_common_ip_funcs = {
.is_idle = cik_common_is_idle,
.wait_for_idle = cik_common_wait_for_idle,
.soft_reset = cik_common_soft_reset,
- .print_status = cik_common_print_status,
.set_clockgating_state = cik_common_set_clockgating_state,
.set_powergating_state = cik_common_set_powergating_state,
};
diff --git a/drivers/gpu/drm/amd/amdgpu/cik_ih.c b/drivers/gpu/drm/amd/amdgpu/cik_ih.c
index 30c9b3be..f2f14fe 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik_ih.c
@@ -372,35 +372,6 @@ static int cik_ih_wait_for_idle(void *handle)
return -ETIMEDOUT;
}
-static void cik_ih_print_status(void *handle)
-{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-
- dev_info(adev->dev, "CIK IH registers\n");
- dev_info(adev->dev, " SRBM_STATUS=0x%08X\n",
- RREG32(mmSRBM_STATUS));
- dev_info(adev->dev, " SRBM_STATUS2=0x%08X\n",
- RREG32(mmSRBM_STATUS2));
- dev_info(adev->dev, " INTERRUPT_CNTL=0x%08X\n",
- RREG32(mmINTERRUPT_CNTL));
- dev_info(adev->dev, " INTERRUPT_CNTL2=0x%08X\n",
- RREG32(mmINTERRUPT_CNTL2));
- dev_info(adev->dev, " IH_CNTL=0x%08X\n",
- RREG32(mmIH_CNTL));
- dev_info(adev->dev, " IH_RB_CNTL=0x%08X\n",
- RREG32(mmIH_RB_CNTL));
- dev_info(adev->dev, " IH_RB_BASE=0x%08X\n",
- RREG32(mmIH_RB_BASE));
- dev_info(adev->dev, " IH_RB_WPTR_ADDR_LO=0x%08X\n",
- RREG32(mmIH_RB_WPTR_ADDR_LO));
- dev_info(adev->dev, " IH_RB_WPTR_ADDR_HI=0x%08X\n",
- RREG32(mmIH_RB_WPTR_ADDR_HI));
- dev_info(adev->dev, " IH_RB_RPTR=0x%08X\n",
- RREG32(mmIH_RB_RPTR));
- dev_info(adev->dev, " IH_RB_WPTR=0x%08X\n",
- RREG32(mmIH_RB_WPTR));
-}
-
static int cik_ih_soft_reset(void *handle)
{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
@@ -412,8 +383,6 @@ static int cik_ih_soft_reset(void *handle)
srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_IH_MASK;
if (srbm_soft_reset) {
- cik_ih_print_status((void *)adev);
-
tmp = RREG32(mmSRBM_SOFT_RESET);
tmp |= srbm_soft_reset;
dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
@@ -428,8 +397,6 @@ static int cik_ih_soft_reset(void *handle)
/* Wait a little for things to settle down */
udelay(50);
-
- cik_ih_print_status((void *)adev);
}
return 0;
@@ -459,7 +426,6 @@ const struct amd_ip_funcs cik_ih_ip_funcs = {
.is_idle = cik_ih_is_idle,
.wait_for_idle = cik_ih_wait_for_idle,
.soft_reset = cik_ih_soft_reset,
- .print_status = cik_ih_print_status,
.set_clockgating_state = cik_ih_set_clockgating_state,
.set_powergating_state = cik_ih_set_powergating_state,
};
diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
index 3edf26a..b7ed9d3 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
@@ -1064,57 +1064,6 @@ static int cik_sdma_wait_for_idle(void *handle)
return -ETIMEDOUT;
}
-static void cik_sdma_print_status(void *handle)
-{
- int i, j;
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-
- dev_info(adev->dev, "CIK SDMA registers\n");
- dev_info(adev->dev, " SRBM_STATUS2=0x%08X\n",
- RREG32(mmSRBM_STATUS2));
- for (i = 0; i < adev->sdma.num_instances; i++) {
- dev_info(adev->dev, " SDMA%d_STATUS_REG=0x%08X\n",
- i, RREG32(mmSDMA0_STATUS_REG + sdma_offsets[i]));
- dev_info(adev->dev, " SDMA%d_ME_CNTL=0x%08X\n",
- i, RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]));
- dev_info(adev->dev, " SDMA%d_CNTL=0x%08X\n",
- i, RREG32(mmSDMA0_CNTL + sdma_offsets[i]));
- dev_info(adev->dev, " SDMA%d_SEM_INCOMPLETE_TIMER_CNTL=0x%08X\n",
- i, RREG32(mmSDMA0_SEM_INCOMPLETE_TIMER_CNTL + sdma_offsets[i]));
- dev_info(adev->dev, " SDMA%d_SEM_WAIT_FAIL_TIMER_CNTL=0x%08X\n",
- i, RREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i]));
- dev_info(adev->dev, " SDMA%d_GFX_IB_CNTL=0x%08X\n",
- i, RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]));
- dev_info(adev->dev, " SDMA%d_GFX_RB_CNTL=0x%08X\n",
- i, RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]));
- dev_info(adev->dev, " SDMA%d_GFX_RB_RPTR=0x%08X\n",
- i, RREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i]));
- dev_info(adev->dev, " SDMA%d_GFX_RB_WPTR=0x%08X\n",
- i, RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i]));
- dev_info(adev->dev, " SDMA%d_GFX_RB_RPTR_ADDR_HI=0x%08X\n",
- i, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i]));
- dev_info(adev->dev, " SDMA%d_GFX_RB_RPTR_ADDR_LO=0x%08X\n",
- i, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i]));
- dev_info(adev->dev, " SDMA%d_GFX_RB_BASE=0x%08X\n",
- i, RREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i]));
- dev_info(adev->dev, " SDMA%d_GFX_RB_BASE_HI=0x%08X\n",
- i, RREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i]));
- dev_info(adev->dev, " SDMA%d_TILING_CONFIG=0x%08X\n",
- i, RREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i]));
- mutex_lock(&adev->srbm_mutex);
- for (j = 0; j < 16; j++) {
- cik_srbm_select(adev, 0, 0, 0, j);
- dev_info(adev->dev, " VM %d:\n", j);
- dev_info(adev->dev, " SDMA0_GFX_VIRTUAL_ADDR=0x%08X\n",
- RREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i]));
- dev_info(adev->dev, " SDMA0_GFX_APE1_CNTL=0x%08X\n",
- RREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i]));
- }
- cik_srbm_select(adev, 0, 0, 0, 0);
- mutex_unlock(&adev->srbm_mutex);
- }
-}
-
static int cik_sdma_soft_reset(void *handle)
{
u32 srbm_soft_reset = 0;
@@ -1137,8 +1086,6 @@ static int cik_sdma_soft_reset(void *handle)
}
if (srbm_soft_reset) {
- cik_sdma_print_status((void *)adev);
-
tmp = RREG32(mmSRBM_SOFT_RESET);
tmp |= srbm_soft_reset;
dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
@@ -1153,8 +1100,6 @@ static int cik_sdma_soft_reset(void *handle)
/* Wait a little for things to settle down */
udelay(50);
-
- cik_sdma_print_status((void *)adev);
}
return 0;
@@ -1289,7 +1234,6 @@ const struct amd_ip_funcs cik_sdma_ip_funcs = {
.is_idle = cik_sdma_is_idle,
.wait_for_idle = cik_sdma_wait_for_idle,
.soft_reset = cik_sdma_soft_reset,
- .print_status = cik_sdma_print_status,
.set_clockgating_state = cik_sdma_set_clockgating_state,
.set_powergating_state = cik_sdma_set_powergating_state,
};
diff --git a/drivers/gpu/drm/amd/amdgpu/cz_dpm.c b/drivers/gpu/drm/amd/amdgpu/cz_dpm.c
index e7ef226..bf1847b 100644
--- a/drivers/gpu/drm/amd/amdgpu/cz_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/cz_dpm.c
@@ -2241,7 +2241,6 @@ const struct amd_ip_funcs cz_dpm_ip_funcs = {
.is_idle = NULL,
.wait_for_idle = NULL,
.soft_reset = NULL,
- .print_status = NULL,
.set_clockgating_state = cz_dpm_set_clockgating_state,
.set_powergating_state = cz_dpm_set_powergating_state,
};
diff --git a/drivers/gpu/drm/amd/amdgpu/cz_ih.c b/drivers/gpu/drm/amd/amdgpu/cz_ih.c
index c79638f..23bd912 100644
--- a/drivers/gpu/drm/amd/amdgpu/cz_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/cz_ih.c
@@ -351,35 +351,6 @@ static int cz_ih_wait_for_idle(void *handle)
return -ETIMEDOUT;
}
-static void cz_ih_print_status(void *handle)
-{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-
- dev_info(adev->dev, "CZ IH registers\n");
- dev_info(adev->dev, " SRBM_STATUS=0x%08X\n",
- RREG32(mmSRBM_STATUS));
- dev_info(adev->dev, " SRBM_STATUS2=0x%08X\n",
- RREG32(mmSRBM_STATUS2));
- dev_info(adev->dev, " INTERRUPT_CNTL=0x%08X\n",
- RREG32(mmINTERRUPT_CNTL));
- dev_info(adev->dev, " INTERRUPT_CNTL2=0x%08X\n",
- RREG32(mmINTERRUPT_CNTL2));
- dev_info(adev->dev, " IH_CNTL=0x%08X\n",
- RREG32(mmIH_CNTL));
- dev_info(adev->dev, " IH_RB_CNTL=0x%08X\n",
- RREG32(mmIH_RB_CNTL));
- dev_info(adev->dev, " IH_RB_BASE=0x%08X\n",
- RREG32(mmIH_RB_BASE));
- dev_info(adev->dev, " IH_RB_WPTR_ADDR_LO=0x%08X\n",
- RREG32(mmIH_RB_WPTR_ADDR_LO));
- dev_info(adev->dev, " IH_RB_WPTR_ADDR_HI=0x%08X\n",
- RREG32(mmIH_RB_WPTR_ADDR_HI));
- dev_info(adev->dev, " IH_RB_RPTR=0x%08X\n",
- RREG32(mmIH_RB_RPTR));
- dev_info(adev->dev, " IH_RB_WPTR=0x%08X\n",
- RREG32(mmIH_RB_WPTR));
-}
-
static int cz_ih_soft_reset(void *handle)
{
u32 srbm_soft_reset = 0;
@@ -391,8 +362,6 @@ static int cz_ih_soft_reset(void *handle)
SOFT_RESET_IH, 1);
if (srbm_soft_reset) {
- cz_ih_print_status((void *)adev);
-
tmp = RREG32(mmSRBM_SOFT_RESET);
tmp |= srbm_soft_reset;
dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
@@ -407,8 +376,6 @@ static int cz_ih_soft_reset(void *handle)
/* Wait a little for things to settle down */
udelay(50);
-
- cz_ih_print_status((void *)adev);
}
return 0;
@@ -440,7 +407,6 @@ const struct amd_ip_funcs cz_ih_ip_funcs = {
.is_idle = cz_ih_is_idle,
.wait_for_idle = cz_ih_wait_for_idle,
.soft_reset = cz_ih_soft_reset,
- .print_status = cz_ih_print_status,
.set_clockgating_state = cz_ih_set_clockgating_state,
.set_powergating_state = cz_ih_set_powergating_state,
};
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
index 6de2ce53..f7f67f3 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
@@ -3130,14 +3130,6 @@ static int dce_v10_0_wait_for_idle(void *handle)
return 0;
}
-static void dce_v10_0_print_status(void *handle)
-{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-
- dev_info(adev->dev, "DCE 10.x registers\n");
- /* XXX todo */
-}
-
static int dce_v10_0_soft_reset(void *handle)
{
u32 srbm_soft_reset = 0, tmp;
@@ -3147,8 +3139,6 @@ static int dce_v10_0_soft_reset(void *handle)
srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK;
if (srbm_soft_reset) {
- dce_v10_0_print_status((void *)adev);
-
tmp = RREG32(mmSRBM_SOFT_RESET);
tmp |= srbm_soft_reset;
dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
@@ -3163,7 +3153,6 @@ static int dce_v10_0_soft_reset(void *handle)
/* Wait a little for things to settle down */
udelay(50);
- dce_v10_0_print_status((void *)adev);
}
return 0;
}
@@ -3512,7 +3501,6 @@ const struct amd_ip_funcs dce_v10_0_ip_funcs = {
.is_idle = dce_v10_0_is_idle,
.wait_for_idle = dce_v10_0_wait_for_idle,
.soft_reset = dce_v10_0_soft_reset,
- .print_status = dce_v10_0_print_status,
.set_clockgating_state = dce_v10_0_set_clockgating_state,
.set_powergating_state = dce_v10_0_set_powergating_state,
};
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
index d28873c..e4f3dc7 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
@@ -3193,14 +3193,6 @@ static int dce_v11_0_wait_for_idle(void *handle)
return 0;
}
-static void dce_v11_0_print_status(void *handle)
-{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-
- dev_info(adev->dev, "DCE 10.x registers\n");
- /* XXX todo */
-}
-
static int dce_v11_0_soft_reset(void *handle)
{
u32 srbm_soft_reset = 0, tmp;
@@ -3210,8 +3202,6 @@ static int dce_v11_0_soft_reset(void *handle)
srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK;
if (srbm_soft_reset) {
- dce_v11_0_print_status((void *)adev);
-
tmp = RREG32(mmSRBM_SOFT_RESET);
tmp |= srbm_soft_reset;
dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
@@ -3226,7 +3216,6 @@ static int dce_v11_0_soft_reset(void *handle)
/* Wait a little for things to settle down */
udelay(50);
- dce_v11_0_print_status((void *)adev);
}
return 0;
}
@@ -3575,7 +3564,6 @@ const struct amd_ip_funcs dce_v11_0_ip_funcs = {
.is_idle = dce_v11_0_is_idle,
.wait_for_idle = dce_v11_0_wait_for_idle,
.soft_reset = dce_v11_0_soft_reset,
- .print_status = dce_v11_0_print_status,
.set_clockgating_state = dce_v11_0_set_clockgating_state,
.set_powergating_state = dce_v11_0_set_powergating_state,
};
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
index e56b55d..429e98a 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
@@ -3038,14 +3038,6 @@ static int dce_v8_0_wait_for_idle(void *handle)
return 0;
}
-static void dce_v8_0_print_status(void *handle)
-{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-
- dev_info(adev->dev, "DCE 8.x registers\n");
- /* XXX todo */
-}
-
static int dce_v8_0_soft_reset(void *handle)
{
u32 srbm_soft_reset = 0, tmp;
@@ -3055,8 +3047,6 @@ static int dce_v8_0_soft_reset(void *handle)
srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK;
if (srbm_soft_reset) {
- dce_v8_0_print_status((void *)adev);
-
tmp = RREG32(mmSRBM_SOFT_RESET);
tmp |= srbm_soft_reset;
dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
@@ -3071,7 +3061,6 @@ static int dce_v8_0_soft_reset(void *handle)
/* Wait a little for things to settle down */
udelay(50);
- dce_v8_0_print_status((void *)adev);
}
return 0;
}
@@ -3442,7 +3431,6 @@ const struct amd_ip_funcs dce_v8_0_ip_funcs = {
.is_idle = dce_v8_0_is_idle,
.wait_for_idle = dce_v8_0_wait_for_idle,
.soft_reset = dce_v8_0_soft_reset,
- .print_status = dce_v8_0_print_status,
.set_clockgating_state = dce_v8_0_set_clockgating_state,
.set_powergating_state = dce_v8_0_set_powergating_state,
};
diff --git a/drivers/gpu/drm/amd/amdgpu/fiji_dpm.c b/drivers/gpu/drm/amd/amdgpu/fiji_dpm.c
index 4b0e45a..6d13345 100644
--- a/drivers/gpu/drm/amd/amdgpu/fiji_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/fiji_dpm.c
@@ -154,7 +154,6 @@ const struct amd_ip_funcs fiji_dpm_ip_funcs = {
.is_idle = NULL,
.wait_for_idle = NULL,
.soft_reset = NULL,
- .print_status = NULL,
.set_clockgating_state = fiji_dpm_set_clockgating_state,
.set_powergating_state = fiji_dpm_set_powergating_state,
};
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
index 86657e3..6686c9c 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
@@ -4572,256 +4572,6 @@ static int gfx_v7_0_wait_for_idle(void *handle)
return -ETIMEDOUT;
}
-static void gfx_v7_0_print_status(void *handle)
-{
- int i;
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-
- dev_info(adev->dev, "GFX 7.x registers\n");
- dev_info(adev->dev, " GRBM_STATUS=0x%08X\n",
- RREG32(mmGRBM_STATUS));
- dev_info(adev->dev, " GRBM_STATUS2=0x%08X\n",
- RREG32(mmGRBM_STATUS2));
- dev_info(adev->dev, " GRBM_STATUS_SE0=0x%08X\n",
- RREG32(mmGRBM_STATUS_SE0));
- dev_info(adev->dev, " GRBM_STATUS_SE1=0x%08X\n",
- RREG32(mmGRBM_STATUS_SE1));
- dev_info(adev->dev, " GRBM_STATUS_SE2=0x%08X\n",
- RREG32(mmGRBM_STATUS_SE2));
- dev_info(adev->dev, " GRBM_STATUS_SE3=0x%08X\n",
- RREG32(mmGRBM_STATUS_SE3));
- dev_info(adev->dev, " CP_STAT = 0x%08x\n", RREG32(mmCP_STAT));
- dev_info(adev->dev, " CP_STALLED_STAT1 = 0x%08x\n",
- RREG32(mmCP_STALLED_STAT1));
- dev_info(adev->dev, " CP_STALLED_STAT2 = 0x%08x\n",
- RREG32(mmCP_STALLED_STAT2));
- dev_info(adev->dev, " CP_STALLED_STAT3 = 0x%08x\n",
- RREG32(mmCP_STALLED_STAT3));
- dev_info(adev->dev, " CP_CPF_BUSY_STAT = 0x%08x\n",
- RREG32(mmCP_CPF_BUSY_STAT));
- dev_info(adev->dev, " CP_CPF_STALLED_STAT1 = 0x%08x\n",
- RREG32(mmCP_CPF_STALLED_STAT1));
- dev_info(adev->dev, " CP_CPF_STATUS = 0x%08x\n", RREG32(mmCP_CPF_STATUS));
- dev_info(adev->dev, " CP_CPC_BUSY_STAT = 0x%08x\n", RREG32(mmCP_CPC_BUSY_STAT));
- dev_info(adev->dev, " CP_CPC_STALLED_STAT1 = 0x%08x\n",
- RREG32(mmCP_CPC_STALLED_STAT1));
- dev_info(adev->dev, " CP_CPC_STATUS = 0x%08x\n", RREG32(mmCP_CPC_STATUS));
-
- for (i = 0; i < 32; i++) {
- dev_info(adev->dev, " GB_TILE_MODE%d=0x%08X\n",
- i, RREG32(mmGB_TILE_MODE0 + (i * 4)));
- }
- for (i = 0; i < 16; i++) {
- dev_info(adev->dev, " GB_MACROTILE_MODE%d=0x%08X\n",
- i, RREG32(mmGB_MACROTILE_MODE0 + (i * 4)));
- }
- for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
- dev_info(adev->dev, " se: %d\n", i);
- gfx_v7_0_select_se_sh(adev, i, 0xffffffff);
- dev_info(adev->dev, " PA_SC_RASTER_CONFIG=0x%08X\n",
- RREG32(mmPA_SC_RASTER_CONFIG));
- dev_info(adev->dev, " PA_SC_RASTER_CONFIG_1=0x%08X\n",
- RREG32(mmPA_SC_RASTER_CONFIG_1));
- }
- gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
-
- dev_info(adev->dev, " GB_ADDR_CONFIG=0x%08X\n",
- RREG32(mmGB_ADDR_CONFIG));
- dev_info(adev->dev, " HDP_ADDR_CONFIG=0x%08X\n",
- RREG32(mmHDP_ADDR_CONFIG));
- dev_info(adev->dev, " DMIF_ADDR_CALC=0x%08X\n",
- RREG32(mmDMIF_ADDR_CALC));
-
- dev_info(adev->dev, " CP_MEQ_THRESHOLDS=0x%08X\n",
- RREG32(mmCP_MEQ_THRESHOLDS));
- dev_info(adev->dev, " SX_DEBUG_1=0x%08X\n",
- RREG32(mmSX_DEBUG_1));
- dev_info(adev->dev, " TA_CNTL_AUX=0x%08X\n",
- RREG32(mmTA_CNTL_AUX));
- dev_info(adev->dev, " SPI_CONFIG_CNTL=0x%08X\n",
- RREG32(mmSPI_CONFIG_CNTL));
- dev_info(adev->dev, " SQ_CONFIG=0x%08X\n",
- RREG32(mmSQ_CONFIG));
- dev_info(adev->dev, " DB_DEBUG=0x%08X\n",
- RREG32(mmDB_DEBUG));
- dev_info(adev->dev, " DB_DEBUG2=0x%08X\n",
- RREG32(mmDB_DEBUG2));
- dev_info(adev->dev, " DB_DEBUG3=0x%08X\n",
- RREG32(mmDB_DEBUG3));
- dev_info(adev->dev, " CB_HW_CONTROL=0x%08X\n",
- RREG32(mmCB_HW_CONTROL));
- dev_info(adev->dev, " SPI_CONFIG_CNTL_1=0x%08X\n",
- RREG32(mmSPI_CONFIG_CNTL_1));
- dev_info(adev->dev, " PA_SC_FIFO_SIZE=0x%08X\n",
- RREG32(mmPA_SC_FIFO_SIZE));
- dev_info(adev->dev, " VGT_NUM_INSTANCES=0x%08X\n",
- RREG32(mmVGT_NUM_INSTANCES));
- dev_info(adev->dev, " CP_PERFMON_CNTL=0x%08X\n",
- RREG32(mmCP_PERFMON_CNTL));
- dev_info(adev->dev, " PA_SC_FORCE_EOV_MAX_CNTS=0x%08X\n",
- RREG32(mmPA_SC_FORCE_EOV_MAX_CNTS));
- dev_info(adev->dev, " VGT_CACHE_INVALIDATION=0x%08X\n",
- RREG32(mmVGT_CACHE_INVALIDATION));
- dev_info(adev->dev, " VGT_GS_VERTEX_REUSE=0x%08X\n",
- RREG32(mmVGT_GS_VERTEX_REUSE));
- dev_info(adev->dev, " PA_SC_LINE_STIPPLE_STATE=0x%08X\n",
- RREG32(mmPA_SC_LINE_STIPPLE_STATE));
- dev_info(adev->dev, " PA_CL_ENHANCE=0x%08X\n",
- RREG32(mmPA_CL_ENHANCE));
- dev_info(adev->dev, " PA_SC_ENHANCE=0x%08X\n",
- RREG32(mmPA_SC_ENHANCE));
-
- dev_info(adev->dev, " CP_ME_CNTL=0x%08X\n",
- RREG32(mmCP_ME_CNTL));
- dev_info(adev->dev, " CP_MAX_CONTEXT=0x%08X\n",
- RREG32(mmCP_MAX_CONTEXT));
- dev_info(adev->dev, " CP_ENDIAN_SWAP=0x%08X\n",
- RREG32(mmCP_ENDIAN_SWAP));
- dev_info(adev->dev, " CP_DEVICE_ID=0x%08X\n",
- RREG32(mmCP_DEVICE_ID));
-
- dev_info(adev->dev, " CP_SEM_WAIT_TIMER=0x%08X\n",
- RREG32(mmCP_SEM_WAIT_TIMER));
- if (adev->asic_type != CHIP_HAWAII)
- dev_info(adev->dev, " CP_SEM_INCOMPLETE_TIMER_CNTL=0x%08X\n",
- RREG32(mmCP_SEM_INCOMPLETE_TIMER_CNTL));
-
- dev_info(adev->dev, " CP_RB_WPTR_DELAY=0x%08X\n",
- RREG32(mmCP_RB_WPTR_DELAY));
- dev_info(adev->dev, " CP_RB_VMID=0x%08X\n",
- RREG32(mmCP_RB_VMID));
- dev_info(adev->dev, " CP_RB0_CNTL=0x%08X\n",
- RREG32(mmCP_RB0_CNTL));
- dev_info(adev->dev, " CP_RB0_WPTR=0x%08X\n",
- RREG32(mmCP_RB0_WPTR));
- dev_info(adev->dev, " CP_RB0_RPTR_ADDR=0x%08X\n",
- RREG32(mmCP_RB0_RPTR_ADDR));
- dev_info(adev->dev, " CP_RB0_RPTR_ADDR_HI=0x%08X\n",
- RREG32(mmCP_RB0_RPTR_ADDR_HI));
- dev_info(adev->dev, " CP_RB0_CNTL=0x%08X\n",
- RREG32(mmCP_RB0_CNTL));
- dev_info(adev->dev, " CP_RB0_BASE=0x%08X\n",
- RREG32(mmCP_RB0_BASE));
- dev_info(adev->dev, " CP_RB0_BASE_HI=0x%08X\n",
- RREG32(mmCP_RB0_BASE_HI));
- dev_info(adev->dev, " CP_MEC_CNTL=0x%08X\n",
- RREG32(mmCP_MEC_CNTL));
- dev_info(adev->dev, " CP_CPF_DEBUG=0x%08X\n",
- RREG32(mmCP_CPF_DEBUG));
-
- dev_info(adev->dev, " SCRATCH_ADDR=0x%08X\n",
- RREG32(mmSCRATCH_ADDR));
- dev_info(adev->dev, " SCRATCH_UMSK=0x%08X\n",
- RREG32(mmSCRATCH_UMSK));
-
- /* init the pipes */
- mutex_lock(&adev->srbm_mutex);
- for (i = 0; i < (adev->gfx.mec.num_pipe * adev->gfx.mec.num_mec); i++) {
- int me = (i < 4) ? 1 : 2;
- int pipe = (i < 4) ? i : (i - 4);
- int queue;
-
- dev_info(adev->dev, " me: %d, pipe: %d\n", me, pipe);
- cik_srbm_select(adev, me, pipe, 0, 0);
- dev_info(adev->dev, " CP_HPD_EOP_BASE_ADDR=0x%08X\n",
- RREG32(mmCP_HPD_EOP_BASE_ADDR));
- dev_info(adev->dev, " CP_HPD_EOP_BASE_ADDR_HI=0x%08X\n",
- RREG32(mmCP_HPD_EOP_BASE_ADDR_HI));
- dev_info(adev->dev, " CP_HPD_EOP_VMID=0x%08X\n",
- RREG32(mmCP_HPD_EOP_VMID));
- dev_info(adev->dev, " CP_HPD_EOP_CONTROL=0x%08X\n",
- RREG32(mmCP_HPD_EOP_CONTROL));
-
- for (queue = 0; queue < 8; queue++) {
- cik_srbm_select(adev, me, pipe, queue, 0);
- dev_info(adev->dev, " queue: %d\n", queue);
- dev_info(adev->dev, " CP_PQ_WPTR_POLL_CNTL=0x%08X\n",
- RREG32(mmCP_PQ_WPTR_POLL_CNTL));
- dev_info(adev->dev, " CP_HQD_PQ_DOORBELL_CONTROL=0x%08X\n",
- RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL));
- dev_info(adev->dev, " CP_HQD_ACTIVE=0x%08X\n",
- RREG32(mmCP_HQD_ACTIVE));
- dev_info(adev->dev, " CP_HQD_DEQUEUE_REQUEST=0x%08X\n",
- RREG32(mmCP_HQD_DEQUEUE_REQUEST));
- dev_info(adev->dev, " CP_HQD_PQ_RPTR=0x%08X\n",
- RREG32(mmCP_HQD_PQ_RPTR));
- dev_info(adev->dev, " CP_HQD_PQ_WPTR=0x%08X\n",
- RREG32(mmCP_HQD_PQ_WPTR));
- dev_info(adev->dev, " CP_HQD_PQ_BASE=0x%08X\n",
- RREG32(mmCP_HQD_PQ_BASE));
- dev_info(adev->dev, " CP_HQD_PQ_BASE_HI=0x%08X\n",
- RREG32(mmCP_HQD_PQ_BASE_HI));
- dev_info(adev->dev, " CP_HQD_PQ_CONTROL=0x%08X\n",
- RREG32(mmCP_HQD_PQ_CONTROL));
- dev_info(adev->dev, " CP_HQD_PQ_WPTR_POLL_ADDR=0x%08X\n",
- RREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR));
- dev_info(adev->dev, " CP_HQD_PQ_WPTR_POLL_ADDR_HI=0x%08X\n",
- RREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR_HI));
- dev_info(adev->dev, " CP_HQD_PQ_RPTR_REPORT_ADDR=0x%08X\n",
- RREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR));
- dev_info(adev->dev, " CP_HQD_PQ_RPTR_REPORT_ADDR_HI=0x%08X\n",
- RREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI));
- dev_info(adev->dev, " CP_HQD_PQ_DOORBELL_CONTROL=0x%08X\n",
- RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL));
- dev_info(adev->dev, " CP_HQD_PQ_WPTR=0x%08X\n",
- RREG32(mmCP_HQD_PQ_WPTR));
- dev_info(adev->dev, " CP_HQD_VMID=0x%08X\n",
- RREG32(mmCP_HQD_VMID));
- dev_info(adev->dev, " CP_MQD_BASE_ADDR=0x%08X\n",
- RREG32(mmCP_MQD_BASE_ADDR));
- dev_info(adev->dev, " CP_MQD_BASE_ADDR_HI=0x%08X\n",
- RREG32(mmCP_MQD_BASE_ADDR_HI));
- dev_info(adev->dev, " CP_MQD_CONTROL=0x%08X\n",
- RREG32(mmCP_MQD_CONTROL));
- }
- }
- cik_srbm_select(adev, 0, 0, 0, 0);
- mutex_unlock(&adev->srbm_mutex);
-
- dev_info(adev->dev, " CP_INT_CNTL_RING0=0x%08X\n",
- RREG32(mmCP_INT_CNTL_RING0));
- dev_info(adev->dev, " RLC_LB_CNTL=0x%08X\n",
- RREG32(mmRLC_LB_CNTL));
- dev_info(adev->dev, " RLC_CNTL=0x%08X\n",
- RREG32(mmRLC_CNTL));
- dev_info(adev->dev, " RLC_CGCG_CGLS_CTRL=0x%08X\n",
- RREG32(mmRLC_CGCG_CGLS_CTRL));
- dev_info(adev->dev, " RLC_LB_CNTR_INIT=0x%08X\n",
- RREG32(mmRLC_LB_CNTR_INIT));
- dev_info(adev->dev, " RLC_LB_CNTR_MAX=0x%08X\n",
- RREG32(mmRLC_LB_CNTR_MAX));
- dev_info(adev->dev, " RLC_LB_INIT_CU_MASK=0x%08X\n",
- RREG32(mmRLC_LB_INIT_CU_MASK));
- dev_info(adev->dev, " RLC_LB_PARAMS=0x%08X\n",
- RREG32(mmRLC_LB_PARAMS));
- dev_info(adev->dev, " RLC_LB_CNTL=0x%08X\n",
- RREG32(mmRLC_LB_CNTL));
- dev_info(adev->dev, " RLC_MC_CNTL=0x%08X\n",
- RREG32(mmRLC_MC_CNTL));
- dev_info(adev->dev, " RLC_UCODE_CNTL=0x%08X\n",
- RREG32(mmRLC_UCODE_CNTL));
-
- if (adev->asic_type == CHIP_BONAIRE)
- dev_info(adev->dev, " RLC_DRIVER_CPDMA_STATUS=0x%08X\n",
- RREG32(mmRLC_DRIVER_CPDMA_STATUS));
-
- mutex_lock(&adev->srbm_mutex);
- for (i = 0; i < 16; i++) {
- cik_srbm_select(adev, 0, 0, 0, i);
- dev_info(adev->dev, " VM %d:\n", i);
- dev_info(adev->dev, " SH_MEM_CONFIG=0x%08X\n",
- RREG32(mmSH_MEM_CONFIG));
- dev_info(adev->dev, " SH_MEM_APE1_BASE=0x%08X\n",
- RREG32(mmSH_MEM_APE1_BASE));
- dev_info(adev->dev, " SH_MEM_APE1_LIMIT=0x%08X\n",
- RREG32(mmSH_MEM_APE1_LIMIT));
- dev_info(adev->dev, " SH_MEM_BASES=0x%08X\n",
- RREG32(mmSH_MEM_BASES));
- }
- cik_srbm_select(adev, 0, 0, 0, 0);
- mutex_unlock(&adev->srbm_mutex);
-}
-
static int gfx_v7_0_soft_reset(void *handle)
{
u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
@@ -4855,7 +4605,6 @@ static int gfx_v7_0_soft_reset(void *handle)
srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_GRBM_MASK;
if (grbm_soft_reset || srbm_soft_reset) {
- gfx_v7_0_print_status((void *)adev);
/* disable CG/PG */
gfx_v7_0_fini_pg(adev);
gfx_v7_0_update_cg(adev, false);
@@ -4898,7 +4647,6 @@ static int gfx_v7_0_soft_reset(void *handle)
}
/* Wait a little for things to settle down */
udelay(50);
- gfx_v7_0_print_status((void *)adev);
}
return 0;
}
@@ -5161,7 +4909,6 @@ const struct amd_ip_funcs gfx_v7_0_ip_funcs = {
.is_idle = gfx_v7_0_is_idle,
.wait_for_idle = gfx_v7_0_wait_for_idle,
.soft_reset = gfx_v7_0_soft_reset,
- .print_status = gfx_v7_0_print_status,
.set_clockgating_state = gfx_v7_0_set_clockgating_state,
.set_powergating_state = gfx_v7_0_set_powergating_state,
};
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index aeb9cae..021c17e 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -4826,185 +4826,6 @@ static int gfx_v8_0_wait_for_idle(void *handle)
return -ETIMEDOUT;
}
-static void gfx_v8_0_print_status(void *handle)
-{
- int i;
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-
- dev_info(adev->dev, "GFX 8.x registers\n");
- dev_info(adev->dev, " GRBM_STATUS=0x%08X\n",
- RREG32(mmGRBM_STATUS));
- dev_info(adev->dev, " GRBM_STATUS2=0x%08X\n",
- RREG32(mmGRBM_STATUS2));
- dev_info(adev->dev, " GRBM_STATUS_SE0=0x%08X\n",
- RREG32(mmGRBM_STATUS_SE0));
- dev_info(adev->dev, " GRBM_STATUS_SE1=0x%08X\n",
- RREG32(mmGRBM_STATUS_SE1));
- dev_info(adev->dev, " GRBM_STATUS_SE2=0x%08X\n",
- RREG32(mmGRBM_STATUS_SE2));
- dev_info(adev->dev, " GRBM_STATUS_SE3=0x%08X\n",
- RREG32(mmGRBM_STATUS_SE3));
- dev_info(adev->dev, " CP_STAT = 0x%08x\n", RREG32(mmCP_STAT));
- dev_info(adev->dev, " CP_STALLED_STAT1 = 0x%08x\n",
- RREG32(mmCP_STALLED_STAT1));
- dev_info(adev->dev, " CP_STALLED_STAT2 = 0x%08x\n",
- RREG32(mmCP_STALLED_STAT2));
- dev_info(adev->dev, " CP_STALLED_STAT3 = 0x%08x\n",
- RREG32(mmCP_STALLED_STAT3));
- dev_info(adev->dev, " CP_CPF_BUSY_STAT = 0x%08x\n",
- RREG32(mmCP_CPF_BUSY_STAT));
- dev_info(adev->dev, " CP_CPF_STALLED_STAT1 = 0x%08x\n",
- RREG32(mmCP_CPF_STALLED_STAT1));
- dev_info(adev->dev, " CP_CPF_STATUS = 0x%08x\n", RREG32(mmCP_CPF_STATUS));
- dev_info(adev->dev, " CP_CPC_BUSY_STAT = 0x%08x\n", RREG32(mmCP_CPC_BUSY_STAT));
- dev_info(adev->dev, " CP_CPC_STALLED_STAT1 = 0x%08x\n",
- RREG32(mmCP_CPC_STALLED_STAT1));
- dev_info(adev->dev, " CP_CPC_STATUS = 0x%08x\n", RREG32(mmCP_CPC_STATUS));
-
- for (i = 0; i < 32; i++) {
- dev_info(adev->dev, " GB_TILE_MODE%d=0x%08X\n",
- i, RREG32(mmGB_TILE_MODE0 + (i * 4)));
- }
- for (i = 0; i < 16; i++) {
- dev_info(adev->dev, " GB_MACROTILE_MODE%d=0x%08X\n",
- i, RREG32(mmGB_MACROTILE_MODE0 + (i * 4)));
- }
- for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
- dev_info(adev->dev, " se: %d\n", i);
- gfx_v8_0_select_se_sh(adev, i, 0xffffffff);
- dev_info(adev->dev, " PA_SC_RASTER_CONFIG=0x%08X\n",
- RREG32(mmPA_SC_RASTER_CONFIG));
- dev_info(adev->dev, " PA_SC_RASTER_CONFIG_1=0x%08X\n",
- RREG32(mmPA_SC_RASTER_CONFIG_1));
- }
- gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
-
- dev_info(adev->dev, " GB_ADDR_CONFIG=0x%08X\n",
- RREG32(mmGB_ADDR_CONFIG));
- dev_info(adev->dev, " HDP_ADDR_CONFIG=0x%08X\n",
- RREG32(mmHDP_ADDR_CONFIG));
- dev_info(adev->dev, " DMIF_ADDR_CALC=0x%08X\n",
- RREG32(mmDMIF_ADDR_CALC));
-
- dev_info(adev->dev, " CP_MEQ_THRESHOLDS=0x%08X\n",
- RREG32(mmCP_MEQ_THRESHOLDS));
- dev_info(adev->dev, " SX_DEBUG_1=0x%08X\n",
- RREG32(mmSX_DEBUG_1));
- dev_info(adev->dev, " TA_CNTL_AUX=0x%08X\n",
- RREG32(mmTA_CNTL_AUX));
- dev_info(adev->dev, " SPI_CONFIG_CNTL=0x%08X\n",
- RREG32(mmSPI_CONFIG_CNTL));
- dev_info(adev->dev, " SQ_CONFIG=0x%08X\n",
- RREG32(mmSQ_CONFIG));
- dev_info(adev->dev, " DB_DEBUG=0x%08X\n",
- RREG32(mmDB_DEBUG));
- dev_info(adev->dev, " DB_DEBUG2=0x%08X\n",
- RREG32(mmDB_DEBUG2));
- dev_info(adev->dev, " DB_DEBUG3=0x%08X\n",
- RREG32(mmDB_DEBUG3));
- dev_info(adev->dev, " CB_HW_CONTROL=0x%08X\n",
- RREG32(mmCB_HW_CONTROL));
- dev_info(adev->dev, " SPI_CONFIG_CNTL_1=0x%08X\n",
- RREG32(mmSPI_CONFIG_CNTL_1));
- dev_info(adev->dev, " PA_SC_FIFO_SIZE=0x%08X\n",
- RREG32(mmPA_SC_FIFO_SIZE));
- dev_info(adev->dev, " VGT_NUM_INSTANCES=0x%08X\n",
- RREG32(mmVGT_NUM_INSTANCES));
- dev_info(adev->dev, " CP_PERFMON_CNTL=0x%08X\n",
- RREG32(mmCP_PERFMON_CNTL));
- dev_info(adev->dev, " PA_SC_FORCE_EOV_MAX_CNTS=0x%08X\n",
- RREG32(mmPA_SC_FORCE_EOV_MAX_CNTS));
- dev_info(adev->dev, " VGT_CACHE_INVALIDATION=0x%08X\n",
- RREG32(mmVGT_CACHE_INVALIDATION));
- dev_info(adev->dev, " VGT_GS_VERTEX_REUSE=0x%08X\n",
- RREG32(mmVGT_GS_VERTEX_REUSE));
- dev_info(adev->dev, " PA_SC_LINE_STIPPLE_STATE=0x%08X\n",
- RREG32(mmPA_SC_LINE_STIPPLE_STATE));
- dev_info(adev->dev, " PA_CL_ENHANCE=0x%08X\n",
- RREG32(mmPA_CL_ENHANCE));
- dev_info(adev->dev, " PA_SC_ENHANCE=0x%08X\n",
- RREG32(mmPA_SC_ENHANCE));
-
- dev_info(adev->dev, " CP_ME_CNTL=0x%08X\n",
- RREG32(mmCP_ME_CNTL));
- dev_info(adev->dev, " CP_MAX_CONTEXT=0x%08X\n",
- RREG32(mmCP_MAX_CONTEXT));
- dev_info(adev->dev, " CP_ENDIAN_SWAP=0x%08X\n",
- RREG32(mmCP_ENDIAN_SWAP));
- dev_info(adev->dev, " CP_DEVICE_ID=0x%08X\n",
- RREG32(mmCP_DEVICE_ID));
-
- dev_info(adev->dev, " CP_SEM_WAIT_TIMER=0x%08X\n",
- RREG32(mmCP_SEM_WAIT_TIMER));
-
- dev_info(adev->dev, " CP_RB_WPTR_DELAY=0x%08X\n",
- RREG32(mmCP_RB_WPTR_DELAY));
- dev_info(adev->dev, " CP_RB_VMID=0x%08X\n",
- RREG32(mmCP_RB_VMID));
- dev_info(adev->dev, " CP_RB0_CNTL=0x%08X\n",
- RREG32(mmCP_RB0_CNTL));
- dev_info(adev->dev, " CP_RB0_WPTR=0x%08X\n",
- RREG32(mmCP_RB0_WPTR));
- dev_info(adev->dev, " CP_RB0_RPTR_ADDR=0x%08X\n",
- RREG32(mmCP_RB0_RPTR_ADDR));
- dev_info(adev->dev, " CP_RB0_RPTR_ADDR_HI=0x%08X\n",
- RREG32(mmCP_RB0_RPTR_ADDR_HI));
- dev_info(adev->dev, " CP_RB0_CNTL=0x%08X\n",
- RREG32(mmCP_RB0_CNTL));
- dev_info(adev->dev, " CP_RB0_BASE=0x%08X\n",
- RREG32(mmCP_RB0_BASE));
- dev_info(adev->dev, " CP_RB0_BASE_HI=0x%08X\n",
- RREG32(mmCP_RB0_BASE_HI));
- dev_info(adev->dev, " CP_MEC_CNTL=0x%08X\n",
- RREG32(mmCP_MEC_CNTL));
- dev_info(adev->dev, " CP_CPF_DEBUG=0x%08X\n",
- RREG32(mmCP_CPF_DEBUG));
-
- dev_info(adev->dev, " SCRATCH_ADDR=0x%08X\n",
- RREG32(mmSCRATCH_ADDR));
- dev_info(adev->dev, " SCRATCH_UMSK=0x%08X\n",
- RREG32(mmSCRATCH_UMSK));
-
- dev_info(adev->dev, " CP_INT_CNTL_RING0=0x%08X\n",
- RREG32(mmCP_INT_CNTL_RING0));
- dev_info(adev->dev, " RLC_LB_CNTL=0x%08X\n",
- RREG32(mmRLC_LB_CNTL));
- dev_info(adev->dev, " RLC_CNTL=0x%08X\n",
- RREG32(mmRLC_CNTL));
- dev_info(adev->dev, " RLC_CGCG_CGLS_CTRL=0x%08X\n",
- RREG32(mmRLC_CGCG_CGLS_CTRL));
- dev_info(adev->dev, " RLC_LB_CNTR_INIT=0x%08X\n",
- RREG32(mmRLC_LB_CNTR_INIT));
- dev_info(adev->dev, " RLC_LB_CNTR_MAX=0x%08X\n",
- RREG32(mmRLC_LB_CNTR_MAX));
- dev_info(adev->dev, " RLC_LB_INIT_CU_MASK=0x%08X\n",
- RREG32(mmRLC_LB_INIT_CU_MASK));
- dev_info(adev->dev, " RLC_LB_PARAMS=0x%08X\n",
- RREG32(mmRLC_LB_PARAMS));
- dev_info(adev->dev, " RLC_LB_CNTL=0x%08X\n",
- RREG32(mmRLC_LB_CNTL));
- dev_info(adev->dev, " RLC_MC_CNTL=0x%08X\n",
- RREG32(mmRLC_MC_CNTL));
- dev_info(adev->dev, " RLC_UCODE_CNTL=0x%08X\n",
- RREG32(mmRLC_UCODE_CNTL));
-
- mutex_lock(&adev->srbm_mutex);
- for (i = 0; i < 16; i++) {
- vi_srbm_select(adev, 0, 0, 0, i);
- dev_info(adev->dev, " VM %d:\n", i);
- dev_info(adev->dev, " SH_MEM_CONFIG=0x%08X\n",
- RREG32(mmSH_MEM_CONFIG));
- dev_info(adev->dev, " SH_MEM_APE1_BASE=0x%08X\n",
- RREG32(mmSH_MEM_APE1_BASE));
- dev_info(adev->dev, " SH_MEM_APE1_LIMIT=0x%08X\n",
- RREG32(mmSH_MEM_APE1_LIMIT));
- dev_info(adev->dev, " SH_MEM_BASES=0x%08X\n",
- RREG32(mmSH_MEM_BASES));
- }
- vi_srbm_select(adev, 0, 0, 0, 0);
- mutex_unlock(&adev->srbm_mutex);
-}
-
static int gfx_v8_0_soft_reset(void *handle)
{
u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
@@ -5045,7 +4866,6 @@ static int gfx_v8_0_soft_reset(void *handle)
SRBM_SOFT_RESET, SOFT_RESET_GRBM, 1);
if (grbm_soft_reset || srbm_soft_reset) {
- gfx_v8_0_print_status((void *)adev);
/* stop the rlc */
gfx_v8_0_rlc_stop(adev);
@@ -5105,7 +4925,6 @@ static int gfx_v8_0_soft_reset(void *handle)
/* Wait a little for things to settle down */
udelay(50);
- gfx_v8_0_print_status((void *)adev);
}
return 0;
}
@@ -6256,7 +6075,6 @@ const struct amd_ip_funcs gfx_v8_0_ip_funcs = {
.is_idle = gfx_v8_0_is_idle,
.wait_for_idle = gfx_v8_0_wait_for_idle,
.soft_reset = gfx_v8_0_soft_reset,
- .print_status = gfx_v8_0_print_status,
.set_clockgating_state = gfx_v8_0_set_clockgating_state,
.set_powergating_state = gfx_v8_0_set_powergating_state,
};
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
index 05b0353..3b620a8 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
@@ -1114,114 +1114,6 @@ static int gmc_v7_0_wait_for_idle(void *handle)
}
-static void gmc_v7_0_print_status(void *handle)
-{
- int i, j;
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-
- dev_info(adev->dev, "GMC 8.x registers\n");
- dev_info(adev->dev, " SRBM_STATUS=0x%08X\n",
- RREG32(mmSRBM_STATUS));
- dev_info(adev->dev, " SRBM_STATUS2=0x%08X\n",
- RREG32(mmSRBM_STATUS2));
-
- dev_info(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
- RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR));
- dev_info(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
- RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS));
- dev_info(adev->dev, " MC_VM_MX_L1_TLB_CNTL=0x%08X\n",
- RREG32(mmMC_VM_MX_L1_TLB_CNTL));
- dev_info(adev->dev, " VM_L2_CNTL=0x%08X\n",
- RREG32(mmVM_L2_CNTL));
- dev_info(adev->dev, " VM_L2_CNTL2=0x%08X\n",
- RREG32(mmVM_L2_CNTL2));
- dev_info(adev->dev, " VM_L2_CNTL3=0x%08X\n",
- RREG32(mmVM_L2_CNTL3));
- dev_info(adev->dev, " VM_CONTEXT0_PAGE_TABLE_START_ADDR=0x%08X\n",
- RREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR));
- dev_info(adev->dev, " VM_CONTEXT0_PAGE_TABLE_END_ADDR=0x%08X\n",
- RREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR));
- dev_info(adev->dev, " VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR=0x%08X\n",
- RREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR));
- dev_info(adev->dev, " VM_CONTEXT0_CNTL2=0x%08X\n",
- RREG32(mmVM_CONTEXT0_CNTL2));
- dev_info(adev->dev, " VM_CONTEXT0_CNTL=0x%08X\n",
- RREG32(mmVM_CONTEXT0_CNTL));
- dev_info(adev->dev, " 0x15D4=0x%08X\n",
- RREG32(0x575));
- dev_info(adev->dev, " 0x15D8=0x%08X\n",
- RREG32(0x576));
- dev_info(adev->dev, " 0x15DC=0x%08X\n",
- RREG32(0x577));
- dev_info(adev->dev, " VM_CONTEXT1_PAGE_TABLE_START_ADDR=0x%08X\n",
- RREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR));
- dev_info(adev->dev, " VM_CONTEXT1_PAGE_TABLE_END_ADDR=0x%08X\n",
- RREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR));
- dev_info(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR=0x%08X\n",
- RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR));
- dev_info(adev->dev, " VM_CONTEXT1_CNTL2=0x%08X\n",
- RREG32(mmVM_CONTEXT1_CNTL2));
- dev_info(adev->dev, " VM_CONTEXT1_CNTL=0x%08X\n",
- RREG32(mmVM_CONTEXT1_CNTL));
- for (i = 0; i < 16; i++) {
- if (i < 8)
- dev_info(adev->dev, " VM_CONTEXT%d_PAGE_TABLE_BASE_ADDR=0x%08X\n",
- i, RREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i));
- else
- dev_info(adev->dev, " VM_CONTEXT%d_PAGE_TABLE_BASE_ADDR=0x%08X\n",
- i, RREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8));
- }
- dev_info(adev->dev, " MC_VM_SYSTEM_APERTURE_LOW_ADDR=0x%08X\n",
- RREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR));
- dev_info(adev->dev, " MC_VM_SYSTEM_APERTURE_HIGH_ADDR=0x%08X\n",
- RREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR));
- dev_info(adev->dev, " MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR=0x%08X\n",
- RREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR));
- dev_info(adev->dev, " MC_VM_FB_LOCATION=0x%08X\n",
- RREG32(mmMC_VM_FB_LOCATION));
- dev_info(adev->dev, " MC_VM_AGP_BASE=0x%08X\n",
- RREG32(mmMC_VM_AGP_BASE));
- dev_info(adev->dev, " MC_VM_AGP_TOP=0x%08X\n",
- RREG32(mmMC_VM_AGP_TOP));
- dev_info(adev->dev, " MC_VM_AGP_BOT=0x%08X\n",
- RREG32(mmMC_VM_AGP_BOT));
-
- if (adev->asic_type == CHIP_KAVERI) {
- dev_info(adev->dev, " CHUB_CONTROL=0x%08X\n",
- RREG32(mmCHUB_CONTROL));
- }
-
- dev_info(adev->dev, " HDP_REG_COHERENCY_FLUSH_CNTL=0x%08X\n",
- RREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL));
- dev_info(adev->dev, " HDP_NONSURFACE_BASE=0x%08X\n",
- RREG32(mmHDP_NONSURFACE_BASE));
- dev_info(adev->dev, " HDP_NONSURFACE_INFO=0x%08X\n",
- RREG32(mmHDP_NONSURFACE_INFO));
- dev_info(adev->dev, " HDP_NONSURFACE_SIZE=0x%08X\n",
- RREG32(mmHDP_NONSURFACE_SIZE));
- dev_info(adev->dev, " HDP_MISC_CNTL=0x%08X\n",
- RREG32(mmHDP_MISC_CNTL));
- dev_info(adev->dev, " HDP_HOST_PATH_CNTL=0x%08X\n",
- RREG32(mmHDP_HOST_PATH_CNTL));
-
- for (i = 0, j = 0; i < 32; i++, j += 0x6) {
- dev_info(adev->dev, " %d:\n", i);
- dev_info(adev->dev, " 0x%04X=0x%08X\n",
- 0xb05 + j, RREG32(0xb05 + j));
- dev_info(adev->dev, " 0x%04X=0x%08X\n",
- 0xb06 + j, RREG32(0xb06 + j));
- dev_info(adev->dev, " 0x%04X=0x%08X\n",
- 0xb07 + j, RREG32(0xb07 + j));
- dev_info(adev->dev, " 0x%04X=0x%08X\n",
- 0xb08 + j, RREG32(0xb08 + j));
- dev_info(adev->dev, " 0x%04X=0x%08X\n",
- 0xb09 + j, RREG32(0xb09 + j));
- }
-
- dev_info(adev->dev, " BIF_FB_EN=0x%08X\n",
- RREG32(mmBIF_FB_EN));
-}
-
static int gmc_v7_0_soft_reset(void *handle)
{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
@@ -1241,8 +1133,6 @@ static int gmc_v7_0_soft_reset(void *handle)
}
if (srbm_soft_reset) {
- gmc_v7_0_print_status((void *)adev);
-
gmc_v7_0_mc_stop(adev, &save);
if (gmc_v7_0_wait_for_idle(adev)) {
dev_warn(adev->dev, "Wait for GMC idle timed out !\n");
@@ -1266,8 +1156,6 @@ static int gmc_v7_0_soft_reset(void *handle)
gmc_v7_0_mc_resume(adev, &save);
udelay(50);
-
- gmc_v7_0_print_status((void *)adev);
}
return 0;
@@ -1381,7 +1269,6 @@ const struct amd_ip_funcs gmc_v7_0_ip_funcs = {
.is_idle = gmc_v7_0_is_idle,
.wait_for_idle = gmc_v7_0_wait_for_idle,
.soft_reset = gmc_v7_0_soft_reset,
- .print_status = gmc_v7_0_print_status,
.set_clockgating_state = gmc_v7_0_set_clockgating_state,
.set_powergating_state = gmc_v7_0_set_powergating_state,
};
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
index e6715ec..c0de22f 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
@@ -1117,111 +1117,6 @@ static int gmc_v8_0_wait_for_idle(void *handle)
}
-static void gmc_v8_0_print_status(void *handle)
-{
- int i, j;
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-
- dev_info(adev->dev, "GMC 8.x registers\n");
- dev_info(adev->dev, " SRBM_STATUS=0x%08X\n",
- RREG32(mmSRBM_STATUS));
- dev_info(adev->dev, " SRBM_STATUS2=0x%08X\n",
- RREG32(mmSRBM_STATUS2));
-
- dev_info(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
- RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR));
- dev_info(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
- RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS));
- dev_info(adev->dev, " MC_VM_MX_L1_TLB_CNTL=0x%08X\n",
- RREG32(mmMC_VM_MX_L1_TLB_CNTL));
- dev_info(adev->dev, " VM_L2_CNTL=0x%08X\n",
- RREG32(mmVM_L2_CNTL));
- dev_info(adev->dev, " VM_L2_CNTL2=0x%08X\n",
- RREG32(mmVM_L2_CNTL2));
- dev_info(adev->dev, " VM_L2_CNTL3=0x%08X\n",
- RREG32(mmVM_L2_CNTL3));
- dev_info(adev->dev, " VM_L2_CNTL4=0x%08X\n",
- RREG32(mmVM_L2_CNTL4));
- dev_info(adev->dev, " VM_CONTEXT0_PAGE_TABLE_START_ADDR=0x%08X\n",
- RREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR));
- dev_info(adev->dev, " VM_CONTEXT0_PAGE_TABLE_END_ADDR=0x%08X\n",
- RREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR));
- dev_info(adev->dev, " VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR=0x%08X\n",
- RREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR));
- dev_info(adev->dev, " VM_CONTEXT0_CNTL2=0x%08X\n",
- RREG32(mmVM_CONTEXT0_CNTL2));
- dev_info(adev->dev, " VM_CONTEXT0_CNTL=0x%08X\n",
- RREG32(mmVM_CONTEXT0_CNTL));
- dev_info(adev->dev, " VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR=0x%08X\n",
- RREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR));
- dev_info(adev->dev, " VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR=0x%08X\n",
- RREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR));
- dev_info(adev->dev, " mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET=0x%08X\n",
- RREG32(mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET));
- dev_info(adev->dev, " VM_CONTEXT1_PAGE_TABLE_START_ADDR=0x%08X\n",
- RREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR));
- dev_info(adev->dev, " VM_CONTEXT1_PAGE_TABLE_END_ADDR=0x%08X\n",
- RREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR));
- dev_info(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR=0x%08X\n",
- RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR));
- dev_info(adev->dev, " VM_CONTEXT1_CNTL2=0x%08X\n",
- RREG32(mmVM_CONTEXT1_CNTL2));
- dev_info(adev->dev, " VM_CONTEXT1_CNTL=0x%08X\n",
- RREG32(mmVM_CONTEXT1_CNTL));
- for (i = 0; i < 16; i++) {
- if (i < 8)
- dev_info(adev->dev, " VM_CONTEXT%d_PAGE_TABLE_BASE_ADDR=0x%08X\n",
- i, RREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i));
- else
- dev_info(adev->dev, " VM_CONTEXT%d_PAGE_TABLE_BASE_ADDR=0x%08X\n",
- i, RREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8));
- }
- dev_info(adev->dev, " MC_VM_SYSTEM_APERTURE_LOW_ADDR=0x%08X\n",
- RREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR));
- dev_info(adev->dev, " MC_VM_SYSTEM_APERTURE_HIGH_ADDR=0x%08X\n",
- RREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR));
- dev_info(adev->dev, " MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR=0x%08X\n",
- RREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR));
- dev_info(adev->dev, " MC_VM_FB_LOCATION=0x%08X\n",
- RREG32(mmMC_VM_FB_LOCATION));
- dev_info(adev->dev, " MC_VM_AGP_BASE=0x%08X\n",
- RREG32(mmMC_VM_AGP_BASE));
- dev_info(adev->dev, " MC_VM_AGP_TOP=0x%08X\n",
- RREG32(mmMC_VM_AGP_TOP));
- dev_info(adev->dev, " MC_VM_AGP_BOT=0x%08X\n",
- RREG32(mmMC_VM_AGP_BOT));
-
- dev_info(adev->dev, " HDP_REG_COHERENCY_FLUSH_CNTL=0x%08X\n",
- RREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL));
- dev_info(adev->dev, " HDP_NONSURFACE_BASE=0x%08X\n",
- RREG32(mmHDP_NONSURFACE_BASE));
- dev_info(adev->dev, " HDP_NONSURFACE_INFO=0x%08X\n",
- RREG32(mmHDP_NONSURFACE_INFO));
- dev_info(adev->dev, " HDP_NONSURFACE_SIZE=0x%08X\n",
- RREG32(mmHDP_NONSURFACE_SIZE));
- dev_info(adev->dev, " HDP_MISC_CNTL=0x%08X\n",
- RREG32(mmHDP_MISC_CNTL));
- dev_info(adev->dev, " HDP_HOST_PATH_CNTL=0x%08X\n",
- RREG32(mmHDP_HOST_PATH_CNTL));
-
- for (i = 0, j = 0; i < 32; i++, j += 0x6) {
- dev_info(adev->dev, " %d:\n", i);
- dev_info(adev->dev, " 0x%04X=0x%08X\n",
- 0xb05 + j, RREG32(0xb05 + j));
- dev_info(adev->dev, " 0x%04X=0x%08X\n",
- 0xb06 + j, RREG32(0xb06 + j));
- dev_info(adev->dev, " 0x%04X=0x%08X\n",
- 0xb07 + j, RREG32(0xb07 + j));
- dev_info(adev->dev, " 0x%04X=0x%08X\n",
- 0xb08 + j, RREG32(0xb08 + j));
- dev_info(adev->dev, " 0x%04X=0x%08X\n",
- 0xb09 + j, RREG32(0xb09 + j));
- }
-
- dev_info(adev->dev, " BIF_FB_EN=0x%08X\n",
- RREG32(mmBIF_FB_EN));
-}
-
static int gmc_v8_0_soft_reset(void *handle)
{
struct amdgpu_mode_mc_save save;
@@ -1241,8 +1136,6 @@ static int gmc_v8_0_soft_reset(void *handle)
}
if (srbm_soft_reset) {
- gmc_v8_0_print_status((void *)adev);
-
gmc_v8_0_mc_stop(adev, &save);
if (gmc_v8_0_wait_for_idle(adev)) {
dev_warn(adev->dev, "Wait for GMC idle timed out !\n");
@@ -1266,8 +1159,6 @@ static int gmc_v8_0_soft_reset(void *handle)
gmc_v8_0_mc_resume(adev, &save);
udelay(50);
-
- gmc_v8_0_print_status((void *)adev);
}
return 0;
@@ -1540,7 +1431,6 @@ const struct amd_ip_funcs gmc_v8_0_ip_funcs = {
.is_idle = gmc_v8_0_is_idle,
.wait_for_idle = gmc_v8_0_wait_for_idle,
.soft_reset = gmc_v8_0_soft_reset,
- .print_status = gmc_v8_0_print_status,
.set_clockgating_state = gmc_v8_0_set_clockgating_state,
.set_powergating_state = gmc_v8_0_set_powergating_state,
};
diff --git a/drivers/gpu/drm/amd/amdgpu/iceland_dpm.c b/drivers/gpu/drm/amd/amdgpu/iceland_dpm.c
index 208d55f4..57a9613 100644
--- a/drivers/gpu/drm/amd/amdgpu/iceland_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/iceland_dpm.c
@@ -168,7 +168,6 @@ const struct amd_ip_funcs iceland_dpm_ip_funcs = {
.is_idle = NULL,
.wait_for_idle = NULL,
.soft_reset = NULL,
- .print_status = NULL,
.set_clockgating_state = iceland_dpm_set_clockgating_state,
.set_powergating_state = iceland_dpm_set_powergating_state,
};
diff --git a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
index 679e739..5c4001e 100644
--- a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
@@ -351,35 +351,6 @@ static int iceland_ih_wait_for_idle(void *handle)
return -ETIMEDOUT;
}
-static void iceland_ih_print_status(void *handle)
-{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-
- dev_info(adev->dev, "ICELAND IH registers\n");
- dev_info(adev->dev, " SRBM_STATUS=0x%08X\n",
- RREG32(mmSRBM_STATUS));
- dev_info(adev->dev, " SRBM_STATUS2=0x%08X\n",
- RREG32(mmSRBM_STATUS2));
- dev_info(adev->dev, " INTERRUPT_CNTL=0x%08X\n",
- RREG32(mmINTERRUPT_CNTL));
- dev_info(adev->dev, " INTERRUPT_CNTL2=0x%08X\n",
- RREG32(mmINTERRUPT_CNTL2));
- dev_info(adev->dev, " IH_CNTL=0x%08X\n",
- RREG32(mmIH_CNTL));
- dev_info(adev->dev, " IH_RB_CNTL=0x%08X\n",
- RREG32(mmIH_RB_CNTL));
- dev_info(adev->dev, " IH_RB_BASE=0x%08X\n",
- RREG32(mmIH_RB_BASE));
- dev_info(adev->dev, " IH_RB_WPTR_ADDR_LO=0x%08X\n",
- RREG32(mmIH_RB_WPTR_ADDR_LO));
- dev_info(adev->dev, " IH_RB_WPTR_ADDR_HI=0x%08X\n",
- RREG32(mmIH_RB_WPTR_ADDR_HI));
- dev_info(adev->dev, " IH_RB_RPTR=0x%08X\n",
- RREG32(mmIH_RB_RPTR));
- dev_info(adev->dev, " IH_RB_WPTR=0x%08X\n",
- RREG32(mmIH_RB_WPTR));
-}
-
static int iceland_ih_soft_reset(void *handle)
{
u32 srbm_soft_reset = 0;
@@ -391,8 +362,6 @@ static int iceland_ih_soft_reset(void *handle)
SOFT_RESET_IH, 1);
if (srbm_soft_reset) {
- iceland_ih_print_status((void *)adev);
-
tmp = RREG32(mmSRBM_SOFT_RESET);
tmp |= srbm_soft_reset;
dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
@@ -407,8 +376,6 @@ static int iceland_ih_soft_reset(void *handle)
/* Wait a little for things to settle down */
udelay(50);
-
- iceland_ih_print_status((void *)adev);
}
return 0;
@@ -438,7 +405,6 @@ const struct amd_ip_funcs iceland_ih_ip_funcs = {
.is_idle = iceland_ih_is_idle,
.wait_for_idle = iceland_ih_wait_for_idle,
.soft_reset = iceland_ih_soft_reset,
- .print_status = iceland_ih_print_status,
.set_clockgating_state = iceland_ih_set_clockgating_state,
.set_powergating_state = iceland_ih_set_powergating_state,
};
diff --git a/drivers/gpu/drm/amd/amdgpu/kv_dpm.c b/drivers/gpu/drm/amd/amdgpu/kv_dpm.c
index 654d767..4bd1e55 100644
--- a/drivers/gpu/drm/amd/amdgpu/kv_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/kv_dpm.c
@@ -3147,62 +3147,6 @@ static int kv_dpm_wait_for_idle(void *handle)
return 0;
}
-static void kv_dpm_print_status(void *handle)
-{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-
- dev_info(adev->dev, "KV/KB DPM registers\n");
- dev_info(adev->dev, " DIDT_SQ_CTRL0=0x%08X\n",
- RREG32_DIDT(ixDIDT_SQ_CTRL0));
- dev_info(adev->dev, " DIDT_DB_CTRL0=0x%08X\n",
- RREG32_DIDT(ixDIDT_DB_CTRL0));
- dev_info(adev->dev, " DIDT_TD_CTRL0=0x%08X\n",
- RREG32_DIDT(ixDIDT_TD_CTRL0));
- dev_info(adev->dev, " DIDT_TCP_CTRL0=0x%08X\n",
- RREG32_DIDT(ixDIDT_TCP_CTRL0));
- dev_info(adev->dev, " LCAC_SX0_OVR_SEL=0x%08X\n",
- RREG32_SMC(ixLCAC_SX0_OVR_SEL));
- dev_info(adev->dev, " LCAC_SX0_OVR_VAL=0x%08X\n",
- RREG32_SMC(ixLCAC_SX0_OVR_VAL));
- dev_info(adev->dev, " LCAC_MC0_OVR_SEL=0x%08X\n",
- RREG32_SMC(ixLCAC_MC0_OVR_SEL));
- dev_info(adev->dev, " LCAC_MC0_OVR_VAL=0x%08X\n",
- RREG32_SMC(ixLCAC_MC0_OVR_VAL));
- dev_info(adev->dev, " LCAC_MC1_OVR_SEL=0x%08X\n",
- RREG32_SMC(ixLCAC_MC1_OVR_SEL));
- dev_info(adev->dev, " LCAC_MC1_OVR_VAL=0x%08X\n",
- RREG32_SMC(ixLCAC_MC1_OVR_VAL));
- dev_info(adev->dev, " LCAC_MC2_OVR_SEL=0x%08X\n",
- RREG32_SMC(ixLCAC_MC2_OVR_SEL));
- dev_info(adev->dev, " LCAC_MC2_OVR_VAL=0x%08X\n",
- RREG32_SMC(ixLCAC_MC2_OVR_VAL));
- dev_info(adev->dev, " LCAC_MC3_OVR_SEL=0x%08X\n",
- RREG32_SMC(ixLCAC_MC3_OVR_SEL));
- dev_info(adev->dev, " LCAC_MC3_OVR_VAL=0x%08X\n",
- RREG32_SMC(ixLCAC_MC3_OVR_VAL));
- dev_info(adev->dev, " LCAC_CPL_OVR_SEL=0x%08X\n",
- RREG32_SMC(ixLCAC_CPL_OVR_SEL));
- dev_info(adev->dev, " LCAC_CPL_OVR_VAL=0x%08X\n",
- RREG32_SMC(ixLCAC_CPL_OVR_VAL));
- dev_info(adev->dev, " CG_FREQ_TRAN_VOTING_0=0x%08X\n",
- RREG32_SMC(ixCG_FREQ_TRAN_VOTING_0));
- dev_info(adev->dev, " GENERAL_PWRMGT=0x%08X\n",
- RREG32_SMC(ixGENERAL_PWRMGT));
- dev_info(adev->dev, " SCLK_PWRMGT_CNTL=0x%08X\n",
- RREG32_SMC(ixSCLK_PWRMGT_CNTL));
- dev_info(adev->dev, " SMC_MESSAGE_0=0x%08X\n",
- RREG32(mmSMC_MESSAGE_0));
- dev_info(adev->dev, " SMC_RESP_0=0x%08X\n",
- RREG32(mmSMC_RESP_0));
- dev_info(adev->dev, " SMC_MSG_ARG_0=0x%08X\n",
- RREG32(mmSMC_MSG_ARG_0));
- dev_info(adev->dev, " SMC_IND_INDEX_0=0x%08X\n",
- RREG32(mmSMC_IND_INDEX_0));
- dev_info(adev->dev, " SMC_IND_DATA_0=0x%08X\n",
- RREG32(mmSMC_IND_DATA_0));
- dev_info(adev->dev, " SMC_IND_ACCESS_CNTL=0x%08X\n",
- RREG32(mmSMC_IND_ACCESS_CNTL));
-}
static int kv_dpm_soft_reset(void *handle)
{
@@ -3311,7 +3255,6 @@ const struct amd_ip_funcs kv_dpm_ip_funcs = {
.is_idle = kv_dpm_is_idle,
.wait_for_idle = kv_dpm_wait_for_idle,
.soft_reset = kv_dpm_soft_reset,
- .print_status = kv_dpm_print_status,
.set_clockgating_state = kv_dpm_set_clockgating_state,
.set_powergating_state = kv_dpm_set_powergating_state,
};
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
index 6f2e2a4..e6d3544 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
@@ -1080,55 +1080,6 @@ static int sdma_v2_4_wait_for_idle(void *handle)
return -ETIMEDOUT;
}
-static void sdma_v2_4_print_status(void *handle)
-{
- int i, j;
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-
- dev_info(adev->dev, "VI SDMA registers\n");
- dev_info(adev->dev, " SRBM_STATUS2=0x%08X\n",
- RREG32(mmSRBM_STATUS2));
- for (i = 0; i < adev->sdma.num_instances; i++) {
- dev_info(adev->dev, " SDMA%d_STATUS_REG=0x%08X\n",
- i, RREG32(mmSDMA0_STATUS_REG + sdma_offsets[i]));
- dev_info(adev->dev, " SDMA%d_F32_CNTL=0x%08X\n",
- i, RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]));
- dev_info(adev->dev, " SDMA%d_CNTL=0x%08X\n",
- i, RREG32(mmSDMA0_CNTL + sdma_offsets[i]));
- dev_info(adev->dev, " SDMA%d_SEM_WAIT_FAIL_TIMER_CNTL=0x%08X\n",
- i, RREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i]));
- dev_info(adev->dev, " SDMA%d_GFX_IB_CNTL=0x%08X\n",
- i, RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]));
- dev_info(adev->dev, " SDMA%d_GFX_RB_CNTL=0x%08X\n",
- i, RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]));
- dev_info(adev->dev, " SDMA%d_GFX_RB_RPTR=0x%08X\n",
- i, RREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i]));
- dev_info(adev->dev, " SDMA%d_GFX_RB_WPTR=0x%08X\n",
- i, RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i]));
- dev_info(adev->dev, " SDMA%d_GFX_RB_RPTR_ADDR_HI=0x%08X\n",
- i, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i]));
- dev_info(adev->dev, " SDMA%d_GFX_RB_RPTR_ADDR_LO=0x%08X\n",
- i, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i]));
- dev_info(adev->dev, " SDMA%d_GFX_RB_BASE=0x%08X\n",
- i, RREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i]));
- dev_info(adev->dev, " SDMA%d_GFX_RB_BASE_HI=0x%08X\n",
- i, RREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i]));
- dev_info(adev->dev, " SDMA%d_TILING_CONFIG=0x%08X\n",
- i, RREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i]));
- mutex_lock(&adev->srbm_mutex);
- for (j = 0; j < 16; j++) {
- vi_srbm_select(adev, 0, 0, 0, j);
- dev_info(adev->dev, " VM %d:\n", j);
- dev_info(adev->dev, " SDMA%d_GFX_VIRTUAL_ADDR=0x%08X\n",
- i, RREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i]));
- dev_info(adev->dev, " SDMA%d_GFX_APE1_CNTL=0x%08X\n",
- i, RREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i]));
- }
- vi_srbm_select(adev, 0, 0, 0, 0);
- mutex_unlock(&adev->srbm_mutex);
- }
-}
-
static int sdma_v2_4_soft_reset(void *handle)
{
u32 srbm_soft_reset = 0;
@@ -1151,8 +1102,6 @@ static int sdma_v2_4_soft_reset(void *handle)
}
if (srbm_soft_reset) {
- sdma_v2_4_print_status((void *)adev);
-
tmp = RREG32(mmSRBM_SOFT_RESET);
tmp |= srbm_soft_reset;
dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
@@ -1167,8 +1116,6 @@ static int sdma_v2_4_soft_reset(void *handle)
/* Wait a little for things to settle down */
udelay(50);
-
- sdma_v2_4_print_status((void *)adev);
}
return 0;
@@ -1294,7 +1241,6 @@ const struct amd_ip_funcs sdma_v2_4_ip_funcs = {
.is_idle = sdma_v2_4_is_idle,
.wait_for_idle = sdma_v2_4_wait_for_idle,
.soft_reset = sdma_v2_4_soft_reset,
- .print_status = sdma_v2_4_print_status,
.set_clockgating_state = sdma_v2_4_set_clockgating_state,
.set_powergating_state = sdma_v2_4_set_powergating_state,
};
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
index 1b5053f..00b4370 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
@@ -1314,57 +1314,6 @@ static int sdma_v3_0_wait_for_idle(void *handle)
return -ETIMEDOUT;
}
-static void sdma_v3_0_print_status(void *handle)
-{
- int i, j;
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-
- dev_info(adev->dev, "VI SDMA registers\n");
- dev_info(adev->dev, " SRBM_STATUS2=0x%08X\n",
- RREG32(mmSRBM_STATUS2));
- for (i = 0; i < adev->sdma.num_instances; i++) {
- dev_info(adev->dev, " SDMA%d_STATUS_REG=0x%08X\n",
- i, RREG32(mmSDMA0_STATUS_REG + sdma_offsets[i]));
- dev_info(adev->dev, " SDMA%d_F32_CNTL=0x%08X\n",
- i, RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]));
- dev_info(adev->dev, " SDMA%d_CNTL=0x%08X\n",
- i, RREG32(mmSDMA0_CNTL + sdma_offsets[i]));
- dev_info(adev->dev, " SDMA%d_SEM_WAIT_FAIL_TIMER_CNTL=0x%08X\n",
- i, RREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i]));
- dev_info(adev->dev, " SDMA%d_GFX_IB_CNTL=0x%08X\n",
- i, RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]));
- dev_info(adev->dev, " SDMA%d_GFX_RB_CNTL=0x%08X\n",
- i, RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]));
- dev_info(adev->dev, " SDMA%d_GFX_RB_RPTR=0x%08X\n",
- i, RREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i]));
- dev_info(adev->dev, " SDMA%d_GFX_RB_WPTR=0x%08X\n",
- i, RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i]));
- dev_info(adev->dev, " SDMA%d_GFX_RB_RPTR_ADDR_HI=0x%08X\n",
- i, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i]));
- dev_info(adev->dev, " SDMA%d_GFX_RB_RPTR_ADDR_LO=0x%08X\n",
- i, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i]));
- dev_info(adev->dev, " SDMA%d_GFX_RB_BASE=0x%08X\n",
- i, RREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i]));
- dev_info(adev->dev, " SDMA%d_GFX_RB_BASE_HI=0x%08X\n",
- i, RREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i]));
- dev_info(adev->dev, " SDMA%d_GFX_DOORBELL=0x%08X\n",
- i, RREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i]));
- dev_info(adev->dev, " SDMA%d_TILING_CONFIG=0x%08X\n",
- i, RREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i]));
- mutex_lock(&adev->srbm_mutex);
- for (j = 0; j < 16; j++) {
- vi_srbm_select(adev, 0, 0, 0, j);
- dev_info(adev->dev, " VM %d:\n", j);
- dev_info(adev->dev, " SDMA%d_GFX_VIRTUAL_ADDR=0x%08X\n",
- i, RREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i]));
- dev_info(adev->dev, " SDMA%d_GFX_APE1_CNTL=0x%08X\n",
- i, RREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i]));
- }
- vi_srbm_select(adev, 0, 0, 0, 0);
- mutex_unlock(&adev->srbm_mutex);
- }
-}
-
static int sdma_v3_0_soft_reset(void *handle)
{
u32 srbm_soft_reset = 0;
@@ -1387,8 +1336,6 @@ static int sdma_v3_0_soft_reset(void *handle)
}
if (srbm_soft_reset) {
- sdma_v3_0_print_status((void *)adev);
-
tmp = RREG32(mmSRBM_SOFT_RESET);
tmp |= srbm_soft_reset;
dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
@@ -1403,8 +1350,6 @@ static int sdma_v3_0_soft_reset(void *handle)
/* Wait a little for things to settle down */
udelay(50);
-
- sdma_v3_0_print_status((void *)adev);
}
return 0;
@@ -1608,7 +1553,6 @@ const struct amd_ip_funcs sdma_v3_0_ip_funcs = {
.is_idle = sdma_v3_0_is_idle,
.wait_for_idle = sdma_v3_0_wait_for_idle,
.soft_reset = sdma_v3_0_soft_reset,
- .print_status = sdma_v3_0_print_status,
.set_clockgating_state = sdma_v3_0_set_clockgating_state,
.set_powergating_state = sdma_v3_0_set_powergating_state,
};
diff --git a/drivers/gpu/drm/amd/amdgpu/tonga_dpm.c b/drivers/gpu/drm/amd/amdgpu/tonga_dpm.c
index 0497784..552f0f4 100644
--- a/drivers/gpu/drm/amd/amdgpu/tonga_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/tonga_dpm.c
@@ -154,7 +154,6 @@ const struct amd_ip_funcs tonga_dpm_ip_funcs = {
.is_idle = NULL,
.wait_for_idle = NULL,
.soft_reset = NULL,
- .print_status = NULL,
.set_clockgating_state = tonga_dpm_set_clockgating_state,
.set_powergating_state = tonga_dpm_set_powergating_state,
};
diff --git a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
index b6f7d7b..dd9e5e3 100644
--- a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
@@ -374,35 +374,6 @@ static int tonga_ih_wait_for_idle(void *handle)
return -ETIMEDOUT;
}
-static void tonga_ih_print_status(void *handle)
-{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-
- dev_info(adev->dev, "TONGA IH registers\n");
- dev_info(adev->dev, " SRBM_STATUS=0x%08X\n",
- RREG32(mmSRBM_STATUS));
- dev_info(adev->dev, " SRBM_STATUS2=0x%08X\n",
- RREG32(mmSRBM_STATUS2));
- dev_info(adev->dev, " INTERRUPT_CNTL=0x%08X\n",
- RREG32(mmINTERRUPT_CNTL));
- dev_info(adev->dev, " INTERRUPT_CNTL2=0x%08X\n",
- RREG32(mmINTERRUPT_CNTL2));
- dev_info(adev->dev, " IH_CNTL=0x%08X\n",
- RREG32(mmIH_CNTL));
- dev_info(adev->dev, " IH_RB_CNTL=0x%08X\n",
- RREG32(mmIH_RB_CNTL));
- dev_info(adev->dev, " IH_RB_BASE=0x%08X\n",
- RREG32(mmIH_RB_BASE));
- dev_info(adev->dev, " IH_RB_WPTR_ADDR_LO=0x%08X\n",
- RREG32(mmIH_RB_WPTR_ADDR_LO));
- dev_info(adev->dev, " IH_RB_WPTR_ADDR_HI=0x%08X\n",
- RREG32(mmIH_RB_WPTR_ADDR_HI));
- dev_info(adev->dev, " IH_RB_RPTR=0x%08X\n",
- RREG32(mmIH_RB_RPTR));
- dev_info(adev->dev, " IH_RB_WPTR=0x%08X\n",
- RREG32(mmIH_RB_WPTR));
-}
-
static int tonga_ih_soft_reset(void *handle)
{
u32 srbm_soft_reset = 0;
@@ -414,8 +385,6 @@ static int tonga_ih_soft_reset(void *handle)
SOFT_RESET_IH, 1);
if (srbm_soft_reset) {
- tonga_ih_print_status(adev);
-
tmp = RREG32(mmSRBM_SOFT_RESET);
tmp |= srbm_soft_reset;
dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
@@ -430,8 +399,6 @@ static int tonga_ih_soft_reset(void *handle)
/* Wait a little for things to settle down */
udelay(50);
-
- tonga_ih_print_status(adev);
}
return 0;
@@ -461,7 +428,6 @@ const struct amd_ip_funcs tonga_ih_ip_funcs = {
.is_idle = tonga_ih_is_idle,
.wait_for_idle = tonga_ih_wait_for_idle,
.soft_reset = tonga_ih_soft_reset,
- .print_status = tonga_ih_print_status,
.set_clockgating_state = tonga_ih_set_clockgating_state,
.set_powergating_state = tonga_ih_set_powergating_state,
};
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
index c257cfa..abd37a7 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
@@ -680,117 +680,6 @@ static int uvd_v4_2_soft_reset(void *handle)
return uvd_v4_2_start(adev);
}
-static void uvd_v4_2_print_status(void *handle)
-{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- dev_info(adev->dev, "UVD 4.2 registers\n");
- dev_info(adev->dev, " UVD_SEMA_ADDR_LOW=0x%08X\n",
- RREG32(mmUVD_SEMA_ADDR_LOW));
- dev_info(adev->dev, " UVD_SEMA_ADDR_HIGH=0x%08X\n",
- RREG32(mmUVD_SEMA_ADDR_HIGH));
- dev_info(adev->dev, " UVD_SEMA_CMD=0x%08X\n",
- RREG32(mmUVD_SEMA_CMD));
- dev_info(adev->dev, " UVD_GPCOM_VCPU_CMD=0x%08X\n",
- RREG32(mmUVD_GPCOM_VCPU_CMD));
- dev_info(adev->dev, " UVD_GPCOM_VCPU_DATA0=0x%08X\n",
- RREG32(mmUVD_GPCOM_VCPU_DATA0));
- dev_info(adev->dev, " UVD_GPCOM_VCPU_DATA1=0x%08X\n",
- RREG32(mmUVD_GPCOM_VCPU_DATA1));
- dev_info(adev->dev, " UVD_ENGINE_CNTL=0x%08X\n",
- RREG32(mmUVD_ENGINE_CNTL));
- dev_info(adev->dev, " UVD_UDEC_ADDR_CONFIG=0x%08X\n",
- RREG32(mmUVD_UDEC_ADDR_CONFIG));
- dev_info(adev->dev, " UVD_UDEC_DB_ADDR_CONFIG=0x%08X\n",
- RREG32(mmUVD_UDEC_DB_ADDR_CONFIG));
- dev_info(adev->dev, " UVD_UDEC_DBW_ADDR_CONFIG=0x%08X\n",
- RREG32(mmUVD_UDEC_DBW_ADDR_CONFIG));
- dev_info(adev->dev, " UVD_SEMA_CNTL=0x%08X\n",
- RREG32(mmUVD_SEMA_CNTL));
- dev_info(adev->dev, " UVD_LMI_EXT40_ADDR=0x%08X\n",
- RREG32(mmUVD_LMI_EXT40_ADDR));
- dev_info(adev->dev, " UVD_CTX_INDEX=0x%08X\n",
- RREG32(mmUVD_CTX_INDEX));
- dev_info(adev->dev, " UVD_CTX_DATA=0x%08X\n",
- RREG32(mmUVD_CTX_DATA));
- dev_info(adev->dev, " UVD_CGC_GATE=0x%08X\n",
- RREG32(mmUVD_CGC_GATE));
- dev_info(adev->dev, " UVD_CGC_CTRL=0x%08X\n",
- RREG32(mmUVD_CGC_CTRL));
- dev_info(adev->dev, " UVD_LMI_CTRL2=0x%08X\n",
- RREG32(mmUVD_LMI_CTRL2));
- dev_info(adev->dev, " UVD_MASTINT_EN=0x%08X\n",
- RREG32(mmUVD_MASTINT_EN));
- dev_info(adev->dev, " UVD_LMI_ADDR_EXT=0x%08X\n",
- RREG32(mmUVD_LMI_ADDR_EXT));
- dev_info(adev->dev, " UVD_LMI_CTRL=0x%08X\n",
- RREG32(mmUVD_LMI_CTRL));
- dev_info(adev->dev, " UVD_LMI_SWAP_CNTL=0x%08X\n",
- RREG32(mmUVD_LMI_SWAP_CNTL));
- dev_info(adev->dev, " UVD_MP_SWAP_CNTL=0x%08X\n",
- RREG32(mmUVD_MP_SWAP_CNTL));
- dev_info(adev->dev, " UVD_MPC_SET_MUXA0=0x%08X\n",
- RREG32(mmUVD_MPC_SET_MUXA0));
- dev_info(adev->dev, " UVD_MPC_SET_MUXA1=0x%08X\n",
- RREG32(mmUVD_MPC_SET_MUXA1));
- dev_info(adev->dev, " UVD_MPC_SET_MUXB0=0x%08X\n",
- RREG32(mmUVD_MPC_SET_MUXB0));
- dev_info(adev->dev, " UVD_MPC_SET_MUXB1=0x%08X\n",
- RREG32(mmUVD_MPC_SET_MUXB1));
- dev_info(adev->dev, " UVD_MPC_SET_MUX=0x%08X\n",
- RREG32(mmUVD_MPC_SET_MUX));
- dev_info(adev->dev, " UVD_MPC_SET_ALU=0x%08X\n",
- RREG32(mmUVD_MPC_SET_ALU));
- dev_info(adev->dev, " UVD_VCPU_CACHE_OFFSET0=0x%08X\n",
- RREG32(mmUVD_VCPU_CACHE_OFFSET0));
- dev_info(adev->dev, " UVD_VCPU_CACHE_SIZE0=0x%08X\n",
- RREG32(mmUVD_VCPU_CACHE_SIZE0));
- dev_info(adev->dev, " UVD_VCPU_CACHE_OFFSET1=0x%08X\n",
- RREG32(mmUVD_VCPU_CACHE_OFFSET1));
- dev_info(adev->dev, " UVD_VCPU_CACHE_SIZE1=0x%08X\n",
- RREG32(mmUVD_VCPU_CACHE_SIZE1));
- dev_info(adev->dev, " UVD_VCPU_CACHE_OFFSET2=0x%08X\n",
- RREG32(mmUVD_VCPU_CACHE_OFFSET2));
- dev_info(adev->dev, " UVD_VCPU_CACHE_SIZE2=0x%08X\n",
- RREG32(mmUVD_VCPU_CACHE_SIZE2));
- dev_info(adev->dev, " UVD_VCPU_CNTL=0x%08X\n",
- RREG32(mmUVD_VCPU_CNTL));
- dev_info(adev->dev, " UVD_SOFT_RESET=0x%08X\n",
- RREG32(mmUVD_SOFT_RESET));
- dev_info(adev->dev, " UVD_RBC_IB_BASE=0x%08X\n",
- RREG32(mmUVD_RBC_IB_BASE));
- dev_info(adev->dev, " UVD_RBC_IB_SIZE=0x%08X\n",
- RREG32(mmUVD_RBC_IB_SIZE));
- dev_info(adev->dev, " UVD_RBC_RB_BASE=0x%08X\n",
- RREG32(mmUVD_RBC_RB_BASE));
- dev_info(adev->dev, " UVD_RBC_RB_RPTR=0x%08X\n",
- RREG32(mmUVD_RBC_RB_RPTR));
- dev_info(adev->dev, " UVD_RBC_RB_WPTR=0x%08X\n",
- RREG32(mmUVD_RBC_RB_WPTR));
- dev_info(adev->dev, " UVD_RBC_RB_WPTR_CNTL=0x%08X\n",
- RREG32(mmUVD_RBC_RB_WPTR_CNTL));
- dev_info(adev->dev, " UVD_RBC_RB_CNTL=0x%08X\n",
- RREG32(mmUVD_RBC_RB_CNTL));
- dev_info(adev->dev, " UVD_STATUS=0x%08X\n",
- RREG32(mmUVD_STATUS));
- dev_info(adev->dev, " UVD_SEMA_TIMEOUT_STATUS=0x%08X\n",
- RREG32(mmUVD_SEMA_TIMEOUT_STATUS));
- dev_info(adev->dev, " UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL=0x%08X\n",
- RREG32(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL));
- dev_info(adev->dev, " UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL=0x%08X\n",
- RREG32(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL));
- dev_info(adev->dev, " UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL=0x%08X\n",
- RREG32(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL));
- dev_info(adev->dev, " UVD_CONTEXT_ID=0x%08X\n",
- RREG32(mmUVD_CONTEXT_ID));
- dev_info(adev->dev, " UVD_UDEC_ADDR_CONFIG=0x%08X\n",
- RREG32(mmUVD_UDEC_ADDR_CONFIG));
- dev_info(adev->dev, " UVD_UDEC_DB_ADDR_CONFIG=0x%08X\n",
- RREG32(mmUVD_UDEC_DB_ADDR_CONFIG));
- dev_info(adev->dev, " UVD_UDEC_DBW_ADDR_CONFIG=0x%08X\n",
- RREG32(mmUVD_UDEC_DBW_ADDR_CONFIG));
-
-}
-
static int uvd_v4_2_set_interrupt_state(struct amdgpu_device *adev,
struct amdgpu_irq_src *source,
unsigned type,
@@ -861,7 +750,6 @@ const struct amd_ip_funcs uvd_v4_2_ip_funcs = {
.is_idle = uvd_v4_2_is_idle,
.wait_for_idle = uvd_v4_2_wait_for_idle,
.soft_reset = uvd_v4_2_soft_reset,
- .print_status = uvd_v4_2_print_status,
.set_clockgating_state = uvd_v4_2_set_clockgating_state,
.set_powergating_state = uvd_v4_2_set_powergating_state,
};
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
index 5f0d4f7..1c1a0e2c 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
@@ -624,120 +624,6 @@ static int uvd_v5_0_soft_reset(void *handle)
return uvd_v5_0_start(adev);
}
-static void uvd_v5_0_print_status(void *handle)
-{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- dev_info(adev->dev, "UVD 5.0 registers\n");
- dev_info(adev->dev, " UVD_SEMA_ADDR_LOW=0x%08X\n",
- RREG32(mmUVD_SEMA_ADDR_LOW));
- dev_info(adev->dev, " UVD_SEMA_ADDR_HIGH=0x%08X\n",
- RREG32(mmUVD_SEMA_ADDR_HIGH));
- dev_info(adev->dev, " UVD_SEMA_CMD=0x%08X\n",
- RREG32(mmUVD_SEMA_CMD));
- dev_info(adev->dev, " UVD_GPCOM_VCPU_CMD=0x%08X\n",
- RREG32(mmUVD_GPCOM_VCPU_CMD));
- dev_info(adev->dev, " UVD_GPCOM_VCPU_DATA0=0x%08X\n",
- RREG32(mmUVD_GPCOM_VCPU_DATA0));
- dev_info(adev->dev, " UVD_GPCOM_VCPU_DATA1=0x%08X\n",
- RREG32(mmUVD_GPCOM_VCPU_DATA1));
- dev_info(adev->dev, " UVD_ENGINE_CNTL=0x%08X\n",
- RREG32(mmUVD_ENGINE_CNTL));
- dev_info(adev->dev, " UVD_UDEC_ADDR_CONFIG=0x%08X\n",
- RREG32(mmUVD_UDEC_ADDR_CONFIG));
- dev_info(adev->dev, " UVD_UDEC_DB_ADDR_CONFIG=0x%08X\n",
- RREG32(mmUVD_UDEC_DB_ADDR_CONFIG));
- dev_info(adev->dev, " UVD_UDEC_DBW_ADDR_CONFIG=0x%08X\n",
- RREG32(mmUVD_UDEC_DBW_ADDR_CONFIG));
- dev_info(adev->dev, " UVD_SEMA_CNTL=0x%08X\n",
- RREG32(mmUVD_SEMA_CNTL));
- dev_info(adev->dev, " UVD_LMI_EXT40_ADDR=0x%08X\n",
- RREG32(mmUVD_LMI_EXT40_ADDR));
- dev_info(adev->dev, " UVD_CTX_INDEX=0x%08X\n",
- RREG32(mmUVD_CTX_INDEX));
- dev_info(adev->dev, " UVD_CTX_DATA=0x%08X\n",
- RREG32(mmUVD_CTX_DATA));
- dev_info(adev->dev, " UVD_CGC_GATE=0x%08X\n",
- RREG32(mmUVD_CGC_GATE));
- dev_info(adev->dev, " UVD_CGC_CTRL=0x%08X\n",
- RREG32(mmUVD_CGC_CTRL));
- dev_info(adev->dev, " UVD_LMI_CTRL2=0x%08X\n",
- RREG32(mmUVD_LMI_CTRL2));
- dev_info(adev->dev, " UVD_MASTINT_EN=0x%08X\n",
- RREG32(mmUVD_MASTINT_EN));
- dev_info(adev->dev, " UVD_LMI_ADDR_EXT=0x%08X\n",
- RREG32(mmUVD_LMI_ADDR_EXT));
- dev_info(adev->dev, " UVD_LMI_CTRL=0x%08X\n",
- RREG32(mmUVD_LMI_CTRL));
- dev_info(adev->dev, " UVD_LMI_SWAP_CNTL=0x%08X\n",
- RREG32(mmUVD_LMI_SWAP_CNTL));
- dev_info(adev->dev, " UVD_MP_SWAP_CNTL=0x%08X\n",
- RREG32(mmUVD_MP_SWAP_CNTL));
- dev_info(adev->dev, " UVD_MPC_SET_MUXA0=0x%08X\n",
- RREG32(mmUVD_MPC_SET_MUXA0));
- dev_info(adev->dev, " UVD_MPC_SET_MUXA1=0x%08X\n",
- RREG32(mmUVD_MPC_SET_MUXA1));
- dev_info(adev->dev, " UVD_MPC_SET_MUXB0=0x%08X\n",
- RREG32(mmUVD_MPC_SET_MUXB0));
- dev_info(adev->dev, " UVD_MPC_SET_MUXB1=0x%08X\n",
- RREG32(mmUVD_MPC_SET_MUXB1));
- dev_info(adev->dev, " UVD_MPC_SET_MUX=0x%08X\n",
- RREG32(mmUVD_MPC_SET_MUX));
- dev_info(adev->dev, " UVD_MPC_SET_ALU=0x%08X\n",
- RREG32(mmUVD_MPC_SET_ALU));
- dev_info(adev->dev, " UVD_VCPU_CACHE_OFFSET0=0x%08X\n",
- RREG32(mmUVD_VCPU_CACHE_OFFSET0));
- dev_info(adev->dev, " UVD_VCPU_CACHE_SIZE0=0x%08X\n",
- RREG32(mmUVD_VCPU_CACHE_SIZE0));
- dev_info(adev->dev, " UVD_VCPU_CACHE_OFFSET1=0x%08X\n",
- RREG32(mmUVD_VCPU_CACHE_OFFSET1));
- dev_info(adev->dev, " UVD_VCPU_CACHE_SIZE1=0x%08X\n",
- RREG32(mmUVD_VCPU_CACHE_SIZE1));
- dev_info(adev->dev, " UVD_VCPU_CACHE_OFFSET2=0x%08X\n",
- RREG32(mmUVD_VCPU_CACHE_OFFSET2));
- dev_info(adev->dev, " UVD_VCPU_CACHE_SIZE2=0x%08X\n",
- RREG32(mmUVD_VCPU_CACHE_SIZE2));
- dev_info(adev->dev, " UVD_VCPU_CNTL=0x%08X\n",
- RREG32(mmUVD_VCPU_CNTL));
- dev_info(adev->dev, " UVD_SOFT_RESET=0x%08X\n",
- RREG32(mmUVD_SOFT_RESET));
- dev_info(adev->dev, " UVD_LMI_RBC_IB_64BIT_BAR_LOW=0x%08X\n",
- RREG32(mmUVD_LMI_RBC_IB_64BIT_BAR_LOW));
- dev_info(adev->dev, " UVD_LMI_RBC_IB_64BIT_BAR_HIGH=0x%08X\n",
- RREG32(mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH));
- dev_info(adev->dev, " UVD_RBC_IB_SIZE=0x%08X\n",
- RREG32(mmUVD_RBC_IB_SIZE));
- dev_info(adev->dev, " UVD_LMI_RBC_RB_64BIT_BAR_LOW=0x%08X\n",
- RREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_LOW));
- dev_info(adev->dev, " UVD_LMI_RBC_RB_64BIT_BAR_HIGH=0x%08X\n",
- RREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH));
- dev_info(adev->dev, " UVD_RBC_RB_RPTR=0x%08X\n",
- RREG32(mmUVD_RBC_RB_RPTR));
- dev_info(adev->dev, " UVD_RBC_RB_WPTR=0x%08X\n",
- RREG32(mmUVD_RBC_RB_WPTR));
- dev_info(adev->dev, " UVD_RBC_RB_WPTR_CNTL=0x%08X\n",
- RREG32(mmUVD_RBC_RB_WPTR_CNTL));
- dev_info(adev->dev, " UVD_RBC_RB_CNTL=0x%08X\n",
- RREG32(mmUVD_RBC_RB_CNTL));
- dev_info(adev->dev, " UVD_STATUS=0x%08X\n",
- RREG32(mmUVD_STATUS));
- dev_info(adev->dev, " UVD_SEMA_TIMEOUT_STATUS=0x%08X\n",
- RREG32(mmUVD_SEMA_TIMEOUT_STATUS));
- dev_info(adev->dev, " UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL=0x%08X\n",
- RREG32(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL));
- dev_info(adev->dev, " UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL=0x%08X\n",
- RREG32(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL));
- dev_info(adev->dev, " UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL=0x%08X\n",
- RREG32(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL));
- dev_info(adev->dev, " UVD_CONTEXT_ID=0x%08X\n",
- RREG32(mmUVD_CONTEXT_ID));
- dev_info(adev->dev, " UVD_UDEC_ADDR_CONFIG=0x%08X\n",
- RREG32(mmUVD_UDEC_ADDR_CONFIG));
- dev_info(adev->dev, " UVD_UDEC_DB_ADDR_CONFIG=0x%08X\n",
- RREG32(mmUVD_UDEC_DB_ADDR_CONFIG));
- dev_info(adev->dev, " UVD_UDEC_DBW_ADDR_CONFIG=0x%08X\n",
- RREG32(mmUVD_UDEC_DBW_ADDR_CONFIG));
-}
-
static int uvd_v5_0_set_interrupt_state(struct amdgpu_device *adev,
struct amdgpu_irq_src *source,
unsigned type,
@@ -916,7 +802,6 @@ const struct amd_ip_funcs uvd_v5_0_ip_funcs = {
.is_idle = uvd_v5_0_is_idle,
.wait_for_idle = uvd_v5_0_wait_for_idle,
.soft_reset = uvd_v5_0_soft_reset,
- .print_status = uvd_v5_0_print_status,
.set_clockgating_state = uvd_v5_0_set_clockgating_state,
.set_powergating_state = uvd_v5_0_set_powergating_state,
};
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
index 7e7c3da..5665a4f 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
@@ -706,112 +706,6 @@ static int uvd_v6_0_soft_reset(void *handle)
return uvd_v6_0_start(adev);
}
-static void uvd_v6_0_print_status(void *handle)
-{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- dev_info(adev->dev, "UVD 6.0 registers\n");
- dev_info(adev->dev, " UVD_SEMA_ADDR_LOW=0x%08X\n",
- RREG32(mmUVD_SEMA_ADDR_LOW));
- dev_info(adev->dev, " UVD_SEMA_ADDR_HIGH=0x%08X\n",
- RREG32(mmUVD_SEMA_ADDR_HIGH));
- dev_info(adev->dev, " UVD_SEMA_CMD=0x%08X\n",
- RREG32(mmUVD_SEMA_CMD));
- dev_info(adev->dev, " UVD_GPCOM_VCPU_CMD=0x%08X\n",
- RREG32(mmUVD_GPCOM_VCPU_CMD));
- dev_info(adev->dev, " UVD_GPCOM_VCPU_DATA0=0x%08X\n",
- RREG32(mmUVD_GPCOM_VCPU_DATA0));
- dev_info(adev->dev, " UVD_GPCOM_VCPU_DATA1=0x%08X\n",
- RREG32(mmUVD_GPCOM_VCPU_DATA1));
- dev_info(adev->dev, " UVD_ENGINE_CNTL=0x%08X\n",
- RREG32(mmUVD_ENGINE_CNTL));
- dev_info(adev->dev, " UVD_UDEC_ADDR_CONFIG=0x%08X\n",
- RREG32(mmUVD_UDEC_ADDR_CONFIG));
- dev_info(adev->dev, " UVD_UDEC_DB_ADDR_CONFIG=0x%08X\n",
- RREG32(mmUVD_UDEC_DB_ADDR_CONFIG));
- dev_info(adev->dev, " UVD_UDEC_DBW_ADDR_CONFIG=0x%08X\n",
- RREG32(mmUVD_UDEC_DBW_ADDR_CONFIG));
- dev_info(adev->dev, " UVD_SEMA_CNTL=0x%08X\n",
- RREG32(mmUVD_SEMA_CNTL));
- dev_info(adev->dev, " UVD_LMI_EXT40_ADDR=0x%08X\n",
- RREG32(mmUVD_LMI_EXT40_ADDR));
- dev_info(adev->dev, " UVD_CTX_INDEX=0x%08X\n",
- RREG32(mmUVD_CTX_INDEX));
- dev_info(adev->dev, " UVD_CTX_DATA=0x%08X\n",
- RREG32(mmUVD_CTX_DATA));
- dev_info(adev->dev, " UVD_CGC_GATE=0x%08X\n",
- RREG32(mmUVD_CGC_GATE));
- dev_info(adev->dev, " UVD_CGC_CTRL=0x%08X\n",
- RREG32(mmUVD_CGC_CTRL));
- dev_info(adev->dev, " UVD_LMI_CTRL2=0x%08X\n",
- RREG32(mmUVD_LMI_CTRL2));
- dev_info(adev->dev, " UVD_MASTINT_EN=0x%08X\n",
- RREG32(mmUVD_MASTINT_EN));
- dev_info(adev->dev, " UVD_LMI_ADDR_EXT=0x%08X\n",
- RREG32(mmUVD_LMI_ADDR_EXT));
- dev_info(adev->dev, " UVD_LMI_CTRL=0x%08X\n",
- RREG32(mmUVD_LMI_CTRL));
- dev_info(adev->dev, " UVD_LMI_SWAP_CNTL=0x%08X\n",
- RREG32(mmUVD_LMI_SWAP_CNTL));
- dev_info(adev->dev, " UVD_MP_SWAP_CNTL=0x%08X\n",
- RREG32(mmUVD_MP_SWAP_CNTL));
- dev_info(adev->dev, " UVD_MPC_SET_MUXA0=0x%08X\n",
- RREG32(mmUVD_MPC_SET_MUXA0));
- dev_info(adev->dev, " UVD_MPC_SET_MUXA1=0x%08X\n",
- RREG32(mmUVD_MPC_SET_MUXA1));
- dev_info(adev->dev, " UVD_MPC_SET_MUXB0=0x%08X\n",
- RREG32(mmUVD_MPC_SET_MUXB0));
- dev_info(adev->dev, " UVD_MPC_SET_MUXB1=0x%08X\n",
- RREG32(mmUVD_MPC_SET_MUXB1));
- dev_info(adev->dev, " UVD_MPC_SET_MUX=0x%08X\n",
- RREG32(mmUVD_MPC_SET_MUX));
- dev_info(adev->dev, " UVD_MPC_SET_ALU=0x%08X\n",
- RREG32(mmUVD_MPC_SET_ALU));
- dev_info(adev->dev, " UVD_VCPU_CACHE_OFFSET0=0x%08X\n",
- RREG32(mmUVD_VCPU_CACHE_OFFSET0));
- dev_info(adev->dev, " UVD_VCPU_CACHE_SIZE0=0x%08X\n",
- RREG32(mmUVD_VCPU_CACHE_SIZE0));
- dev_info(adev->dev, " UVD_VCPU_CACHE_OFFSET1=0x%08X\n",
- RREG32(mmUVD_VCPU_CACHE_OFFSET1));
- dev_info(adev->dev, " UVD_VCPU_CACHE_SIZE1=0x%08X\n",
- RREG32(mmUVD_VCPU_CACHE_SIZE1));
- dev_info(adev->dev, " UVD_VCPU_CACHE_OFFSET2=0x%08X\n",
- RREG32(mmUVD_VCPU_CACHE_OFFSET2));
- dev_info(adev->dev, " UVD_VCPU_CACHE_SIZE2=0x%08X\n",
- RREG32(mmUVD_VCPU_CACHE_SIZE2));
- dev_info(adev->dev, " UVD_VCPU_CNTL=0x%08X\n",
- RREG32(mmUVD_VCPU_CNTL));
- dev_info(adev->dev, " UVD_SOFT_RESET=0x%08X\n",
- RREG32(mmUVD_SOFT_RESET));
- dev_info(adev->dev, " UVD_RBC_IB_SIZE=0x%08X\n",
- RREG32(mmUVD_RBC_IB_SIZE));
- dev_info(adev->dev, " UVD_RBC_RB_RPTR=0x%08X\n",
- RREG32(mmUVD_RBC_RB_RPTR));
- dev_info(adev->dev, " UVD_RBC_RB_WPTR=0x%08X\n",
- RREG32(mmUVD_RBC_RB_WPTR));
- dev_info(adev->dev, " UVD_RBC_RB_WPTR_CNTL=0x%08X\n",
- RREG32(mmUVD_RBC_RB_WPTR_CNTL));
- dev_info(adev->dev, " UVD_RBC_RB_CNTL=0x%08X\n",
- RREG32(mmUVD_RBC_RB_CNTL));
- dev_info(adev->dev, " UVD_STATUS=0x%08X\n",
- RREG32(mmUVD_STATUS));
- dev_info(adev->dev, " UVD_SEMA_TIMEOUT_STATUS=0x%08X\n",
- RREG32(mmUVD_SEMA_TIMEOUT_STATUS));
- dev_info(adev->dev, " UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL=0x%08X\n",
- RREG32(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL));
- dev_info(adev->dev, " UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL=0x%08X\n",
- RREG32(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL));
- dev_info(adev->dev, " UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL=0x%08X\n",
- RREG32(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL));
- dev_info(adev->dev, " UVD_CONTEXT_ID=0x%08X\n",
- RREG32(mmUVD_CONTEXT_ID));
- dev_info(adev->dev, " UVD_UDEC_ADDR_CONFIG=0x%08X\n",
- RREG32(mmUVD_UDEC_ADDR_CONFIG));
- dev_info(adev->dev, " UVD_UDEC_DB_ADDR_CONFIG=0x%08X\n",
- RREG32(mmUVD_UDEC_DB_ADDR_CONFIG));
- dev_info(adev->dev, " UVD_UDEC_DBW_ADDR_CONFIG=0x%08X\n",
- RREG32(mmUVD_UDEC_DBW_ADDR_CONFIG));
-}
-
static int uvd_v6_0_set_interrupt_state(struct amdgpu_device *adev,
struct amdgpu_irq_src *source,
unsigned type,
@@ -993,7 +887,6 @@ const struct amd_ip_funcs uvd_v6_0_ip_funcs = {
.is_idle = uvd_v6_0_is_idle,
.wait_for_idle = uvd_v6_0_wait_for_idle,
.soft_reset = uvd_v6_0_soft_reset,
- .print_status = uvd_v6_0_print_status,
.set_clockgating_state = uvd_v6_0_set_clockgating_state,
.set_powergating_state = uvd_v6_0_set_powergating_state,
};
diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
index ab9ee2a..95f6e57 100644
--- a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
@@ -495,75 +495,6 @@ static int vce_v2_0_soft_reset(void *handle)
return vce_v2_0_start(adev);
}
-static void vce_v2_0_print_status(void *handle)
-{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-
- dev_info(adev->dev, "VCE 2.0 registers\n");
- dev_info(adev->dev, " VCE_STATUS=0x%08X\n",
- RREG32(mmVCE_STATUS));
- dev_info(adev->dev, " VCE_VCPU_CNTL=0x%08X\n",
- RREG32(mmVCE_VCPU_CNTL));
- dev_info(adev->dev, " VCE_VCPU_CACHE_OFFSET0=0x%08X\n",
- RREG32(mmVCE_VCPU_CACHE_OFFSET0));
- dev_info(adev->dev, " VCE_VCPU_CACHE_SIZE0=0x%08X\n",
- RREG32(mmVCE_VCPU_CACHE_SIZE0));
- dev_info(adev->dev, " VCE_VCPU_CACHE_OFFSET1=0x%08X\n",
- RREG32(mmVCE_VCPU_CACHE_OFFSET1));
- dev_info(adev->dev, " VCE_VCPU_CACHE_SIZE1=0x%08X\n",
- RREG32(mmVCE_VCPU_CACHE_SIZE1));
- dev_info(adev->dev, " VCE_VCPU_CACHE_OFFSET2=0x%08X\n",
- RREG32(mmVCE_VCPU_CACHE_OFFSET2));
- dev_info(adev->dev, " VCE_VCPU_CACHE_SIZE2=0x%08X\n",
- RREG32(mmVCE_VCPU_CACHE_SIZE2));
- dev_info(adev->dev, " VCE_SOFT_RESET=0x%08X\n",
- RREG32(mmVCE_SOFT_RESET));
- dev_info(adev->dev, " VCE_RB_BASE_LO2=0x%08X\n",
- RREG32(mmVCE_RB_BASE_LO2));
- dev_info(adev->dev, " VCE_RB_BASE_HI2=0x%08X\n",
- RREG32(mmVCE_RB_BASE_HI2));
- dev_info(adev->dev, " VCE_RB_SIZE2=0x%08X\n",
- RREG32(mmVCE_RB_SIZE2));
- dev_info(adev->dev, " VCE_RB_RPTR2=0x%08X\n",
- RREG32(mmVCE_RB_RPTR2));
- dev_info(adev->dev, " VCE_RB_WPTR2=0x%08X\n",
- RREG32(mmVCE_RB_WPTR2));
- dev_info(adev->dev, " VCE_RB_BASE_LO=0x%08X\n",
- RREG32(mmVCE_RB_BASE_LO));
- dev_info(adev->dev, " VCE_RB_BASE_HI=0x%08X\n",
- RREG32(mmVCE_RB_BASE_HI));
- dev_info(adev->dev, " VCE_RB_SIZE=0x%08X\n",
- RREG32(mmVCE_RB_SIZE));
- dev_info(adev->dev, " VCE_RB_RPTR=0x%08X\n",
- RREG32(mmVCE_RB_RPTR));
- dev_info(adev->dev, " VCE_RB_WPTR=0x%08X\n",
- RREG32(mmVCE_RB_WPTR));
- dev_info(adev->dev, " VCE_CLOCK_GATING_A=0x%08X\n",
- RREG32(mmVCE_CLOCK_GATING_A));
- dev_info(adev->dev, " VCE_CLOCK_GATING_B=0x%08X\n",
- RREG32(mmVCE_CLOCK_GATING_B));
- dev_info(adev->dev, " VCE_CGTT_CLK_OVERRIDE=0x%08X\n",
- RREG32(mmVCE_CGTT_CLK_OVERRIDE));
- dev_info(adev->dev, " VCE_UENC_CLOCK_GATING=0x%08X\n",
- RREG32(mmVCE_UENC_CLOCK_GATING));
- dev_info(adev->dev, " VCE_UENC_REG_CLOCK_GATING=0x%08X\n",
- RREG32(mmVCE_UENC_REG_CLOCK_GATING));
- dev_info(adev->dev, " VCE_SYS_INT_EN=0x%08X\n",
- RREG32(mmVCE_SYS_INT_EN));
- dev_info(adev->dev, " VCE_LMI_CTRL2=0x%08X\n",
- RREG32(mmVCE_LMI_CTRL2));
- dev_info(adev->dev, " VCE_LMI_CTRL=0x%08X\n",
- RREG32(mmVCE_LMI_CTRL));
- dev_info(adev->dev, " VCE_LMI_VM_CTRL=0x%08X\n",
- RREG32(mmVCE_LMI_VM_CTRL));
- dev_info(adev->dev, " VCE_LMI_SWAP_CNTL=0x%08X\n",
- RREG32(mmVCE_LMI_SWAP_CNTL));
- dev_info(adev->dev, " VCE_LMI_SWAP_CNTL1=0x%08X\n",
- RREG32(mmVCE_LMI_SWAP_CNTL1));
- dev_info(adev->dev, " VCE_LMI_CACHE_CTRL=0x%08X\n",
- RREG32(mmVCE_LMI_CACHE_CTRL));
-}
-
static int vce_v2_0_set_interrupt_state(struct amdgpu_device *adev,
struct amdgpu_irq_src *source,
unsigned type,
@@ -647,7 +578,6 @@ const struct amd_ip_funcs vce_v2_0_ip_funcs = {
.is_idle = vce_v2_0_is_idle,
.wait_for_idle = vce_v2_0_wait_for_idle,
.soft_reset = vce_v2_0_soft_reset,
- .print_status = vce_v2_0_print_status,
.set_clockgating_state = vce_v2_0_set_clockgating_state,
.set_powergating_state = vce_v2_0_set_powergating_state,
};
diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
index 5834285..e1d6ae7 100644
--- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
@@ -566,73 +566,6 @@ static int vce_v3_0_soft_reset(void *handle)
return vce_v3_0_start(adev);
}
-static void vce_v3_0_print_status(void *handle)
-{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-
- dev_info(adev->dev, "VCE 3.0 registers\n");
- dev_info(adev->dev, " VCE_STATUS=0x%08X\n",
- RREG32(mmVCE_STATUS));
- dev_info(adev->dev, " VCE_VCPU_CNTL=0x%08X\n",
- RREG32(mmVCE_VCPU_CNTL));
- dev_info(adev->dev, " VCE_VCPU_CACHE_OFFSET0=0x%08X\n",
- RREG32(mmVCE_VCPU_CACHE_OFFSET0));
- dev_info(adev->dev, " VCE_VCPU_CACHE_SIZE0=0x%08X\n",
- RREG32(mmVCE_VCPU_CACHE_SIZE0));
- dev_info(adev->dev, " VCE_VCPU_CACHE_OFFSET1=0x%08X\n",
- RREG32(mmVCE_VCPU_CACHE_OFFSET1));
- dev_info(adev->dev, " VCE_VCPU_CACHE_SIZE1=0x%08X\n",
- RREG32(mmVCE_VCPU_CACHE_SIZE1));
- dev_info(adev->dev, " VCE_VCPU_CACHE_OFFSET2=0x%08X\n",
- RREG32(mmVCE_VCPU_CACHE_OFFSET2));
- dev_info(adev->dev, " VCE_VCPU_CACHE_SIZE2=0x%08X\n",
- RREG32(mmVCE_VCPU_CACHE_SIZE2));
- dev_info(adev->dev, " VCE_SOFT_RESET=0x%08X\n",
- RREG32(mmVCE_SOFT_RESET));
- dev_info(adev->dev, " VCE_RB_BASE_LO2=0x%08X\n",
- RREG32(mmVCE_RB_BASE_LO2));
- dev_info(adev->dev, " VCE_RB_BASE_HI2=0x%08X\n",
- RREG32(mmVCE_RB_BASE_HI2));
- dev_info(adev->dev, " VCE_RB_SIZE2=0x%08X\n",
- RREG32(mmVCE_RB_SIZE2));
- dev_info(adev->dev, " VCE_RB_RPTR2=0x%08X\n",
- RREG32(mmVCE_RB_RPTR2));
- dev_info(adev->dev, " VCE_RB_WPTR2=0x%08X\n",
- RREG32(mmVCE_RB_WPTR2));
- dev_info(adev->dev, " VCE_RB_BASE_LO=0x%08X\n",
- RREG32(mmVCE_RB_BASE_LO));
- dev_info(adev->dev, " VCE_RB_BASE_HI=0x%08X\n",
- RREG32(mmVCE_RB_BASE_HI));
- dev_info(adev->dev, " VCE_RB_SIZE=0x%08X\n",
- RREG32(mmVCE_RB_SIZE));
- dev_info(adev->dev, " VCE_RB_RPTR=0x%08X\n",
- RREG32(mmVCE_RB_RPTR));
- dev_info(adev->dev, " VCE_RB_WPTR=0x%08X\n",
- RREG32(mmVCE_RB_WPTR));
- dev_info(adev->dev, " VCE_CLOCK_GATING_A=0x%08X\n",
- RREG32(mmVCE_CLOCK_GATING_A));
- dev_info(adev->dev, " VCE_CLOCK_GATING_B=0x%08X\n",
- RREG32(mmVCE_CLOCK_GATING_B));
- dev_info(adev->dev, " VCE_UENC_CLOCK_GATING=0x%08X\n",
- RREG32(mmVCE_UENC_CLOCK_GATING));
- dev_info(adev->dev, " VCE_UENC_REG_CLOCK_GATING=0x%08X\n",
- RREG32(mmVCE_UENC_REG_CLOCK_GATING));
- dev_info(adev->dev, " VCE_SYS_INT_EN=0x%08X\n",
- RREG32(mmVCE_SYS_INT_EN));
- dev_info(adev->dev, " VCE_LMI_CTRL2=0x%08X\n",
- RREG32(mmVCE_LMI_CTRL2));
- dev_info(adev->dev, " VCE_LMI_CTRL=0x%08X\n",
- RREG32(mmVCE_LMI_CTRL));
- dev_info(adev->dev, " VCE_LMI_VM_CTRL=0x%08X\n",
- RREG32(mmVCE_LMI_VM_CTRL));
- dev_info(adev->dev, " VCE_LMI_SWAP_CNTL=0x%08X\n",
- RREG32(mmVCE_LMI_SWAP_CNTL));
- dev_info(adev->dev, " VCE_LMI_SWAP_CNTL1=0x%08X\n",
- RREG32(mmVCE_LMI_SWAP_CNTL1));
- dev_info(adev->dev, " VCE_LMI_CACHE_CTRL=0x%08X\n",
- RREG32(mmVCE_LMI_CACHE_CTRL));
-}
-
static int vce_v3_0_set_interrupt_state(struct amdgpu_device *adev,
struct amdgpu_irq_src *source,
unsigned type,
@@ -752,7 +685,6 @@ const struct amd_ip_funcs vce_v3_0_ip_funcs = {
.is_idle = vce_v3_0_is_idle,
.wait_for_idle = vce_v3_0_wait_for_idle,
.soft_reset = vce_v3_0_soft_reset,
- .print_status = vce_v3_0_print_status,
.set_clockgating_state = vce_v3_0_set_clockgating_state,
.set_powergating_state = vce_v3_0_set_powergating_state,
};
diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
index 0bd567d..340a166 100644
--- a/drivers/gpu/drm/amd/amdgpu/vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
@@ -1295,11 +1295,6 @@ static int vi_common_wait_for_idle(void *handle)
return 0;
}
-static void vi_common_print_status(void *handle)
-{
- return;
-}
-
static int vi_common_soft_reset(void *handle)
{
return 0;
@@ -1424,7 +1419,6 @@ const struct amd_ip_funcs vi_common_ip_funcs = {
.is_idle = vi_common_is_idle,
.wait_for_idle = vi_common_wait_for_idle,
.soft_reset = vi_common_soft_reset,
- .print_status = vi_common_print_status,
.set_clockgating_state = vi_common_set_clockgating_state,
.set_powergating_state = vi_common_set_powergating_state,
};
diff --git a/drivers/gpu/drm/amd/include/amd_shared.h b/drivers/gpu/drm/amd/include/amd_shared.h
index e56d8a3..ea9ee46 100644
--- a/drivers/gpu/drm/amd/include/amd_shared.h
+++ b/drivers/gpu/drm/amd/include/amd_shared.h
@@ -165,8 +165,6 @@ struct amd_ip_funcs {
int (*wait_for_idle)(void *handle);
/* soft reset the IP block */
int (*soft_reset)(void *handle);
- /* dump the IP block status registers */
- void (*print_status)(void *handle);
/* enable/disable cg for the IP block */
int (*set_clockgating_state)(void *handle,
enum amd_clockgating_state state);
diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
index 0527ae3..aba587c 100644
--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
@@ -180,10 +180,6 @@ static int pp_sw_reset(void *handle)
return 0;
}
-static void pp_print_status(void *handle)
-{
-
-}
static int pp_set_clockgating_state(void *handle,
enum amd_clockgating_state state)
@@ -355,7 +351,6 @@ const struct amd_ip_funcs pp_ip_funcs = {
.is_idle = pp_is_idle,
.wait_for_idle = pp_wait_for_idle,
.soft_reset = pp_sw_reset,
- .print_status = pp_print_status,
.set_clockgating_state = pp_set_clockgating_state,
.set_powergating_state = pp_set_powergating_state,
};
--
2.5.5
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^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH] drm/amd/amdgpu: Add debugfs entries for smc/didt/pcie
2016-05-02 20:00 Misc amdgpu patches Alex Deucher
` (41 preceding siblings ...)
2016-05-02 20:00 ` [PATCH] drm/amd/amdgpu: Drop print_status callbacks Alex Deucher
@ 2016-05-02 20:00 ` Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/powerplay: add missing clockgating callback for tonga Alex Deucher
` (2 subsequent siblings)
45 siblings, 0 replies; 47+ messages in thread
From: Alex Deucher @ 2016-05-02 20:00 UTC (permalink / raw)
To: dri-devel; +Cc: Tom St Denis, Alex Deucher
From: Tom St Denis <tom.stdenis@amd.com>
This adds 3 new files that can be read/written to access
indirect GPU registers.
Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 230 ++++++++++++++++++++++++++++-
2 files changed, 223 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 6cc174f..1012bd3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1953,7 +1953,7 @@ struct amdgpu_device {
struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
unsigned debugfs_count;
#if defined(CONFIG_DEBUG_FS)
- struct dentry *debugfs_regs;
+ struct dentry *debugfs_regs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
#endif
struct amdgpu_atif atif;
struct amdgpu_atcs atcs;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 14e832f..8f037e5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2134,32 +2134,246 @@ static ssize_t amdgpu_debugfs_regs_write(struct file *f, const char __user *buf,
return result;
}
+static ssize_t amdgpu_debugfs_regs_pcie_read(struct file *f, char __user *buf,
+ size_t size, loff_t *pos)
+{
+ struct amdgpu_device *adev = f->f_inode->i_private;
+ ssize_t result = 0;
+ int r;
+
+ if (size & 0x3 || *pos & 0x3)
+ return -EINVAL;
+
+ while (size) {
+ uint32_t value;
+
+ value = RREG32_PCIE(*pos >> 2);
+ r = put_user(value, (uint32_t *)buf);
+ if (r)
+ return r;
+
+ result += 4;
+ buf += 4;
+ *pos += 4;
+ size -= 4;
+ }
+
+ return result;
+}
+
+static ssize_t amdgpu_debugfs_regs_pcie_write(struct file *f, const char __user *buf,
+ size_t size, loff_t *pos)
+{
+ struct amdgpu_device *adev = f->f_inode->i_private;
+ ssize_t result = 0;
+ int r;
+
+ if (size & 0x3 || *pos & 0x3)
+ return -EINVAL;
+
+ while (size) {
+ uint32_t value;
+
+ r = get_user(value, (uint32_t *)buf);
+ if (r)
+ return r;
+
+ WREG32_PCIE(*pos >> 2, value);
+
+ result += 4;
+ buf += 4;
+ *pos += 4;
+ size -= 4;
+ }
+
+ return result;
+}
+
+static ssize_t amdgpu_debugfs_regs_didt_read(struct file *f, char __user *buf,
+ size_t size, loff_t *pos)
+{
+ struct amdgpu_device *adev = f->f_inode->i_private;
+ ssize_t result = 0;
+ int r;
+
+ if (size & 0x3 || *pos & 0x3)
+ return -EINVAL;
+
+ while (size) {
+ uint32_t value;
+
+ value = RREG32_DIDT(*pos >> 2);
+ r = put_user(value, (uint32_t *)buf);
+ if (r)
+ return r;
+
+ result += 4;
+ buf += 4;
+ *pos += 4;
+ size -= 4;
+ }
+
+ return result;
+}
+
+static ssize_t amdgpu_debugfs_regs_didt_write(struct file *f, const char __user *buf,
+ size_t size, loff_t *pos)
+{
+ struct amdgpu_device *adev = f->f_inode->i_private;
+ ssize_t result = 0;
+ int r;
+
+ if (size & 0x3 || *pos & 0x3)
+ return -EINVAL;
+
+ while (size) {
+ uint32_t value;
+
+ r = get_user(value, (uint32_t *)buf);
+ if (r)
+ return r;
+
+ WREG32_DIDT(*pos >> 2, value);
+
+ result += 4;
+ buf += 4;
+ *pos += 4;
+ size -= 4;
+ }
+
+ return result;
+}
+
+static ssize_t amdgpu_debugfs_regs_smc_read(struct file *f, char __user *buf,
+ size_t size, loff_t *pos)
+{
+ struct amdgpu_device *adev = f->f_inode->i_private;
+ ssize_t result = 0;
+ int r;
+
+ if (size & 0x3 || *pos & 0x3)
+ return -EINVAL;
+
+ while (size) {
+ uint32_t value;
+
+ value = RREG32_SMC(*pos >> 2);
+ r = put_user(value, (uint32_t *)buf);
+ if (r)
+ return r;
+
+ result += 4;
+ buf += 4;
+ *pos += 4;
+ size -= 4;
+ }
+
+ return result;
+}
+
+static ssize_t amdgpu_debugfs_regs_smc_write(struct file *f, const char __user *buf,
+ size_t size, loff_t *pos)
+{
+ struct amdgpu_device *adev = f->f_inode->i_private;
+ ssize_t result = 0;
+ int r;
+
+ if (size & 0x3 || *pos & 0x3)
+ return -EINVAL;
+
+ while (size) {
+ uint32_t value;
+
+ r = get_user(value, (uint32_t *)buf);
+ if (r)
+ return r;
+
+ WREG32_SMC(*pos >> 2, value);
+
+ result += 4;
+ buf += 4;
+ *pos += 4;
+ size -= 4;
+ }
+
+ return result;
+}
+
static const struct file_operations amdgpu_debugfs_regs_fops = {
.owner = THIS_MODULE,
.read = amdgpu_debugfs_regs_read,
.write = amdgpu_debugfs_regs_write,
.llseek = default_llseek
};
+static const struct file_operations amdgpu_debugfs_regs_didt_fops = {
+ .owner = THIS_MODULE,
+ .read = amdgpu_debugfs_regs_didt_read,
+ .write = amdgpu_debugfs_regs_didt_write,
+ .llseek = default_llseek
+};
+static const struct file_operations amdgpu_debugfs_regs_pcie_fops = {
+ .owner = THIS_MODULE,
+ .read = amdgpu_debugfs_regs_pcie_read,
+ .write = amdgpu_debugfs_regs_pcie_write,
+ .llseek = default_llseek
+};
+static const struct file_operations amdgpu_debugfs_regs_smc_fops = {
+ .owner = THIS_MODULE,
+ .read = amdgpu_debugfs_regs_smc_read,
+ .write = amdgpu_debugfs_regs_smc_write,
+ .llseek = default_llseek
+};
+
+static const struct file_operations *debugfs_regs[] = {
+ &amdgpu_debugfs_regs_fops,
+ &amdgpu_debugfs_regs_didt_fops,
+ &amdgpu_debugfs_regs_pcie_fops,
+ &amdgpu_debugfs_regs_smc_fops,
+};
+
+static const char *debugfs_regs_names[] = {
+ "amdgpu_regs",
+ "amdgpu_regs_didt",
+ "amdgpu_regs_pcie",
+ "amdgpu_regs_smc",
+};
static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev)
{
struct drm_minor *minor = adev->ddev->primary;
struct dentry *ent, *root = minor->debugfs_root;
+ unsigned i, j;
+
+ for (i = 0; i < ARRAY_SIZE(debugfs_regs); i++) {
+ ent = debugfs_create_file(debugfs_regs_names[i],
+ S_IFREG | S_IRUGO, root,
+ adev, debugfs_regs[i]);
+ if (IS_ERR(ent)) {
+ for (j = 0; j < i; j++) {
+ debugfs_remove(adev->debugfs_regs[i]);
+ adev->debugfs_regs[i] = NULL;
+ }
+ return PTR_ERR(ent);
+ }
- ent = debugfs_create_file("amdgpu_regs", S_IFREG | S_IRUGO, root,
- adev, &amdgpu_debugfs_regs_fops);
- if (IS_ERR(ent))
- return PTR_ERR(ent);
- i_size_write(ent->d_inode, adev->rmmio_size);
- adev->debugfs_regs = ent;
+ if (!i)
+ i_size_write(ent->d_inode, adev->rmmio_size);
+ adev->debugfs_regs[i] = ent;
+ }
return 0;
}
static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev)
{
- debugfs_remove(adev->debugfs_regs);
- adev->debugfs_regs = NULL;
+ unsigned i;
+
+ for (i = 0; i < ARRAY_SIZE(debugfs_regs); i++) {
+ if (adev->debugfs_regs[i]) {
+ debugfs_remove(adev->debugfs_regs[i]);
+ adev->debugfs_regs[i] = NULL;
+ }
+ }
}
int amdgpu_debugfs_init(struct drm_minor *minor)
--
2.5.5
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dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH] drm/powerplay: add missing clockgating callback for tonga
2016-05-02 20:00 Misc amdgpu patches Alex Deucher
` (42 preceding siblings ...)
2016-05-02 20:00 ` [PATCH] drm/amd/amdgpu: Add debugfs entries for smc/didt/pcie Alex Deucher
@ 2016-05-02 20:00 ` Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amdgpu/fiji: set UVD CG state when enabling UVD DPM (v2) Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amdgpu/uvd6: add bypass support for fiji (v3) Alex Deucher
45 siblings, 0 replies; 47+ messages in thread
From: Alex Deucher @ 2016-05-02 20:00 UTC (permalink / raw)
To: dri-devel; +Cc: Alex Deucher
Without this clockgating is not enabled.
Reviewed-by: Ken Wang <Qingqing.Wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
index 9aaf194..670b628 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
@@ -6214,6 +6214,7 @@ static const struct pp_hwmgr_func tonga_hwmgr_funcs = {
.powergate_uvd = tonga_phm_powergate_uvd,
.powergate_vce = tonga_phm_powergate_vce,
.disable_clock_power_gating = tonga_phm_disable_clock_power_gating,
+ .update_clock_gatings = tonga_phm_update_clock_gatings,
.notify_smc_display_config_after_ps_adjustment = tonga_notify_smc_display_config_after_ps_adjustment,
.display_config_changed = tonga_display_configuration_changed_task,
.set_max_fan_pwm_output = tonga_set_max_fan_pwm_output,
--
2.5.5
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https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH] drm/amdgpu/fiji: set UVD CG state when enabling UVD DPM (v2)
2016-05-02 20:00 Misc amdgpu patches Alex Deucher
` (43 preceding siblings ...)
2016-05-02 20:00 ` [PATCH] drm/powerplay: add missing clockgating callback for tonga Alex Deucher
@ 2016-05-02 20:00 ` Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amdgpu/uvd6: add bypass support for fiji (v3) Alex Deucher
45 siblings, 0 replies; 47+ messages in thread
From: Alex Deucher @ 2016-05-02 20:00 UTC (permalink / raw)
To: dri-devel; +Cc: Alex Deucher
Need to call the IP cg callbacks.
v2: fix gate logic
Reviewed-by: Eric Huang <JinHuiEric.Huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/powerplay/hwmgr/fiji_clockpowergating.c | 11 +++++++++--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_clockpowergating.c b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_clockpowergating.c
index e68edf0..e1b649b 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_clockpowergating.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_clockpowergating.c
@@ -47,10 +47,17 @@ int fiji_phm_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate)
data->uvd_power_gated = bgate;
- if (bgate)
+ if (bgate) {
+ cgs_set_clockgating_state(hwmgr->device,
+ AMD_IP_BLOCK_TYPE_UVD,
+ AMD_CG_STATE_GATE);
fiji_update_uvd_dpm(hwmgr, true);
- else
+ } else {
fiji_update_uvd_dpm(hwmgr, false);
+ cgs_set_clockgating_state(hwmgr->device,
+ AMD_IP_BLOCK_TYPE_UVD,
+ AMD_PG_STATE_UNGATE);
+ }
return 0;
}
--
2.5.5
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https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH] drm/amdgpu/uvd6: add bypass support for fiji (v3)
2016-05-02 20:00 Misc amdgpu patches Alex Deucher
` (44 preceding siblings ...)
2016-05-02 20:00 ` [PATCH] drm/amdgpu/fiji: set UVD CG state when enabling UVD DPM (v2) Alex Deucher
@ 2016-05-02 20:00 ` Alex Deucher
45 siblings, 0 replies; 47+ messages in thread
From: Alex Deucher @ 2016-05-02 20:00 UTC (permalink / raw)
To: dri-devel; +Cc: Alex Deucher
Handle uvd clock bypass settings as part of clockgating
setup.
v2: fix gate logic
v3: fix header include
Reviewed-by: Eric Huang <JinHuiEric.Huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
index 5665a4f..d015cb0 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
@@ -31,6 +31,8 @@
#include "uvd/uvd_6_0_sh_mask.h"
#include "oss/oss_2_0_d.h"
#include "oss/oss_2_0_sh_mask.h"
+#include "smu/smu_7_1_3_d.h"
+#include "smu/smu_7_1_3_sh_mask.h"
#include "vi.h"
static void uvd_v6_0_set_ring_funcs(struct amdgpu_device *adev);
@@ -823,6 +825,20 @@ static void uvd_v6_0_set_hw_clock_gating(struct amdgpu_device *adev)
}
#endif
+static void uvd_v6_set_bypass_mode(struct amdgpu_device *adev, bool enable)
+{
+ u32 tmp = RREG32_SMC(ixGCK_DFS_BYPASS_CNTL);
+
+ if (enable)
+ tmp |= (GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK |
+ GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK);
+ else
+ tmp &= ~(GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK |
+ GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK);
+
+ WREG32_SMC(ixGCK_DFS_BYPASS_CNTL, tmp);
+}
+
static int uvd_v6_0_set_clockgating_state(void *handle,
enum amd_clockgating_state state)
{
@@ -830,6 +846,9 @@ static int uvd_v6_0_set_clockgating_state(void *handle,
bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
static int curstate = -1;
+ if (adev->asic_type == CHIP_FIJI)
+ uvd_v6_set_bypass_mode(adev, enable);
+
if (!(adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG))
return 0;
--
2.5.5
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https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 47+ messages in thread
end of thread, other threads:[~2016-05-02 20:01 UTC | newest]
Thread overview: 47+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2016-05-02 20:00 Misc amdgpu patches Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amdgpu/dce11: fix vertical bars appear on monitor Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amd/amdgpu: Add SW clock gating support to UVD 5 and 6 Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amd/amdgpu: Enable clockgating for UVD5 on Tonga Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amd/amdgpu: Enable clockgating in UVD6 for Stoney Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amd/powerplay: use min_clock_in_sr for deep sleep feature Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amdgpu: Set PFLIP_SUBMITTED for crtc after address update Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amdgpu: add new CG flag for ROM clockgating Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amdgpu/gfx: add proper CG flags for fiji Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amdgpu/sdma: " Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amdgpu/common: " Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amdgpu/gmc: " Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amdgpu/gfx8: rename send_serdes_cmd Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amdgpu/gfx: adjust gfx_v8_0_send_serdes_cmd for ST Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amdgpu: add a new set of rlc function pointers Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amdgpu/gfx: rework fiji cg functions so they can be shared Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amdgpu: enable gfx clockgating for CZ Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amdgpu: enable gfx clockgating for ST (v2) Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amdgpu/vi: rename fiji cg functions Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amdgpu: enable gmc clockgating for CZ Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amdgpu: enable gmc clockgating for ST Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amdgpu/sdma: rename fiji cg functions Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amdgpu: enable sdma clockgating on CZ Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amdgpu: enable sdma clockgating on ST Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amdgpu: add ELM/BAF DCE11 configs (v2) Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amdgpu: add ELM/BAF support to dce_v11_0_pick_pll (v2) Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amd/powerplay: enable some feature for baffin/ellesmere. (v2) Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amd/powerplay: add fan control mode interface for baffin Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amd/powerplay: parameter updates according to SMC Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amd/powerplay: fix issue that get wrong reference clock value Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amd/powerplay: Fix a bug for enabling ACDC gpio interrupt Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amd/powerplay: update vce power gate state for baffin Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amdgpu: fix memory leak in CGS (FW info) Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amd/powerplay: return 0 when interface not implement on some asic Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amd/powerplay: fix some initialize error on polaris10 Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amd/powerplay: fix bug dpm can't work when resume back on Polaris Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amd/powerplay: fix fan speed percent setting error on Polaris10 Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amd/powerplay: add dpm force multiple levels on cz/tonga/fiji/polaris (v2) Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amd/powerplay: revise caching the soft pptable and add it's size Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amd/powerplay: revise reading/writing pptable on Fiji Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amd/powerplay: revise reading/writing pptable on Tonga Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amd/powerplay: revise reading/writing pptable on Polaris10 Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amd/amdgpu: Drop print_status callbacks Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amd/amdgpu: Add debugfs entries for smc/didt/pcie Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/powerplay: add missing clockgating callback for tonga Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amdgpu/fiji: set UVD CG state when enabling UVD DPM (v2) Alex Deucher
2016-05-02 20:00 ` [PATCH] drm/amdgpu/uvd6: add bypass support for fiji (v3) Alex Deucher
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