* [PATCH 0/5] Add mclk OD (OverDrive) support
@ 2016-05-25 21:26 Alex Deucher
2016-05-25 21:26 ` [PATCH 1/5] drm/amdgpu: add the common code to support mclk OD Alex Deucher
` (4 more replies)
0 siblings, 5 replies; 6+ messages in thread
From: Alex Deucher @ 2016-05-25 21:26 UTC (permalink / raw)
To: dri-devel; +Cc: Alex Deucher
This patch set adds mclk (memory clock) overclocking support
to amdgpu for dGPUs. The interface is the same as for sclk
(engine clock), a percentage from 0 to 20.
Eric Huang (5):
drm/amdgpu: add the common code to support mclk OD
drm/amdgpu: add mclk OD(overdrive) support for CI
drm/amd/powerplay: add mclk OD(overdrive) support for Tonga
drm/amd/powerplay: add mclk OD(overdrive) support for Fiji
drm/amd/powerplay: add mclk OD(overdrive) support for Polaris10
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 8 ++++
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 55 ++++++++++++++++++++++
drivers/gpu/drm/amd/amdgpu/ci_dpm.c | 36 ++++++++++++++
drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 40 ++++++++++++++++
drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c | 44 +++++++++++++++++
.../gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c | 43 +++++++++++++++++
drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c | 44 +++++++++++++++++
drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h | 2 +
drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 2 +
9 files changed, 274 insertions(+)
--
2.5.5
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^ permalink raw reply [flat|nested] 6+ messages in thread* [PATCH 1/5] drm/amdgpu: add the common code to support mclk OD 2016-05-25 21:26 [PATCH 0/5] Add mclk OD (OverDrive) support Alex Deucher @ 2016-05-25 21:26 ` Alex Deucher 2016-05-25 21:26 ` [PATCH 2/5] drm/amdgpu: add mclk OD(overdrive) support for CI Alex Deucher ` (3 subsequent siblings) 4 siblings, 0 replies; 6+ messages in thread From: Alex Deucher @ 2016-05-25 21:26 UTC (permalink / raw) To: dri-devel; +Cc: Eric Huang, Alex Deucher From: Eric Huang <JinHuiEric.Huang@amd.com> This implements mclk OverDrive(OD) through sysfs. The new entry pp_mclk_od is read/write. The value of input/output is an integer of the overclocking percentage. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 8 ++++ drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 55 +++++++++++++++++++++++ drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 40 +++++++++++++++++ drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h | 2 + drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 2 + 5 files changed, 107 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index bfc994bc..ab122cc4 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -1563,6 +1563,8 @@ struct amdgpu_dpm_funcs { int (*print_clock_levels)(struct amdgpu_device *adev, enum pp_clock_type type, char *buf); int (*get_sclk_od)(struct amdgpu_device *adev); int (*set_sclk_od)(struct amdgpu_device *adev, uint32_t value); + int (*get_mclk_od)(struct amdgpu_device *adev); + int (*set_mclk_od)(struct amdgpu_device *adev, uint32_t value); }; struct amdgpu_dpm { @@ -2344,6 +2346,12 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring) #define amdgpu_dpm_set_sclk_od(adev, value) \ (adev)->powerplay.pp_funcs->set_sclk_od((adev)->powerplay.pp_handle, value) +#define amdgpu_dpm_get_mclk_od(adev) \ + ((adev)->powerplay.pp_funcs->get_mclk_od((adev)->powerplay.pp_handle)) + +#define amdgpu_dpm_set_mclk_od(adev, value) \ + ((adev)->powerplay.pp_funcs->set_mclk_od((adev)->powerplay.pp_handle, value)) + #define amdgpu_dpm_dispatch_task(adev, event_id, input, output) \ (adev)->powerplay.pp_funcs->dispatch_tasks((adev)->powerplay.pp_handle, (event_id), (input), (output)) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c index ebb99fd..7f84154 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c @@ -529,6 +529,52 @@ fail: return count; } +static ssize_t amdgpu_get_pp_mclk_od(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct drm_device *ddev = dev_get_drvdata(dev); + struct amdgpu_device *adev = ddev->dev_private; + uint32_t value = 0; + + if (adev->pp_enabled) + value = amdgpu_dpm_get_mclk_od(adev); + else if (adev->pm.funcs->get_mclk_od) + value = adev->pm.funcs->get_mclk_od(adev); + + return snprintf(buf, PAGE_SIZE, "%d\n", value); +} + +static ssize_t amdgpu_set_pp_mclk_od(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t count) +{ + struct drm_device *ddev = dev_get_drvdata(dev); + struct amdgpu_device *adev = ddev->dev_private; + int ret; + long int value; + + ret = kstrtol(buf, 0, &value); + + if (ret) { + count = -EINVAL; + goto fail; + } + + if (adev->pp_enabled) { + amdgpu_dpm_set_mclk_od(adev, (uint32_t)value); + amdgpu_dpm_dispatch_task(adev, AMD_PP_EVENT_READJUST_POWER_STATE, NULL, NULL); + } else if (adev->pm.funcs->set_mclk_od) { + adev->pm.funcs->set_mclk_od(adev, (uint32_t)value); + adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps; + amdgpu_pm_compute_clocks(adev); + } + +fail: + return count; +} + static DEVICE_ATTR(power_dpm_state, S_IRUGO | S_IWUSR, amdgpu_get_dpm_state, amdgpu_set_dpm_state); static DEVICE_ATTR(power_dpm_force_performance_level, S_IRUGO | S_IWUSR, amdgpu_get_dpm_forced_performance_level, @@ -553,6 +599,9 @@ static DEVICE_ATTR(pp_dpm_pcie, S_IRUGO | S_IWUSR, static DEVICE_ATTR(pp_sclk_od, S_IRUGO | S_IWUSR, amdgpu_get_pp_sclk_od, amdgpu_set_pp_sclk_od); +static DEVICE_ATTR(pp_mclk_od, S_IRUGO | S_IWUSR, + amdgpu_get_pp_mclk_od, + amdgpu_set_pp_mclk_od); static ssize_t amdgpu_hwmon_show_temp(struct device *dev, struct device_attribute *attr, @@ -1193,6 +1242,11 @@ int amdgpu_pm_sysfs_init(struct amdgpu_device *adev) DRM_ERROR("failed to create device file pp_sclk_od\n"); return ret; } + ret = device_create_file(adev->dev, &dev_attr_pp_mclk_od); + if (ret) { + DRM_ERROR("failed to create device file pp_mclk_od\n"); + return ret; + } ret = amdgpu_debugfs_pm_init(adev); if (ret) { @@ -1221,6 +1275,7 @@ void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev) device_remove_file(adev->dev, &dev_attr_pp_dpm_mclk); device_remove_file(adev->dev, &dev_attr_pp_dpm_pcie); device_remove_file(adev->dev, &dev_attr_pp_sclk_od); + device_remove_file(adev->dev, &dev_attr_pp_mclk_od); } void amdgpu_pm_compute_clocks(struct amdgpu_device *adev) diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c index e0f2440..294e029 100644 --- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c +++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c @@ -842,6 +842,44 @@ static int pp_dpm_set_sclk_od(void *handle, uint32_t value) return hwmgr->hwmgr_func->set_sclk_od(hwmgr, value); } +static int pp_dpm_get_mclk_od(void *handle) +{ + struct pp_hwmgr *hwmgr; + + if (!handle) + return -EINVAL; + + hwmgr = ((struct pp_instance *)handle)->hwmgr; + + PP_CHECK_HW(hwmgr); + + if (hwmgr->hwmgr_func->get_mclk_od == NULL) { + printk(KERN_INFO "%s was not implemented.\n", __func__); + return 0; + } + + return hwmgr->hwmgr_func->get_mclk_od(hwmgr); +} + +static int pp_dpm_set_mclk_od(void *handle, uint32_t value) +{ + struct pp_hwmgr *hwmgr; + + if (!handle) + return -EINVAL; + + hwmgr = ((struct pp_instance *)handle)->hwmgr; + + PP_CHECK_HW(hwmgr); + + if (hwmgr->hwmgr_func->set_mclk_od == NULL) { + printk(KERN_INFO "%s was not implemented.\n", __func__); + return 0; + } + + return hwmgr->hwmgr_func->set_mclk_od(hwmgr, value); +} + const struct amd_powerplay_funcs pp_dpm_funcs = { .get_temperature = pp_dpm_get_temperature, .load_firmware = pp_dpm_load_fw, @@ -866,6 +904,8 @@ const struct amd_powerplay_funcs pp_dpm_funcs = { .print_clock_levels = pp_dpm_print_clock_levels, .get_sclk_od = pp_dpm_get_sclk_od, .set_sclk_od = pp_dpm_set_sclk_od, + .get_mclk_od = pp_dpm_get_mclk_od, + .set_mclk_od = pp_dpm_set_mclk_od, }; static int amd_pp_instance_init(struct amd_pp_init *pp_init, diff --git a/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h b/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h index de1d6a8..d0dfaf9 100644 --- a/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h +++ b/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h @@ -345,6 +345,8 @@ struct amd_powerplay_funcs { int (*print_clock_levels)(void *handle, enum pp_clock_type type, char *buf); int (*get_sclk_od)(void *handle); int (*set_sclk_od)(void *handle, uint32_t value); + int (*get_mclk_od)(void *handle); + int (*set_mclk_od)(void *handle, uint32_t value); }; struct amd_powerplay { diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h index 3d9a413c..bcb224b 100644 --- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h +++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h @@ -340,6 +340,8 @@ struct pp_hwmgr_func { int (*enable_per_cu_power_gating)(struct pp_hwmgr *hwmgr, bool enable); int (*get_sclk_od)(struct pp_hwmgr *hwmgr); int (*set_sclk_od)(struct pp_hwmgr *hwmgr, uint32_t value); + int (*get_mclk_od)(struct pp_hwmgr *hwmgr); + int (*set_mclk_od)(struct pp_hwmgr *hwmgr, uint32_t value); }; struct pp_table_func { -- 2.5.5 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 2/5] drm/amdgpu: add mclk OD(overdrive) support for CI 2016-05-25 21:26 [PATCH 0/5] Add mclk OD (OverDrive) support Alex Deucher 2016-05-25 21:26 ` [PATCH 1/5] drm/amdgpu: add the common code to support mclk OD Alex Deucher @ 2016-05-25 21:26 ` Alex Deucher 2016-05-25 21:26 ` [PATCH 3/5] drm/amd/powerplay: add mclk OD(overdrive) support for Tonga Alex Deucher ` (2 subsequent siblings) 4 siblings, 0 replies; 6+ messages in thread From: Alex Deucher @ 2016-05-25 21:26 UTC (permalink / raw) To: dri-devel; +Cc: Eric Huang, Alex Deucher From: Eric Huang <JinHuiEric.Huang@amd.com> The maximum OD percentage is 20. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> --- drivers/gpu/drm/amd/amdgpu/ci_dpm.c | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c index fb968dd..671d032 100644 --- a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c +++ b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c @@ -6551,6 +6551,40 @@ static int ci_dpm_set_sclk_od(struct amdgpu_device *adev, uint32_t value) return 0; } +static int ci_dpm_get_mclk_od(struct amdgpu_device *adev) +{ + struct ci_power_info *pi = ci_get_pi(adev); + struct ci_single_dpm_table *mclk_table = &(pi->dpm_table.mclk_table); + struct ci_single_dpm_table *golden_mclk_table = + &(pi->golden_dpm_table.mclk_table); + int value; + + value = (mclk_table->dpm_levels[mclk_table->count - 1].value - + golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value) * + 100 / + golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value; + + return value; +} + +static int ci_dpm_set_mclk_od(struct amdgpu_device *adev, uint32_t value) +{ + struct ci_power_info *pi = ci_get_pi(adev); + struct ci_ps *ps = ci_get_ps(adev->pm.dpm.requested_ps); + struct ci_single_dpm_table *golden_mclk_table = + &(pi->golden_dpm_table.mclk_table); + + if (value > 20) + value = 20; + + ps->performance_levels[ps->performance_level_count - 1].mclk = + golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value * + value / 100 + + golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value; + + return 0; +} + const struct amd_ip_funcs ci_dpm_ip_funcs = { .name = "ci_dpm", .early_init = ci_dpm_early_init, @@ -6589,6 +6623,8 @@ static const struct amdgpu_dpm_funcs ci_dpm_funcs = { .force_clock_level = ci_dpm_force_clock_level, .get_sclk_od = ci_dpm_get_sclk_od, .set_sclk_od = ci_dpm_set_sclk_od, + .get_mclk_od = ci_dpm_get_mclk_od, + .set_mclk_od = ci_dpm_set_mclk_od, }; static void ci_dpm_set_dpm_funcs(struct amdgpu_device *adev) -- 2.5.5 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 3/5] drm/amd/powerplay: add mclk OD(overdrive) support for Tonga 2016-05-25 21:26 [PATCH 0/5] Add mclk OD (OverDrive) support Alex Deucher 2016-05-25 21:26 ` [PATCH 1/5] drm/amdgpu: add the common code to support mclk OD Alex Deucher 2016-05-25 21:26 ` [PATCH 2/5] drm/amdgpu: add mclk OD(overdrive) support for CI Alex Deucher @ 2016-05-25 21:26 ` Alex Deucher 2016-05-25 21:26 ` [PATCH 4/5] drm/amd/powerplay: add mclk OD(overdrive) support for Fiji Alex Deucher 2016-05-25 21:26 ` [PATCH 5/5] drm/amd/powerplay: add mclk OD(overdrive) support for Polaris10 Alex Deucher 4 siblings, 0 replies; 6+ messages in thread From: Alex Deucher @ 2016-05-25 21:26 UTC (permalink / raw) To: dri-devel; +Cc: Eric Huang, Alex Deucher From: Eric Huang <JinHuiEric.Huang@amd.com> The maximum OD percentage is 20. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> --- drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c | 44 +++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c index 01bf983..3e50b29 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c @@ -6236,6 +6236,48 @@ static int tonga_set_sclk_od(struct pp_hwmgr *hwmgr, uint32_t value) return 0; } +static int tonga_get_mclk_od(struct pp_hwmgr *hwmgr) +{ + struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend); + struct tonga_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table); + struct tonga_single_dpm_table *golden_mclk_table = + &(data->golden_dpm_table.mclk_table); + int value; + + value = (mclk_table->dpm_levels[mclk_table->count - 1].value - + golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value) * + 100 / + golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value; + + return value; +} + +static int tonga_set_mclk_od(struct pp_hwmgr *hwmgr, uint32_t value) +{ + struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend); + struct tonga_single_dpm_table *golden_mclk_table = + &(data->golden_dpm_table.mclk_table); + struct pp_power_state *ps; + struct tonga_power_state *tonga_ps; + + if (value > 20) + value = 20; + + ps = hwmgr->request_ps; + + if (ps == NULL) + return -EINVAL; + + tonga_ps = cast_phw_tonga_power_state(&ps->hardware); + + tonga_ps->performance_levels[tonga_ps->performance_level_count - 1].memory_clock = + golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value * + value / 100 + + golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value; + + return 0; +} + static const struct pp_hwmgr_func tonga_hwmgr_funcs = { .backend_init = &tonga_hwmgr_backend_init, .backend_fini = &tonga_hwmgr_backend_fini, @@ -6280,6 +6322,8 @@ static const struct pp_hwmgr_func tonga_hwmgr_funcs = { .print_clock_levels = tonga_print_clock_levels, .get_sclk_od = tonga_get_sclk_od, .set_sclk_od = tonga_set_sclk_od, + .get_mclk_od = tonga_get_mclk_od, + .set_mclk_od = tonga_set_mclk_od, }; int tonga_hwmgr_init(struct pp_hwmgr *hwmgr) -- 2.5.5 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 4/5] drm/amd/powerplay: add mclk OD(overdrive) support for Fiji 2016-05-25 21:26 [PATCH 0/5] Add mclk OD (OverDrive) support Alex Deucher ` (2 preceding siblings ...) 2016-05-25 21:26 ` [PATCH 3/5] drm/amd/powerplay: add mclk OD(overdrive) support for Tonga Alex Deucher @ 2016-05-25 21:26 ` Alex Deucher 2016-05-25 21:26 ` [PATCH 5/5] drm/amd/powerplay: add mclk OD(overdrive) support for Polaris10 Alex Deucher 4 siblings, 0 replies; 6+ messages in thread From: Alex Deucher @ 2016-05-25 21:26 UTC (permalink / raw) To: dri-devel; +Cc: Eric Huang, Alex Deucher From: Eric Huang <JinHuiEric.Huang@amd.com> The maximum OD percentage is 20. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> --- drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c | 44 ++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c index 76beaf8..f5df116 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c @@ -5316,6 +5316,48 @@ static int fiji_set_sclk_od(struct pp_hwmgr *hwmgr, uint32_t value) return 0; } +static int fiji_get_mclk_od(struct pp_hwmgr *hwmgr) +{ + struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend); + struct fiji_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table); + struct fiji_single_dpm_table *golden_mclk_table = + &(data->golden_dpm_table.mclk_table); + int value; + + value = (mclk_table->dpm_levels[mclk_table->count - 1].value - + golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value) * + 100 / + golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value; + + return value; +} + +static int fiji_set_mclk_od(struct pp_hwmgr *hwmgr, uint32_t value) +{ + struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend); + struct fiji_single_dpm_table *golden_mclk_table = + &(data->golden_dpm_table.mclk_table); + struct pp_power_state *ps; + struct fiji_power_state *fiji_ps; + + if (value > 20) + value = 20; + + ps = hwmgr->request_ps; + + if (ps == NULL) + return -EINVAL; + + fiji_ps = cast_phw_fiji_power_state(&ps->hardware); + + fiji_ps->performance_levels[fiji_ps->performance_level_count - 1].memory_clock = + golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value * + value / 100 + + golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value; + + return 0; +} + static const struct pp_hwmgr_func fiji_hwmgr_funcs = { .backend_init = &fiji_hwmgr_backend_init, .backend_fini = &fiji_hwmgr_backend_fini, @@ -5359,6 +5401,8 @@ static const struct pp_hwmgr_func fiji_hwmgr_funcs = { .print_clock_levels = fiji_print_clock_levels, .get_sclk_od = fiji_get_sclk_od, .set_sclk_od = fiji_set_sclk_od, + .get_mclk_od = fiji_get_mclk_od, + .set_mclk_od = fiji_set_mclk_od, }; int fiji_hwmgr_init(struct pp_hwmgr *hwmgr) -- 2.5.5 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 5/5] drm/amd/powerplay: add mclk OD(overdrive) support for Polaris10 2016-05-25 21:26 [PATCH 0/5] Add mclk OD (OverDrive) support Alex Deucher ` (3 preceding siblings ...) 2016-05-25 21:26 ` [PATCH 4/5] drm/amd/powerplay: add mclk OD(overdrive) support for Fiji Alex Deucher @ 2016-05-25 21:26 ` Alex Deucher 4 siblings, 0 replies; 6+ messages in thread From: Alex Deucher @ 2016-05-25 21:26 UTC (permalink / raw) To: dri-devel; +Cc: Eric Huang, Alex Deucher From: Eric Huang <JinHuiEric.Huang@amd.com> The maximum OD percentage is 20. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> --- .../gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c | 43 ++++++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c index f91be22..9be0b66 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c @@ -4946,6 +4946,47 @@ static int polaris10_set_sclk_od(struct pp_hwmgr *hwmgr, uint32_t value) return 0; } +static int polaris10_get_mclk_od(struct pp_hwmgr *hwmgr) +{ + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + struct polaris10_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table); + struct polaris10_single_dpm_table *golden_mclk_table = + &(data->golden_dpm_table.mclk_table); + int value; + + value = (mclk_table->dpm_levels[mclk_table->count - 1].value - + golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value) * + 100 / + golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value; + + return value; +} + +static int polaris10_set_mclk_od(struct pp_hwmgr *hwmgr, uint32_t value) +{ + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + struct polaris10_single_dpm_table *golden_mclk_table = + &(data->golden_dpm_table.mclk_table); + struct pp_power_state *ps; + struct polaris10_power_state *polaris10_ps; + + if (value > 20) + value = 20; + + ps = hwmgr->request_ps; + + if (ps == NULL) + return -EINVAL; + + polaris10_ps = cast_phw_polaris10_power_state(&ps->hardware); + + polaris10_ps->performance_levels[polaris10_ps->performance_level_count - 1].memory_clock = + golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value * + value / 100 + + golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value; + + return 0; +} static const struct pp_hwmgr_func polaris10_hwmgr_funcs = { .backend_init = &polaris10_hwmgr_backend_init, .backend_fini = &polaris10_hwmgr_backend_fini, @@ -4991,6 +5032,8 @@ static const struct pp_hwmgr_func polaris10_hwmgr_funcs = { .enable_per_cu_power_gating = polaris10_phm_enable_per_cu_power_gating, .get_sclk_od = polaris10_get_sclk_od, .set_sclk_od = polaris10_set_sclk_od, + .get_mclk_od = polaris10_get_mclk_od, + .set_mclk_od = polaris10_set_mclk_od, }; int polaris10_hwmgr_init(struct pp_hwmgr *hwmgr) -- 2.5.5 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply related [flat|nested] 6+ messages in thread
end of thread, other threads:[~2016-05-25 21:26 UTC | newest] Thread overview: 6+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2016-05-25 21:26 [PATCH 0/5] Add mclk OD (OverDrive) support Alex Deucher 2016-05-25 21:26 ` [PATCH 1/5] drm/amdgpu: add the common code to support mclk OD Alex Deucher 2016-05-25 21:26 ` [PATCH 2/5] drm/amdgpu: add mclk OD(overdrive) support for CI Alex Deucher 2016-05-25 21:26 ` [PATCH 3/5] drm/amd/powerplay: add mclk OD(overdrive) support for Tonga Alex Deucher 2016-05-25 21:26 ` [PATCH 4/5] drm/amd/powerplay: add mclk OD(overdrive) support for Fiji Alex Deucher 2016-05-25 21:26 ` [PATCH 5/5] drm/amd/powerplay: add mclk OD(overdrive) support for Polaris10 Alex Deucher
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