From: "Pandiyan, Dhinakaran" <dhinakaran.pandiyan@intel.com>
To: "chris@chris-wilson.co.uk" <chris@chris-wilson.co.uk>
Cc: "intel-gfx@lists.freedesktop.org"
<intel-gfx@lists.freedesktop.org>,
"dri-devel@lists.freedesktop.org"
<dri-devel@lists.freedesktop.org>
Subject: Re: [PATCH 3/4] drm/dp: Clarify clock recovery and channel equalization failures
Date: Thu, 4 Aug 2016 16:50:35 +0000 [thread overview]
Message-ID: <1470330284.10898.11.camel@dk-H97M-D3H> (raw)
In-Reply-To: <20160804031251.GC9872@nuc-i3427.alporthouse.com>
On Thu, 2016-08-04 at 04:12 +0100, Chris Wilson wrote:
> On Wed, Aug 03, 2016 at 08:07:40PM -0700, Dhinakaran Pandiyan wrote:
> > The causes of clock recovery and channel equalization failures are not
> > explicitly printed in debug messages. Help debugging link training
> > failures by printing why it failed.
> >
> > Doing this in the driver would mean re-implementing some of the drm static
> > functions that decode link status. Let's avoid that with these debug
> > messages in drm.
> >
> > Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> > ---
> > drivers/gpu/drm/drm_dp_helper.c | 12 +++++++++---
> > 1 file changed, 9 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
> > index 091053e..d763b57 100644
> > --- a/drivers/gpu/drm/drm_dp_helper.c
> > +++ b/drivers/gpu/drm/drm_dp_helper.c
> > @@ -64,12 +64,16 @@ bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
> >
> > lane_align = dp_link_status(link_status,
> > DP_LANE_ALIGN_STATUS_UPDATED);
> > - if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
> > + if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0) {
> > + DRM_DEBUG_KMS("Inter-lane alignment not done\n");
> > return false;
> > + }
> > for (lane = 0; lane < lane_count; lane++) {
> > lane_status = dp_get_lane_status(link_status, lane);
> > - if ((lane_status & DP_CHANNEL_EQ_BITS) != DP_CHANNEL_EQ_BITS)
> > + if ((lane_status & DP_CHANNEL_EQ_BITS) != DP_CHANNEL_EQ_BITS) {
> > + DRM_DEBUG_KMS("Channel equalization not done for lane %d\n", lane);
> > return false;
> > + }
> > }
> > return true;
> > }
> > @@ -83,8 +87,10 @@ bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
> >
> > for (lane = 0; lane < lane_count; lane++) {
> > lane_status = dp_get_lane_status(link_status, lane);
> > - if ((lane_status & DP_LANE_CR_DONE) == 0)
> > + if ((lane_status & DP_LANE_CR_DONE) == 0) {
> > + DRM_DEBUG_KMS("Clock recovery not done for lane %d\n", lane);
>
> Please petition, with patch, for DRM_DEBUG_DP.
> -Chris
>
Is that because DRM_DEBUG_KMS in not appropriate or that we have plenty
of DP related debug messages that it warrants it's own debug macro?
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next prev parent reply other threads:[~2016-08-04 16:50 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-08-04 3:07 [PATCH 0/4] Improve logging for DP link training Dhinakaran Pandiyan
2016-08-04 3:07 ` [PATCH 1/4] drm/i915/dp: Add debug messages to print DP link training pattern Dhinakaran Pandiyan
2016-08-04 3:07 ` [Intel-gfx] " Chris Wilson
2016-08-04 16:51 ` Pandiyan, Dhinakaran
2016-08-04 3:07 ` [PATCH 2/4] drm/i915/dp: Switch to using the DRM function for reading DP link status Dhinakaran Pandiyan
2016-08-04 3:11 ` Chris Wilson
2016-08-04 5:48 ` Ville Syrjälä
2016-08-04 3:07 ` [PATCH 3/4] drm/dp: Clarify clock recovery and channel equalization failures Dhinakaran Pandiyan
2016-08-04 3:12 ` Chris Wilson
2016-08-04 16:50 ` Pandiyan, Dhinakaran [this message]
2016-08-04 17:07 ` [Intel-gfx] " chris
2016-08-04 3:07 ` [PATCH 4/4] drm/i915/dp: Dump DP link status when link training stages fails Dhinakaran Pandiyan
2016-08-04 7:46 ` [Intel-gfx] " Jani Nikula
2016-08-04 16:46 ` Pandiyan, Dhinakaran
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