Re: [PATCH v3 05/10] drm/i915/psr/cnl: Enable Y-coordinate support in source

From: "Pandiyan, Dhinakaran" <dhinakaran.pandiyan@intel.com>
To: "Souza, Jose" <jose.souza@intel.com>
Cc: "intel-gfx@lists.freedesktop.org"
	<intel-gfx@lists.freedesktop.org>,
	"dri-devel@lists.freedesktop.org"
	<dri-devel@lists.freedesktop.org>
Subject: Re: [PATCH v3 05/10] drm/i915/psr/cnl: Enable Y-coordinate support in source
Date: Fri, 30 Mar 2018 17:36:27 +0000	[thread overview]
Message-ID: <1522432854.14329.9.camel@dk-H97M-D3H> (raw)
In-Reply-To: <20180328223046.16125-5-jose.souza@intel.com>

On Wed, 2018-03-28 at 15:30 -0700, José Roberto de Souza wrote:
> For Geminilake and Cannonlake+ the Y-coordinate support must be
> enabled in PSR2_CTL too.
> 
> Spec: 7713 and 7720
> 
> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
> 
> v3: rebased
> 
>  drivers/gpu/drm/i915/i915_reg.h  |  3 +++
>  drivers/gpu/drm/i915/intel_psr.c | 16 ++++++++++++----
>  2 files changed, 15 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 33e52cc98d99..9d61ab1288d3 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4058,6 +4058,8 @@ enum {
>  #define EDP_PSR2_CTL			_MMIO(0x6f900)
>  #define   EDP_PSR2_ENABLE		(1<<31)
>  #define   EDP_SU_TRACK_ENABLE		(1<<30)
> +#define   EDP_Y_COORDINATE_VALID	(1<<26) /* GLK and CNL+ */
> +#define   EDP_Y_COORDINATE_ENABLE	(1<<25) /* GLK and CNL+ */
>  #define   EDP_MAX_SU_DISABLE_TIME(t)	((t)<<20)
>  #define   EDP_MAX_SU_DISABLE_TIME_MASK	(0x1f<<20)
>  #define   EDP_PSR2_TP2_TIME_500		(0<<8)
> @@ -7064,6 +7066,7 @@ enum {
>  #define CHICKEN_TRANS_A         0x420c0
>  #define CHICKEN_TRANS_B         0x420c4
>  #define CHICKEN_TRANS(trans) _MMIO_TRANS(trans, CHICKEN_TRANS_A, CHICKEN_TRANS_B)
> +#define  VSC_DATA_SEL_SOFTWARE_CONTROL	(1<<25) /* GLK and CNL+ */
>  #define  DDI_TRAINING_OVERRIDE_ENABLE	(1<<19)
>  #define  DDI_TRAINING_OVERRIDE_VALUE	(1<<18)
>  #define  DDIE_TRAINING_OVERRIDE_ENABLE	(1<<17) /* CHICKEN_TRANS_A only */
> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> index fb2d0fe7106b..84e1f8be5c48 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -386,8 +386,10 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
>  	/* FIXME: selective update is probably totally broken because it doesn't
>  	 * mesh at all with our frontbuffer tracking. And the hw alone isn't
>  	 * good enough. */
> -	val |= EDP_PSR2_ENABLE |
> -		EDP_SU_TRACK_ENABLE;
> +	val |= EDP_PSR2_ENABLE | EDP_SU_TRACK_ENABLE;
> +	if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
> +		val |= EDP_Y_COORDINATE_VALID | EDP_Y_COORDINATE_ENABLE;

Bspecs says Bit 26 : Y-coordinate valid
1b stands for "Do not include Y-coordinate valid eDP 1.4".

Was "val |= EDP_Y_COORDINATE_VALID" intended?

> +	}
>  
>  	if (drm_dp_dpcd_readb(&intel_dp->aux,
>  				DP_SYNCHRONIZATION_LATENCY_IN_SINK,
> @@ -569,8 +571,14 @@ static void hsw_psr_enable_source(struct intel_dp *intel_dp,
>  		hsw_psr_setup_aux(intel_dp);
>  
>  	if (dev_priv->psr.psr2_support) {
> -		u32 chicken = PSR2_VSC_ENABLE_PROG_HEADER
> -			      | PSR2_ADD_VERTICAL_LINE_COUNT;
> +		u32 chicken = I915_READ(CHICKEN_TRANS(cpu_transcoder));
> +
> +		if (INTEL_GEN(dev_priv) == 9 && !IS_GEMINILAKE(dev_priv))
> +			chicken |= (PSR2_VSC_ENABLE_PROG_HEADER
> +				   | PSR2_ADD_VERTICAL_LINE_COUNT);
> +
> +		else
> +			chicken &= ~VSC_DATA_SEL_SOFTWARE_CONTROL;
>  		I915_WRITE(CHICKEN_TRANS(cpu_transcoder), chicken);
>  
>  		I915_WRITE(EDP_PSR_DEBUG,
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