From: "José Roberto de Souza" <jose.souza@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: dri-devel@lists.freedesktop.org
Subject: [PATCH v3 07/10] drm/i915/psr: Use PSR2 macro for PSR2
Date: Wed, 28 Mar 2018 15:30:43 -0700 [thread overview]
Message-ID: <20180328223046.16125-7-jose.souza@intel.com> (raw)
In-Reply-To: <20180328223046.16125-1-jose.souza@intel.com>
Cosmetic change.
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
v3: rebased
drivers/gpu/drm/i915/i915_reg.h | 3 ++-
drivers/gpu/drm/i915/intel_psr.c | 2 +-
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9d61ab1288d3..dad0e4b82aab 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4069,8 +4069,9 @@ enum {
#define EDP_PSR2_TP2_TIME_MASK (3<<8)
#define EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4
#define EDP_PSR2_FRAME_BEFORE_SU_MASK (0xf<<4)
-#define EDP_PSR2_IDLE_MASK 0xf
#define EDP_PSR2_FRAME_BEFORE_SU(a) ((a)<<4)
+#define EDP_PSR2_IDLE_FRAME_MASK 0xf
+#define EDP_PSR2_IDLE_FRAME_SHIFT 0
#define EDP_PSR2_STATUS _MMIO(0x6f940)
#define EDP_PSR2_STATUS_STATE_MASK (0xf<<28)
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 5efddd920681..bec455e28943 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -382,7 +382,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
uint32_t val;
uint8_t sink_latency;
- val = idle_frames << EDP_PSR_IDLE_FRAME_SHIFT;
+ val = idle_frames << EDP_PSR2_IDLE_FRAME_SHIFT;
/* FIXME: selective update is probably totally broken because it doesn't
* mesh at all with our frontbuffer tracking. And the hw alone isn't
--
2.16.3
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next prev parent reply other threads:[~2018-03-28 22:30 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-03-28 22:30 [PATCH v3 01/10] drm: Add DP PSR2 sink enable bit José Roberto de Souza
2018-03-28 22:30 ` [PATCH v3 02/10] drm: Add DP last received PSR SDP VSC register and bits José Roberto de Souza
2018-03-28 22:30 ` [PATCH v3 03/10] drm/i915/psr: Nuke aux frame sync José Roberto de Souza
2018-03-28 22:30 ` [PATCH v3 04/10] drm/i915/psr: Tie PSR2 support to Y coordinate requirement José Roberto de Souza
2018-03-28 22:30 ` [PATCH v3 05/10] drm/i915/psr/cnl: Enable Y-coordinate support in source José Roberto de Souza
2018-03-30 17:36 ` Pandiyan, Dhinakaran
2018-03-30 17:49 ` Souza, Jose
2018-03-28 22:30 ` [PATCH v3 06/10] drm/i915/psr: Do not override PSR2 sink support José Roberto de Souza
2018-03-28 22:30 ` José Roberto de Souza [this message]
2018-03-28 22:30 ` [PATCH v3 08/10] drm/i915/psr: Cache sink synchronization latency José Roberto de Souza
2018-03-28 22:30 ` [PATCH v3 09/10] drm/i915/psr: Set DPCD PSR2 enable bit when needed José Roberto de Souza
2018-03-30 17:41 ` Rodrigo Vivi
2018-04-05 9:53 ` [Intel-gfx] " Chris Wilson
2018-03-28 22:30 ` [PATCH v3 10/10] drm/i915/debugfs: Print sink PSR status José Roberto de Souza
2018-03-30 18:28 ` Pandiyan, Dhinakaran
2018-03-30 19:19 ` [Intel-gfx] " Souza, Jose
2018-03-30 20:55 ` Pandiyan, Dhinakaran
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