[PATCH v3 0/4] HDCP1.4 fixes

[PATCH v3 0/4] HDCP1.4 fixes

[Ramalingam C]

First two patches needed for below DP HDCP compliance tests
	1A-06 and 1B-05

Third patch fixes the HDCP1.4 Key loadability check. where as fourth
one fixes the downstream device count read.

Fix for HDMI HDCP1.4 CTS tests: 1A-04 and 1A-07a are functional.
But the change from v2, as thinking to put through more regressive
testing before upstreaming.

Ramalingam C (4):
  drm/i915: Read HDCP R0 thrice in case of mismatch
  drm/i915: Read Vprime thrice incase of mismatch
  drm/i915: Check hdcp key loadability
  drm/i915: Fix reading downstream dev count

 drivers/gpu/drm/i915/intel_hdcp.c | 182 +++++++++++++++++++++++++++-----------
 include/drm/drm_hdcp.h            |   2 +-
 2 files changed, 130 insertions(+), 54 deletions(-)

-- 
2.7.4

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[PATCH v3 1/4] drm/i915: Read HDCP R0 thrice in case of mismatch

[Ramalingam C]

As per DP spec when R0 mismatch is detected, HDCP source supported
re-read the R0 atleast twice.

And For HDMI and DP minimum wait required for the R0 availability is
100mSec. So this patch changes the wait time to 100mSec but retries
twice with the time interval of 100mSec for each attempt.

This patch is needed for DP HDCP1.4 CTS Test: 1A-06.

v2:
  No Change
v3:
  Comment on R0 retry is moved closer to the code[Seanpaul]

Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
---
 drivers/gpu/drm/i915/intel_hdcp.c | 29 ++++++++++++++++++++---------
 1 file changed, 20 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_hdcp.c b/drivers/gpu/drm/i915/intel_hdcp.c
index 14ca5d3057a7..838c8cd0f543 100644
--- a/drivers/gpu/drm/i915/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/intel_hdcp.c
@@ -498,7 +498,7 @@ static int intel_hdcp_auth(struct intel_digital_port *intel_dig_port,
 	/*
 	 * Wait for R0' to become available. The spec says 100ms from Aksv, but
 	 * some monitors can take longer than this. We'll set the timeout at
-	 * 300ms just to be sure.
+-        * 300ms just to be sure.
 	 *
 	 * On DP, there's an R0_READY bit available but no such bit
 	 * exists on HDMI. Since the upper-bound is the same, we'll just do
@@ -506,15 +506,26 @@ static int intel_hdcp_auth(struct intel_digital_port *intel_dig_port,
 	 */
 	wait_remaining_ms_from_jiffies(r0_prime_gen_start, 300);
 
-	ri.reg = 0;
-	ret = shim->read_ri_prime(intel_dig_port, ri.shim);
-	if (ret)
-		return ret;
-	I915_WRITE(PORT_HDCP_RPRIME(port), ri.reg);
+	tries = 3;
 
-	/* Wait for Ri prime match */
-	if (wait_for(I915_READ(PORT_HDCP_STATUS(port)) &
-		     (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1)) {
+	/*
+	 * DP HDCP Spec mandates the two more reattempt to read R0, incase
+	 * of R0 mismatch.
+	 */
+	for (i = 0; i < tries; i++) {
+		ri.reg = 0;
+		ret = shim->read_ri_prime(intel_dig_port, ri.shim);
+		if (ret)
+			return ret;
+		I915_WRITE(PORT_HDCP_RPRIME(port), ri.reg);
+
+		/* Wait for Ri prime match */
+		if (!wait_for(I915_READ(PORT_HDCP_STATUS(port)) &
+		    (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1))
+			break;
+	}
+
+	if (i == tries) {
 		DRM_ERROR("Timed out waiting for Ri prime match (%x)\n",
 			  I915_READ(PORT_HDCP_STATUS(port)));
 		return -ETIMEDOUT;
-- 
2.7.4

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[PATCH v4 1/4] drm/i915: Read HDCP R0 thrice in case of mismatch

[Ramalingam C]

As per DP spec when R0 mismatch is detected, HDCP source supported
re-read the R0 atleast twice.

And For HDMI and DP minimum wait required for the R0 availability is
100mSec. So this patch changes the wait time to 100mSec but retries
twice with the time interval of 100mSec for each attempt.

This patch is needed for DP HDCP1.4 CTS Test: 1A-06.

v2:
  No Change
v3:
  Comment on R0 retry is moved closer to the code[Seanpaul]
v4:
  Removing unwanted noise introduced in v3.

Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
---
 drivers/gpu/drm/i915/intel_hdcp.c | 27 +++++++++++++++++++--------
 1 file changed, 19 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_hdcp.c b/drivers/gpu/drm/i915/intel_hdcp.c
index 14ca5d3057a7..f2cf2e3acd3c 100644
--- a/drivers/gpu/drm/i915/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/intel_hdcp.c
@@ -506,15 +506,26 @@ static int intel_hdcp_auth(struct intel_digital_port *intel_dig_port,
 	 */
 	wait_remaining_ms_from_jiffies(r0_prime_gen_start, 300);
 
-	ri.reg = 0;
-	ret = shim->read_ri_prime(intel_dig_port, ri.shim);
-	if (ret)
-		return ret;
-	I915_WRITE(PORT_HDCP_RPRIME(port), ri.reg);
+	tries = 3;
 
-	/* Wait for Ri prime match */
-	if (wait_for(I915_READ(PORT_HDCP_STATUS(port)) &
-		     (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1)) {
+	/*
+	 * DP HDCP Spec mandates the two more reattempt to read R0, incase
+	 * of R0 mismatch.
+	 */
+	for (i = 0; i < tries; i++) {
+		ri.reg = 0;
+		ret = shim->read_ri_prime(intel_dig_port, ri.shim);
+		if (ret)
+			return ret;
+		I915_WRITE(PORT_HDCP_RPRIME(port), ri.reg);
+
+		/* Wait for Ri prime match */
+		if (!wait_for(I915_READ(PORT_HDCP_STATUS(port)) &
+		    (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1))
+			break;
+	}
+
+	if (i == tries) {
 		DRM_ERROR("Timed out waiting for Ri prime match (%x)\n",
 			  I915_READ(PORT_HDCP_STATUS(port)));
 		return -ETIMEDOUT;
-- 
2.7.4

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Re: [PATCH v4 1/4] drm/i915: Read HDCP R0 thrice in case of mismatch

[Sean Paul]

On Mon, Apr 02, 2018 at 05:20:22PM +0530, Ramalingam C wrote:
> As per DP spec when R0 mismatch is detected, HDCP source supported
> re-read the R0 atleast twice.
> 
> And For HDMI and DP minimum wait required for the R0 availability is
> 100mSec. So this patch changes the wait time to 100mSec but retries
> twice with the time interval of 100mSec for each attempt.
> 
> This patch is needed for DP HDCP1.4 CTS Test: 1A-06.
> 
> v2:
>   No Change
> v3:
>   Comment on R0 retry is moved closer to the code[Seanpaul]
> v4:
>   Removing unwanted noise introduced in v3.
> 
> Signed-off-by: Ramalingam C <ramalingam.c@intel.com>

Reviewed-by: Sean Paul <seanpaul@chromium.org>

> ---
>  drivers/gpu/drm/i915/intel_hdcp.c | 27 +++++++++++++++++++--------
>  1 file changed, 19 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_hdcp.c b/drivers/gpu/drm/i915/intel_hdcp.c
> index 14ca5d3057a7..f2cf2e3acd3c 100644
> --- a/drivers/gpu/drm/i915/intel_hdcp.c
> +++ b/drivers/gpu/drm/i915/intel_hdcp.c
> @@ -506,15 +506,26 @@ static int intel_hdcp_auth(struct intel_digital_port *intel_dig_port,
>  	 */
>  	wait_remaining_ms_from_jiffies(r0_prime_gen_start, 300);
>  
> -	ri.reg = 0;
> -	ret = shim->read_ri_prime(intel_dig_port, ri.shim);
> -	if (ret)
> -		return ret;
> -	I915_WRITE(PORT_HDCP_RPRIME(port), ri.reg);
> +	tries = 3;
>  
> -	/* Wait for Ri prime match */
> -	if (wait_for(I915_READ(PORT_HDCP_STATUS(port)) &
> -		     (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1)) {
> +	/*
> +	 * DP HDCP Spec mandates the two more reattempt to read R0, incase
> +	 * of R0 mismatch.
> +	 */
> +	for (i = 0; i < tries; i++) {
> +		ri.reg = 0;
> +		ret = shim->read_ri_prime(intel_dig_port, ri.shim);
> +		if (ret)
> +			return ret;
> +		I915_WRITE(PORT_HDCP_RPRIME(port), ri.reg);
> +
> +		/* Wait for Ri prime match */
> +		if (!wait_for(I915_READ(PORT_HDCP_STATUS(port)) &
> +		    (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1))
> +			break;
> +	}
> +
> +	if (i == tries) {
>  		DRM_ERROR("Timed out waiting for Ri prime match (%x)\n",
>  			  I915_READ(PORT_HDCP_STATUS(port)));
>  		return -ETIMEDOUT;
> -- 
> 2.7.4
> 

-- 
Sean Paul, Software Engineer, Google / Chromium OS
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[PATCH v3 2/4] drm/i915: Read Vprime thrice incase of mismatch

[Ramalingam C]

In case of V prime mismatch, DP HDCP spec mandates the re-read of
Vprime atleast twice.

This patch needed for DP HDCP1.4 CTS Test: 1B-05.

v2:
  Moved the V' validation into a function for retry. [Sean Paul]
v3:
  Removed Inline keyword and DRM_DEBUG_KMS are used [Sean Paul]

Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
---
 drivers/gpu/drm/i915/intel_hdcp.c | 112 ++++++++++++++++++++++++--------------
 1 file changed, 70 insertions(+), 42 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_hdcp.c b/drivers/gpu/drm/i915/intel_hdcp.c
index 838c8cd0f543..e0bc03eee941 100644
--- a/drivers/gpu/drm/i915/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/intel_hdcp.c
@@ -142,53 +142,17 @@ bool intel_hdcp_is_ksv_valid(u8 *ksv)
 	return true;
 }
 
-/* Implements Part 2 of the HDCP authorization procedure */
 static
-int intel_hdcp_auth_downstream(struct intel_digital_port *intel_dig_port,
-			       const struct intel_hdcp_shim *shim)
+int intel_hdcp_validate_v_prime(struct intel_digital_port *intel_dig_port,
+				const struct intel_hdcp_shim *shim,
+				u8 *ksv_fifo, u8 num_downstream, u8 *bstatus)
 {
 	struct drm_i915_private *dev_priv;
 	u32 vprime, sha_text, sha_leftovers, rep_ctl;
-	u8 bstatus[2], num_downstream, *ksv_fifo;
 	int ret, i, j, sha_idx;
 
 	dev_priv = intel_dig_port->base.base.dev->dev_private;
 
-	ret = intel_hdcp_poll_ksv_fifo(intel_dig_port, shim);
-	if (ret) {
-		DRM_ERROR("KSV list failed to become ready (%d)\n", ret);
-		return ret;
-	}
-
-	ret = shim->read_bstatus(intel_dig_port, bstatus);
-	if (ret)
-		return ret;
-
-	if (DRM_HDCP_MAX_DEVICE_EXCEEDED(bstatus[0]) ||
-	    DRM_HDCP_MAX_CASCADE_EXCEEDED(bstatus[1])) {
-		DRM_ERROR("Max Topology Limit Exceeded\n");
-		return -EPERM;
-	}
-
-	/*
-	 * When repeater reports 0 device count, HDCP1.4 spec allows disabling
-	 * the HDCP encryption. That implies that repeater can't have its own
-	 * display. As there is no consumption of encrypted content in the
-	 * repeater with 0 downstream devices, we are failing the
-	 * authentication.
-	 */
-	num_downstream = DRM_HDCP_NUM_DOWNSTREAM(bstatus[0]);
-	if (num_downstream == 0)
-		return -EINVAL;
-
-	ksv_fifo = kzalloc(num_downstream * DRM_HDCP_KSV_LEN, GFP_KERNEL);
-	if (!ksv_fifo)
-		return -ENOMEM;
-
-	ret = shim->read_ksv_fifo(intel_dig_port, num_downstream, ksv_fifo);
-	if (ret)
-		return ret;
-
 	/* Process V' values from the receiver */
 	for (i = 0; i < DRM_HDCP_V_PRIME_NUM_PARTS; i++) {
 		ret = shim->read_v_prime_part(intel_dig_port, i, &vprime);
@@ -353,7 +317,8 @@ int intel_hdcp_auth_downstream(struct intel_digital_port *intel_dig_port,
 			return ret;
 		sha_idx += sizeof(sha_text);
 	} else {
-		DRM_ERROR("Invalid number of leftovers %d\n", sha_leftovers);
+		DRM_DEBUG_KMS("Invalid number of leftovers %d\n",
+			      sha_leftovers);
 		return -EINVAL;
 	}
 
@@ -381,14 +346,77 @@ int intel_hdcp_auth_downstream(struct intel_digital_port *intel_dig_port,
 	if (intel_wait_for_register(dev_priv, HDCP_REP_CTL,
 				    HDCP_SHA1_COMPLETE,
 				    HDCP_SHA1_COMPLETE, 1)) {
-		DRM_ERROR("Timed out waiting for SHA1 complete\n");
+		DRM_DEBUG_KMS("Timed out waiting for SHA1 complete\n");
 		return -ETIMEDOUT;
 	}
 	if (!(I915_READ(HDCP_REP_CTL) & HDCP_SHA1_V_MATCH)) {
-		DRM_ERROR("SHA-1 mismatch, HDCP failed\n");
+		DRM_DEBUG_KMS("SHA-1 mismatch, HDCP failed\n");
 		return -ENXIO;
 	}
 
+	return 0;
+}
+
+/* Implements Part 2 of the HDCP authorization procedure */
+static
+int intel_hdcp_auth_downstream(struct intel_digital_port *intel_dig_port,
+			       const struct intel_hdcp_shim *shim)
+{
+	u8 bstatus[2], num_downstream, *ksv_fifo;
+	int ret, i, tries = 3;
+
+	ret = intel_hdcp_poll_ksv_fifo(intel_dig_port, shim);
+	if (ret) {
+		DRM_ERROR("KSV list failed to become ready (%d)\n", ret);
+		return ret;
+	}
+
+	ret = shim->read_bstatus(intel_dig_port, bstatus);
+	if (ret)
+		return ret;
+
+	if (DRM_HDCP_MAX_DEVICE_EXCEEDED(bstatus[0]) ||
+	    DRM_HDCP_MAX_CASCADE_EXCEEDED(bstatus[1])) {
+		DRM_ERROR("Max Topology Limit Exceeded\n");
+		return -EPERM;
+	}
+
+	/*
+	 * When repeater reports 0 device count, HDCP1.4 spec allows disabling
+	 * the HDCP encryption. That implies that repeater can't have its own
+	 * display. As there is no consumption of encrypted content in the
+	 * repeater with 0 downstream devices, we are failing the
+	 * authentication.
+	 */
+	num_downstream = DRM_HDCP_NUM_DOWNSTREAM(bstatus[0]);
+	if (num_downstream == 0)
+		return -EINVAL;
+
+	ksv_fifo = kzalloc(num_downstream * DRM_HDCP_KSV_LEN, GFP_KERNEL);
+	if (!ksv_fifo)
+		return -ENOMEM;
+
+	ret = shim->read_ksv_fifo(intel_dig_port, num_downstream, ksv_fifo);
+	if (ret)
+		return ret;
+
+	/*
+	 * When V prime mismatches, DP Spec mandates re-read of
+	 * V prime atleast twice.
+	 */
+	for (i = 0; i < tries; i++) {
+		ret = intel_hdcp_validate_v_prime(intel_dig_port, shim,
+						  ksv_fifo, num_downstream,
+						  bstatus);
+		if (!ret)
+			break;
+	}
+
+	if (i == tries) {
+		DRM_ERROR("V Prime validation failed.(%d)\n", ret);
+		return ret;
+	}
+
 	DRM_DEBUG_KMS("HDCP is enabled (%d downstream devices)\n",
 		      num_downstream);
 	return 0;
-- 
2.7.4

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Re: [PATCH v3 2/4] drm/i915: Read Vprime thrice incase of mismatch

[Sean Paul]

On Mon, Apr 02, 2018 at 03:40:32PM +0530, Ramalingam C wrote:
> In case of V prime mismatch, DP HDCP spec mandates the re-read of
> Vprime atleast twice.
> 
> This patch needed for DP HDCP1.4 CTS Test: 1B-05.
> 
> v2:
>   Moved the V' validation into a function for retry. [Sean Paul]
> v3:
>   Removed Inline keyword and DRM_DEBUG_KMS are used [Sean Paul]
> 
> Signed-off-by: Ramalingam C <ramalingam.c@intel.com>

Reviewed-by: Sean Paul <seanpaul@chromium.org>

> ---
>  drivers/gpu/drm/i915/intel_hdcp.c | 112 ++++++++++++++++++++++++--------------
>  1 file changed, 70 insertions(+), 42 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_hdcp.c b/drivers/gpu/drm/i915/intel_hdcp.c
> index 838c8cd0f543..e0bc03eee941 100644
> --- a/drivers/gpu/drm/i915/intel_hdcp.c
> +++ b/drivers/gpu/drm/i915/intel_hdcp.c
> @@ -142,53 +142,17 @@ bool intel_hdcp_is_ksv_valid(u8 *ksv)
>  	return true;
>  }
>  
> -/* Implements Part 2 of the HDCP authorization procedure */
>  static
> -int intel_hdcp_auth_downstream(struct intel_digital_port *intel_dig_port,
> -			       const struct intel_hdcp_shim *shim)
> +int intel_hdcp_validate_v_prime(struct intel_digital_port *intel_dig_port,
> +				const struct intel_hdcp_shim *shim,
> +				u8 *ksv_fifo, u8 num_downstream, u8 *bstatus)
>  {
>  	struct drm_i915_private *dev_priv;
>  	u32 vprime, sha_text, sha_leftovers, rep_ctl;
> -	u8 bstatus[2], num_downstream, *ksv_fifo;
>  	int ret, i, j, sha_idx;
>  
>  	dev_priv = intel_dig_port->base.base.dev->dev_private;
>  
> -	ret = intel_hdcp_poll_ksv_fifo(intel_dig_port, shim);
> -	if (ret) {
> -		DRM_ERROR("KSV list failed to become ready (%d)\n", ret);
> -		return ret;
> -	}
> -
> -	ret = shim->read_bstatus(intel_dig_port, bstatus);
> -	if (ret)
> -		return ret;
> -
> -	if (DRM_HDCP_MAX_DEVICE_EXCEEDED(bstatus[0]) ||
> -	    DRM_HDCP_MAX_CASCADE_EXCEEDED(bstatus[1])) {
> -		DRM_ERROR("Max Topology Limit Exceeded\n");
> -		return -EPERM;
> -	}
> -
> -	/*
> -	 * When repeater reports 0 device count, HDCP1.4 spec allows disabling
> -	 * the HDCP encryption. That implies that repeater can't have its own
> -	 * display. As there is no consumption of encrypted content in the
> -	 * repeater with 0 downstream devices, we are failing the
> -	 * authentication.
> -	 */
> -	num_downstream = DRM_HDCP_NUM_DOWNSTREAM(bstatus[0]);
> -	if (num_downstream == 0)
> -		return -EINVAL;
> -
> -	ksv_fifo = kzalloc(num_downstream * DRM_HDCP_KSV_LEN, GFP_KERNEL);
> -	if (!ksv_fifo)
> -		return -ENOMEM;
> -
> -	ret = shim->read_ksv_fifo(intel_dig_port, num_downstream, ksv_fifo);
> -	if (ret)
> -		return ret;
> -
>  	/* Process V' values from the receiver */
>  	for (i = 0; i < DRM_HDCP_V_PRIME_NUM_PARTS; i++) {
>  		ret = shim->read_v_prime_part(intel_dig_port, i, &vprime);
> @@ -353,7 +317,8 @@ int intel_hdcp_auth_downstream(struct intel_digital_port *intel_dig_port,
>  			return ret;
>  		sha_idx += sizeof(sha_text);
>  	} else {
> -		DRM_ERROR("Invalid number of leftovers %d\n", sha_leftovers);
> +		DRM_DEBUG_KMS("Invalid number of leftovers %d\n",
> +			      sha_leftovers);
>  		return -EINVAL;
>  	}
>  
> @@ -381,14 +346,77 @@ int intel_hdcp_auth_downstream(struct intel_digital_port *intel_dig_port,
>  	if (intel_wait_for_register(dev_priv, HDCP_REP_CTL,
>  				    HDCP_SHA1_COMPLETE,
>  				    HDCP_SHA1_COMPLETE, 1)) {
> -		DRM_ERROR("Timed out waiting for SHA1 complete\n");
> +		DRM_DEBUG_KMS("Timed out waiting for SHA1 complete\n");
>  		return -ETIMEDOUT;
>  	}
>  	if (!(I915_READ(HDCP_REP_CTL) & HDCP_SHA1_V_MATCH)) {
> -		DRM_ERROR("SHA-1 mismatch, HDCP failed\n");
> +		DRM_DEBUG_KMS("SHA-1 mismatch, HDCP failed\n");
>  		return -ENXIO;
>  	}
>  
> +	return 0;
> +}
> +
> +/* Implements Part 2 of the HDCP authorization procedure */
> +static
> +int intel_hdcp_auth_downstream(struct intel_digital_port *intel_dig_port,
> +			       const struct intel_hdcp_shim *shim)
> +{
> +	u8 bstatus[2], num_downstream, *ksv_fifo;
> +	int ret, i, tries = 3;
> +
> +	ret = intel_hdcp_poll_ksv_fifo(intel_dig_port, shim);
> +	if (ret) {
> +		DRM_ERROR("KSV list failed to become ready (%d)\n", ret);
> +		return ret;
> +	}
> +
> +	ret = shim->read_bstatus(intel_dig_port, bstatus);
> +	if (ret)
> +		return ret;
> +
> +	if (DRM_HDCP_MAX_DEVICE_EXCEEDED(bstatus[0]) ||
> +	    DRM_HDCP_MAX_CASCADE_EXCEEDED(bstatus[1])) {
> +		DRM_ERROR("Max Topology Limit Exceeded\n");
> +		return -EPERM;
> +	}
> +
> +	/*
> +	 * When repeater reports 0 device count, HDCP1.4 spec allows disabling
> +	 * the HDCP encryption. That implies that repeater can't have its own
> +	 * display. As there is no consumption of encrypted content in the
> +	 * repeater with 0 downstream devices, we are failing the
> +	 * authentication.
> +	 */
> +	num_downstream = DRM_HDCP_NUM_DOWNSTREAM(bstatus[0]);
> +	if (num_downstream == 0)
> +		return -EINVAL;
> +
> +	ksv_fifo = kzalloc(num_downstream * DRM_HDCP_KSV_LEN, GFP_KERNEL);
> +	if (!ksv_fifo)
> +		return -ENOMEM;
> +
> +	ret = shim->read_ksv_fifo(intel_dig_port, num_downstream, ksv_fifo);
> +	if (ret)
> +		return ret;
> +
> +	/*
> +	 * When V prime mismatches, DP Spec mandates re-read of
> +	 * V prime atleast twice.
> +	 */
> +	for (i = 0; i < tries; i++) {
> +		ret = intel_hdcp_validate_v_prime(intel_dig_port, shim,
> +						  ksv_fifo, num_downstream,
> +						  bstatus);
> +		if (!ret)
> +			break;
> +	}
> +
> +	if (i == tries) {
> +		DRM_ERROR("V Prime validation failed.(%d)\n", ret);
> +		return ret;
> +	}
> +
>  	DRM_DEBUG_KMS("HDCP is enabled (%d downstream devices)\n",
>  		      num_downstream);
>  	return 0;
> -- 
> 2.7.4
> 

-- 
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[PATCH v3 3/4] drm/i915: Check hdcp key loadability

[Ramalingam C]

HDCP1.4 key can be loaded, only when Power well #1 is enabled and cdclk
is enabled. Using the I915 power well infrastruture, above requirement
is verified.

This patch enables the hdcp initialization for HSW, BDW, and BXT.

v2:
  Choose the PW# based on the platform.
v3:
  No Changes.

Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
Reviewed-by: Sean Paul <seanpaul@chromium.org>
---
 drivers/gpu/drm/i915/intel_hdcp.c | 41 +++++++++++++++++++++++++++++++++++++--
 1 file changed, 39 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_hdcp.c b/drivers/gpu/drm/i915/intel_hdcp.c
index e0bc03eee941..94b7b5158169 100644
--- a/drivers/gpu/drm/i915/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/intel_hdcp.c
@@ -37,6 +37,43 @@ static int intel_hdcp_poll_ksv_fifo(struct intel_digital_port *intel_dig_port,
 	return 0;
 }
 
+static bool hdcp_key_loadable(struct drm_i915_private *dev_priv)
+{
+	struct i915_power_domains *power_domains = &dev_priv->power_domains;
+	struct i915_power_well *power_well;
+	enum i915_power_well_id id;
+	bool enabled = false;
+
+	/*
+	 * On HSW and BDW, Display HW loads the Key as soon as Display resumes.
+	 * On all BXT+, SW can load the keys only when the PW#1 is turned on.
+	 */
+	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
+		id = HSW_DISP_PW_GLOBAL;
+	else
+		id = SKL_DISP_PW_1;
+
+	mutex_lock(&power_domains->lock);
+
+	/* PG1 (power well #1) needs to be enabled */
+	for_each_power_well(dev_priv, power_well) {
+		if (power_well->id == id) {
+			enabled = power_well->ops->is_enabled(dev_priv,
+							      power_well);
+			break;
+		}
+	}
+	mutex_unlock(&power_domains->lock);
+
+	/*
+	 * Another req for hdcp key loadability is enabled state of pll for
+	 * cdclk. Without active crtc we wont land here. So we are assuming that
+	 * cdclk is already on.
+	 */
+
+	return enabled;
+}
+
 static void intel_hdcp_clear_keys(struct drm_i915_private *dev_priv)
 {
 	I915_WRITE(HDCP_KEY_CONF, HDCP_CLEAR_KEYS_TRIGGER);
@@ -619,8 +656,8 @@ static int _intel_hdcp_enable(struct intel_connector *connector)
 	DRM_DEBUG_KMS("[%s:%d] HDCP is being enabled...\n",
 		      connector->base.name, connector->base.base.id);
 
-	if (!(I915_READ(SKL_FUSE_STATUS) & SKL_FUSE_PG_DIST_STATUS(1))) {
-		DRM_ERROR("PG1 is disabled, cannot load keys\n");
+	if (!hdcp_key_loadable(dev_priv)) {
+		DRM_ERROR("HDCP key Load is not possible\n");
 		return -ENXIO;
 	}
 
-- 
2.7.4

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[PATCH v3 4/4] drm/i915: Fix reading downstream dev count

[Ramalingam C]

In both HDMI and DP, device count is represented by 6:0 bits of a
register(BInfo/Bstatus)

So macro for bitmasking the device_count is fixed(0x3F->0x7F).

v3:
  Retained the Rb-ed

Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
cc: Sean Paul <seanpaul@chromium.org>
Reviewed-by: Sean Paul <seanpaul@chromium.org>
---
 include/drm/drm_hdcp.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/drm/drm_hdcp.h b/include/drm/drm_hdcp.h
index 562fa7df2637..98e63d870139 100644
--- a/include/drm/drm_hdcp.h
+++ b/include/drm/drm_hdcp.h
@@ -19,7 +19,7 @@
 #define DRM_HDCP_RI_LEN				2
 #define DRM_HDCP_V_PRIME_PART_LEN		4
 #define DRM_HDCP_V_PRIME_NUM_PARTS		5
-#define DRM_HDCP_NUM_DOWNSTREAM(x)		(x & 0x3f)
+#define DRM_HDCP_NUM_DOWNSTREAM(x)		(x & 0x7f)
 #define DRM_HDCP_MAX_CASCADE_EXCEEDED(x)	(x & BIT(3))
 #define DRM_HDCP_MAX_DEVICE_EXCEEDED(x)		(x & BIT(7))
 
-- 
2.7.4

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[PATCH v4] drm: Fix downstream dev count read

[Ramalingam C]

In both HDMI and DP, device count is represented by 6:0 bits of a
register(BInfo/Bstatus)

So macro for bitmasking the device_count is fixed(0x3F->0x7F).

v3:
  Retained the Rb-ed.
v4:
  %s/drm\/i915/drm [rodrigo]

Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
cc: Sean Paul <seanpaul@chromium.org>
Reviewed-by: Sean Paul <seanpaul@chromium.org>
---
 include/drm/drm_hdcp.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/drm/drm_hdcp.h b/include/drm/drm_hdcp.h
index 562fa7df2637..98e63d870139 100644
--- a/include/drm/drm_hdcp.h
+++ b/include/drm/drm_hdcp.h
@@ -19,7 +19,7 @@
 #define DRM_HDCP_RI_LEN				2
 #define DRM_HDCP_V_PRIME_PART_LEN		4
 #define DRM_HDCP_V_PRIME_NUM_PARTS		5
-#define DRM_HDCP_NUM_DOWNSTREAM(x)		(x & 0x3f)
+#define DRM_HDCP_NUM_DOWNSTREAM(x)		(x & 0x7f)
 #define DRM_HDCP_MAX_CASCADE_EXCEEDED(x)	(x & BIT(3))
 #define DRM_HDCP_MAX_DEVICE_EXCEEDED(x)		(x & BIT(7))
 
-- 
2.7.4

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Re: [PATCH v4] drm: Fix downstream dev count read

[Rodrigo Vivi]

On Wed, Apr 04, 2018 at 11:57:42PM +0530, Ramalingam C wrote:
> In both HDMI and DP, device count is represented by 6:0 bits of a
> register(BInfo/Bstatus)
> 
> So macro for bitmasking the device_count is fixed(0x3F->0x7F).
> 
> v3:
>   Retained the Rb-ed.
> v4:
>   %s/drm\/i915/drm [rodrigo]
> 

Shouldn't this patch have a "Fixes:" ?
cc: stable?

I pushed first 3 patches on the series to dinq.
I believe this one here could be there with Dave's ack or
maybe on drm-misc-fixes?

> Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
> cc: Sean Paul <seanpaul@chromium.org>
> Reviewed-by: Sean Paul <seanpaul@chromium.org>
> ---
>  include/drm/drm_hdcp.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/include/drm/drm_hdcp.h b/include/drm/drm_hdcp.h
> index 562fa7df2637..98e63d870139 100644
> --- a/include/drm/drm_hdcp.h
> +++ b/include/drm/drm_hdcp.h
> @@ -19,7 +19,7 @@
>  #define DRM_HDCP_RI_LEN				2
>  #define DRM_HDCP_V_PRIME_PART_LEN		4
>  #define DRM_HDCP_V_PRIME_NUM_PARTS		5
> -#define DRM_HDCP_NUM_DOWNSTREAM(x)		(x & 0x3f)
> +#define DRM_HDCP_NUM_DOWNSTREAM(x)		(x & 0x7f)
>  #define DRM_HDCP_MAX_CASCADE_EXCEEDED(x)	(x & BIT(3))
>  #define DRM_HDCP_MAX_DEVICE_EXCEEDED(x)		(x & BIT(7))
>  
> -- 
> 2.7.4
> 
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Re: [PATCH v4] drm: Fix downstream dev count read

[Sean Paul]

On Wed, Apr 04, 2018 at 12:07:41PM -0700, Rodrigo Vivi wrote:
> On Wed, Apr 04, 2018 at 11:57:42PM +0530, Ramalingam C wrote:
> > In both HDMI and DP, device count is represented by 6:0 bits of a
> > register(BInfo/Bstatus)
> > 
> > So macro for bitmasking the device_count is fixed(0x3F->0x7F).
> > 
> > v3:
> >   Retained the Rb-ed.
> > v4:
> >   %s/drm\/i915/drm [rodrigo]
> > 
> 
> Shouldn't this patch have a "Fixes:" ?

Yes, I think that'd be good.

> cc: stable?

It couldn't hurt.

> 
> I pushed first 3 patches on the series to dinq.
> I believe this one here could be there with Dave's ack or
> maybe on drm-misc-fixes?

Meh. The severity of this isn't too big, given that I doubt people care _too_
much about plugging in more than 64 HDCP-enabled devices. If you want to drop it
in -misc-next-fixes, I can send it out next week.

While we're asking for a respin, could we add HDCP somewhere in the subject?

Sean

> 
> > Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
> > cc: Sean Paul <seanpaul@chromium.org>
> > Reviewed-by: Sean Paul <seanpaul@chromium.org>
> > ---
> >  include/drm/drm_hdcp.h | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> > 
> > diff --git a/include/drm/drm_hdcp.h b/include/drm/drm_hdcp.h
> > index 562fa7df2637..98e63d870139 100644
> > --- a/include/drm/drm_hdcp.h
> > +++ b/include/drm/drm_hdcp.h
> > @@ -19,7 +19,7 @@
> >  #define DRM_HDCP_RI_LEN				2
> >  #define DRM_HDCP_V_PRIME_PART_LEN		4
> >  #define DRM_HDCP_V_PRIME_NUM_PARTS		5
> > -#define DRM_HDCP_NUM_DOWNSTREAM(x)		(x & 0x3f)
> > +#define DRM_HDCP_NUM_DOWNSTREAM(x)		(x & 0x7f)
> >  #define DRM_HDCP_MAX_CASCADE_EXCEEDED(x)	(x & BIT(3))
> >  #define DRM_HDCP_MAX_DEVICE_EXCEEDED(x)		(x & BIT(7))
> >  
> > -- 
> > 2.7.4
> > 

-- 
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Re: [PATCH v4] drm: Fix downstream dev count read

[Ramalingam C]

On Thursday 05 April 2018 12:53 AM, Sean Paul wrote:
> On Wed, Apr 04, 2018 at 12:07:41PM -0700, Rodrigo Vivi wrote:
>> On Wed, Apr 04, 2018 at 11:57:42PM +0530, Ramalingam C wrote:
>>> In both HDMI and DP, device count is represented by 6:0 bits of a
>>> register(BInfo/Bstatus)
>>>
>>> So macro for bitmasking the device_count is fixed(0x3F->0x7F).
>>>
>>> v3:
>>>    Retained the Rb-ed.
>>> v4:
>>>    %s/drm\/i915/drm [rodrigo]
>>>
>> Shouldn't this patch have a "Fixes:" ?
> Yes, I think that'd be good.
Will add
Fixes: 495eb7f877ab drm: Add some HDCP related #defines
>
>> cc: stable?
> It couldn't hurt.
Sorry what is needed here?
>
>> I pushed first 3 patches on the series to dinq.
>> I believe this one here could be there with Dave's ack or
>> maybe on drm-misc-fixes?
> Meh. The severity of this isn't too big, given that I doubt people care _too_
> much about plugging in more than 64 HDCP-enabled devices. If you want to drop it
> in -misc-next-fixes, I can send it out next week.
>
> While we're asking for a respin, could we add HDCP somewhere in the subject?
will change the sub to
drm: Fix HDCP downstream dev count read

--Ram
>
> Sean
>
>>> Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
>>> cc: Sean Paul <seanpaul@chromium.org>
>>> Reviewed-by: Sean Paul <seanpaul@chromium.org>
>>> ---
>>>   include/drm/drm_hdcp.h | 2 +-
>>>   1 file changed, 1 insertion(+), 1 deletion(-)
>>>
>>> diff --git a/include/drm/drm_hdcp.h b/include/drm/drm_hdcp.h
>>> index 562fa7df2637..98e63d870139 100644
>>> --- a/include/drm/drm_hdcp.h
>>> +++ b/include/drm/drm_hdcp.h
>>> @@ -19,7 +19,7 @@
>>>   #define DRM_HDCP_RI_LEN				2
>>>   #define DRM_HDCP_V_PRIME_PART_LEN		4
>>>   #define DRM_HDCP_V_PRIME_NUM_PARTS		5
>>> -#define DRM_HDCP_NUM_DOWNSTREAM(x)		(x & 0x3f)
>>> +#define DRM_HDCP_NUM_DOWNSTREAM(x)		(x & 0x7f)
>>>   #define DRM_HDCP_MAX_CASCADE_EXCEEDED(x)	(x & BIT(3))
>>>   #define DRM_HDCP_MAX_DEVICE_EXCEEDED(x)		(x & BIT(7))
>>>   
>>> -- 
>>> 2.7.4
>>>

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Re: [PATCH v4] drm: Fix downstream dev count read

[Rodrigo Vivi]

On Thu, Apr 05, 2018 at 04:04:14AM +0530, Ramalingam C wrote:
> 
> 
> On Thursday 05 April 2018 12:53 AM, Sean Paul wrote:
> > On Wed, Apr 04, 2018 at 12:07:41PM -0700, Rodrigo Vivi wrote:
> > > On Wed, Apr 04, 2018 at 11:57:42PM +0530, Ramalingam C wrote:
> > > > In both HDMI and DP, device count is represented by 6:0 bits of a
> > > > register(BInfo/Bstatus)
> > > > 
> > > > So macro for bitmasking the device_count is fixed(0x3F->0x7F).
> > > > 
> > > > v3:
> > > >    Retained the Rb-ed.
> > > > v4:
> > > >    %s/drm\/i915/drm [rodrigo]
> > > > 
> > > Shouldn't this patch have a "Fixes:" ?
> > Yes, I think that'd be good.
> Will add
> Fixes: 495eb7f877ab drm: Add some HDCP related #defines
> > 
> > > cc: stable?
> > It couldn't hurt.
> Sorry what is needed here?

nothing actually...

$ dim fixes 495eb7f877ab3
Fixes: 495eb7f877ab ("drm: Add some HDCP related #defines")
Cc: Daniel Vetter <daniel.vetter@intel.com>
Cc: Ramalingam C <ramalingm.c@intel.com>
Cc: Sean Paul <seanpaul@chromium.org>
Cc: Gustavo Padovan <gustavo@padovan.org>
Cc: David Airlie <airlied@linux.ie>
Cc: dri-devel@lists.freedesktop.org

CC: Stable wasn't returned here so it is not needed.

> > 
> > > I pushed first 3 patches on the series to dinq.
> > > I believe this one here could be there with Dave's ack or
> > > maybe on drm-misc-fixes?
> > Meh. The severity of this isn't too big, given that I doubt people care _too_
> > much about plugging in more than 64 HDCP-enabled devices. If you want to drop it
> > in -misc-next-fixes, I can send it out next week.
> > 
> > While we're asking for a respin, could we add HDCP somewhere in the subject?
> will change the sub to
> drm: Fix HDCP downstream dev count read
> 
> --Ram
> > 
> > Sean
> > 
> > > > Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
> > > > cc: Sean Paul <seanpaul@chromium.org>
> > > > Reviewed-by: Sean Paul <seanpaul@chromium.org>
> > > > ---
> > > >   include/drm/drm_hdcp.h | 2 +-
> > > >   1 file changed, 1 insertion(+), 1 deletion(-)
> > > > 
> > > > diff --git a/include/drm/drm_hdcp.h b/include/drm/drm_hdcp.h
> > > > index 562fa7df2637..98e63d870139 100644
> > > > --- a/include/drm/drm_hdcp.h
> > > > +++ b/include/drm/drm_hdcp.h
> > > > @@ -19,7 +19,7 @@
> > > >   #define DRM_HDCP_RI_LEN				2
> > > >   #define DRM_HDCP_V_PRIME_PART_LEN		4
> > > >   #define DRM_HDCP_V_PRIME_NUM_PARTS		5
> > > > -#define DRM_HDCP_NUM_DOWNSTREAM(x)		(x & 0x3f)
> > > > +#define DRM_HDCP_NUM_DOWNSTREAM(x)		(x & 0x7f)
> > > >   #define DRM_HDCP_MAX_CASCADE_EXCEEDED(x)	(x & BIT(3))
> > > >   #define DRM_HDCP_MAX_DEVICE_EXCEEDED(x)		(x & BIT(7))
> > > > -- 
> > > > 2.7.4
> > > > 
> 
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[PATCH v5] drm: Fix HDCP downstream dev count read

[Ramalingam C]

In both HDMI and DP, device count is represented by 6:0 bits of a
register(BInfo/Bstatus)

So macro for bitmasking the device_count is fixed(0x3F->0x7F).

v3:
  Retained the Rb-ed.
v4:
  %s/drm\/i915/drm [rodrigo]
v5:
  Added "Fixes:" and HDCP keyword in subject [Rodrigo, Sean Paul]

Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
Fixes: 495eb7f877ab drm: Add some HDCP related #defines
cc: Sean Paul <seanpaul@chromium.org>
Reviewed-by: Sean Paul <seanpaul@chromium.org>
---
 include/drm/drm_hdcp.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/drm/drm_hdcp.h b/include/drm/drm_hdcp.h
index 562fa7df2637..98e63d870139 100644
--- a/include/drm/drm_hdcp.h
+++ b/include/drm/drm_hdcp.h
@@ -19,7 +19,7 @@
 #define DRM_HDCP_RI_LEN				2
 #define DRM_HDCP_V_PRIME_PART_LEN		4
 #define DRM_HDCP_V_PRIME_NUM_PARTS		5
-#define DRM_HDCP_NUM_DOWNSTREAM(x)		(x & 0x3f)
+#define DRM_HDCP_NUM_DOWNSTREAM(x)		(x & 0x7f)
 #define DRM_HDCP_MAX_CASCADE_EXCEEDED(x)	(x & BIT(3))
 #define DRM_HDCP_MAX_DEVICE_EXCEEDED(x)		(x & BIT(7))
 
-- 
2.7.4

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Re: [PATCH v5] drm: Fix HDCP downstream dev count read

[Sean Paul]

On Thu, Apr 5, 2018 at 8:09 AM Ramalingam C <ramalingam.c@intel.com> wrote:

> In both HDMI and DP, device count is represented by 6:0 bits of a
> register(BInfo/Bstatus)

> So macro for bitmasking the device_count is fixed(0x3F->0x7F).

> v3:
>    Retained the Rb-ed.
> v4:
>    %s/drm\/i915/drm [rodrigo]
> v5:
>    Added "Fixes:" and HDCP keyword in subject [Rodrigo, Sean Paul]

> Signed-off-by: Ramalingam C <ramalingam.c@intel.com>


Thank you for your patch, I've pushed it to -misc-fixes

Sean


> Fixes: 495eb7f877ab drm: Add some HDCP related #defines
> cc: Sean Paul <seanpaul@chromium.org>
> Reviewed-by: Sean Paul <seanpaul@chromium.org>
> ---
>   include/drm/drm_hdcp.h | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)

> diff --git a/include/drm/drm_hdcp.h b/include/drm/drm_hdcp.h
> index 562fa7df2637..98e63d870139 100644
> --- a/include/drm/drm_hdcp.h
> +++ b/include/drm/drm_hdcp.h
> @@ -19,7 +19,7 @@
>   #define DRM_HDCP_RI_LEN                                2
>   #define DRM_HDCP_V_PRIME_PART_LEN              4
>   #define DRM_HDCP_V_PRIME_NUM_PARTS             5
> -#define DRM_HDCP_NUM_DOWNSTREAM(x)             (x & 0x3f)
> +#define DRM_HDCP_NUM_DOWNSTREAM(x)             (x & 0x7f)
>   #define DRM_HDCP_MAX_CASCADE_EXCEEDED(x)       (x & BIT(3))
>   #define DRM_HDCP_MAX_DEVICE_EXCEEDED(x)                (x & BIT(7))

> --
> 2.7.4
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