dri-devel Archive on lore.kernel.org
 help / color / mirror / Atom feed
From: Manasi Navare <manasi.d.navare@intel.com>
To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org
Subject: [PATCH v7 08/19] drm/dsc: Define the DSC 1.1 and 1.2 Line Buffer depth constants
Date: Thu,  1 Nov 2018 23:46:48 -0700	[thread overview]
Message-ID: <20181102064659.8991-9-manasi.d.navare@intel.com> (raw)
In-Reply-To: <20181102064659.8991-1-manasi.d.navare@intel.com>

DSC specification defines linebuf_depth which contains the
line buffer bit depth used to generate the bitstream.
These values are defined as per Table 4.1 in DSC 1.2 spec

v2 (From Manasi):
* Rename as MAX_LINEBUF_DEPTH for DSC 1.1 and DSC 1.2

Cc: dri-devel@lists.freedesktop.org
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
 include/drm/drm_dsc.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/include/drm/drm_dsc.h b/include/drm/drm_dsc.h
index 52e57ceaff80..d03f1b83421a 100644
--- a/include/drm/drm_dsc.h
+++ b/include/drm/drm_dsc.h
@@ -40,6 +40,9 @@
 #define DSC_PPS_RC_RANGE_MINQP_SHIFT		11
 #define DSC_PPS_RC_RANGE_MAXQP_SHIFT		6
 #define DSC_PPS_NATIVE_420_SHIFT		1
+#define DSC_1_2_MAX_LINEBUF_DEPTH_BITS		16
+#define DSC_1_2_MAX_LINEBUF_DEPTH_VAL		0
+#define DSC_1_1_MAX_LINEBUF_DEPTH_BITS		13
 
 /* Configuration for a single Rate Control model range */
 struct drm_dsc_rc_range_parameters {
-- 
2.18.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

  parent reply	other threads:[~2018-11-02  6:46 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-11-02  6:46 [PATCH v7 00/19] DSC enabling remaining patches Manasi Navare
2018-11-02  6:46 ` [PATCH v7 01/19] drm/dsc: Define Display Stream Compression PPS infoframe Manasi Navare
2018-11-02  6:46 ` [PATCH v7 02/19] drm/dsc: Define VESA Display Stream Compression Capabilities Manasi Navare
2018-11-02  6:46 ` [PATCH v7 03/19] drm/dsc: Define Rate Control values that do not change over configurations Manasi Navare
2018-11-02  6:46 ` [PATCH v7 04/19] drm/dsc: Add helpers for DSC picture parameter set infoframes Manasi Navare
2018-11-02  6:46 ` [PATCH v7 05/19] drm/i915/dp: Add DSC params and DSC config to intel_crtc_state Manasi Navare
2018-11-02  6:46 ` [PATCH v7 06/19] drm/i915/dp: Compute DSC pipe config in atomic check Manasi Navare
2018-11-02 17:51   ` Ville Syrjälä
2018-11-02  6:46 ` [PATCH v7 07/19] drm/i915/dp: Do not enable PSR2 if DSC is enabled Manasi Navare
2018-11-02 17:51   ` Ville Syrjälä
2018-11-02 20:35     ` Manasi Navare
2018-11-02  6:46 ` Manasi Navare [this message]
2018-11-02  6:46 ` [PATCH v7 09/19] drm/i915/dsc: Define & Compute VESA DSC params Manasi Navare
2018-11-02 17:51   ` Ville Syrjälä
2018-11-02  6:46 ` [PATCH v7 10/19] drm/i915/dsc: Compute Rate Control parameters for DSC Manasi Navare
2018-11-02 17:52   ` Ville Syrjälä
2018-11-02  6:46 ` [PATCH v7 11/19] drm/i915/dp: Enable/Disable DSC in DP Sink Manasi Navare
2018-11-02  6:46 ` [PATCH v7 12/19] drm/i915/dsc: Add a power domain for VDSC on eDP/MIPI DSI Manasi Navare
2018-11-02  6:46 ` [PATCH v7 13/19] drm/i915/dp: Configure i915 Picture parameter Set registers during DSC enabling Manasi Navare
2018-11-02 17:52   ` Ville Syrjälä
2018-11-02 21:07     ` Manasi Navare
2018-11-02  6:46 ` [PATCH v7 14/19] drm/i915/dp: Use the existing write_infoframe() for DSC PPS SDPs Manasi Navare
2018-11-02  6:46 ` [PATCH v7 15/19] drm/i915/dp: Populate DSC PPS SDP and send PPS infoframes Manasi Navare
2018-11-02  6:46 ` [PATCH v7 16/19] drm/i915/dp: Configure Display stream splitter registers during DSC enable Manasi Navare
2018-11-02  6:46 ` [PATCH v7 17/19] drm/i915/dp: Disable DSC in source by disabling DSS CTL bits Manasi Navare
2018-11-02  6:46 ` [PATCH v7 18/19] drm/i915/dsc: Enable and disable appropriate power wells for VDSC Manasi Navare
2018-11-02 17:53   ` Ville Syrjälä
2018-11-02  6:46 ` [PATCH v7 19/19] drm/i915/dsc: Add Per connector debugfs node for DSC support/enable Manasi Navare
2018-11-02 18:06 ` [PATCH v7 00/19] DSC enabling remaining patches Ville Syrjälä
2018-11-02 19:51   ` Manasi Navare

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20181102064659.8991-9-manasi.d.navare@intel.com \
    --to=manasi.d.navare@intel.com \
    --cc=dri-devel@lists.freedesktop.org \
    --cc=intel-gfx@lists.freedesktop.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox