[PATCH v4 0/4] HDCP1.4 Fixes - II

[PATCH v4 0/4] HDCP1.4 Fixes - II

[Ramalingam C]

Couple of more HDCP1.4 fixes on
  - Key load process for CFL
  - Encryption status change time
  - debug log addition
  - active platform coverage

v1 and v2 went into old series https://patchwork.freedesktop.org/series/38978/
as v8 and v9, due to the same series title. Now changed the title.

v3-->v4:
  Respining with minor fix on 2nd patch [Ville]

Thanks Sean Paul for the reviews.

Ramalingam C (4):
  drm/i915: Fix GEN9 HDCP1.4 key load process
  drm/i915: Fix platform coverage for HDCP1.4
  drm/i915: debug log for REPLY_ACK missing
  drm/i915: Increase timeout for Encrypt status change

 drivers/gpu/drm/i915/intel_dp.c   |  7 ++++++-
 drivers/gpu/drm/i915/intel_hdcp.c | 16 +++++++++-------
 2 files changed, 15 insertions(+), 8 deletions(-)

-- 
2.7.4

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[PATCH v4 1/4] drm/i915: Fix GEN9 HDCP1.4 key load process

[Ramalingam C]

HDCP1.4 key load process varies between Intel platform to platform.

For Gen9 platforms except BXT and GLK, HDCP1.4 key is loaded using
the GT Driver Mailbox interface. So all GEN9_BC platforms will use
the GT Driver Mailbox interface for HDCP1.4 key load.

v2:
  Using the IS_GEN9_BC for filtering the platforms [Ville]

Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
Reviewed-by: Sean Paul <sean@poorly.run>
---
 drivers/gpu/drm/i915/intel_hdcp.c | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_hdcp.c b/drivers/gpu/drm/i915/intel_hdcp.c
index 1bf487f94254..c16bffcce3b0 100644
--- a/drivers/gpu/drm/i915/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/intel_hdcp.c
@@ -157,10 +157,11 @@ static int intel_hdcp_load_keys(struct drm_i915_private *dev_priv)
 	/*
 	 * Initiate loading the HDCP key from fuses.
 	 *
-	 * BXT+ platforms, HDCP key needs to be loaded by SW. Only SKL and KBL
-	 * differ in the key load trigger process from other platforms.
+	 * BXT+ platforms, HDCP key needs to be loaded by SW. Only Gen 9
+	 * platforms except BXT and GLK, differ in the key load trigger process
+	 * from other platforms. So GEN9_BC uses the GT Driver Mailbox i/f.
 	 */
-	if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
+	if (IS_GEN9_BC(dev_priv)) {
 		mutex_lock(&dev_priv->pcu_lock);
 		ret = sandybridge_pcode_write(dev_priv,
 					      SKL_PCODE_LOAD_HDCP_KEYS, 1);
-- 
2.7.4

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[PATCH v4 2/4] drm/i915: Fix platform coverage for HDCP1.4

[Ramalingam C]

HDCP1.4 is enabled and validated only on GEN9+ platforms.

v2:
  Removed the unnecessary parens [Ville]

Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
Reviewed-by: Sean Paul <sean@poorly.run>
---
 drivers/gpu/drm/i915/intel_hdcp.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_hdcp.c b/drivers/gpu/drm/i915/intel_hdcp.c
index c16bffcce3b0..1e5a1e07e343 100644
--- a/drivers/gpu/drm/i915/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/intel_hdcp.c
@@ -769,8 +769,7 @@ static void intel_hdcp_prop_work(struct work_struct *work)
 bool is_hdcp_supported(struct drm_i915_private *dev_priv, enum port port)
 {
 	/* PORT E doesn't have HDCP, and PORT F is disabled */
-	return ((INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv)) &&
-		!IS_CHERRYVIEW(dev_priv) && port < PORT_E);
+	return INTEL_GEN(dev_priv) >= 9 && port < PORT_E;
 }
 
 int intel_hdcp_init(struct intel_connector *connector,
-- 
2.7.4

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[PATCH v4 3/4] drm/i915: debug log for REPLY_ACK missing

[Ramalingam C]

Adding a debug log when the DP_AUX_NATIVE_REPLY_ACK is missing
for aksv write. This helps to locate the possible non responding
DP HDCP sinks.

v2:
  Rewritten for readability [Sean Paul]

Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
Reviewed-by: Sean Paul <sean@poorly.run>
---
 drivers/gpu/drm/i915/intel_dp.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 38a6e82153fd..9f75ca04a344 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -5579,7 +5579,12 @@ int intel_dp_hdcp_write_an_aksv(struct intel_digital_port *intel_dig_port,
 	}
 
 	reply = (rxbuf[0] >> 4) & DP_AUX_NATIVE_REPLY_MASK;
-	return reply == DP_AUX_NATIVE_REPLY_ACK ? 0 : -EIO;
+	if (reply != DP_AUX_NATIVE_REPLY_ACK) {
+		DRM_DEBUG_KMS("Aksv write: no DP_AUX_NATIVE_REPLY_ACK %x\n",
+			      reply);
+		return -EIO;
+	}
+	return 0;
 }
 
 static int intel_dp_hdcp_read_bksv(struct intel_digital_port *intel_dig_port,
-- 
2.7.4

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[PATCH v4 4/4] drm/i915: Increase timeout for Encrypt status change

[Ramalingam C]

At enable/disable of the HDCP encryption, for encryption status change
we need minimum one frame duration. And we might program this bit any
point(start/End) in the previous frame.

With 20mSec, observed the timeout for change in encryption status.
Since this is not time critical operation and we need to hold on
until the status is changed, fixing the timeout to 50mSec. (Based on
trial and error method!)

v2:
  %s/TIME_FOR_ENCRYPT_STATUS_CHANGE/ENCRYPT_STATUS_CHANGE_TIMEOUT_MS
	[Sean Paul]

Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
Reviewed-by: Sean Paul <sean@poorly.run>
---
 drivers/gpu/drm/i915/intel_hdcp.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_hdcp.c b/drivers/gpu/drm/i915/intel_hdcp.c
index 1e5a1e07e343..e000e54ad569 100644
--- a/drivers/gpu/drm/i915/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/intel_hdcp.c
@@ -15,6 +15,7 @@
 #include "i915_reg.h"
 
 #define KEY_LOAD_TRIES	5
+#define ENCRYPT_STATUS_CHANGE_TIMEOUT_MS	50
 
 static
 bool intel_hdcp_is_ksv_valid(u8 *ksv)
@@ -637,7 +638,8 @@ static int intel_hdcp_auth(struct intel_digital_port *intel_dig_port,
 
 	/* Wait for encryption confirmation */
 	if (intel_wait_for_register(dev_priv, PORT_HDCP_STATUS(port),
-				    HDCP_STATUS_ENC, HDCP_STATUS_ENC, 20)) {
+				    HDCP_STATUS_ENC, HDCP_STATUS_ENC,
+				    ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) {
 		DRM_ERROR("Timed out waiting for encryption\n");
 		return -ETIMEDOUT;
 	}
@@ -667,7 +669,7 @@ static int _intel_hdcp_disable(struct intel_connector *connector)
 
 	I915_WRITE(PORT_HDCP_CONF(port), 0);
 	if (intel_wait_for_register(dev_priv, PORT_HDCP_STATUS(port), ~0, 0,
-				    20)) {
+				    ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) {
 		DRM_ERROR("Failed to disable HDCP, timeout clearing status\n");
 		return -ETIMEDOUT;
 	}
-- 
2.7.4

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Re: [PATCH v4 0/4] HDCP1.4 Fixes - II

[Daniel Vetter]

On Wed, Dec 05, 2018 at 05:14:39PM +0530, Ramalingam C wrote:
> Couple of more HDCP1.4 fixes on
>   - Key load process for CFL
>   - Encryption status change time
>   - debug log addition
>   - active platform coverage
> 
> v1 and v2 went into old series https://patchwork.freedesktop.org/series/38978/
> as v8 and v9, due to the same series title. Now changed the title.
> 
> v3-->v4:
>   Respining with minor fix on 2nd patch [Ville]

All applied, thanks for patches&organizing the review too.
-Daniel

> 
> Thanks Sean Paul for the reviews.
> 
> Ramalingam C (4):
>   drm/i915: Fix GEN9 HDCP1.4 key load process
>   drm/i915: Fix platform coverage for HDCP1.4
>   drm/i915: debug log for REPLY_ACK missing
>   drm/i915: Increase timeout for Encrypt status change
> 
>  drivers/gpu/drm/i915/intel_dp.c   |  7 ++++++-
>  drivers/gpu/drm/i915/intel_hdcp.c | 16 +++++++++-------
>  2 files changed, 15 insertions(+), 8 deletions(-)
> 
> -- 
> 2.7.4
> 

-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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