[PATCH libdrm 1/7] new syncobj extension v3

[PATCH libdrm 1/7] new syncobj extension v3

[Chunming Zhou]

v2: drop not implemented IOCTLs and flags
v3: add transfer/signal ioctls

Signed-off-by: Chunming Zhou <david1.zhou@amd.com>
Signed-off-by: Christian König <christian.koenig@amd.com>
---
 include/drm/drm.h | 35 +++++++++++++++++++++++++++++++++++
 1 file changed, 35 insertions(+)

diff --git a/include/drm/drm.h b/include/drm/drm.h
index 85c685a2..26f51bca 100644
--- a/include/drm/drm.h
+++ b/include/drm/drm.h
@@ -729,8 +729,18 @@ struct drm_syncobj_handle {
 	__u32 pad;
 };
 
+struct drm_syncobj_transfer {
+        __u32 src_handle;
+        __u32 dst_handle;
+        __u64 src_point;
+        __u64 dst_point;
+        __u32 flags;
+        __u32 pad;
+};
+
 #define DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL (1 << 0)
 #define DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT (1 << 1)
+#define DRM_SYNCOBJ_WAIT_FLAGS_WAIT_AVAILABLE (1 << 2)
 struct drm_syncobj_wait {
 	__u64 handles;
 	/* absolute timeout */
@@ -741,12 +751,31 @@ struct drm_syncobj_wait {
 	__u32 pad;
 };
 
+struct drm_syncobj_timeline_wait {
+        __u64 handles;
+        /* wait on specific timeline point for every handles*/
+        __u64 points;
+        /* absolute timeout */
+        __s64 timeout_nsec;
+        __u32 count_handles;
+        __u32 flags;
+        __u32 first_signaled; /* only valid when not waiting all */
+        __u32 pad;
+};
+
 struct drm_syncobj_array {
 	__u64 handles;
 	__u32 count_handles;
 	__u32 pad;
 };
 
+struct drm_syncobj_timeline_array {
+        __u64 handles;
+        __u64 points;
+        __u32 count_handles;
+        __u32 pad;
+};
+
 /* Query current scanout sequence number */
 struct drm_crtc_get_sequence {
 	__u32 crtc_id;		/* requested crtc_id */
@@ -903,6 +932,12 @@ extern "C" {
 #define DRM_IOCTL_MODE_GET_LEASE	DRM_IOWR(0xC8, struct drm_mode_get_lease)
 #define DRM_IOCTL_MODE_REVOKE_LEASE	DRM_IOWR(0xC9, struct drm_mode_revoke_lease)
 
+#define DRM_IOCTL_SYNCOBJ_TIMELINE_WAIT DRM_IOWR(0xCA, struct drm_syncobj_timeline_wait)
+#define DRM_IOCTL_SYNCOBJ_QUERY         DRM_IOWR(0xCB, struct drm_syncobj_timeline_array)
+#define DRM_IOCTL_SYNCOBJ_TRANSFER	DRM_IOWR(0xCC, struct drm_syncobj_transfer)
+#define DRM_IOCTL_SYNCOBJ_TIMELINE_SIGNAL       DRM_IOWR(0xCD, struct drm_syncobj_timeline_array)
+
+
 /**
  * Device specific ioctls should only be in their respective headers
  * The device specific ioctl range is from 0x40 to 0x9f.
-- 
2.17.1

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH libdrm 3/7] add timeline wait/query ioctl v2

[Chunming Zhou]

v2: drop export/import

Signed-off-by: Chunming Zhou <david1.zhou@amd.com>
---
 xf86drm.c | 44 ++++++++++++++++++++++++++++++++++++++++++++
 xf86drm.h |  6 ++++++
 2 files changed, 50 insertions(+)

diff --git a/xf86drm.c b/xf86drm.c
index 71ad54ba..9816b3b2 100644
--- a/xf86drm.c
+++ b/xf86drm.c
@@ -4277,3 +4277,47 @@ drm_public int drmSyncobjSignal(int fd, const uint32_t *handles,
     ret = drmIoctl(fd, DRM_IOCTL_SYNCOBJ_SIGNAL, &args);
     return ret;
 }
+
+drm_public int drmSyncobjTimelineWait(int fd, uint32_t *handles, uint64_t *points,
+				      unsigned num_handles,
+				      int64_t timeout_nsec, unsigned flags,
+				      uint32_t *first_signaled)
+{
+    struct drm_syncobj_timeline_wait args;
+    int ret;
+
+    memclear(args);
+    args.handles = (uintptr_t)handles;
+    args.points = (uint64_t)(uintptr_t)points;
+    args.timeout_nsec = timeout_nsec;
+    args.count_handles = num_handles;
+    args.flags = flags;
+
+    ret = drmIoctl(fd, DRM_IOCTL_SYNCOBJ_TIMELINE_WAIT, &args);
+    if (ret < 0)
+        return -errno;
+
+    if (first_signaled)
+        *first_signaled = args.first_signaled;
+    return ret;
+}
+
+
+drm_public int drmSyncobjQuery(int fd, uint32_t *handles, uint64_t *points,
+			       uint32_t handle_count)
+{
+    struct drm_syncobj_timeline_array args;
+    int ret;
+
+    memclear(args);
+    args.handles = (uintptr_t)handles;
+    args.points = (uint64_t)(uintptr_t)points;
+    args.count_handles = handle_count;
+
+    ret = drmIoctl(fd, DRM_IOCTL_SYNCOBJ_QUERY, &args);
+    if (ret)
+        return ret;
+    return 0;
+}
+
+
diff --git a/xf86drm.h b/xf86drm.h
index 7773d71a..49a40633 100644
--- a/xf86drm.h
+++ b/xf86drm.h
@@ -875,6 +875,12 @@ extern int drmSyncobjWait(int fd, uint32_t *handles, unsigned num_handles,
 			  uint32_t *first_signaled);
 extern int drmSyncobjReset(int fd, const uint32_t *handles, uint32_t handle_count);
 extern int drmSyncobjSignal(int fd, const uint32_t *handles, uint32_t handle_count);
+extern int drmSyncobjTimelineWait(int fd, uint32_t *handles, uint64_t *points,
+				  unsigned num_handles,
+				  int64_t timeout_nsec, unsigned flags,
+				  uint32_t *first_signaled);
+extern int drmSyncobjQuery(int fd, uint32_t *handles, uint64_t *points,
+			   uint32_t handle_count);
 
 #if defined(__cplusplus)
 }
-- 
2.17.1

_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

[PATCH libdrm 4/7] wrap syncobj timeline query/wait APIs for amdgpu v3

[Chunming Zhou]

v2: symbos are stored in lexical order.
v3: drop export/import and extra query indirection

Signed-off-by: Chunming Zhou <david1.zhou@amd.com>
Signed-off-by: Christian König <christian.koenig@amd.com>
---
 amdgpu/amdgpu-symbol-check |  2 ++
 amdgpu/amdgpu.h            | 39 ++++++++++++++++++++++++++++++++++++++
 amdgpu/amdgpu_cs.c         | 23 ++++++++++++++++++++++
 3 files changed, 64 insertions(+)

diff --git a/amdgpu/amdgpu-symbol-check b/amdgpu/amdgpu-symbol-check
index 6f5e0f95..4553736f 100755
--- a/amdgpu/amdgpu-symbol-check
+++ b/amdgpu/amdgpu-symbol-check
@@ -49,8 +49,10 @@ amdgpu_cs_submit
 amdgpu_cs_submit_raw
 amdgpu_cs_syncobj_export_sync_file
 amdgpu_cs_syncobj_import_sync_file
+amdgpu_cs_syncobj_query
 amdgpu_cs_syncobj_reset
 amdgpu_cs_syncobj_signal
+amdgpu_cs_syncobj_timeline_wait
 amdgpu_cs_syncobj_wait
 amdgpu_cs_wait_fences
 amdgpu_cs_wait_semaphore
diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h
index dc51659a..330658a0 100644
--- a/amdgpu/amdgpu.h
+++ b/amdgpu/amdgpu.h
@@ -1489,6 +1489,45 @@ int amdgpu_cs_syncobj_wait(amdgpu_device_handle dev,
 			   int64_t timeout_nsec, unsigned flags,
 			   uint32_t *first_signaled);
 
+/**
+ *  Wait for one or all sync objects on their points to signal.
+ *
+ * \param   dev	    - \c [in] self-explanatory
+ * \param   handles - \c [in] array of sync object handles
+ * \param   points - \c [in] array of sync points to wait
+ * \param   num_handles - \c [in] self-explanatory
+ * \param   timeout_nsec - \c [in] self-explanatory
+ * \param   flags   - \c [in] a bitmask of DRM_SYNCOBJ_WAIT_FLAGS_*
+ * \param   first_signaled - \c [in] self-explanatory
+ *
+ * \return   0 on success\n
+ *          -ETIME - Timeout
+ *          <0 - Negative POSIX Error code
+ *
+ */
+int amdgpu_cs_syncobj_timeline_wait(amdgpu_device_handle dev,
+				    uint32_t *handles, uint64_t *points,
+				    unsigned num_handles,
+				    int64_t timeout_nsec, unsigned flags,
+				    uint32_t *first_signaled);
+/**
+ *  Query sync objects payloads.
+ *
+ * \param   dev	    - \c [in] self-explanatory
+ * \param   handles - \c [in] array of sync object handles
+ * \param   points - \c [out] array of sync points returned, which presents
+ * syncobj payload.
+ * \param   num_handles - \c [in] self-explanatory
+ *
+ * \return   0 on success\n
+ *          -ETIME - Timeout
+ *          <0 - Negative POSIX Error code
+ *
+ */
+int amdgpu_cs_syncobj_query(amdgpu_device_handle dev,
+			    uint32_t *handles, uint64_t *points,
+			    unsigned num_handles);
+
 /**
  *  Export kernel sync object to shareable fd.
  *
diff --git a/amdgpu/amdgpu_cs.c b/amdgpu/amdgpu_cs.c
index 3b8231aa..e4a547c6 100644
--- a/amdgpu/amdgpu_cs.c
+++ b/amdgpu/amdgpu_cs.c
@@ -661,6 +661,29 @@ drm_public int amdgpu_cs_syncobj_wait(amdgpu_device_handle dev,
 			      flags, first_signaled);
 }
 
+drm_public int amdgpu_cs_syncobj_timeline_wait(amdgpu_device_handle dev,
+					       uint32_t *handles, uint64_t *points,
+					       unsigned num_handles,
+					       int64_t timeout_nsec, unsigned flags,
+					       uint32_t *first_signaled)
+{
+	if (NULL == dev)
+		return -EINVAL;
+
+	return drmSyncobjTimelineWait(dev->fd, handles, points, num_handles,
+				      timeout_nsec, flags, first_signaled);
+}
+
+drm_public int amdgpu_cs_syncobj_query(amdgpu_device_handle dev,
+				       uint32_t *handles, uint64_t *points,
+				       unsigned num_handles)
+{
+	if (NULL == dev)
+		return -EINVAL;
+
+	return drmSyncobjQuery(dev->fd, handles, points, num_handles);
+}
+
 drm_public int amdgpu_cs_export_syncobj(amdgpu_device_handle dev,
 					uint32_t handle,
 					int *shared_fd)
-- 
2.17.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH libdrm 5/7] add timeline signal/transfer ioctls v2

[Chunming Zhou]

v2: use one transfer ioctl

Signed-off-by: Chunming Zhou <david1.zhou@amd.com>
---
 xf86drm.c | 33 +++++++++++++++++++++++++++++++++
 xf86drm.h |  6 ++++++
 2 files changed, 39 insertions(+)

diff --git a/xf86drm.c b/xf86drm.c
index 9816b3b2..2a089616 100644
--- a/xf86drm.c
+++ b/xf86drm.c
@@ -4278,6 +4278,21 @@ drm_public int drmSyncobjSignal(int fd, const uint32_t *handles,
     return ret;
 }
 
+drm_public int drmSyncobjTimelineSignal(int fd, const uint32_t *handles,
+					uint64_t *points, uint32_t handle_count)
+{
+    struct drm_syncobj_timeline_array args;
+    int ret;
+
+    memclear(args);
+    args.handles = (uintptr_t)handles;
+    args.points = (uint64_t)(uintptr_t)points;
+    args.count_handles = handle_count;
+
+    ret = drmIoctl(fd, DRM_IOCTL_SYNCOBJ_TIMELINE_SIGNAL, &args);
+    return ret;
+}
+
 drm_public int drmSyncobjTimelineWait(int fd, uint32_t *handles, uint64_t *points,
 				      unsigned num_handles,
 				      int64_t timeout_nsec, unsigned flags,
@@ -4320,4 +4335,22 @@ drm_public int drmSyncobjQuery(int fd, uint32_t *handles, uint64_t *points,
     return 0;
 }
 
+drm_public int drmSyncobjTransfer(int fd,
+				  uint32_t dst_handle, uint64_t dst_point,
+				  uint32_t src_handle, uint64_t src_point,
+				  uint32_t flags)
+{
+    struct drm_syncobj_transfer args;
+    int ret;
+
+    memclear(args);
+    args.src_handle = src_handle;
+    args.dst_handle = dst_handle;
+    args.src_point = src_point;
+    args.dst_point = dst_point;
+    args.flags = flags;
+
+    ret = drmIoctl(fd, DRM_IOCTL_SYNCOBJ_TRANSFER, &args);
 
+    return ret;
+}
diff --git a/xf86drm.h b/xf86drm.h
index 49a40633..799d9b9e 100644
--- a/xf86drm.h
+++ b/xf86drm.h
@@ -875,12 +875,18 @@ extern int drmSyncobjWait(int fd, uint32_t *handles, unsigned num_handles,
 			  uint32_t *first_signaled);
 extern int drmSyncobjReset(int fd, const uint32_t *handles, uint32_t handle_count);
 extern int drmSyncobjSignal(int fd, const uint32_t *handles, uint32_t handle_count);
+extern int drmSyncobjTimelineSignal(int fd, const uint32_t *handles,
+				    uint64_t *points, uint32_t handle_count);
 extern int drmSyncobjTimelineWait(int fd, uint32_t *handles, uint64_t *points,
 				  unsigned num_handles,
 				  int64_t timeout_nsec, unsigned flags,
 				  uint32_t *first_signaled);
 extern int drmSyncobjQuery(int fd, uint32_t *handles, uint64_t *points,
 			   uint32_t handle_count);
+extern int drmSyncobjTransfer(int fd,
+			      uint32_t dst_handle, uint64_t dst_point,
+			      uint32_t src_handle, uint64_t src_point,
+			      uint32_t flags);
 
 #if defined(__cplusplus)
 }
-- 
2.17.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH libdrm 2/7] addr cs chunk for syncobj timeline

[Chunming Zhou]

Signed-off-by: Chunming Zhou <david1.zhou@amd.com>
---
 include/drm/amdgpu_drm.h | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h
index 1ceec56d..a3c067dd 100644
--- a/include/drm/amdgpu_drm.h
+++ b/include/drm/amdgpu_drm.h
@@ -517,6 +517,8 @@ struct drm_amdgpu_gem_va {
 #define AMDGPU_CHUNK_ID_SYNCOBJ_IN      0x04
 #define AMDGPU_CHUNK_ID_SYNCOBJ_OUT     0x05
 #define AMDGPU_CHUNK_ID_BO_HANDLES      0x06
+#define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT    0x07
+#define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL  0x08
 
 struct drm_amdgpu_cs_chunk {
 	__u32		chunk_id;
@@ -592,6 +594,13 @@ struct drm_amdgpu_cs_chunk_sem {
 	__u32 handle;
 };
 
+struct drm_amdgpu_cs_chunk_syncobj {
+	__u32 handle;
+	__u32 flags;
+	__u64 point;
+};
+
+
 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ	0
 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD	1
 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD	2
-- 
2.17.1

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH libdrm 6/7] expose timeline signal/export/import interfaces v2

[Chunming Zhou]

v2: adapt to new one transfer ioctl

Signed-off-by: Chunming Zhou <david1.zhou@amd.com>
---
 amdgpu/amdgpu-symbol-check |  3 ++
 amdgpu/amdgpu.h            | 51 +++++++++++++++++++++++++++++++
 amdgpu/amdgpu_cs.c         | 62 ++++++++++++++++++++++++++++++++++++++
 3 files changed, 116 insertions(+)

diff --git a/amdgpu/amdgpu-symbol-check b/amdgpu/amdgpu-symbol-check
index 4553736f..255d25e5 100755
--- a/amdgpu/amdgpu-symbol-check
+++ b/amdgpu/amdgpu-symbol-check
@@ -48,10 +48,13 @@ amdgpu_cs_signal_semaphore
 amdgpu_cs_submit
 amdgpu_cs_submit_raw
 amdgpu_cs_syncobj_export_sync_file
+amdgpu_cs_syncobj_export_sync_file2
 amdgpu_cs_syncobj_import_sync_file
+amdgpu_cs_syncobj_import_sync_file2
 amdgpu_cs_syncobj_query
 amdgpu_cs_syncobj_reset
 amdgpu_cs_syncobj_signal
+amdgpu_cs_syncobj_timeline_signal
 amdgpu_cs_syncobj_timeline_wait
 amdgpu_cs_syncobj_wait
 amdgpu_cs_wait_fences
diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h
index 330658a0..5536d2d5 100644
--- a/amdgpu/amdgpu.h
+++ b/amdgpu/amdgpu.h
@@ -1469,6 +1469,23 @@ int amdgpu_cs_syncobj_reset(amdgpu_device_handle dev,
 int amdgpu_cs_syncobj_signal(amdgpu_device_handle dev,
 			     const uint32_t *syncobjs, uint32_t syncobj_count);
 
+/**
+ * Signal kernel timeline sync objects.
+ *
+ * \param dev           - \c [in] device handle
+ * \param syncobjs      - \c [in] array of sync object handles
+ * \param points	- \c [in] array of timeline points
+ * \param syncobj_count - \c [in] number of handles in syncobjs
+ *
+ * \return   0 on success\n
+ *          <0 - Negative POSIX Error code
+ *
+*/
+int amdgpu_cs_syncobj_timeline_signal(amdgpu_device_handle dev,
+				      const uint32_t *syncobjs,
+				      uint64_t *points,
+				      uint32_t syncobj_count);
+
 /**
  *  Wait for one or all sync objects to signal.
  *
@@ -1586,7 +1603,41 @@ int amdgpu_cs_syncobj_export_sync_file(amdgpu_device_handle dev,
 int amdgpu_cs_syncobj_import_sync_file(amdgpu_device_handle dev,
 				       uint32_t syncobj,
 				       int sync_file_fd);
+/**
+ *  Export kernel timeline sync object to a sync_file.
+ *
+ * \param   dev		- \c [in] device handle
+ * \param   syncobj	- \c [in] sync object handle
+ * \param   point	- \c [in] timeline point
+ * \param   flags	- \c [in] flags
+ * \param   sync_file_fd - \c [out] sync_file file descriptor.
+ *
+ * \return   0 on success\n
+ *          <0 - Negative POSIX Error code
+ *
+ */
+int amdgpu_cs_syncobj_export_sync_file2(amdgpu_device_handle dev,
+					uint32_t syncobj,
+					uint64_t point,
+					uint32_t flags,
+					int *sync_file_fd);
 
+/**
+ *  Import kernel timeline sync object from a sync_file.
+ *
+ * \param   dev		- \c [in] device handle
+ * \param   syncobj	- \c [in] sync object handle
+ * \param   point	- \c [in] timeline point
+ * \param   sync_file_fd - \c [in] sync_file file descriptor.
+ *
+ * \return   0 on success\n
+ *          <0 - Negative POSIX Error code
+ *
+ */
+int amdgpu_cs_syncobj_import_sync_file2(amdgpu_device_handle dev,
+					uint32_t syncobj,
+					uint64_t point,
+					int sync_file_fd);
 /**
  * Export an amdgpu fence as a handle (syncobj or fd).
  *
diff --git a/amdgpu/amdgpu_cs.c b/amdgpu/amdgpu_cs.c
index e4a547c6..f9feee60 100644
--- a/amdgpu/amdgpu_cs.c
+++ b/amdgpu/amdgpu_cs.c
@@ -649,6 +649,18 @@ drm_public int amdgpu_cs_syncobj_signal(amdgpu_device_handle dev,
 	return drmSyncobjSignal(dev->fd, syncobjs, syncobj_count);
 }
 
+drm_public int amdgpu_cs_syncobj_timeline_signal(amdgpu_device_handle dev,
+						 const uint32_t *syncobjs,
+						 uint64_t *points,
+						 uint32_t syncobj_count)
+{
+	if (NULL == dev)
+		return -EINVAL;
+
+	return drmSyncobjTimelineSignal(dev->fd, syncobjs,
+					points, syncobj_count);
+}
+
 drm_public int amdgpu_cs_syncobj_wait(amdgpu_device_handle dev,
 				      uint32_t *handles, unsigned num_handles,
 				      int64_t timeout_nsec, unsigned flags,
@@ -724,6 +736,56 @@ drm_public int amdgpu_cs_syncobj_import_sync_file(amdgpu_device_handle dev,
 	return drmSyncobjImportSyncFile(dev->fd, syncobj, sync_file_fd);
 }
 
+drm_public int amdgpu_cs_syncobj_export_sync_file2(amdgpu_device_handle dev,
+						   uint32_t syncobj,
+						   uint64_t point,
+						   uint32_t flags,
+						   int *sync_file_fd)
+{
+	uint32_t binary_handle;
+	int ret;
+
+	if (NULL == dev)
+		return -EINVAL;
+
+	ret = drmSyncobjCreate(dev->fd, 0, &binary_handle);
+	if (ret)
+		return ret;
+
+	ret = drmSyncobjTransfer(dev->fd, binary_handle, 0,
+				 syncobj, point, flags);
+	if (ret)
+		goto out;
+	ret = drmSyncobjExportSyncFile(dev->fd, binary_handle, sync_file_fd);
+out:
+	drmSyncobjDestroy(dev->fd, binary_handle);
+	return ret;
+}
+
+drm_public int amdgpu_cs_syncobj_import_sync_file2(amdgpu_device_handle dev,
+						   uint32_t syncobj,
+						   uint64_t point,
+						   int sync_file_fd)
+{
+	uint32_t binary_handle;
+	int ret;
+
+	if (NULL == dev)
+		return -EINVAL;
+
+	ret = drmSyncobjCreate(dev->fd, 0, &binary_handle);
+	if (ret)
+		return ret;
+	ret = drmSyncobjImportSyncFile(dev->fd, binary_handle, sync_file_fd);
+	if (ret)
+		goto out;
+	ret = drmSyncobjTransfer(dev->fd, syncobj, point,
+				 binary_handle, 0, 0);
+out:
+	drmSyncobjDestroy(dev->fd, binary_handle);
+	return ret;
+}
+
 drm_public int amdgpu_cs_submit_raw(amdgpu_device_handle dev,
 				    amdgpu_context_handle context,
 				    amdgpu_bo_list_handle bo_list_handle,
-- 
2.17.1

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH libdrm 7/7] add syncobj timeline tests v3

[Chunming Zhou]

v2: drop DRM_SYNCOBJ_CREATE_TYPE_TIMELINE, fix timeout calculation,
    fix some warnings
v3: add export/import and cpu signal testing cases

Signed-off-by: Chunming Zhou <david1.zhou@amd.com>
Signed-off-by: Christian König <christian.koenig@amd.com>
---
 tests/amdgpu/Makefile.am     |   3 +-
 tests/amdgpu/amdgpu_test.c   |  12 ++
 tests/amdgpu/amdgpu_test.h   |  21 +++
 tests/amdgpu/meson.build     |   2 +-
 tests/amdgpu/syncobj_tests.c | 290 +++++++++++++++++++++++++++++++++++
 5 files changed, 326 insertions(+), 2 deletions(-)
 create mode 100644 tests/amdgpu/syncobj_tests.c

diff --git a/tests/amdgpu/Makefile.am b/tests/amdgpu/Makefile.am
index 447ff217..d3fbe2bb 100644
--- a/tests/amdgpu/Makefile.am
+++ b/tests/amdgpu/Makefile.am
@@ -33,4 +33,5 @@ amdgpu_test_SOURCES = \
 	vcn_tests.c \
 	uve_ib.h \
 	deadlock_tests.c \
-	vm_tests.c
+	vm_tests.c \
+	syncobj_tests.c
diff --git a/tests/amdgpu/amdgpu_test.c b/tests/amdgpu/amdgpu_test.c
index ebf44098..ff1448f3 100644
--- a/tests/amdgpu/amdgpu_test.c
+++ b/tests/amdgpu/amdgpu_test.c
@@ -56,6 +56,7 @@
 #define UVD_ENC_TESTS_STR "UVD ENC Tests"
 #define DEADLOCK_TESTS_STR "Deadlock Tests"
 #define VM_TESTS_STR "VM Tests"
+#define SYNCOBJ_TIMELINE_TESTS_STR "SYNCOBJ TIMELINE Tests"
 
 /**
  *  Open handles for amdgpu devices
@@ -116,6 +117,12 @@ static CU_SuiteInfo suites[] = {
 		.pCleanupFunc = suite_vm_tests_clean,
 		.pTests = vm_tests,
 	},
+	{
+		.pName = SYNCOBJ_TIMELINE_TESTS_STR,
+		.pInitFunc = suite_syncobj_timeline_tests_init,
+		.pCleanupFunc = suite_syncobj_timeline_tests_clean,
+		.pTests = syncobj_timeline_tests,
+	},
 
 	CU_SUITE_INFO_NULL,
 };
@@ -165,6 +172,11 @@ static Suites_Active_Status suites_active_stat[] = {
 			.pName = VM_TESTS_STR,
 			.pActive = suite_vm_tests_enable,
 		},
+		{
+			.pName = SYNCOBJ_TIMELINE_TESTS_STR,
+			.pActive = suite_syncobj_timeline_tests_enable,
+		},
+
 };
 
 
diff --git a/tests/amdgpu/amdgpu_test.h b/tests/amdgpu/amdgpu_test.h
index af81eea8..24d64b64 100644
--- a/tests/amdgpu/amdgpu_test.h
+++ b/tests/amdgpu/amdgpu_test.h
@@ -194,6 +194,27 @@ CU_BOOL suite_vm_tests_enable(void);
  */
 extern CU_TestInfo vm_tests[];
 
+/**
+ * Initialize syncobj timeline test suite
+ */
+int suite_syncobj_timeline_tests_init();
+
+/**
+ * Deinitialize syncobj timeline test suite
+ */
+int suite_syncobj_timeline_tests_clean();
+
+/**
+ * Decide if the suite is enabled by default or not.
+ */
+CU_BOOL suite_syncobj_timeline_tests_enable(void);
+
+/**
+ * Tests in syncobj timeline test suite
+ */
+extern CU_TestInfo syncobj_timeline_tests[];
+
+
 /**
  * Helper functions
  */
diff --git a/tests/amdgpu/meson.build b/tests/amdgpu/meson.build
index 4c1237c6..3ceec715 100644
--- a/tests/amdgpu/meson.build
+++ b/tests/amdgpu/meson.build
@@ -24,7 +24,7 @@ if dep_cunit.found()
     files(
       'amdgpu_test.c', 'basic_tests.c', 'bo_tests.c', 'cs_tests.c',
       'vce_tests.c', 'uvd_enc_tests.c', 'vcn_tests.c', 'deadlock_tests.c',
-      'vm_tests.c',
+      'vm_tests.c', 'syncobj_tests.c',
     ),
     dependencies : [dep_cunit, dep_threads],
     include_directories : [inc_root, inc_drm, include_directories('../../amdgpu')],
diff --git a/tests/amdgpu/syncobj_tests.c b/tests/amdgpu/syncobj_tests.c
new file mode 100644
index 00000000..a0c627d7
--- /dev/null
+++ b/tests/amdgpu/syncobj_tests.c
@@ -0,0 +1,290 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+*/
+
+#include "CUnit/Basic.h"
+
+#include "amdgpu_test.h"
+#include "amdgpu_drm.h"
+#include "amdgpu_internal.h"
+#include <pthread.h>
+
+static  amdgpu_device_handle device_handle;
+static  uint32_t  major_version;
+static  uint32_t  minor_version;
+
+static void amdgpu_syncobj_timeline_test(void);
+
+CU_BOOL suite_syncobj_timeline_tests_enable(void)
+{
+	return CU_TRUE;
+}
+
+int suite_syncobj_timeline_tests_init(void)
+{
+	int r;
+
+	r = amdgpu_device_initialize(drm_amdgpu[0], &major_version,
+				   &minor_version, &device_handle);
+
+	if (r) {
+		if ((r == -EACCES) && (errno == EACCES))
+			printf("\n\nError:%s. "
+				"Hint:Try to run this test program as root.",
+				strerror(errno));
+		return CUE_SINIT_FAILED;
+	}
+
+	return CUE_SUCCESS;
+}
+
+int suite_syncobj_timeline_tests_clean(void)
+{
+	int r = amdgpu_device_deinitialize(device_handle);
+
+	if (r == 0)
+		return CUE_SUCCESS;
+	else
+		return CUE_SCLEAN_FAILED;
+}
+
+
+CU_TestInfo syncobj_timeline_tests[] = {
+	{ "syncobj timeline test",  amdgpu_syncobj_timeline_test },
+	CU_TEST_INFO_NULL,
+};
+
+#define GFX_COMPUTE_NOP  0xffff1000
+#define SDMA_NOP  0x0
+static int syncobj_command_submission_helper(uint32_t syncobj_handle, bool
+					     wait_or_signal, uint64_t point)
+{
+	amdgpu_context_handle context_handle;
+	amdgpu_bo_handle ib_result_handle;
+	void *ib_result_cpu;
+	uint64_t ib_result_mc_address;
+	struct drm_amdgpu_cs_chunk chunks[2];
+	struct drm_amdgpu_cs_chunk_data chunk_data;
+	struct drm_amdgpu_cs_chunk_syncobj syncobj_data;
+	struct amdgpu_cs_fence fence_status;
+	amdgpu_bo_list_handle bo_list;
+	amdgpu_va_handle va_handle;
+	uint32_t expired, flags;
+	int i, r;
+	uint64_t seq_no;
+	static uint32_t *ptr;
+
+	r = amdgpu_cs_ctx_create(device_handle, &context_handle);
+	CU_ASSERT_EQUAL(r, 0);
+
+	r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096,
+				    AMDGPU_GEM_DOMAIN_GTT, 0,
+				    &ib_result_handle, &ib_result_cpu,
+				    &ib_result_mc_address, &va_handle);
+	CU_ASSERT_EQUAL(r, 0);
+
+	r = amdgpu_get_bo_list(device_handle, ib_result_handle, NULL,
+			       &bo_list);
+	CU_ASSERT_EQUAL(r, 0);
+
+	ptr = ib_result_cpu;
+
+	for (i = 0; i < 16; ++i)
+		ptr[i] = wait_or_signal ? GFX_COMPUTE_NOP: SDMA_NOP;
+
+	chunks[0].chunk_id = AMDGPU_CHUNK_ID_IB;
+	chunks[0].length_dw = sizeof(struct drm_amdgpu_cs_chunk_ib) / 4;
+	chunks[0].chunk_data = (uint64_t)(uintptr_t)&chunk_data;
+	chunk_data.ib_data._pad = 0;
+	chunk_data.ib_data.va_start = ib_result_mc_address;
+	chunk_data.ib_data.ib_bytes = 16 * 4;
+	chunk_data.ib_data.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX :
+		AMDGPU_HW_IP_DMA;
+	chunk_data.ib_data.ip_instance = 0;
+	chunk_data.ib_data.ring = 0;
+	chunk_data.ib_data.flags = 0;
+
+	chunks[1].chunk_id = wait_or_signal ?
+		AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT :
+		AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL;
+	chunks[1].length_dw = sizeof(struct drm_amdgpu_cs_chunk_syncobj) / 4;
+	chunks[1].chunk_data = (uint64_t)(uintptr_t)&syncobj_data;
+	syncobj_data.handle = syncobj_handle;
+	syncobj_data.point = point;
+	syncobj_data.flags = DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT;
+
+	r = amdgpu_cs_submit_raw(device_handle,
+				 context_handle,
+				 bo_list,
+				 2,
+				 chunks,
+				 &seq_no);
+	CU_ASSERT_EQUAL(r, 0);
+
+
+	memset(&fence_status, 0, sizeof(struct amdgpu_cs_fence));
+	fence_status.context = context_handle;
+	fence_status.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX:
+		AMDGPU_HW_IP_DMA;
+	fence_status.ip_instance = 0;
+	fence_status.ring = 0;
+	fence_status.fence = seq_no;
+
+	r = amdgpu_cs_query_fence_status(&fence_status,
+			AMDGPU_TIMEOUT_INFINITE,0, &expired);
+	CU_ASSERT_EQUAL(r, 0);
+
+	r = amdgpu_bo_list_destroy(bo_list);
+	CU_ASSERT_EQUAL(r, 0);
+
+	r = amdgpu_bo_unmap_and_free(ib_result_handle, va_handle,
+				     ib_result_mc_address, 4096);
+	CU_ASSERT_EQUAL(r, 0);
+
+	r = amdgpu_cs_ctx_free(context_handle);
+	CU_ASSERT_EQUAL(r, 0);
+
+	return r;
+}
+
+struct syncobj_point {
+	uint32_t syncobj_handle;
+	uint64_t point;
+};
+
+static void *syncobj_wait(void *data)
+{
+	struct syncobj_point *sp = (struct syncobj_point *)data;
+	int r;
+
+	r = syncobj_command_submission_helper(sp->syncobj_handle, true,
+					      sp->point);
+	CU_ASSERT_EQUAL(r, 0);
+
+	return (void *)(long)r;
+}
+
+static void *syncobj_signal(void *data)
+{
+	struct syncobj_point *sp = (struct syncobj_point *)data;
+	int r;
+
+	r = syncobj_command_submission_helper(sp->syncobj_handle, false,
+					      sp->point);
+	CU_ASSERT_EQUAL(r, 0);
+
+	return (void *)(long)r;
+}
+
+static void amdgpu_syncobj_timeline_test(void)
+{
+	static pthread_t wait_thread;
+	static pthread_t signal_thread;
+	static pthread_t c_thread;
+	struct syncobj_point sp1, sp2, sp3;
+	uint32_t syncobj_handle;
+	uint64_t payload;
+	uint64_t wait_point, signal_point;
+	uint64_t timeout;
+	struct timespec tp;
+	int r, sync_fd;
+	void *tmp;
+
+	r =  amdgpu_cs_create_syncobj2(device_handle, 0, &syncobj_handle);
+	CU_ASSERT_EQUAL(r, 0);
+
+	// wait on point 5
+	sp1.syncobj_handle = syncobj_handle;
+	sp1.point = 5;
+	r = pthread_create(&wait_thread, NULL, syncobj_wait, &sp1);
+	CU_ASSERT_EQUAL(r, 0);
+
+	// signal on point 10
+	sp2.syncobj_handle = syncobj_handle;
+	sp2.point = 10;
+	r = pthread_create(&signal_thread, NULL, syncobj_signal, &sp2);
+	CU_ASSERT_EQUAL(r, 0);
+
+	r = pthread_join(wait_thread, &tmp);
+	CU_ASSERT_EQUAL(r, 0);
+	CU_ASSERT_EQUAL(tmp, 0);
+
+	r = pthread_join(signal_thread, &tmp);
+	CU_ASSERT_EQUAL(r, 0);
+	CU_ASSERT_EQUAL(tmp, 0);
+
+	//query timeline payload
+	r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
+				    &payload, 1);
+	CU_ASSERT_EQUAL(r, 0);
+	CU_ASSERT_EQUAL(payload, 10);
+
+	//signal on point 16
+	sp3.syncobj_handle = syncobj_handle;
+	sp3.point = 16;
+	r = pthread_create(&c_thread, NULL, syncobj_signal, &sp3);
+	CU_ASSERT_EQUAL(r, 0);
+	//CPU wait on point 16
+	wait_point = 16;
+	timeout = 0;
+	clock_gettime(CLOCK_MONOTONIC, &tp);
+	timeout = tp.tv_sec * 1000000000ULL + tp.tv_nsec;
+	timeout += 0x10000000000; //10s
+	r = amdgpu_cs_syncobj_timeline_wait(device_handle, &syncobj_handle,
+					    &wait_point, 1, timeout,
+					    DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL |
+					    DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
+					    NULL);
+
+	CU_ASSERT_EQUAL(r, 0);
+	r = pthread_join(c_thread, &tmp);
+	CU_ASSERT_EQUAL(r, 0);
+	CU_ASSERT_EQUAL(tmp, 0);
+
+	// export point 16 and import to point 18
+	r = amdgpu_cs_syncobj_export_sync_file2(device_handle, syncobj_handle,
+						16,
+						DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
+						&sync_fd);
+	CU_ASSERT_EQUAL(r, 0);
+	r = amdgpu_cs_syncobj_import_sync_file2(device_handle, syncobj_handle,
+						18, sync_fd);
+	CU_ASSERT_EQUAL(r, 0);
+	r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
+				    &payload, 1);
+	CU_ASSERT_EQUAL(r, 0);
+	CU_ASSERT_EQUAL(payload, 18);
+
+	// CPU signal on point 20
+	signal_point = 20;
+	r = amdgpu_cs_syncobj_timeline_signal(device_handle, &syncobj_handle,
+					      &signal_point, 1);
+	CU_ASSERT_EQUAL(r, 0);
+	r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
+				    &payload, 1);
+	CU_ASSERT_EQUAL(r, 0);
+	CU_ASSERT_EQUAL(payload, 20);
+
+	r = amdgpu_cs_destroy_syncobj(device_handle, syncobj_handle);
+	CU_ASSERT_EQUAL(r, 0);
+
+}
-- 
2.17.1

_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

[PATCH libdrm 1/7] add cs chunk for syncobj timeline

[Chunming Zhou]

Signed-off-by: Chunming Zhou <david1.zhou@amd.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
---
 include/drm/amdgpu_drm.h | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h
index d0701ffc..3d0318e6 100644
--- a/include/drm/amdgpu_drm.h
+++ b/include/drm/amdgpu_drm.h
@@ -528,6 +528,8 @@ struct drm_amdgpu_gem_va {
 #define AMDGPU_CHUNK_ID_SYNCOBJ_OUT     0x05
 #define AMDGPU_CHUNK_ID_BO_HANDLES      0x06
 #define AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES	0x07
+#define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT    0x08
+#define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL  0x09
 
 struct drm_amdgpu_cs_chunk {
 	__u32		chunk_id;
@@ -608,6 +610,13 @@ struct drm_amdgpu_cs_chunk_sem {
 	__u32 handle;
 };
 
+struct drm_amdgpu_cs_chunk_syncobj {
+	__u32 handle;
+	__u32 flags;
+	__u64 point;
+};
+
+
 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ	0
 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD	1
 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD	2
-- 
2.17.1

_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

[PATCH libdrm 7/7] add syncobj timeline tests v3

[Chunming Zhou]

v2: drop DRM_SYNCOBJ_CREATE_TYPE_TIMELINE, fix timeout calculation,
    fix some warnings
v3: add export/import and cpu signal testing cases

Signed-off-by: Chunming Zhou <david1.zhou@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
---
 tests/amdgpu/Makefile.am     |   3 +-
 tests/amdgpu/amdgpu_test.c   |  11 ++
 tests/amdgpu/amdgpu_test.h   |  21 +++
 tests/amdgpu/meson.build     |   2 +-
 tests/amdgpu/syncobj_tests.c | 290 +++++++++++++++++++++++++++++++++++
 5 files changed, 325 insertions(+), 2 deletions(-)
 create mode 100644 tests/amdgpu/syncobj_tests.c

diff --git a/tests/amdgpu/Makefile.am b/tests/amdgpu/Makefile.am
index 48278848..920882d0 100644
--- a/tests/amdgpu/Makefile.am
+++ b/tests/amdgpu/Makefile.am
@@ -34,4 +34,5 @@ amdgpu_test_SOURCES = \
 	uve_ib.h \
 	deadlock_tests.c \
 	vm_tests.c	\
-	ras_tests.c
+	ras_tests.c \
+	syncobj_tests.c
diff --git a/tests/amdgpu/amdgpu_test.c b/tests/amdgpu/amdgpu_test.c
index 35c8bf6c..73403fb4 100644
--- a/tests/amdgpu/amdgpu_test.c
+++ b/tests/amdgpu/amdgpu_test.c
@@ -57,6 +57,7 @@
 #define DEADLOCK_TESTS_STR "Deadlock Tests"
 #define VM_TESTS_STR "VM Tests"
 #define RAS_TESTS_STR "RAS Tests"
+#define SYNCOBJ_TIMELINE_TESTS_STR "SYNCOBJ TIMELINE Tests"
 
 /**
  *  Open handles for amdgpu devices
@@ -123,6 +124,12 @@ static CU_SuiteInfo suites[] = {
 		.pCleanupFunc = suite_ras_tests_clean,
 		.pTests = ras_tests,
 	},
+	{
+		.pName = SYNCOBJ_TIMELINE_TESTS_STR,
+		.pInitFunc = suite_syncobj_timeline_tests_init,
+		.pCleanupFunc = suite_syncobj_timeline_tests_clean,
+		.pTests = syncobj_timeline_tests,
+	},
 
 	CU_SUITE_INFO_NULL,
 };
@@ -176,6 +183,10 @@ static Suites_Active_Status suites_active_stat[] = {
 			.pName = RAS_TESTS_STR,
 			.pActive = suite_ras_tests_enable,
 		},
+		{
+			.pName = SYNCOBJ_TIMELINE_TESTS_STR,
+			.pActive = suite_syncobj_timeline_tests_enable,
+		},
 };
 
 
diff --git a/tests/amdgpu/amdgpu_test.h b/tests/amdgpu/amdgpu_test.h
index bcd0bc7e..36675ea3 100644
--- a/tests/amdgpu/amdgpu_test.h
+++ b/tests/amdgpu/amdgpu_test.h
@@ -216,6 +216,27 @@ CU_BOOL suite_ras_tests_enable(void);
 extern CU_TestInfo ras_tests[];
 
 
+/**
+ * Initialize syncobj timeline test suite
+ */
+int suite_syncobj_timeline_tests_init();
+
+/**
+ * Deinitialize syncobj timeline test suite
+ */
+int suite_syncobj_timeline_tests_clean();
+
+/**
+ * Decide if the suite is enabled by default or not.
+ */
+CU_BOOL suite_syncobj_timeline_tests_enable(void);
+
+/**
+ * Tests in syncobj timeline test suite
+ */
+extern CU_TestInfo syncobj_timeline_tests[];
+
+
 /**
  * Helper functions
  */
diff --git a/tests/amdgpu/meson.build b/tests/amdgpu/meson.build
index 95ed9305..1726cb43 100644
--- a/tests/amdgpu/meson.build
+++ b/tests/amdgpu/meson.build
@@ -24,7 +24,7 @@ if dep_cunit.found()
     files(
       'amdgpu_test.c', 'basic_tests.c', 'bo_tests.c', 'cs_tests.c',
       'vce_tests.c', 'uvd_enc_tests.c', 'vcn_tests.c', 'deadlock_tests.c',
-      'vm_tests.c', 'ras_tests.c',
+      'vm_tests.c', 'ras_tests.c', 'syncobj_tests.c',
     ),
     dependencies : [dep_cunit, dep_threads],
     include_directories : [inc_root, inc_drm, include_directories('../../amdgpu')],
diff --git a/tests/amdgpu/syncobj_tests.c b/tests/amdgpu/syncobj_tests.c
new file mode 100644
index 00000000..a0c627d7
--- /dev/null
+++ b/tests/amdgpu/syncobj_tests.c
@@ -0,0 +1,290 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+*/
+
+#include "CUnit/Basic.h"
+
+#include "amdgpu_test.h"
+#include "amdgpu_drm.h"
+#include "amdgpu_internal.h"
+#include <pthread.h>
+
+static  amdgpu_device_handle device_handle;
+static  uint32_t  major_version;
+static  uint32_t  minor_version;
+
+static void amdgpu_syncobj_timeline_test(void);
+
+CU_BOOL suite_syncobj_timeline_tests_enable(void)
+{
+	return CU_TRUE;
+}
+
+int suite_syncobj_timeline_tests_init(void)
+{
+	int r;
+
+	r = amdgpu_device_initialize(drm_amdgpu[0], &major_version,
+				   &minor_version, &device_handle);
+
+	if (r) {
+		if ((r == -EACCES) && (errno == EACCES))
+			printf("\n\nError:%s. "
+				"Hint:Try to run this test program as root.",
+				strerror(errno));
+		return CUE_SINIT_FAILED;
+	}
+
+	return CUE_SUCCESS;
+}
+
+int suite_syncobj_timeline_tests_clean(void)
+{
+	int r = amdgpu_device_deinitialize(device_handle);
+
+	if (r == 0)
+		return CUE_SUCCESS;
+	else
+		return CUE_SCLEAN_FAILED;
+}
+
+
+CU_TestInfo syncobj_timeline_tests[] = {
+	{ "syncobj timeline test",  amdgpu_syncobj_timeline_test },
+	CU_TEST_INFO_NULL,
+};
+
+#define GFX_COMPUTE_NOP  0xffff1000
+#define SDMA_NOP  0x0
+static int syncobj_command_submission_helper(uint32_t syncobj_handle, bool
+					     wait_or_signal, uint64_t point)
+{
+	amdgpu_context_handle context_handle;
+	amdgpu_bo_handle ib_result_handle;
+	void *ib_result_cpu;
+	uint64_t ib_result_mc_address;
+	struct drm_amdgpu_cs_chunk chunks[2];
+	struct drm_amdgpu_cs_chunk_data chunk_data;
+	struct drm_amdgpu_cs_chunk_syncobj syncobj_data;
+	struct amdgpu_cs_fence fence_status;
+	amdgpu_bo_list_handle bo_list;
+	amdgpu_va_handle va_handle;
+	uint32_t expired, flags;
+	int i, r;
+	uint64_t seq_no;
+	static uint32_t *ptr;
+
+	r = amdgpu_cs_ctx_create(device_handle, &context_handle);
+	CU_ASSERT_EQUAL(r, 0);
+
+	r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096,
+				    AMDGPU_GEM_DOMAIN_GTT, 0,
+				    &ib_result_handle, &ib_result_cpu,
+				    &ib_result_mc_address, &va_handle);
+	CU_ASSERT_EQUAL(r, 0);
+
+	r = amdgpu_get_bo_list(device_handle, ib_result_handle, NULL,
+			       &bo_list);
+	CU_ASSERT_EQUAL(r, 0);
+
+	ptr = ib_result_cpu;
+
+	for (i = 0; i < 16; ++i)
+		ptr[i] = wait_or_signal ? GFX_COMPUTE_NOP: SDMA_NOP;
+
+	chunks[0].chunk_id = AMDGPU_CHUNK_ID_IB;
+	chunks[0].length_dw = sizeof(struct drm_amdgpu_cs_chunk_ib) / 4;
+	chunks[0].chunk_data = (uint64_t)(uintptr_t)&chunk_data;
+	chunk_data.ib_data._pad = 0;
+	chunk_data.ib_data.va_start = ib_result_mc_address;
+	chunk_data.ib_data.ib_bytes = 16 * 4;
+	chunk_data.ib_data.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX :
+		AMDGPU_HW_IP_DMA;
+	chunk_data.ib_data.ip_instance = 0;
+	chunk_data.ib_data.ring = 0;
+	chunk_data.ib_data.flags = 0;
+
+	chunks[1].chunk_id = wait_or_signal ?
+		AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT :
+		AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL;
+	chunks[1].length_dw = sizeof(struct drm_amdgpu_cs_chunk_syncobj) / 4;
+	chunks[1].chunk_data = (uint64_t)(uintptr_t)&syncobj_data;
+	syncobj_data.handle = syncobj_handle;
+	syncobj_data.point = point;
+	syncobj_data.flags = DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT;
+
+	r = amdgpu_cs_submit_raw(device_handle,
+				 context_handle,
+				 bo_list,
+				 2,
+				 chunks,
+				 &seq_no);
+	CU_ASSERT_EQUAL(r, 0);
+
+
+	memset(&fence_status, 0, sizeof(struct amdgpu_cs_fence));
+	fence_status.context = context_handle;
+	fence_status.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX:
+		AMDGPU_HW_IP_DMA;
+	fence_status.ip_instance = 0;
+	fence_status.ring = 0;
+	fence_status.fence = seq_no;
+
+	r = amdgpu_cs_query_fence_status(&fence_status,
+			AMDGPU_TIMEOUT_INFINITE,0, &expired);
+	CU_ASSERT_EQUAL(r, 0);
+
+	r = amdgpu_bo_list_destroy(bo_list);
+	CU_ASSERT_EQUAL(r, 0);
+
+	r = amdgpu_bo_unmap_and_free(ib_result_handle, va_handle,
+				     ib_result_mc_address, 4096);
+	CU_ASSERT_EQUAL(r, 0);
+
+	r = amdgpu_cs_ctx_free(context_handle);
+	CU_ASSERT_EQUAL(r, 0);
+
+	return r;
+}
+
+struct syncobj_point {
+	uint32_t syncobj_handle;
+	uint64_t point;
+};
+
+static void *syncobj_wait(void *data)
+{
+	struct syncobj_point *sp = (struct syncobj_point *)data;
+	int r;
+
+	r = syncobj_command_submission_helper(sp->syncobj_handle, true,
+					      sp->point);
+	CU_ASSERT_EQUAL(r, 0);
+
+	return (void *)(long)r;
+}
+
+static void *syncobj_signal(void *data)
+{
+	struct syncobj_point *sp = (struct syncobj_point *)data;
+	int r;
+
+	r = syncobj_command_submission_helper(sp->syncobj_handle, false,
+					      sp->point);
+	CU_ASSERT_EQUAL(r, 0);
+
+	return (void *)(long)r;
+}
+
+static void amdgpu_syncobj_timeline_test(void)
+{
+	static pthread_t wait_thread;
+	static pthread_t signal_thread;
+	static pthread_t c_thread;
+	struct syncobj_point sp1, sp2, sp3;
+	uint32_t syncobj_handle;
+	uint64_t payload;
+	uint64_t wait_point, signal_point;
+	uint64_t timeout;
+	struct timespec tp;
+	int r, sync_fd;
+	void *tmp;
+
+	r =  amdgpu_cs_create_syncobj2(device_handle, 0, &syncobj_handle);
+	CU_ASSERT_EQUAL(r, 0);
+
+	// wait on point 5
+	sp1.syncobj_handle = syncobj_handle;
+	sp1.point = 5;
+	r = pthread_create(&wait_thread, NULL, syncobj_wait, &sp1);
+	CU_ASSERT_EQUAL(r, 0);
+
+	// signal on point 10
+	sp2.syncobj_handle = syncobj_handle;
+	sp2.point = 10;
+	r = pthread_create(&signal_thread, NULL, syncobj_signal, &sp2);
+	CU_ASSERT_EQUAL(r, 0);
+
+	r = pthread_join(wait_thread, &tmp);
+	CU_ASSERT_EQUAL(r, 0);
+	CU_ASSERT_EQUAL(tmp, 0);
+
+	r = pthread_join(signal_thread, &tmp);
+	CU_ASSERT_EQUAL(r, 0);
+	CU_ASSERT_EQUAL(tmp, 0);
+
+	//query timeline payload
+	r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
+				    &payload, 1);
+	CU_ASSERT_EQUAL(r, 0);
+	CU_ASSERT_EQUAL(payload, 10);
+
+	//signal on point 16
+	sp3.syncobj_handle = syncobj_handle;
+	sp3.point = 16;
+	r = pthread_create(&c_thread, NULL, syncobj_signal, &sp3);
+	CU_ASSERT_EQUAL(r, 0);
+	//CPU wait on point 16
+	wait_point = 16;
+	timeout = 0;
+	clock_gettime(CLOCK_MONOTONIC, &tp);
+	timeout = tp.tv_sec * 1000000000ULL + tp.tv_nsec;
+	timeout += 0x10000000000; //10s
+	r = amdgpu_cs_syncobj_timeline_wait(device_handle, &syncobj_handle,
+					    &wait_point, 1, timeout,
+					    DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL |
+					    DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
+					    NULL);
+
+	CU_ASSERT_EQUAL(r, 0);
+	r = pthread_join(c_thread, &tmp);
+	CU_ASSERT_EQUAL(r, 0);
+	CU_ASSERT_EQUAL(tmp, 0);
+
+	// export point 16 and import to point 18
+	r = amdgpu_cs_syncobj_export_sync_file2(device_handle, syncobj_handle,
+						16,
+						DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
+						&sync_fd);
+	CU_ASSERT_EQUAL(r, 0);
+	r = amdgpu_cs_syncobj_import_sync_file2(device_handle, syncobj_handle,
+						18, sync_fd);
+	CU_ASSERT_EQUAL(r, 0);
+	r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
+				    &payload, 1);
+	CU_ASSERT_EQUAL(r, 0);
+	CU_ASSERT_EQUAL(payload, 18);
+
+	// CPU signal on point 20
+	signal_point = 20;
+	r = amdgpu_cs_syncobj_timeline_signal(device_handle, &syncobj_handle,
+					      &signal_point, 1);
+	CU_ASSERT_EQUAL(r, 0);
+	r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
+				    &payload, 1);
+	CU_ASSERT_EQUAL(r, 0);
+	CU_ASSERT_EQUAL(payload, 20);
+
+	r = amdgpu_cs_destroy_syncobj(device_handle, syncobj_handle);
+	CU_ASSERT_EQUAL(r, 0);
+
+}
-- 
2.17.1

_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

Re: [PATCH libdrm 7/7] add syncobj timeline tests v3

[zhoucm1]

I was able to push changes to libdrm, but now seems after libdrm is 
migrated to gitlab, I cannot yet. What step do I need to get back my 
permission? I already can login into gitlab with old freedesktop account.

@Christian, Can you help submit this patch set to libdrm first?


Thanks,

-David


On 2019年05月16日 16:07, Chunming Zhou wrote:
> v2: drop DRM_SYNCOBJ_CREATE_TYPE_TIMELINE, fix timeout calculation,
>      fix some warnings
> v3: add export/import and cpu signal testing cases
>
> Signed-off-by: Chunming Zhou <david1.zhou@amd.com>
> Acked-by: Christian König <christian.koenig@amd.com>
> Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
> ---
>   tests/amdgpu/Makefile.am     |   3 +-
>   tests/amdgpu/amdgpu_test.c   |  11 ++
>   tests/amdgpu/amdgpu_test.h   |  21 +++
>   tests/amdgpu/meson.build     |   2 +-
>   tests/amdgpu/syncobj_tests.c | 290 +++++++++++++++++++++++++++++++++++
>   5 files changed, 325 insertions(+), 2 deletions(-)
>   create mode 100644 tests/amdgpu/syncobj_tests.c
>
> diff --git a/tests/amdgpu/Makefile.am b/tests/amdgpu/Makefile.am
> index 48278848..920882d0 100644
> --- a/tests/amdgpu/Makefile.am
> +++ b/tests/amdgpu/Makefile.am
> @@ -34,4 +34,5 @@ amdgpu_test_SOURCES = \
>   	uve_ib.h \
>   	deadlock_tests.c \
>   	vm_tests.c	\
> -	ras_tests.c
> +	ras_tests.c \
> +	syncobj_tests.c
> diff --git a/tests/amdgpu/amdgpu_test.c b/tests/amdgpu/amdgpu_test.c
> index 35c8bf6c..73403fb4 100644
> --- a/tests/amdgpu/amdgpu_test.c
> +++ b/tests/amdgpu/amdgpu_test.c
> @@ -57,6 +57,7 @@
>   #define DEADLOCK_TESTS_STR "Deadlock Tests"
>   #define VM_TESTS_STR "VM Tests"
>   #define RAS_TESTS_STR "RAS Tests"
> +#define SYNCOBJ_TIMELINE_TESTS_STR "SYNCOBJ TIMELINE Tests"
>   
>   /**
>    *  Open handles for amdgpu devices
> @@ -123,6 +124,12 @@ static CU_SuiteInfo suites[] = {
>   		.pCleanupFunc = suite_ras_tests_clean,
>   		.pTests = ras_tests,
>   	},
> +	{
> +		.pName = SYNCOBJ_TIMELINE_TESTS_STR,
> +		.pInitFunc = suite_syncobj_timeline_tests_init,
> +		.pCleanupFunc = suite_syncobj_timeline_tests_clean,
> +		.pTests = syncobj_timeline_tests,
> +	},
>   
>   	CU_SUITE_INFO_NULL,
>   };
> @@ -176,6 +183,10 @@ static Suites_Active_Status suites_active_stat[] = {
>   			.pName = RAS_TESTS_STR,
>   			.pActive = suite_ras_tests_enable,
>   		},
> +		{
> +			.pName = SYNCOBJ_TIMELINE_TESTS_STR,
> +			.pActive = suite_syncobj_timeline_tests_enable,
> +		},
>   };
>   
>   
> diff --git a/tests/amdgpu/amdgpu_test.h b/tests/amdgpu/amdgpu_test.h
> index bcd0bc7e..36675ea3 100644
> --- a/tests/amdgpu/amdgpu_test.h
> +++ b/tests/amdgpu/amdgpu_test.h
> @@ -216,6 +216,27 @@ CU_BOOL suite_ras_tests_enable(void);
>   extern CU_TestInfo ras_tests[];
>   
>   
> +/**
> + * Initialize syncobj timeline test suite
> + */
> +int suite_syncobj_timeline_tests_init();
> +
> +/**
> + * Deinitialize syncobj timeline test suite
> + */
> +int suite_syncobj_timeline_tests_clean();
> +
> +/**
> + * Decide if the suite is enabled by default or not.
> + */
> +CU_BOOL suite_syncobj_timeline_tests_enable(void);
> +
> +/**
> + * Tests in syncobj timeline test suite
> + */
> +extern CU_TestInfo syncobj_timeline_tests[];
> +
> +
>   /**
>    * Helper functions
>    */
> diff --git a/tests/amdgpu/meson.build b/tests/amdgpu/meson.build
> index 95ed9305..1726cb43 100644
> --- a/tests/amdgpu/meson.build
> +++ b/tests/amdgpu/meson.build
> @@ -24,7 +24,7 @@ if dep_cunit.found()
>       files(
>         'amdgpu_test.c', 'basic_tests.c', 'bo_tests.c', 'cs_tests.c',
>         'vce_tests.c', 'uvd_enc_tests.c', 'vcn_tests.c', 'deadlock_tests.c',
> -      'vm_tests.c', 'ras_tests.c',
> +      'vm_tests.c', 'ras_tests.c', 'syncobj_tests.c',
>       ),
>       dependencies : [dep_cunit, dep_threads],
>       include_directories : [inc_root, inc_drm, include_directories('../../amdgpu')],
> diff --git a/tests/amdgpu/syncobj_tests.c b/tests/amdgpu/syncobj_tests.c
> new file mode 100644
> index 00000000..a0c627d7
> --- /dev/null
> +++ b/tests/amdgpu/syncobj_tests.c
> @@ -0,0 +1,290 @@
> +/*
> + * Copyright 2017 Advanced Micro Devices, Inc.
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
> + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + *
> +*/
> +
> +#include "CUnit/Basic.h"
> +
> +#include "amdgpu_test.h"
> +#include "amdgpu_drm.h"
> +#include "amdgpu_internal.h"
> +#include <pthread.h>
> +
> +static  amdgpu_device_handle device_handle;
> +static  uint32_t  major_version;
> +static  uint32_t  minor_version;
> +
> +static void amdgpu_syncobj_timeline_test(void);
> +
> +CU_BOOL suite_syncobj_timeline_tests_enable(void)
> +{
> +	return CU_TRUE;
> +}
> +
> +int suite_syncobj_timeline_tests_init(void)
> +{
> +	int r;
> +
> +	r = amdgpu_device_initialize(drm_amdgpu[0], &major_version,
> +				   &minor_version, &device_handle);
> +
> +	if (r) {
> +		if ((r == -EACCES) && (errno == EACCES))
> +			printf("\n\nError:%s. "
> +				"Hint:Try to run this test program as root.",
> +				strerror(errno));
> +		return CUE_SINIT_FAILED;
> +	}
> +
> +	return CUE_SUCCESS;
> +}
> +
> +int suite_syncobj_timeline_tests_clean(void)
> +{
> +	int r = amdgpu_device_deinitialize(device_handle);
> +
> +	if (r == 0)
> +		return CUE_SUCCESS;
> +	else
> +		return CUE_SCLEAN_FAILED;
> +}
> +
> +
> +CU_TestInfo syncobj_timeline_tests[] = {
> +	{ "syncobj timeline test",  amdgpu_syncobj_timeline_test },
> +	CU_TEST_INFO_NULL,
> +};
> +
> +#define GFX_COMPUTE_NOP  0xffff1000
> +#define SDMA_NOP  0x0
> +static int syncobj_command_submission_helper(uint32_t syncobj_handle, bool
> +					     wait_or_signal, uint64_t point)
> +{
> +	amdgpu_context_handle context_handle;
> +	amdgpu_bo_handle ib_result_handle;
> +	void *ib_result_cpu;
> +	uint64_t ib_result_mc_address;
> +	struct drm_amdgpu_cs_chunk chunks[2];
> +	struct drm_amdgpu_cs_chunk_data chunk_data;
> +	struct drm_amdgpu_cs_chunk_syncobj syncobj_data;
> +	struct amdgpu_cs_fence fence_status;
> +	amdgpu_bo_list_handle bo_list;
> +	amdgpu_va_handle va_handle;
> +	uint32_t expired, flags;
> +	int i, r;
> +	uint64_t seq_no;
> +	static uint32_t *ptr;
> +
> +	r = amdgpu_cs_ctx_create(device_handle, &context_handle);
> +	CU_ASSERT_EQUAL(r, 0);
> +
> +	r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096,
> +				    AMDGPU_GEM_DOMAIN_GTT, 0,
> +				    &ib_result_handle, &ib_result_cpu,
> +				    &ib_result_mc_address, &va_handle);
> +	CU_ASSERT_EQUAL(r, 0);
> +
> +	r = amdgpu_get_bo_list(device_handle, ib_result_handle, NULL,
> +			       &bo_list);
> +	CU_ASSERT_EQUAL(r, 0);
> +
> +	ptr = ib_result_cpu;
> +
> +	for (i = 0; i < 16; ++i)
> +		ptr[i] = wait_or_signal ? GFX_COMPUTE_NOP: SDMA_NOP;
> +
> +	chunks[0].chunk_id = AMDGPU_CHUNK_ID_IB;
> +	chunks[0].length_dw = sizeof(struct drm_amdgpu_cs_chunk_ib) / 4;
> +	chunks[0].chunk_data = (uint64_t)(uintptr_t)&chunk_data;
> +	chunk_data.ib_data._pad = 0;
> +	chunk_data.ib_data.va_start = ib_result_mc_address;
> +	chunk_data.ib_data.ib_bytes = 16 * 4;
> +	chunk_data.ib_data.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX :
> +		AMDGPU_HW_IP_DMA;
> +	chunk_data.ib_data.ip_instance = 0;
> +	chunk_data.ib_data.ring = 0;
> +	chunk_data.ib_data.flags = 0;
> +
> +	chunks[1].chunk_id = wait_or_signal ?
> +		AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT :
> +		AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL;
> +	chunks[1].length_dw = sizeof(struct drm_amdgpu_cs_chunk_syncobj) / 4;
> +	chunks[1].chunk_data = (uint64_t)(uintptr_t)&syncobj_data;
> +	syncobj_data.handle = syncobj_handle;
> +	syncobj_data.point = point;
> +	syncobj_data.flags = DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT;
> +
> +	r = amdgpu_cs_submit_raw(device_handle,
> +				 context_handle,
> +				 bo_list,
> +				 2,
> +				 chunks,
> +				 &seq_no);
> +	CU_ASSERT_EQUAL(r, 0);
> +
> +
> +	memset(&fence_status, 0, sizeof(struct amdgpu_cs_fence));
> +	fence_status.context = context_handle;
> +	fence_status.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX:
> +		AMDGPU_HW_IP_DMA;
> +	fence_status.ip_instance = 0;
> +	fence_status.ring = 0;
> +	fence_status.fence = seq_no;
> +
> +	r = amdgpu_cs_query_fence_status(&fence_status,
> +			AMDGPU_TIMEOUT_INFINITE,0, &expired);
> +	CU_ASSERT_EQUAL(r, 0);
> +
> +	r = amdgpu_bo_list_destroy(bo_list);
> +	CU_ASSERT_EQUAL(r, 0);
> +
> +	r = amdgpu_bo_unmap_and_free(ib_result_handle, va_handle,
> +				     ib_result_mc_address, 4096);
> +	CU_ASSERT_EQUAL(r, 0);
> +
> +	r = amdgpu_cs_ctx_free(context_handle);
> +	CU_ASSERT_EQUAL(r, 0);
> +
> +	return r;
> +}
> +
> +struct syncobj_point {
> +	uint32_t syncobj_handle;
> +	uint64_t point;
> +};
> +
> +static void *syncobj_wait(void *data)
> +{
> +	struct syncobj_point *sp = (struct syncobj_point *)data;
> +	int r;
> +
> +	r = syncobj_command_submission_helper(sp->syncobj_handle, true,
> +					      sp->point);
> +	CU_ASSERT_EQUAL(r, 0);
> +
> +	return (void *)(long)r;
> +}
> +
> +static void *syncobj_signal(void *data)
> +{
> +	struct syncobj_point *sp = (struct syncobj_point *)data;
> +	int r;
> +
> +	r = syncobj_command_submission_helper(sp->syncobj_handle, false,
> +					      sp->point);
> +	CU_ASSERT_EQUAL(r, 0);
> +
> +	return (void *)(long)r;
> +}
> +
> +static void amdgpu_syncobj_timeline_test(void)
> +{
> +	static pthread_t wait_thread;
> +	static pthread_t signal_thread;
> +	static pthread_t c_thread;
> +	struct syncobj_point sp1, sp2, sp3;
> +	uint32_t syncobj_handle;
> +	uint64_t payload;
> +	uint64_t wait_point, signal_point;
> +	uint64_t timeout;
> +	struct timespec tp;
> +	int r, sync_fd;
> +	void *tmp;
> +
> +	r =  amdgpu_cs_create_syncobj2(device_handle, 0, &syncobj_handle);
> +	CU_ASSERT_EQUAL(r, 0);
> +
> +	// wait on point 5
> +	sp1.syncobj_handle = syncobj_handle;
> +	sp1.point = 5;
> +	r = pthread_create(&wait_thread, NULL, syncobj_wait, &sp1);
> +	CU_ASSERT_EQUAL(r, 0);
> +
> +	// signal on point 10
> +	sp2.syncobj_handle = syncobj_handle;
> +	sp2.point = 10;
> +	r = pthread_create(&signal_thread, NULL, syncobj_signal, &sp2);
> +	CU_ASSERT_EQUAL(r, 0);
> +
> +	r = pthread_join(wait_thread, &tmp);
> +	CU_ASSERT_EQUAL(r, 0);
> +	CU_ASSERT_EQUAL(tmp, 0);
> +
> +	r = pthread_join(signal_thread, &tmp);
> +	CU_ASSERT_EQUAL(r, 0);
> +	CU_ASSERT_EQUAL(tmp, 0);
> +
> +	//query timeline payload
> +	r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
> +				    &payload, 1);
> +	CU_ASSERT_EQUAL(r, 0);
> +	CU_ASSERT_EQUAL(payload, 10);
> +
> +	//signal on point 16
> +	sp3.syncobj_handle = syncobj_handle;
> +	sp3.point = 16;
> +	r = pthread_create(&c_thread, NULL, syncobj_signal, &sp3);
> +	CU_ASSERT_EQUAL(r, 0);
> +	//CPU wait on point 16
> +	wait_point = 16;
> +	timeout = 0;
> +	clock_gettime(CLOCK_MONOTONIC, &tp);
> +	timeout = tp.tv_sec * 1000000000ULL + tp.tv_nsec;
> +	timeout += 0x10000000000; //10s
> +	r = amdgpu_cs_syncobj_timeline_wait(device_handle, &syncobj_handle,
> +					    &wait_point, 1, timeout,
> +					    DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL |
> +					    DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
> +					    NULL);
> +
> +	CU_ASSERT_EQUAL(r, 0);
> +	r = pthread_join(c_thread, &tmp);
> +	CU_ASSERT_EQUAL(r, 0);
> +	CU_ASSERT_EQUAL(tmp, 0);
> +
> +	// export point 16 and import to point 18
> +	r = amdgpu_cs_syncobj_export_sync_file2(device_handle, syncobj_handle,
> +						16,
> +						DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
> +						&sync_fd);
> +	CU_ASSERT_EQUAL(r, 0);
> +	r = amdgpu_cs_syncobj_import_sync_file2(device_handle, syncobj_handle,
> +						18, sync_fd);
> +	CU_ASSERT_EQUAL(r, 0);
> +	r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
> +				    &payload, 1);
> +	CU_ASSERT_EQUAL(r, 0);
> +	CU_ASSERT_EQUAL(payload, 18);
> +
> +	// CPU signal on point 20
> +	signal_point = 20;
> +	r = amdgpu_cs_syncobj_timeline_signal(device_handle, &syncobj_handle,
> +					      &signal_point, 1);
> +	CU_ASSERT_EQUAL(r, 0);
> +	r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
> +				    &payload, 1);
> +	CU_ASSERT_EQUAL(r, 0);
> +	CU_ASSERT_EQUAL(payload, 20);
> +
> +	r = amdgpu_cs_destroy_syncobj(device_handle, syncobj_handle);
> +	CU_ASSERT_EQUAL(r, 0);
> +
> +}

_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

Re: [PATCH libdrm 7/7] add syncobj timeline tests v3

[Christian König]

Am 16.05.19 um 10:16 schrieb zhoucm1:
> I was able to push changes to libdrm, but now seems after libdrm is 
> migrated to gitlab, I cannot yet. What step do I need to get back my 
> permission? I already can login into gitlab with old freedesktop account.
>
> @Christian, Can you help submit this patch set to libdrm first?

Done. And I think you can now request write permission to a repository 
through the web-interface and all the "owners" of the project can grant 
that to you.

Christian.

>
>
> Thanks,
>
> -David
>
>
> On 2019年05月16日 16:07, Chunming Zhou wrote:
>> v2: drop DRM_SYNCOBJ_CREATE_TYPE_TIMELINE, fix timeout calculation,
>>      fix some warnings
>> v3: add export/import and cpu signal testing cases
>>
>> Signed-off-by: Chunming Zhou <david1.zhou@amd.com>
>> Acked-by: Christian König <christian.koenig@amd.com>
>> Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
>> ---
>>   tests/amdgpu/Makefile.am     |   3 +-
>>   tests/amdgpu/amdgpu_test.c   |  11 ++
>>   tests/amdgpu/amdgpu_test.h   |  21 +++
>>   tests/amdgpu/meson.build     |   2 +-
>>   tests/amdgpu/syncobj_tests.c | 290 +++++++++++++++++++++++++++++++++++
>>   5 files changed, 325 insertions(+), 2 deletions(-)
>>   create mode 100644 tests/amdgpu/syncobj_tests.c
>>
>> diff --git a/tests/amdgpu/Makefile.am b/tests/amdgpu/Makefile.am
>> index 48278848..920882d0 100644
>> --- a/tests/amdgpu/Makefile.am
>> +++ b/tests/amdgpu/Makefile.am
>> @@ -34,4 +34,5 @@ amdgpu_test_SOURCES = \
>>       uve_ib.h \
>>       deadlock_tests.c \
>>       vm_tests.c    \
>> -    ras_tests.c
>> +    ras_tests.c \
>> +    syncobj_tests.c
>> diff --git a/tests/amdgpu/amdgpu_test.c b/tests/amdgpu/amdgpu_test.c
>> index 35c8bf6c..73403fb4 100644
>> --- a/tests/amdgpu/amdgpu_test.c
>> +++ b/tests/amdgpu/amdgpu_test.c
>> @@ -57,6 +57,7 @@
>>   #define DEADLOCK_TESTS_STR "Deadlock Tests"
>>   #define VM_TESTS_STR "VM Tests"
>>   #define RAS_TESTS_STR "RAS Tests"
>> +#define SYNCOBJ_TIMELINE_TESTS_STR "SYNCOBJ TIMELINE Tests"
>>     /**
>>    *  Open handles for amdgpu devices
>> @@ -123,6 +124,12 @@ static CU_SuiteInfo suites[] = {
>>           .pCleanupFunc = suite_ras_tests_clean,
>>           .pTests = ras_tests,
>>       },
>> +    {
>> +        .pName = SYNCOBJ_TIMELINE_TESTS_STR,
>> +        .pInitFunc = suite_syncobj_timeline_tests_init,
>> +        .pCleanupFunc = suite_syncobj_timeline_tests_clean,
>> +        .pTests = syncobj_timeline_tests,
>> +    },
>>         CU_SUITE_INFO_NULL,
>>   };
>> @@ -176,6 +183,10 @@ static Suites_Active_Status suites_active_stat[] 
>> = {
>>               .pName = RAS_TESTS_STR,
>>               .pActive = suite_ras_tests_enable,
>>           },
>> +        {
>> +            .pName = SYNCOBJ_TIMELINE_TESTS_STR,
>> +            .pActive = suite_syncobj_timeline_tests_enable,
>> +        },
>>   };
>>     diff --git a/tests/amdgpu/amdgpu_test.h b/tests/amdgpu/amdgpu_test.h
>> index bcd0bc7e..36675ea3 100644
>> --- a/tests/amdgpu/amdgpu_test.h
>> +++ b/tests/amdgpu/amdgpu_test.h
>> @@ -216,6 +216,27 @@ CU_BOOL suite_ras_tests_enable(void);
>>   extern CU_TestInfo ras_tests[];
>>     +/**
>> + * Initialize syncobj timeline test suite
>> + */
>> +int suite_syncobj_timeline_tests_init();
>> +
>> +/**
>> + * Deinitialize syncobj timeline test suite
>> + */
>> +int suite_syncobj_timeline_tests_clean();
>> +
>> +/**
>> + * Decide if the suite is enabled by default or not.
>> + */
>> +CU_BOOL suite_syncobj_timeline_tests_enable(void);
>> +
>> +/**
>> + * Tests in syncobj timeline test suite
>> + */
>> +extern CU_TestInfo syncobj_timeline_tests[];
>> +
>> +
>>   /**
>>    * Helper functions
>>    */
>> diff --git a/tests/amdgpu/meson.build b/tests/amdgpu/meson.build
>> index 95ed9305..1726cb43 100644
>> --- a/tests/amdgpu/meson.build
>> +++ b/tests/amdgpu/meson.build
>> @@ -24,7 +24,7 @@ if dep_cunit.found()
>>       files(
>>         'amdgpu_test.c', 'basic_tests.c', 'bo_tests.c', 'cs_tests.c',
>>         'vce_tests.c', 'uvd_enc_tests.c', 'vcn_tests.c', 
>> 'deadlock_tests.c',
>> -      'vm_tests.c', 'ras_tests.c',
>> +      'vm_tests.c', 'ras_tests.c', 'syncobj_tests.c',
>>       ),
>>       dependencies : [dep_cunit, dep_threads],
>>       include_directories : [inc_root, inc_drm, 
>> include_directories('../../amdgpu')],
>> diff --git a/tests/amdgpu/syncobj_tests.c b/tests/amdgpu/syncobj_tests.c
>> new file mode 100644
>> index 00000000..a0c627d7
>> --- /dev/null
>> +++ b/tests/amdgpu/syncobj_tests.c
>> @@ -0,0 +1,290 @@
>> +/*
>> + * Copyright 2017 Advanced Micro Devices, Inc.
>> + *
>> + * Permission is hereby granted, free of charge, to any person 
>> obtaining a
>> + * copy of this software and associated documentation files (the 
>> "Software"),
>> + * to deal in the Software without restriction, including without 
>> limitation
>> + * the rights to use, copy, modify, merge, publish, distribute, 
>> sublicense,
>> + * and/or sell copies of the Software, and to permit persons to whom 
>> the
>> + * Software is furnished to do so, subject to the following conditions:
>> + *
>> + * The above copyright notice and this permission notice shall be 
>> included in
>> + * all copies or substantial portions of the Software.
>> + *
>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 
>> EXPRESS OR
>> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 
>> MERCHANTABILITY,
>> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO 
>> EVENT SHALL
>> + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, 
>> DAMAGES OR
>> + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 
>> OTHERWISE,
>> + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 
>> USE OR
>> + * OTHER DEALINGS IN THE SOFTWARE.
>> + *
>> +*/
>> +
>> +#include "CUnit/Basic.h"
>> +
>> +#include "amdgpu_test.h"
>> +#include "amdgpu_drm.h"
>> +#include "amdgpu_internal.h"
>> +#include <pthread.h>
>> +
>> +static  amdgpu_device_handle device_handle;
>> +static  uint32_t  major_version;
>> +static  uint32_t  minor_version;
>> +
>> +static void amdgpu_syncobj_timeline_test(void);
>> +
>> +CU_BOOL suite_syncobj_timeline_tests_enable(void)
>> +{
>> +    return CU_TRUE;
>> +}
>> +
>> +int suite_syncobj_timeline_tests_init(void)
>> +{
>> +    int r;
>> +
>> +    r = amdgpu_device_initialize(drm_amdgpu[0], &major_version,
>> +                   &minor_version, &device_handle);
>> +
>> +    if (r) {
>> +        if ((r == -EACCES) && (errno == EACCES))
>> +            printf("\n\nError:%s. "
>> +                "Hint:Try to run this test program as root.",
>> +                strerror(errno));
>> +        return CUE_SINIT_FAILED;
>> +    }
>> +
>> +    return CUE_SUCCESS;
>> +}
>> +
>> +int suite_syncobj_timeline_tests_clean(void)
>> +{
>> +    int r = amdgpu_device_deinitialize(device_handle);
>> +
>> +    if (r == 0)
>> +        return CUE_SUCCESS;
>> +    else
>> +        return CUE_SCLEAN_FAILED;
>> +}
>> +
>> +
>> +CU_TestInfo syncobj_timeline_tests[] = {
>> +    { "syncobj timeline test",  amdgpu_syncobj_timeline_test },
>> +    CU_TEST_INFO_NULL,
>> +};
>> +
>> +#define GFX_COMPUTE_NOP  0xffff1000
>> +#define SDMA_NOP  0x0
>> +static int syncobj_command_submission_helper(uint32_t 
>> syncobj_handle, bool
>> +                         wait_or_signal, uint64_t point)
>> +{
>> +    amdgpu_context_handle context_handle;
>> +    amdgpu_bo_handle ib_result_handle;
>> +    void *ib_result_cpu;
>> +    uint64_t ib_result_mc_address;
>> +    struct drm_amdgpu_cs_chunk chunks[2];
>> +    struct drm_amdgpu_cs_chunk_data chunk_data;
>> +    struct drm_amdgpu_cs_chunk_syncobj syncobj_data;
>> +    struct amdgpu_cs_fence fence_status;
>> +    amdgpu_bo_list_handle bo_list;
>> +    amdgpu_va_handle va_handle;
>> +    uint32_t expired, flags;
>> +    int i, r;
>> +    uint64_t seq_no;
>> +    static uint32_t *ptr;
>> +
>> +    r = amdgpu_cs_ctx_create(device_handle, &context_handle);
>> +    CU_ASSERT_EQUAL(r, 0);
>> +
>> +    r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096,
>> +                    AMDGPU_GEM_DOMAIN_GTT, 0,
>> +                    &ib_result_handle, &ib_result_cpu,
>> +                    &ib_result_mc_address, &va_handle);
>> +    CU_ASSERT_EQUAL(r, 0);
>> +
>> +    r = amdgpu_get_bo_list(device_handle, ib_result_handle, NULL,
>> +                   &bo_list);
>> +    CU_ASSERT_EQUAL(r, 0);
>> +
>> +    ptr = ib_result_cpu;
>> +
>> +    for (i = 0; i < 16; ++i)
>> +        ptr[i] = wait_or_signal ? GFX_COMPUTE_NOP: SDMA_NOP;
>> +
>> +    chunks[0].chunk_id = AMDGPU_CHUNK_ID_IB;
>> +    chunks[0].length_dw = sizeof(struct drm_amdgpu_cs_chunk_ib) / 4;
>> +    chunks[0].chunk_data = (uint64_t)(uintptr_t)&chunk_data;
>> +    chunk_data.ib_data._pad = 0;
>> +    chunk_data.ib_data.va_start = ib_result_mc_address;
>> +    chunk_data.ib_data.ib_bytes = 16 * 4;
>> +    chunk_data.ib_data.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX :
>> +        AMDGPU_HW_IP_DMA;
>> +    chunk_data.ib_data.ip_instance = 0;
>> +    chunk_data.ib_data.ring = 0;
>> +    chunk_data.ib_data.flags = 0;
>> +
>> +    chunks[1].chunk_id = wait_or_signal ?
>> +        AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT :
>> +        AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL;
>> +    chunks[1].length_dw = sizeof(struct drm_amdgpu_cs_chunk_syncobj) 
>> / 4;
>> +    chunks[1].chunk_data = (uint64_t)(uintptr_t)&syncobj_data;
>> +    syncobj_data.handle = syncobj_handle;
>> +    syncobj_data.point = point;
>> +    syncobj_data.flags = DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT;
>> +
>> +    r = amdgpu_cs_submit_raw(device_handle,
>> +                 context_handle,
>> +                 bo_list,
>> +                 2,
>> +                 chunks,
>> +                 &seq_no);
>> +    CU_ASSERT_EQUAL(r, 0);
>> +
>> +
>> +    memset(&fence_status, 0, sizeof(struct amdgpu_cs_fence));
>> +    fence_status.context = context_handle;
>> +    fence_status.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX:
>> +        AMDGPU_HW_IP_DMA;
>> +    fence_status.ip_instance = 0;
>> +    fence_status.ring = 0;
>> +    fence_status.fence = seq_no;
>> +
>> +    r = amdgpu_cs_query_fence_status(&fence_status,
>> +            AMDGPU_TIMEOUT_INFINITE,0, &expired);
>> +    CU_ASSERT_EQUAL(r, 0);
>> +
>> +    r = amdgpu_bo_list_destroy(bo_list);
>> +    CU_ASSERT_EQUAL(r, 0);
>> +
>> +    r = amdgpu_bo_unmap_and_free(ib_result_handle, va_handle,
>> +                     ib_result_mc_address, 4096);
>> +    CU_ASSERT_EQUAL(r, 0);
>> +
>> +    r = amdgpu_cs_ctx_free(context_handle);
>> +    CU_ASSERT_EQUAL(r, 0);
>> +
>> +    return r;
>> +}
>> +
>> +struct syncobj_point {
>> +    uint32_t syncobj_handle;
>> +    uint64_t point;
>> +};
>> +
>> +static void *syncobj_wait(void *data)
>> +{
>> +    struct syncobj_point *sp = (struct syncobj_point *)data;
>> +    int r;
>> +
>> +    r = syncobj_command_submission_helper(sp->syncobj_handle, true,
>> +                          sp->point);
>> +    CU_ASSERT_EQUAL(r, 0);
>> +
>> +    return (void *)(long)r;
>> +}
>> +
>> +static void *syncobj_signal(void *data)
>> +{
>> +    struct syncobj_point *sp = (struct syncobj_point *)data;
>> +    int r;
>> +
>> +    r = syncobj_command_submission_helper(sp->syncobj_handle, false,
>> +                          sp->point);
>> +    CU_ASSERT_EQUAL(r, 0);
>> +
>> +    return (void *)(long)r;
>> +}
>> +
>> +static void amdgpu_syncobj_timeline_test(void)
>> +{
>> +    static pthread_t wait_thread;
>> +    static pthread_t signal_thread;
>> +    static pthread_t c_thread;
>> +    struct syncobj_point sp1, sp2, sp3;
>> +    uint32_t syncobj_handle;
>> +    uint64_t payload;
>> +    uint64_t wait_point, signal_point;
>> +    uint64_t timeout;
>> +    struct timespec tp;
>> +    int r, sync_fd;
>> +    void *tmp;
>> +
>> +    r =  amdgpu_cs_create_syncobj2(device_handle, 0, &syncobj_handle);
>> +    CU_ASSERT_EQUAL(r, 0);
>> +
>> +    // wait on point 5
>> +    sp1.syncobj_handle = syncobj_handle;
>> +    sp1.point = 5;
>> +    r = pthread_create(&wait_thread, NULL, syncobj_wait, &sp1);
>> +    CU_ASSERT_EQUAL(r, 0);
>> +
>> +    // signal on point 10
>> +    sp2.syncobj_handle = syncobj_handle;
>> +    sp2.point = 10;
>> +    r = pthread_create(&signal_thread, NULL, syncobj_signal, &sp2);
>> +    CU_ASSERT_EQUAL(r, 0);
>> +
>> +    r = pthread_join(wait_thread, &tmp);
>> +    CU_ASSERT_EQUAL(r, 0);
>> +    CU_ASSERT_EQUAL(tmp, 0);
>> +
>> +    r = pthread_join(signal_thread, &tmp);
>> +    CU_ASSERT_EQUAL(r, 0);
>> +    CU_ASSERT_EQUAL(tmp, 0);
>> +
>> +    //query timeline payload
>> +    r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
>> +                    &payload, 1);
>> +    CU_ASSERT_EQUAL(r, 0);
>> +    CU_ASSERT_EQUAL(payload, 10);
>> +
>> +    //signal on point 16
>> +    sp3.syncobj_handle = syncobj_handle;
>> +    sp3.point = 16;
>> +    r = pthread_create(&c_thread, NULL, syncobj_signal, &sp3);
>> +    CU_ASSERT_EQUAL(r, 0);
>> +    //CPU wait on point 16
>> +    wait_point = 16;
>> +    timeout = 0;
>> +    clock_gettime(CLOCK_MONOTONIC, &tp);
>> +    timeout = tp.tv_sec * 1000000000ULL + tp.tv_nsec;
>> +    timeout += 0x10000000000; //10s
>> +    r = amdgpu_cs_syncobj_timeline_wait(device_handle, &syncobj_handle,
>> +                        &wait_point, 1, timeout,
>> +                        DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL |
>> +                        DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
>> +                        NULL);
>> +
>> +    CU_ASSERT_EQUAL(r, 0);
>> +    r = pthread_join(c_thread, &tmp);
>> +    CU_ASSERT_EQUAL(r, 0);
>> +    CU_ASSERT_EQUAL(tmp, 0);
>> +
>> +    // export point 16 and import to point 18
>> +    r = amdgpu_cs_syncobj_export_sync_file2(device_handle, 
>> syncobj_handle,
>> +                        16,
>> +                        DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
>> +                        &sync_fd);
>> +    CU_ASSERT_EQUAL(r, 0);
>> +    r = amdgpu_cs_syncobj_import_sync_file2(device_handle, 
>> syncobj_handle,
>> +                        18, sync_fd);
>> +    CU_ASSERT_EQUAL(r, 0);
>> +    r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
>> +                    &payload, 1);
>> +    CU_ASSERT_EQUAL(r, 0);
>> +    CU_ASSERT_EQUAL(payload, 18);
>> +
>> +    // CPU signal on point 20
>> +    signal_point = 20;
>> +    r = amdgpu_cs_syncobj_timeline_signal(device_handle, 
>> &syncobj_handle,
>> +                          &signal_point, 1);
>> +    CU_ASSERT_EQUAL(r, 0);
>> +    r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
>> +                    &payload, 1);
>> +    CU_ASSERT_EQUAL(r, 0);
>> +    CU_ASSERT_EQUAL(payload, 20);
>> +
>> +    r = amdgpu_cs_destroy_syncobj(device_handle, syncobj_handle);
>> +    CU_ASSERT_EQUAL(r, 0);
>> +
>> +}
>
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel

_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

Re: [PATCH libdrm 7/7] add syncobj timeline tests v3

[zhoucm1]

On 2019年05月16日 18:09, Christian König wrote:
> [CAUTION: External Email]
>
> Am 16.05.19 um 10:16 schrieb zhoucm1:
>> I was able to push changes to libdrm, but now seems after libdrm is
>> migrated to gitlab, I cannot yet. What step do I need to get back my
>> permission? I already can login into gitlab with old freedesktop 
>> account.
>>
>> @Christian, Can you help submit this patch set to libdrm first?
>
> Done. And I think you can now request write permission to a repository
> through the web-interface and all the "owners" of the project can grant
> that to you.
Any guide for that? I failed to find where to request permission.

-David
>
> Christian.
>
>>
>>
>> Thanks,
>>
>> -David
>>
>>
>> On 2019年05月16日 16:07, Chunming Zhou wrote:
>>> v2: drop DRM_SYNCOBJ_CREATE_TYPE_TIMELINE, fix timeout calculation,
>>>      fix some warnings
>>> v3: add export/import and cpu signal testing cases
>>>
>>> Signed-off-by: Chunming Zhou <david1.zhou@amd.com>
>>> Acked-by: Christian König <christian.koenig@amd.com>
>>> Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
>>> ---
>>>   tests/amdgpu/Makefile.am     |   3 +-
>>>   tests/amdgpu/amdgpu_test.c   |  11 ++
>>>   tests/amdgpu/amdgpu_test.h   |  21 +++
>>>   tests/amdgpu/meson.build     |   2 +-
>>>   tests/amdgpu/syncobj_tests.c | 290 
>>> +++++++++++++++++++++++++++++++++++
>>>   5 files changed, 325 insertions(+), 2 deletions(-)
>>>   create mode 100644 tests/amdgpu/syncobj_tests.c
>>>
>>> diff --git a/tests/amdgpu/Makefile.am b/tests/amdgpu/Makefile.am
>>> index 48278848..920882d0 100644
>>> --- a/tests/amdgpu/Makefile.am
>>> +++ b/tests/amdgpu/Makefile.am
>>> @@ -34,4 +34,5 @@ amdgpu_test_SOURCES = \
>>>       uve_ib.h \
>>>       deadlock_tests.c \
>>>       vm_tests.c    \
>>> -    ras_tests.c
>>> +    ras_tests.c \
>>> +    syncobj_tests.c
>>> diff --git a/tests/amdgpu/amdgpu_test.c b/tests/amdgpu/amdgpu_test.c
>>> index 35c8bf6c..73403fb4 100644
>>> --- a/tests/amdgpu/amdgpu_test.c
>>> +++ b/tests/amdgpu/amdgpu_test.c
>>> @@ -57,6 +57,7 @@
>>>   #define DEADLOCK_TESTS_STR "Deadlock Tests"
>>>   #define VM_TESTS_STR "VM Tests"
>>>   #define RAS_TESTS_STR "RAS Tests"
>>> +#define SYNCOBJ_TIMELINE_TESTS_STR "SYNCOBJ TIMELINE Tests"
>>>     /**
>>>    *  Open handles for amdgpu devices
>>> @@ -123,6 +124,12 @@ static CU_SuiteInfo suites[] = {
>>>           .pCleanupFunc = suite_ras_tests_clean,
>>>           .pTests = ras_tests,
>>>       },
>>> +    {
>>> +        .pName = SYNCOBJ_TIMELINE_TESTS_STR,
>>> +        .pInitFunc = suite_syncobj_timeline_tests_init,
>>> +        .pCleanupFunc = suite_syncobj_timeline_tests_clean,
>>> +        .pTests = syncobj_timeline_tests,
>>> +    },
>>>         CU_SUITE_INFO_NULL,
>>>   };
>>> @@ -176,6 +183,10 @@ static Suites_Active_Status suites_active_stat[]
>>> = {
>>>               .pName = RAS_TESTS_STR,
>>>               .pActive = suite_ras_tests_enable,
>>>           },
>>> +        {
>>> +            .pName = SYNCOBJ_TIMELINE_TESTS_STR,
>>> +            .pActive = suite_syncobj_timeline_tests_enable,
>>> +        },
>>>   };
>>>     diff --git a/tests/amdgpu/amdgpu_test.h 
>>> b/tests/amdgpu/amdgpu_test.h
>>> index bcd0bc7e..36675ea3 100644
>>> --- a/tests/amdgpu/amdgpu_test.h
>>> +++ b/tests/amdgpu/amdgpu_test.h
>>> @@ -216,6 +216,27 @@ CU_BOOL suite_ras_tests_enable(void);
>>>   extern CU_TestInfo ras_tests[];
>>>     +/**
>>> + * Initialize syncobj timeline test suite
>>> + */
>>> +int suite_syncobj_timeline_tests_init();
>>> +
>>> +/**
>>> + * Deinitialize syncobj timeline test suite
>>> + */
>>> +int suite_syncobj_timeline_tests_clean();
>>> +
>>> +/**
>>> + * Decide if the suite is enabled by default or not.
>>> + */
>>> +CU_BOOL suite_syncobj_timeline_tests_enable(void);
>>> +
>>> +/**
>>> + * Tests in syncobj timeline test suite
>>> + */
>>> +extern CU_TestInfo syncobj_timeline_tests[];
>>> +
>>> +
>>>   /**
>>>    * Helper functions
>>>    */
>>> diff --git a/tests/amdgpu/meson.build b/tests/amdgpu/meson.build
>>> index 95ed9305..1726cb43 100644
>>> --- a/tests/amdgpu/meson.build
>>> +++ b/tests/amdgpu/meson.build
>>> @@ -24,7 +24,7 @@ if dep_cunit.found()
>>>       files(
>>>         'amdgpu_test.c', 'basic_tests.c', 'bo_tests.c', 'cs_tests.c',
>>>         'vce_tests.c', 'uvd_enc_tests.c', 'vcn_tests.c',
>>> 'deadlock_tests.c',
>>> -      'vm_tests.c', 'ras_tests.c',
>>> +      'vm_tests.c', 'ras_tests.c', 'syncobj_tests.c',
>>>       ),
>>>       dependencies : [dep_cunit, dep_threads],
>>>       include_directories : [inc_root, inc_drm,
>>> include_directories('../../amdgpu')],
>>> diff --git a/tests/amdgpu/syncobj_tests.c 
>>> b/tests/amdgpu/syncobj_tests.c
>>> new file mode 100644
>>> index 00000000..a0c627d7
>>> --- /dev/null
>>> +++ b/tests/amdgpu/syncobj_tests.c
>>> @@ -0,0 +1,290 @@
>>> +/*
>>> + * Copyright 2017 Advanced Micro Devices, Inc.
>>> + *
>>> + * Permission is hereby granted, free of charge, to any person
>>> obtaining a
>>> + * copy of this software and associated documentation files (the
>>> "Software"),
>>> + * to deal in the Software without restriction, including without
>>> limitation
>>> + * the rights to use, copy, modify, merge, publish, distribute,
>>> sublicense,
>>> + * and/or sell copies of the Software, and to permit persons to whom
>>> the
>>> + * Software is furnished to do so, subject to the following 
>>> conditions:
>>> + *
>>> + * The above copyright notice and this permission notice shall be
>>> included in
>>> + * all copies or substantial portions of the Software.
>>> + *
>>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
>>> EXPRESS OR
>>> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
>>> MERCHANTABILITY,
>>> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO
>>> EVENT SHALL
>>> + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM,
>>> DAMAGES OR
>>> + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
>>> OTHERWISE,
>>> + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
>>> USE OR
>>> + * OTHER DEALINGS IN THE SOFTWARE.
>>> + *
>>> +*/
>>> +
>>> +#include "CUnit/Basic.h"
>>> +
>>> +#include "amdgpu_test.h"
>>> +#include "amdgpu_drm.h"
>>> +#include "amdgpu_internal.h"
>>> +#include <pthread.h>
>>> +
>>> +static  amdgpu_device_handle device_handle;
>>> +static  uint32_t  major_version;
>>> +static  uint32_t  minor_version;
>>> +
>>> +static void amdgpu_syncobj_timeline_test(void);
>>> +
>>> +CU_BOOL suite_syncobj_timeline_tests_enable(void)
>>> +{
>>> +    return CU_TRUE;
>>> +}
>>> +
>>> +int suite_syncobj_timeline_tests_init(void)
>>> +{
>>> +    int r;
>>> +
>>> +    r = amdgpu_device_initialize(drm_amdgpu[0], &major_version,
>>> +                   &minor_version, &device_handle);
>>> +
>>> +    if (r) {
>>> +        if ((r == -EACCES) && (errno == EACCES))
>>> +            printf("\n\nError:%s. "
>>> +                "Hint:Try to run this test program as root.",
>>> +                strerror(errno));
>>> +        return CUE_SINIT_FAILED;
>>> +    }
>>> +
>>> +    return CUE_SUCCESS;
>>> +}
>>> +
>>> +int suite_syncobj_timeline_tests_clean(void)
>>> +{
>>> +    int r = amdgpu_device_deinitialize(device_handle);
>>> +
>>> +    if (r == 0)
>>> +        return CUE_SUCCESS;
>>> +    else
>>> +        return CUE_SCLEAN_FAILED;
>>> +}
>>> +
>>> +
>>> +CU_TestInfo syncobj_timeline_tests[] = {
>>> +    { "syncobj timeline test",  amdgpu_syncobj_timeline_test },
>>> +    CU_TEST_INFO_NULL,
>>> +};
>>> +
>>> +#define GFX_COMPUTE_NOP  0xffff1000
>>> +#define SDMA_NOP  0x0
>>> +static int syncobj_command_submission_helper(uint32_t
>>> syncobj_handle, bool
>>> +                         wait_or_signal, uint64_t point)
>>> +{
>>> +    amdgpu_context_handle context_handle;
>>> +    amdgpu_bo_handle ib_result_handle;
>>> +    void *ib_result_cpu;
>>> +    uint64_t ib_result_mc_address;
>>> +    struct drm_amdgpu_cs_chunk chunks[2];
>>> +    struct drm_amdgpu_cs_chunk_data chunk_data;
>>> +    struct drm_amdgpu_cs_chunk_syncobj syncobj_data;
>>> +    struct amdgpu_cs_fence fence_status;
>>> +    amdgpu_bo_list_handle bo_list;
>>> +    amdgpu_va_handle va_handle;
>>> +    uint32_t expired, flags;
>>> +    int i, r;
>>> +    uint64_t seq_no;
>>> +    static uint32_t *ptr;
>>> +
>>> +    r = amdgpu_cs_ctx_create(device_handle, &context_handle);
>>> +    CU_ASSERT_EQUAL(r, 0);
>>> +
>>> +    r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096,
>>> +                    AMDGPU_GEM_DOMAIN_GTT, 0,
>>> +                    &ib_result_handle, &ib_result_cpu,
>>> +                    &ib_result_mc_address, &va_handle);
>>> +    CU_ASSERT_EQUAL(r, 0);
>>> +
>>> +    r = amdgpu_get_bo_list(device_handle, ib_result_handle, NULL,
>>> +                   &bo_list);
>>> +    CU_ASSERT_EQUAL(r, 0);
>>> +
>>> +    ptr = ib_result_cpu;
>>> +
>>> +    for (i = 0; i < 16; ++i)
>>> +        ptr[i] = wait_or_signal ? GFX_COMPUTE_NOP: SDMA_NOP;
>>> +
>>> +    chunks[0].chunk_id = AMDGPU_CHUNK_ID_IB;
>>> +    chunks[0].length_dw = sizeof(struct drm_amdgpu_cs_chunk_ib) / 4;
>>> +    chunks[0].chunk_data = (uint64_t)(uintptr_t)&chunk_data;
>>> +    chunk_data.ib_data._pad = 0;
>>> +    chunk_data.ib_data.va_start = ib_result_mc_address;
>>> +    chunk_data.ib_data.ib_bytes = 16 * 4;
>>> +    chunk_data.ib_data.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX :
>>> +        AMDGPU_HW_IP_DMA;
>>> +    chunk_data.ib_data.ip_instance = 0;
>>> +    chunk_data.ib_data.ring = 0;
>>> +    chunk_data.ib_data.flags = 0;
>>> +
>>> +    chunks[1].chunk_id = wait_or_signal ?
>>> +        AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT :
>>> +        AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL;
>>> +    chunks[1].length_dw = sizeof(struct drm_amdgpu_cs_chunk_syncobj)
>>> / 4;
>>> +    chunks[1].chunk_data = (uint64_t)(uintptr_t)&syncobj_data;
>>> +    syncobj_data.handle = syncobj_handle;
>>> +    syncobj_data.point = point;
>>> +    syncobj_data.flags = DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT;
>>> +
>>> +    r = amdgpu_cs_submit_raw(device_handle,
>>> +                 context_handle,
>>> +                 bo_list,
>>> +                 2,
>>> +                 chunks,
>>> +                 &seq_no);
>>> +    CU_ASSERT_EQUAL(r, 0);
>>> +
>>> +
>>> +    memset(&fence_status, 0, sizeof(struct amdgpu_cs_fence));
>>> +    fence_status.context = context_handle;
>>> +    fence_status.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX:
>>> +        AMDGPU_HW_IP_DMA;
>>> +    fence_status.ip_instance = 0;
>>> +    fence_status.ring = 0;
>>> +    fence_status.fence = seq_no;
>>> +
>>> +    r = amdgpu_cs_query_fence_status(&fence_status,
>>> +            AMDGPU_TIMEOUT_INFINITE,0, &expired);
>>> +    CU_ASSERT_EQUAL(r, 0);
>>> +
>>> +    r = amdgpu_bo_list_destroy(bo_list);
>>> +    CU_ASSERT_EQUAL(r, 0);
>>> +
>>> +    r = amdgpu_bo_unmap_and_free(ib_result_handle, va_handle,
>>> +                     ib_result_mc_address, 4096);
>>> +    CU_ASSERT_EQUAL(r, 0);
>>> +
>>> +    r = amdgpu_cs_ctx_free(context_handle);
>>> +    CU_ASSERT_EQUAL(r, 0);
>>> +
>>> +    return r;
>>> +}
>>> +
>>> +struct syncobj_point {
>>> +    uint32_t syncobj_handle;
>>> +    uint64_t point;
>>> +};
>>> +
>>> +static void *syncobj_wait(void *data)
>>> +{
>>> +    struct syncobj_point *sp = (struct syncobj_point *)data;
>>> +    int r;
>>> +
>>> +    r = syncobj_command_submission_helper(sp->syncobj_handle, true,
>>> +                          sp->point);
>>> +    CU_ASSERT_EQUAL(r, 0);
>>> +
>>> +    return (void *)(long)r;
>>> +}
>>> +
>>> +static void *syncobj_signal(void *data)
>>> +{
>>> +    struct syncobj_point *sp = (struct syncobj_point *)data;
>>> +    int r;
>>> +
>>> +    r = syncobj_command_submission_helper(sp->syncobj_handle, false,
>>> +                          sp->point);
>>> +    CU_ASSERT_EQUAL(r, 0);
>>> +
>>> +    return (void *)(long)r;
>>> +}
>>> +
>>> +static void amdgpu_syncobj_timeline_test(void)
>>> +{
>>> +    static pthread_t wait_thread;
>>> +    static pthread_t signal_thread;
>>> +    static pthread_t c_thread;
>>> +    struct syncobj_point sp1, sp2, sp3;
>>> +    uint32_t syncobj_handle;
>>> +    uint64_t payload;
>>> +    uint64_t wait_point, signal_point;
>>> +    uint64_t timeout;
>>> +    struct timespec tp;
>>> +    int r, sync_fd;
>>> +    void *tmp;
>>> +
>>> +    r =  amdgpu_cs_create_syncobj2(device_handle, 0, &syncobj_handle);
>>> +    CU_ASSERT_EQUAL(r, 0);
>>> +
>>> +    // wait on point 5
>>> +    sp1.syncobj_handle = syncobj_handle;
>>> +    sp1.point = 5;
>>> +    r = pthread_create(&wait_thread, NULL, syncobj_wait, &sp1);
>>> +    CU_ASSERT_EQUAL(r, 0);
>>> +
>>> +    // signal on point 10
>>> +    sp2.syncobj_handle = syncobj_handle;
>>> +    sp2.point = 10;
>>> +    r = pthread_create(&signal_thread, NULL, syncobj_signal, &sp2);
>>> +    CU_ASSERT_EQUAL(r, 0);
>>> +
>>> +    r = pthread_join(wait_thread, &tmp);
>>> +    CU_ASSERT_EQUAL(r, 0);
>>> +    CU_ASSERT_EQUAL(tmp, 0);
>>> +
>>> +    r = pthread_join(signal_thread, &tmp);
>>> +    CU_ASSERT_EQUAL(r, 0);
>>> +    CU_ASSERT_EQUAL(tmp, 0);
>>> +
>>> +    //query timeline payload
>>> +    r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
>>> +                    &payload, 1);
>>> +    CU_ASSERT_EQUAL(r, 0);
>>> +    CU_ASSERT_EQUAL(payload, 10);
>>> +
>>> +    //signal on point 16
>>> +    sp3.syncobj_handle = syncobj_handle;
>>> +    sp3.point = 16;
>>> +    r = pthread_create(&c_thread, NULL, syncobj_signal, &sp3);
>>> +    CU_ASSERT_EQUAL(r, 0);
>>> +    //CPU wait on point 16
>>> +    wait_point = 16;
>>> +    timeout = 0;
>>> +    clock_gettime(CLOCK_MONOTONIC, &tp);
>>> +    timeout = tp.tv_sec * 1000000000ULL + tp.tv_nsec;
>>> +    timeout += 0x10000000000; //10s
>>> +    r = amdgpu_cs_syncobj_timeline_wait(device_handle, 
>>> &syncobj_handle,
>>> +                        &wait_point, 1, timeout,
>>> +                        DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL |
>>> + DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
>>> +                        NULL);
>>> +
>>> +    CU_ASSERT_EQUAL(r, 0);
>>> +    r = pthread_join(c_thread, &tmp);
>>> +    CU_ASSERT_EQUAL(r, 0);
>>> +    CU_ASSERT_EQUAL(tmp, 0);
>>> +
>>> +    // export point 16 and import to point 18
>>> +    r = amdgpu_cs_syncobj_export_sync_file2(device_handle,
>>> syncobj_handle,
>>> +                        16,
>>> + DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
>>> +                        &sync_fd);
>>> +    CU_ASSERT_EQUAL(r, 0);
>>> +    r = amdgpu_cs_syncobj_import_sync_file2(device_handle,
>>> syncobj_handle,
>>> +                        18, sync_fd);
>>> +    CU_ASSERT_EQUAL(r, 0);
>>> +    r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
>>> +                    &payload, 1);
>>> +    CU_ASSERT_EQUAL(r, 0);
>>> +    CU_ASSERT_EQUAL(payload, 18);
>>> +
>>> +    // CPU signal on point 20
>>> +    signal_point = 20;
>>> +    r = amdgpu_cs_syncobj_timeline_signal(device_handle,
>>> &syncobj_handle,
>>> +                          &signal_point, 1);
>>> +    CU_ASSERT_EQUAL(r, 0);
>>> +    r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
>>> +                    &payload, 1);
>>> +    CU_ASSERT_EQUAL(r, 0);
>>> +    CU_ASSERT_EQUAL(payload, 20);
>>> +
>>> +    r = amdgpu_cs_destroy_syncobj(device_handle, syncobj_handle);
>>> +    CU_ASSERT_EQUAL(r, 0);
>>> +
>>> +}
>>
>> _______________________________________________
>> dri-devel mailing list
>> dri-devel@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/dri-devel
>

_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

Re: [PATCH libdrm 7/7] add syncobj timeline tests v3

[Christian König]

Am 16.05.19 um 12:19 schrieb zhoucm1:
>
>
> On 2019年05月16日 18:09, Christian König wrote:
>> [CAUTION: External Email]
>>
>> Am 16.05.19 um 10:16 schrieb zhoucm1:
>>> I was able to push changes to libdrm, but now seems after libdrm is
>>> migrated to gitlab, I cannot yet. What step do I need to get back my
>>> permission? I already can login into gitlab with old freedesktop 
>>> account.
>>>
>>> @Christian, Can you help submit this patch set to libdrm first?
>>
>> Done. And I think you can now request write permission to a repository
>> through the web-interface and all the "owners" of the project can grant
>> that to you.
> Any guide for that? I failed to find where to request permission.

Not of hand. What does the system say when you try to push?

Christian.

>
> -David
>>
>> Christian.
>>
>>>
>>>
>>> Thanks,
>>>
>>> -David
>>>
>>>
>>> On 2019年05月16日 16:07, Chunming Zhou wrote:
>>>> v2: drop DRM_SYNCOBJ_CREATE_TYPE_TIMELINE, fix timeout calculation,
>>>>      fix some warnings
>>>> v3: add export/import and cpu signal testing cases
>>>>
>>>> Signed-off-by: Chunming Zhou <david1.zhou@amd.com>
>>>> Acked-by: Christian König <christian.koenig@amd.com>
>>>> Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
>>>> ---
>>>>   tests/amdgpu/Makefile.am     |   3 +-
>>>>   tests/amdgpu/amdgpu_test.c   |  11 ++
>>>>   tests/amdgpu/amdgpu_test.h   |  21 +++
>>>>   tests/amdgpu/meson.build     |   2 +-
>>>>   tests/amdgpu/syncobj_tests.c | 290 
>>>> +++++++++++++++++++++++++++++++++++
>>>>   5 files changed, 325 insertions(+), 2 deletions(-)
>>>>   create mode 100644 tests/amdgpu/syncobj_tests.c
>>>>
>>>> diff --git a/tests/amdgpu/Makefile.am b/tests/amdgpu/Makefile.am
>>>> index 48278848..920882d0 100644
>>>> --- a/tests/amdgpu/Makefile.am
>>>> +++ b/tests/amdgpu/Makefile.am
>>>> @@ -34,4 +34,5 @@ amdgpu_test_SOURCES = \
>>>>       uve_ib.h \
>>>>       deadlock_tests.c \
>>>>       vm_tests.c    \
>>>> -    ras_tests.c
>>>> +    ras_tests.c \
>>>> +    syncobj_tests.c
>>>> diff --git a/tests/amdgpu/amdgpu_test.c b/tests/amdgpu/amdgpu_test.c
>>>> index 35c8bf6c..73403fb4 100644
>>>> --- a/tests/amdgpu/amdgpu_test.c
>>>> +++ b/tests/amdgpu/amdgpu_test.c
>>>> @@ -57,6 +57,7 @@
>>>>   #define DEADLOCK_TESTS_STR "Deadlock Tests"
>>>>   #define VM_TESTS_STR "VM Tests"
>>>>   #define RAS_TESTS_STR "RAS Tests"
>>>> +#define SYNCOBJ_TIMELINE_TESTS_STR "SYNCOBJ TIMELINE Tests"
>>>>     /**
>>>>    *  Open handles for amdgpu devices
>>>> @@ -123,6 +124,12 @@ static CU_SuiteInfo suites[] = {
>>>>           .pCleanupFunc = suite_ras_tests_clean,
>>>>           .pTests = ras_tests,
>>>>       },
>>>> +    {
>>>> +        .pName = SYNCOBJ_TIMELINE_TESTS_STR,
>>>> +        .pInitFunc = suite_syncobj_timeline_tests_init,
>>>> +        .pCleanupFunc = suite_syncobj_timeline_tests_clean,
>>>> +        .pTests = syncobj_timeline_tests,
>>>> +    },
>>>>         CU_SUITE_INFO_NULL,
>>>>   };
>>>> @@ -176,6 +183,10 @@ static Suites_Active_Status suites_active_stat[]
>>>> = {
>>>>               .pName = RAS_TESTS_STR,
>>>>               .pActive = suite_ras_tests_enable,
>>>>           },
>>>> +        {
>>>> +            .pName = SYNCOBJ_TIMELINE_TESTS_STR,
>>>> +            .pActive = suite_syncobj_timeline_tests_enable,
>>>> +        },
>>>>   };
>>>>     diff --git a/tests/amdgpu/amdgpu_test.h 
>>>> b/tests/amdgpu/amdgpu_test.h
>>>> index bcd0bc7e..36675ea3 100644
>>>> --- a/tests/amdgpu/amdgpu_test.h
>>>> +++ b/tests/amdgpu/amdgpu_test.h
>>>> @@ -216,6 +216,27 @@ CU_BOOL suite_ras_tests_enable(void);
>>>>   extern CU_TestInfo ras_tests[];
>>>>     +/**
>>>> + * Initialize syncobj timeline test suite
>>>> + */
>>>> +int suite_syncobj_timeline_tests_init();
>>>> +
>>>> +/**
>>>> + * Deinitialize syncobj timeline test suite
>>>> + */
>>>> +int suite_syncobj_timeline_tests_clean();
>>>> +
>>>> +/**
>>>> + * Decide if the suite is enabled by default or not.
>>>> + */
>>>> +CU_BOOL suite_syncobj_timeline_tests_enable(void);
>>>> +
>>>> +/**
>>>> + * Tests in syncobj timeline test suite
>>>> + */
>>>> +extern CU_TestInfo syncobj_timeline_tests[];
>>>> +
>>>> +
>>>>   /**
>>>>    * Helper functions
>>>>    */
>>>> diff --git a/tests/amdgpu/meson.build b/tests/amdgpu/meson.build
>>>> index 95ed9305..1726cb43 100644
>>>> --- a/tests/amdgpu/meson.build
>>>> +++ b/tests/amdgpu/meson.build
>>>> @@ -24,7 +24,7 @@ if dep_cunit.found()
>>>>       files(
>>>>         'amdgpu_test.c', 'basic_tests.c', 'bo_tests.c', 'cs_tests.c',
>>>>         'vce_tests.c', 'uvd_enc_tests.c', 'vcn_tests.c',
>>>> 'deadlock_tests.c',
>>>> -      'vm_tests.c', 'ras_tests.c',
>>>> +      'vm_tests.c', 'ras_tests.c', 'syncobj_tests.c',
>>>>       ),
>>>>       dependencies : [dep_cunit, dep_threads],
>>>>       include_directories : [inc_root, inc_drm,
>>>> include_directories('../../amdgpu')],
>>>> diff --git a/tests/amdgpu/syncobj_tests.c 
>>>> b/tests/amdgpu/syncobj_tests.c
>>>> new file mode 100644
>>>> index 00000000..a0c627d7
>>>> --- /dev/null
>>>> +++ b/tests/amdgpu/syncobj_tests.c
>>>> @@ -0,0 +1,290 @@
>>>> +/*
>>>> + * Copyright 2017 Advanced Micro Devices, Inc.
>>>> + *
>>>> + * Permission is hereby granted, free of charge, to any person
>>>> obtaining a
>>>> + * copy of this software and associated documentation files (the
>>>> "Software"),
>>>> + * to deal in the Software without restriction, including without
>>>> limitation
>>>> + * the rights to use, copy, modify, merge, publish, distribute,
>>>> sublicense,
>>>> + * and/or sell copies of the Software, and to permit persons to whom
>>>> the
>>>> + * Software is furnished to do so, subject to the following 
>>>> conditions:
>>>> + *
>>>> + * The above copyright notice and this permission notice shall be
>>>> included in
>>>> + * all copies or substantial portions of the Software.
>>>> + *
>>>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
>>>> EXPRESS OR
>>>> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
>>>> MERCHANTABILITY,
>>>> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO
>>>> EVENT SHALL
>>>> + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM,
>>>> DAMAGES OR
>>>> + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
>>>> OTHERWISE,
>>>> + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
>>>> USE OR
>>>> + * OTHER DEALINGS IN THE SOFTWARE.
>>>> + *
>>>> +*/
>>>> +
>>>> +#include "CUnit/Basic.h"
>>>> +
>>>> +#include "amdgpu_test.h"
>>>> +#include "amdgpu_drm.h"
>>>> +#include "amdgpu_internal.h"
>>>> +#include <pthread.h>
>>>> +
>>>> +static  amdgpu_device_handle device_handle;
>>>> +static  uint32_t  major_version;
>>>> +static  uint32_t  minor_version;
>>>> +
>>>> +static void amdgpu_syncobj_timeline_test(void);
>>>> +
>>>> +CU_BOOL suite_syncobj_timeline_tests_enable(void)
>>>> +{
>>>> +    return CU_TRUE;
>>>> +}
>>>> +
>>>> +int suite_syncobj_timeline_tests_init(void)
>>>> +{
>>>> +    int r;
>>>> +
>>>> +    r = amdgpu_device_initialize(drm_amdgpu[0], &major_version,
>>>> +                   &minor_version, &device_handle);
>>>> +
>>>> +    if (r) {
>>>> +        if ((r == -EACCES) && (errno == EACCES))
>>>> +            printf("\n\nError:%s. "
>>>> +                "Hint:Try to run this test program as root.",
>>>> +                strerror(errno));
>>>> +        return CUE_SINIT_FAILED;
>>>> +    }
>>>> +
>>>> +    return CUE_SUCCESS;
>>>> +}
>>>> +
>>>> +int suite_syncobj_timeline_tests_clean(void)
>>>> +{
>>>> +    int r = amdgpu_device_deinitialize(device_handle);
>>>> +
>>>> +    if (r == 0)
>>>> +        return CUE_SUCCESS;
>>>> +    else
>>>> +        return CUE_SCLEAN_FAILED;
>>>> +}
>>>> +
>>>> +
>>>> +CU_TestInfo syncobj_timeline_tests[] = {
>>>> +    { "syncobj timeline test", amdgpu_syncobj_timeline_test },
>>>> +    CU_TEST_INFO_NULL,
>>>> +};
>>>> +
>>>> +#define GFX_COMPUTE_NOP  0xffff1000
>>>> +#define SDMA_NOP  0x0
>>>> +static int syncobj_command_submission_helper(uint32_t
>>>> syncobj_handle, bool
>>>> +                         wait_or_signal, uint64_t point)
>>>> +{
>>>> +    amdgpu_context_handle context_handle;
>>>> +    amdgpu_bo_handle ib_result_handle;
>>>> +    void *ib_result_cpu;
>>>> +    uint64_t ib_result_mc_address;
>>>> +    struct drm_amdgpu_cs_chunk chunks[2];
>>>> +    struct drm_amdgpu_cs_chunk_data chunk_data;
>>>> +    struct drm_amdgpu_cs_chunk_syncobj syncobj_data;
>>>> +    struct amdgpu_cs_fence fence_status;
>>>> +    amdgpu_bo_list_handle bo_list;
>>>> +    amdgpu_va_handle va_handle;
>>>> +    uint32_t expired, flags;
>>>> +    int i, r;
>>>> +    uint64_t seq_no;
>>>> +    static uint32_t *ptr;
>>>> +
>>>> +    r = amdgpu_cs_ctx_create(device_handle, &context_handle);
>>>> +    CU_ASSERT_EQUAL(r, 0);
>>>> +
>>>> +    r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096,
>>>> +                    AMDGPU_GEM_DOMAIN_GTT, 0,
>>>> +                    &ib_result_handle, &ib_result_cpu,
>>>> +                    &ib_result_mc_address, &va_handle);
>>>> +    CU_ASSERT_EQUAL(r, 0);
>>>> +
>>>> +    r = amdgpu_get_bo_list(device_handle, ib_result_handle, NULL,
>>>> +                   &bo_list);
>>>> +    CU_ASSERT_EQUAL(r, 0);
>>>> +
>>>> +    ptr = ib_result_cpu;
>>>> +
>>>> +    for (i = 0; i < 16; ++i)
>>>> +        ptr[i] = wait_or_signal ? GFX_COMPUTE_NOP: SDMA_NOP;
>>>> +
>>>> +    chunks[0].chunk_id = AMDGPU_CHUNK_ID_IB;
>>>> +    chunks[0].length_dw = sizeof(struct drm_amdgpu_cs_chunk_ib) / 4;
>>>> +    chunks[0].chunk_data = (uint64_t)(uintptr_t)&chunk_data;
>>>> +    chunk_data.ib_data._pad = 0;
>>>> +    chunk_data.ib_data.va_start = ib_result_mc_address;
>>>> +    chunk_data.ib_data.ib_bytes = 16 * 4;
>>>> +    chunk_data.ib_data.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX :
>>>> +        AMDGPU_HW_IP_DMA;
>>>> +    chunk_data.ib_data.ip_instance = 0;
>>>> +    chunk_data.ib_data.ring = 0;
>>>> +    chunk_data.ib_data.flags = 0;
>>>> +
>>>> +    chunks[1].chunk_id = wait_or_signal ?
>>>> +        AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT :
>>>> +        AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL;
>>>> +    chunks[1].length_dw = sizeof(struct drm_amdgpu_cs_chunk_syncobj)
>>>> / 4;
>>>> +    chunks[1].chunk_data = (uint64_t)(uintptr_t)&syncobj_data;
>>>> +    syncobj_data.handle = syncobj_handle;
>>>> +    syncobj_data.point = point;
>>>> +    syncobj_data.flags = DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT;
>>>> +
>>>> +    r = amdgpu_cs_submit_raw(device_handle,
>>>> +                 context_handle,
>>>> +                 bo_list,
>>>> +                 2,
>>>> +                 chunks,
>>>> +                 &seq_no);
>>>> +    CU_ASSERT_EQUAL(r, 0);
>>>> +
>>>> +
>>>> +    memset(&fence_status, 0, sizeof(struct amdgpu_cs_fence));
>>>> +    fence_status.context = context_handle;
>>>> +    fence_status.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX:
>>>> +        AMDGPU_HW_IP_DMA;
>>>> +    fence_status.ip_instance = 0;
>>>> +    fence_status.ring = 0;
>>>> +    fence_status.fence = seq_no;
>>>> +
>>>> +    r = amdgpu_cs_query_fence_status(&fence_status,
>>>> +            AMDGPU_TIMEOUT_INFINITE,0, &expired);
>>>> +    CU_ASSERT_EQUAL(r, 0);
>>>> +
>>>> +    r = amdgpu_bo_list_destroy(bo_list);
>>>> +    CU_ASSERT_EQUAL(r, 0);
>>>> +
>>>> +    r = amdgpu_bo_unmap_and_free(ib_result_handle, va_handle,
>>>> +                     ib_result_mc_address, 4096);
>>>> +    CU_ASSERT_EQUAL(r, 0);
>>>> +
>>>> +    r = amdgpu_cs_ctx_free(context_handle);
>>>> +    CU_ASSERT_EQUAL(r, 0);
>>>> +
>>>> +    return r;
>>>> +}
>>>> +
>>>> +struct syncobj_point {
>>>> +    uint32_t syncobj_handle;
>>>> +    uint64_t point;
>>>> +};
>>>> +
>>>> +static void *syncobj_wait(void *data)
>>>> +{
>>>> +    struct syncobj_point *sp = (struct syncobj_point *)data;
>>>> +    int r;
>>>> +
>>>> +    r = syncobj_command_submission_helper(sp->syncobj_handle, true,
>>>> +                          sp->point);
>>>> +    CU_ASSERT_EQUAL(r, 0);
>>>> +
>>>> +    return (void *)(long)r;
>>>> +}
>>>> +
>>>> +static void *syncobj_signal(void *data)
>>>> +{
>>>> +    struct syncobj_point *sp = (struct syncobj_point *)data;
>>>> +    int r;
>>>> +
>>>> +    r = syncobj_command_submission_helper(sp->syncobj_handle, false,
>>>> +                          sp->point);
>>>> +    CU_ASSERT_EQUAL(r, 0);
>>>> +
>>>> +    return (void *)(long)r;
>>>> +}
>>>> +
>>>> +static void amdgpu_syncobj_timeline_test(void)
>>>> +{
>>>> +    static pthread_t wait_thread;
>>>> +    static pthread_t signal_thread;
>>>> +    static pthread_t c_thread;
>>>> +    struct syncobj_point sp1, sp2, sp3;
>>>> +    uint32_t syncobj_handle;
>>>> +    uint64_t payload;
>>>> +    uint64_t wait_point, signal_point;
>>>> +    uint64_t timeout;
>>>> +    struct timespec tp;
>>>> +    int r, sync_fd;
>>>> +    void *tmp;
>>>> +
>>>> +    r =  amdgpu_cs_create_syncobj2(device_handle, 0, 
>>>> &syncobj_handle);
>>>> +    CU_ASSERT_EQUAL(r, 0);
>>>> +
>>>> +    // wait on point 5
>>>> +    sp1.syncobj_handle = syncobj_handle;
>>>> +    sp1.point = 5;
>>>> +    r = pthread_create(&wait_thread, NULL, syncobj_wait, &sp1);
>>>> +    CU_ASSERT_EQUAL(r, 0);
>>>> +
>>>> +    // signal on point 10
>>>> +    sp2.syncobj_handle = syncobj_handle;
>>>> +    sp2.point = 10;
>>>> +    r = pthread_create(&signal_thread, NULL, syncobj_signal, &sp2);
>>>> +    CU_ASSERT_EQUAL(r, 0);
>>>> +
>>>> +    r = pthread_join(wait_thread, &tmp);
>>>> +    CU_ASSERT_EQUAL(r, 0);
>>>> +    CU_ASSERT_EQUAL(tmp, 0);
>>>> +
>>>> +    r = pthread_join(signal_thread, &tmp);
>>>> +    CU_ASSERT_EQUAL(r, 0);
>>>> +    CU_ASSERT_EQUAL(tmp, 0);
>>>> +
>>>> +    //query timeline payload
>>>> +    r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
>>>> +                    &payload, 1);
>>>> +    CU_ASSERT_EQUAL(r, 0);
>>>> +    CU_ASSERT_EQUAL(payload, 10);
>>>> +
>>>> +    //signal on point 16
>>>> +    sp3.syncobj_handle = syncobj_handle;
>>>> +    sp3.point = 16;
>>>> +    r = pthread_create(&c_thread, NULL, syncobj_signal, &sp3);
>>>> +    CU_ASSERT_EQUAL(r, 0);
>>>> +    //CPU wait on point 16
>>>> +    wait_point = 16;
>>>> +    timeout = 0;
>>>> +    clock_gettime(CLOCK_MONOTONIC, &tp);
>>>> +    timeout = tp.tv_sec * 1000000000ULL + tp.tv_nsec;
>>>> +    timeout += 0x10000000000; //10s
>>>> +    r = amdgpu_cs_syncobj_timeline_wait(device_handle, 
>>>> &syncobj_handle,
>>>> +                        &wait_point, 1, timeout,
>>>> +                        DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL |
>>>> + DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
>>>> +                        NULL);
>>>> +
>>>> +    CU_ASSERT_EQUAL(r, 0);
>>>> +    r = pthread_join(c_thread, &tmp);
>>>> +    CU_ASSERT_EQUAL(r, 0);
>>>> +    CU_ASSERT_EQUAL(tmp, 0);
>>>> +
>>>> +    // export point 16 and import to point 18
>>>> +    r = amdgpu_cs_syncobj_export_sync_file2(device_handle,
>>>> syncobj_handle,
>>>> +                        16,
>>>> + DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
>>>> +                        &sync_fd);
>>>> +    CU_ASSERT_EQUAL(r, 0);
>>>> +    r = amdgpu_cs_syncobj_import_sync_file2(device_handle,
>>>> syncobj_handle,
>>>> +                        18, sync_fd);
>>>> +    CU_ASSERT_EQUAL(r, 0);
>>>> +    r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
>>>> +                    &payload, 1);
>>>> +    CU_ASSERT_EQUAL(r, 0);
>>>> +    CU_ASSERT_EQUAL(payload, 18);
>>>> +
>>>> +    // CPU signal on point 20
>>>> +    signal_point = 20;
>>>> +    r = amdgpu_cs_syncobj_timeline_signal(device_handle,
>>>> &syncobj_handle,
>>>> +                          &signal_point, 1);
>>>> +    CU_ASSERT_EQUAL(r, 0);
>>>> +    r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
>>>> +                    &payload, 1);
>>>> +    CU_ASSERT_EQUAL(r, 0);
>>>> +    CU_ASSERT_EQUAL(payload, 20);
>>>> +
>>>> +    r = amdgpu_cs_destroy_syncobj(device_handle, syncobj_handle);
>>>> +    CU_ASSERT_EQUAL(r, 0);
>>>> +
>>>> +}
>>>
>>> _______________________________________________
>>> dri-devel mailing list
>>> dri-devel@lists.freedesktop.org
>>> https://lists.freedesktop.org/mailman/listinfo/dri-devel
>>
>
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel

_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

Re:[PATCH libdrm 7/7] add syncobj timeline tests v3

[Zhou, David(ChunMing)]

[-- Attachment #1.1: Type: text/plain, Size: 17141 bytes --]

It mentioned me I cannot push to gitlab directly. After that, I added my ssh pub to gitlab web, and also added gitlab url to git remote.
then push again, it mentions "connection timeout".

-David

-------- Original Message --------
Subject: Re: [PATCH libdrm 7/7] add syncobj timeline tests v3
From: Christian König
To: "Zhou, David(ChunMing)" ,"Koenig, Christian" ,"Zhou, David(ChunMing)" ,dri-devel@lists.freedesktop.org
CC:

[CAUTION: External Email]

Am 16.05.19 um 12:19 schrieb zhoucm1:
>
>
> On 2019年05月16日 18:09, Christian König wrote:
>> [CAUTION: External Email]
>>
>> Am 16.05.19 um 10:16 schrieb zhoucm1:
>>> I was able to push changes to libdrm, but now seems after libdrm is
>>> migrated to gitlab, I cannot yet. What step do I need to get back my
>>> permission? I already can login into gitlab with old freedesktop
>>> account.
>>>
>>> @Christian, Can you help submit this patch set to libdrm first?
>>
>> Done. And I think you can now request write permission to a repository
>> through the web-interface and all the "owners" of the project can grant
>> that to you.
> Any guide for that? I failed to find where to request permission.

Not of hand. What does the system say when you try to push?

Christian.

>
> -David
>>
>> Christian.
>>
>>>
>>>
>>> Thanks,
>>>
>>> -David
>>>
>>>
>>> On 2019年05月16日 16:07, Chunming Zhou wrote:
>>>> v2: drop DRM_SYNCOBJ_CREATE_TYPE_TIMELINE, fix timeout calculation,
>>>>      fix some warnings
>>>> v3: add export/import and cpu signal testing cases
>>>>
>>>> Signed-off-by: Chunming Zhou <david1.zhou@amd.com>
>>>> Acked-by: Christian König <christian.koenig@amd.com>
>>>> Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
>>>> ---
>>>>   tests/amdgpu/Makefile.am     |   3 +-
>>>>   tests/amdgpu/amdgpu_test.c   |  11 ++
>>>>   tests/amdgpu/amdgpu_test.h   |  21 +++
>>>>   tests/amdgpu/meson.build     |   2 +-
>>>>   tests/amdgpu/syncobj_tests.c | 290
>>>> +++++++++++++++++++++++++++++++++++
>>>>   5 files changed, 325 insertions(+), 2 deletions(-)
>>>>   create mode 100644 tests/amdgpu/syncobj_tests.c
>>>>
>>>> diff --git a/tests/amdgpu/Makefile.am b/tests/amdgpu/Makefile.am
>>>> index 48278848..920882d0 100644
>>>> --- a/tests/amdgpu/Makefile.am
>>>> +++ b/tests/amdgpu/Makefile.am
>>>> @@ -34,4 +34,5 @@ amdgpu_test_SOURCES = \
>>>>       uve_ib.h \
>>>>       deadlock_tests.c \
>>>>       vm_tests.c    \
>>>> -    ras_tests.c
>>>> +    ras_tests.c \
>>>> +    syncobj_tests.c
>>>> diff --git a/tests/amdgpu/amdgpu_test.c b/tests/amdgpu/amdgpu_test.c
>>>> index 35c8bf6c..73403fb4 100644
>>>> --- a/tests/amdgpu/amdgpu_test.c
>>>> +++ b/tests/amdgpu/amdgpu_test.c
>>>> @@ -57,6 +57,7 @@
>>>>   #define DEADLOCK_TESTS_STR "Deadlock Tests"
>>>>   #define VM_TESTS_STR "VM Tests"
>>>>   #define RAS_TESTS_STR "RAS Tests"
>>>> +#define SYNCOBJ_TIMELINE_TESTS_STR "SYNCOBJ TIMELINE Tests"
>>>>     /**
>>>>    *  Open handles for amdgpu devices
>>>> @@ -123,6 +124,12 @@ static CU_SuiteInfo suites[] = {
>>>>           .pCleanupFunc = suite_ras_tests_clean,
>>>>           .pTests = ras_tests,
>>>>       },
>>>> +    {
>>>> +        .pName = SYNCOBJ_TIMELINE_TESTS_STR,
>>>> +        .pInitFunc = suite_syncobj_timeline_tests_init,
>>>> +        .pCleanupFunc = suite_syncobj_timeline_tests_clean,
>>>> +        .pTests = syncobj_timeline_tests,
>>>> +    },
>>>>         CU_SUITE_INFO_NULL,
>>>>   };
>>>> @@ -176,6 +183,10 @@ static Suites_Active_Status suites_active_stat[]
>>>> = {
>>>>               .pName = RAS_TESTS_STR,
>>>>               .pActive = suite_ras_tests_enable,
>>>>           },
>>>> +        {
>>>> +            .pName = SYNCOBJ_TIMELINE_TESTS_STR,
>>>> +            .pActive = suite_syncobj_timeline_tests_enable,
>>>> +        },
>>>>   };
>>>>     diff --git a/tests/amdgpu/amdgpu_test.h
>>>> b/tests/amdgpu/amdgpu_test.h
>>>> index bcd0bc7e..36675ea3 100644
>>>> --- a/tests/amdgpu/amdgpu_test.h
>>>> +++ b/tests/amdgpu/amdgpu_test.h
>>>> @@ -216,6 +216,27 @@ CU_BOOL suite_ras_tests_enable(void);
>>>>   extern CU_TestInfo ras_tests[];
>>>>     +/**
>>>> + * Initialize syncobj timeline test suite
>>>> + */
>>>> +int suite_syncobj_timeline_tests_init();
>>>> +
>>>> +/**
>>>> + * Deinitialize syncobj timeline test suite
>>>> + */
>>>> +int suite_syncobj_timeline_tests_clean();
>>>> +
>>>> +/**
>>>> + * Decide if the suite is enabled by default or not.
>>>> + */
>>>> +CU_BOOL suite_syncobj_timeline_tests_enable(void);
>>>> +
>>>> +/**
>>>> + * Tests in syncobj timeline test suite
>>>> + */
>>>> +extern CU_TestInfo syncobj_timeline_tests[];
>>>> +
>>>> +
>>>>   /**
>>>>    * Helper functions
>>>>    */
>>>> diff --git a/tests/amdgpu/meson.build b/tests/amdgpu/meson.build
>>>> index 95ed9305..1726cb43 100644
>>>> --- a/tests/amdgpu/meson.build
>>>> +++ b/tests/amdgpu/meson.build
>>>> @@ -24,7 +24,7 @@ if dep_cunit.found()
>>>>       files(
>>>>         'amdgpu_test.c', 'basic_tests.c', 'bo_tests.c', 'cs_tests.c',
>>>>         'vce_tests.c', 'uvd_enc_tests.c', 'vcn_tests.c',
>>>> 'deadlock_tests.c',
>>>> -      'vm_tests.c', 'ras_tests.c',
>>>> +      'vm_tests.c', 'ras_tests.c', 'syncobj_tests.c',
>>>>       ),
>>>>       dependencies : [dep_cunit, dep_threads],
>>>>       include_directories : [inc_root, inc_drm,
>>>> include_directories('../../amdgpu')],
>>>> diff --git a/tests/amdgpu/syncobj_tests.c
>>>> b/tests/amdgpu/syncobj_tests.c
>>>> new file mode 100644
>>>> index 00000000..a0c627d7
>>>> --- /dev/null
>>>> +++ b/tests/amdgpu/syncobj_tests.c
>>>> @@ -0,0 +1,290 @@
>>>> +/*
>>>> + * Copyright 2017 Advanced Micro Devices, Inc.
>>>> + *
>>>> + * Permission is hereby granted, free of charge, to any person
>>>> obtaining a
>>>> + * copy of this software and associated documentation files (the
>>>> "Software"),
>>>> + * to deal in the Software without restriction, including without
>>>> limitation
>>>> + * the rights to use, copy, modify, merge, publish, distribute,
>>>> sublicense,
>>>> + * and/or sell copies of the Software, and to permit persons to whom
>>>> the
>>>> + * Software is furnished to do so, subject to the following
>>>> conditions:
>>>> + *
>>>> + * The above copyright notice and this permission notice shall be
>>>> included in
>>>> + * all copies or substantial portions of the Software.
>>>> + *
>>>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
>>>> EXPRESS OR
>>>> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
>>>> MERCHANTABILITY,
>>>> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO
>>>> EVENT SHALL
>>>> + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM,
>>>> DAMAGES OR
>>>> + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
>>>> OTHERWISE,
>>>> + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
>>>> USE OR
>>>> + * OTHER DEALINGS IN THE SOFTWARE.
>>>> + *
>>>> +*/
>>>> +
>>>> +#include "CUnit/Basic.h"
>>>> +
>>>> +#include "amdgpu_test.h"
>>>> +#include "amdgpu_drm.h"
>>>> +#include "amdgpu_internal.h"
>>>> +#include <pthread.h>
>>>> +
>>>> +static  amdgpu_device_handle device_handle;
>>>> +static  uint32_t  major_version;
>>>> +static  uint32_t  minor_version;
>>>> +
>>>> +static void amdgpu_syncobj_timeline_test(void);
>>>> +
>>>> +CU_BOOL suite_syncobj_timeline_tests_enable(void)
>>>> +{
>>>> +    return CU_TRUE;
>>>> +}
>>>> +
>>>> +int suite_syncobj_timeline_tests_init(void)
>>>> +{
>>>> +    int r;
>>>> +
>>>> +    r = amdgpu_device_initialize(drm_amdgpu[0], &major_version,
>>>> +                   &minor_version, &device_handle);
>>>> +
>>>> +    if (r) {
>>>> +        if ((r == -EACCES) && (errno == EACCES))
>>>> +            printf("\n\nError:%s. "
>>>> +                "Hint:Try to run this test program as root.",
>>>> +                strerror(errno));
>>>> +        return CUE_SINIT_FAILED;
>>>> +    }
>>>> +
>>>> +    return CUE_SUCCESS;
>>>> +}
>>>> +
>>>> +int suite_syncobj_timeline_tests_clean(void)
>>>> +{
>>>> +    int r = amdgpu_device_deinitialize(device_handle);
>>>> +
>>>> +    if (r == 0)
>>>> +        return CUE_SUCCESS;
>>>> +    else
>>>> +        return CUE_SCLEAN_FAILED;
>>>> +}
>>>> +
>>>> +
>>>> +CU_TestInfo syncobj_timeline_tests[] = {
>>>> +    { "syncobj timeline test", amdgpu_syncobj_timeline_test },
>>>> +    CU_TEST_INFO_NULL,
>>>> +};
>>>> +
>>>> +#define GFX_COMPUTE_NOP  0xffff1000
>>>> +#define SDMA_NOP  0x0
>>>> +static int syncobj_command_submission_helper(uint32_t
>>>> syncobj_handle, bool
>>>> +                         wait_or_signal, uint64_t point)
>>>> +{
>>>> +    amdgpu_context_handle context_handle;
>>>> +    amdgpu_bo_handle ib_result_handle;
>>>> +    void *ib_result_cpu;
>>>> +    uint64_t ib_result_mc_address;
>>>> +    struct drm_amdgpu_cs_chunk chunks[2];
>>>> +    struct drm_amdgpu_cs_chunk_data chunk_data;
>>>> +    struct drm_amdgpu_cs_chunk_syncobj syncobj_data;
>>>> +    struct amdgpu_cs_fence fence_status;
>>>> +    amdgpu_bo_list_handle bo_list;
>>>> +    amdgpu_va_handle va_handle;
>>>> +    uint32_t expired, flags;
>>>> +    int i, r;
>>>> +    uint64_t seq_no;
>>>> +    static uint32_t *ptr;
>>>> +
>>>> +    r = amdgpu_cs_ctx_create(device_handle, &context_handle);
>>>> +    CU_ASSERT_EQUAL(r, 0);
>>>> +
>>>> +    r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096,
>>>> +                    AMDGPU_GEM_DOMAIN_GTT, 0,
>>>> +                    &ib_result_handle, &ib_result_cpu,
>>>> +                    &ib_result_mc_address, &va_handle);
>>>> +    CU_ASSERT_EQUAL(r, 0);
>>>> +
>>>> +    r = amdgpu_get_bo_list(device_handle, ib_result_handle, NULL,
>>>> +                   &bo_list);
>>>> +    CU_ASSERT_EQUAL(r, 0);
>>>> +
>>>> +    ptr = ib_result_cpu;
>>>> +
>>>> +    for (i = 0; i < 16; ++i)
>>>> +        ptr[i] = wait_or_signal ? GFX_COMPUTE_NOP: SDMA_NOP;
>>>> +
>>>> +    chunks[0].chunk_id = AMDGPU_CHUNK_ID_IB;
>>>> +    chunks[0].length_dw = sizeof(struct drm_amdgpu_cs_chunk_ib) / 4;
>>>> +    chunks[0].chunk_data = (uint64_t)(uintptr_t)&chunk_data;
>>>> +    chunk_data.ib_data._pad = 0;
>>>> +    chunk_data.ib_data.va_start = ib_result_mc_address;
>>>> +    chunk_data.ib_data.ib_bytes = 16 * 4;
>>>> +    chunk_data.ib_data.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX :
>>>> +        AMDGPU_HW_IP_DMA;
>>>> +    chunk_data.ib_data.ip_instance = 0;
>>>> +    chunk_data.ib_data.ring = 0;
>>>> +    chunk_data.ib_data.flags = 0;
>>>> +
>>>> +    chunks[1].chunk_id = wait_or_signal ?
>>>> +        AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT :
>>>> +        AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL;
>>>> +    chunks[1].length_dw = sizeof(struct drm_amdgpu_cs_chunk_syncobj)
>>>> / 4;
>>>> +    chunks[1].chunk_data = (uint64_t)(uintptr_t)&syncobj_data;
>>>> +    syncobj_data.handle = syncobj_handle;
>>>> +    syncobj_data.point = point;
>>>> +    syncobj_data.flags = DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT;
>>>> +
>>>> +    r = amdgpu_cs_submit_raw(device_handle,
>>>> +                 context_handle,
>>>> +                 bo_list,
>>>> +                 2,
>>>> +                 chunks,
>>>> +                 &seq_no);
>>>> +    CU_ASSERT_EQUAL(r, 0);
>>>> +
>>>> +
>>>> +    memset(&fence_status, 0, sizeof(struct amdgpu_cs_fence));
>>>> +    fence_status.context = context_handle;
>>>> +    fence_status.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX:
>>>> +        AMDGPU_HW_IP_DMA;
>>>> +    fence_status.ip_instance = 0;
>>>> +    fence_status.ring = 0;
>>>> +    fence_status.fence = seq_no;
>>>> +
>>>> +    r = amdgpu_cs_query_fence_status(&fence_status,
>>>> +            AMDGPU_TIMEOUT_INFINITE,0, &expired);
>>>> +    CU_ASSERT_EQUAL(r, 0);
>>>> +
>>>> +    r = amdgpu_bo_list_destroy(bo_list);
>>>> +    CU_ASSERT_EQUAL(r, 0);
>>>> +
>>>> +    r = amdgpu_bo_unmap_and_free(ib_result_handle, va_handle,
>>>> +                     ib_result_mc_address, 4096);
>>>> +    CU_ASSERT_EQUAL(r, 0);
>>>> +
>>>> +    r = amdgpu_cs_ctx_free(context_handle);
>>>> +    CU_ASSERT_EQUAL(r, 0);
>>>> +
>>>> +    return r;
>>>> +}
>>>> +
>>>> +struct syncobj_point {
>>>> +    uint32_t syncobj_handle;
>>>> +    uint64_t point;
>>>> +};
>>>> +
>>>> +static void *syncobj_wait(void *data)
>>>> +{
>>>> +    struct syncobj_point *sp = (struct syncobj_point *)data;
>>>> +    int r;
>>>> +
>>>> +    r = syncobj_command_submission_helper(sp->syncobj_handle, true,
>>>> +                          sp->point);
>>>> +    CU_ASSERT_EQUAL(r, 0);
>>>> +
>>>> +    return (void *)(long)r;
>>>> +}
>>>> +
>>>> +static void *syncobj_signal(void *data)
>>>> +{
>>>> +    struct syncobj_point *sp = (struct syncobj_point *)data;
>>>> +    int r;
>>>> +
>>>> +    r = syncobj_command_submission_helper(sp->syncobj_handle, false,
>>>> +                          sp->point);
>>>> +    CU_ASSERT_EQUAL(r, 0);
>>>> +
>>>> +    return (void *)(long)r;
>>>> +}
>>>> +
>>>> +static void amdgpu_syncobj_timeline_test(void)
>>>> +{
>>>> +    static pthread_t wait_thread;
>>>> +    static pthread_t signal_thread;
>>>> +    static pthread_t c_thread;
>>>> +    struct syncobj_point sp1, sp2, sp3;
>>>> +    uint32_t syncobj_handle;
>>>> +    uint64_t payload;
>>>> +    uint64_t wait_point, signal_point;
>>>> +    uint64_t timeout;
>>>> +    struct timespec tp;
>>>> +    int r, sync_fd;
>>>> +    void *tmp;
>>>> +
>>>> +    r =  amdgpu_cs_create_syncobj2(device_handle, 0,
>>>> &syncobj_handle);
>>>> +    CU_ASSERT_EQUAL(r, 0);
>>>> +
>>>> +    // wait on point 5
>>>> +    sp1.syncobj_handle = syncobj_handle;
>>>> +    sp1.point = 5;
>>>> +    r = pthread_create(&wait_thread, NULL, syncobj_wait, &sp1);
>>>> +    CU_ASSERT_EQUAL(r, 0);
>>>> +
>>>> +    // signal on point 10
>>>> +    sp2.syncobj_handle = syncobj_handle;
>>>> +    sp2.point = 10;
>>>> +    r = pthread_create(&signal_thread, NULL, syncobj_signal, &sp2);
>>>> +    CU_ASSERT_EQUAL(r, 0);
>>>> +
>>>> +    r = pthread_join(wait_thread, &tmp);
>>>> +    CU_ASSERT_EQUAL(r, 0);
>>>> +    CU_ASSERT_EQUAL(tmp, 0);
>>>> +
>>>> +    r = pthread_join(signal_thread, &tmp);
>>>> +    CU_ASSERT_EQUAL(r, 0);
>>>> +    CU_ASSERT_EQUAL(tmp, 0);
>>>> +
>>>> +    //query timeline payload
>>>> +    r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
>>>> +                    &payload, 1);
>>>> +    CU_ASSERT_EQUAL(r, 0);
>>>> +    CU_ASSERT_EQUAL(payload, 10);
>>>> +
>>>> +    //signal on point 16
>>>> +    sp3.syncobj_handle = syncobj_handle;
>>>> +    sp3.point = 16;
>>>> +    r = pthread_create(&c_thread, NULL, syncobj_signal, &sp3);
>>>> +    CU_ASSERT_EQUAL(r, 0);
>>>> +    //CPU wait on point 16
>>>> +    wait_point = 16;
>>>> +    timeout = 0;
>>>> +    clock_gettime(CLOCK_MONOTONIC, &tp);
>>>> +    timeout = tp.tv_sec * 1000000000ULL + tp.tv_nsec;
>>>> +    timeout += 0x10000000000; //10s
>>>> +    r = amdgpu_cs_syncobj_timeline_wait(device_handle,
>>>> &syncobj_handle,
>>>> +                        &wait_point, 1, timeout,
>>>> +                        DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL |
>>>> + DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
>>>> +                        NULL);
>>>> +
>>>> +    CU_ASSERT_EQUAL(r, 0);
>>>> +    r = pthread_join(c_thread, &tmp);
>>>> +    CU_ASSERT_EQUAL(r, 0);
>>>> +    CU_ASSERT_EQUAL(tmp, 0);
>>>> +
>>>> +    // export point 16 and import to point 18
>>>> +    r = amdgpu_cs_syncobj_export_sync_file2(device_handle,
>>>> syncobj_handle,
>>>> +                        16,
>>>> + DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
>>>> +                        &sync_fd);
>>>> +    CU_ASSERT_EQUAL(r, 0);
>>>> +    r = amdgpu_cs_syncobj_import_sync_file2(device_handle,
>>>> syncobj_handle,
>>>> +                        18, sync_fd);
>>>> +    CU_ASSERT_EQUAL(r, 0);
>>>> +    r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
>>>> +                    &payload, 1);
>>>> +    CU_ASSERT_EQUAL(r, 0);
>>>> +    CU_ASSERT_EQUAL(payload, 18);
>>>> +
>>>> +    // CPU signal on point 20
>>>> +    signal_point = 20;
>>>> +    r = amdgpu_cs_syncobj_timeline_signal(device_handle,
>>>> &syncobj_handle,
>>>> +                          &signal_point, 1);
>>>> +    CU_ASSERT_EQUAL(r, 0);
>>>> +    r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
>>>> +                    &payload, 1);
>>>> +    CU_ASSERT_EQUAL(r, 0);
>>>> +    CU_ASSERT_EQUAL(payload, 20);
>>>> +
>>>> +    r = amdgpu_cs_destroy_syncobj(device_handle, syncobj_handle);
>>>> +    CU_ASSERT_EQUAL(r, 0);
>>>> +
>>>> +}
>>>
>>> _______________________________________________
>>> dri-devel mailing list
>>> dri-devel@lists.freedesktop.org
>>> https://lists.freedesktop.org/mailman/listinfo/dri-devel
>>
>
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel


[-- Attachment #1.2: Type: text/html, Size: 33645 bytes --]

[-- Attachment #2: Type: text/plain, Size: 159 bytes --]

_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

Re: [PATCH libdrm 7/7] add syncobj timeline tests v3

[Christian König]

[-- Attachment #1.1: Type: text/plain, Size: 19226 bytes --]

Oh, please not that problem again :(

Please just try "ssh gitlab.freedesktop.org" if that also times out like 
this you need to contact AMD network IT and ask why ssh once more 
doesn't work.

Christian.

Am 16.05.19 um 13:43 schrieb Zhou, David(ChunMing):
> It mentioned me I cannot push to gitlab directly. After that, I added 
> my ssh pub to gitlab web, and also added gitlab url to git remote.
> then push again, it mentions "connection timeout".
>
> -David
>
> -------- Original Message --------
> Subject: Re: [PATCH libdrm 7/7] add syncobj timeline tests v3
> From: Christian König
> To: "Zhou, David(ChunMing)" ,"Koenig, Christian" ,"Zhou, 
> David(ChunMing)" ,dri-devel@lists.freedesktop.org
> CC:
>
> [CAUTION: External Email]
>
> Am 16.05.19 um 12:19 schrieb zhoucm1:
> >
> >
> > On 2019年05月16日 18:09, Christian König wrote:
> >> [CAUTION: External Email]
> >>
> >> Am 16.05.19 um 10:16 schrieb zhoucm1:
> >>> I was able to push changes to libdrm, but now seems after libdrm is
> >>> migrated to gitlab, I cannot yet. What step do I need to get back my
> >>> permission? I already can login into gitlab with old freedesktop
> >>> account.
> >>>
> >>> @Christian, Can you help submit this patch set to libdrm first?
> >>
> >> Done. And I think you can now request write permission to a repository
> >> through the web-interface and all the "owners" of the project can grant
> >> that to you.
> > Any guide for that? I failed to find where to request permission.
>
> Not of hand. What does the system say when you try to push?
>
> Christian.
>
> >
> > -David
> >>
> >> Christian.
> >>
> >>>
> >>>
> >>> Thanks,
> >>>
> >>> -David
> >>>
> >>>
> >>> On 2019年05月16日 16:07, Chunming Zhou wrote:
> >>>> v2: drop DRM_SYNCOBJ_CREATE_TYPE_TIMELINE, fix timeout calculation,
> >>>>      fix some warnings
> >>>> v3: add export/import and cpu signal testing cases
> >>>>
> >>>> Signed-off-by: Chunming Zhou <david1.zhou@amd.com>
> >>>> Acked-by: Christian König <christian.koenig@amd.com>
> >>>> Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
> >>>> ---
> >>>>   tests/amdgpu/Makefile.am     |   3 +-
> >>>>   tests/amdgpu/amdgpu_test.c   |  11 ++
> >>>>   tests/amdgpu/amdgpu_test.h   |  21 +++
> >>>>   tests/amdgpu/meson.build     |   2 +-
> >>>>   tests/amdgpu/syncobj_tests.c | 290
> >>>> +++++++++++++++++++++++++++++++++++
> >>>>   5 files changed, 325 insertions(+), 2 deletions(-)
> >>>>   create mode 100644 tests/amdgpu/syncobj_tests.c
> >>>>
> >>>> diff --git a/tests/amdgpu/Makefile.am b/tests/amdgpu/Makefile.am
> >>>> index 48278848..920882d0 100644
> >>>> --- a/tests/amdgpu/Makefile.am
> >>>> +++ b/tests/amdgpu/Makefile.am
> >>>> @@ -34,4 +34,5 @@ amdgpu_test_SOURCES = \
> >>>>       uve_ib.h \
> >>>>       deadlock_tests.c \
> >>>>       vm_tests.c    \
> >>>> -    ras_tests.c
> >>>> +    ras_tests.c \
> >>>> +    syncobj_tests.c
> >>>> diff --git a/tests/amdgpu/amdgpu_test.c b/tests/amdgpu/amdgpu_test.c
> >>>> index 35c8bf6c..73403fb4 100644
> >>>> --- a/tests/amdgpu/amdgpu_test.c
> >>>> +++ b/tests/amdgpu/amdgpu_test.c
> >>>> @@ -57,6 +57,7 @@
> >>>>   #define DEADLOCK_TESTS_STR "Deadlock Tests"
> >>>>   #define VM_TESTS_STR "VM Tests"
> >>>>   #define RAS_TESTS_STR "RAS Tests"
> >>>> +#define SYNCOBJ_TIMELINE_TESTS_STR "SYNCOBJ TIMELINE Tests"
> >>>>     /**
> >>>>    *  Open handles for amdgpu devices
> >>>> @@ -123,6 +124,12 @@ static CU_SuiteInfo suites[] = {
> >>>>           .pCleanupFunc = suite_ras_tests_clean,
> >>>>           .pTests = ras_tests,
> >>>>       },
> >>>> +    {
> >>>> +        .pName = SYNCOBJ_TIMELINE_TESTS_STR,
> >>>> +        .pInitFunc = suite_syncobj_timeline_tests_init,
> >>>> +        .pCleanupFunc = suite_syncobj_timeline_tests_clean,
> >>>> +        .pTests = syncobj_timeline_tests,
> >>>> +    },
> >>>>         CU_SUITE_INFO_NULL,
> >>>>   };
> >>>> @@ -176,6 +183,10 @@ static Suites_Active_Status suites_active_stat[]
> >>>> = {
> >>>>               .pName = RAS_TESTS_STR,
> >>>>               .pActive = suite_ras_tests_enable,
> >>>>           },
> >>>> +        {
> >>>> +            .pName = SYNCOBJ_TIMELINE_TESTS_STR,
> >>>> +            .pActive = suite_syncobj_timeline_tests_enable,
> >>>> +        },
> >>>>   };
> >>>>     diff --git a/tests/amdgpu/amdgpu_test.h
> >>>> b/tests/amdgpu/amdgpu_test.h
> >>>> index bcd0bc7e..36675ea3 100644
> >>>> --- a/tests/amdgpu/amdgpu_test.h
> >>>> +++ b/tests/amdgpu/amdgpu_test.h
> >>>> @@ -216,6 +216,27 @@ CU_BOOL suite_ras_tests_enable(void);
> >>>>   extern CU_TestInfo ras_tests[];
> >>>>     +/**
> >>>> + * Initialize syncobj timeline test suite
> >>>> + */
> >>>> +int suite_syncobj_timeline_tests_init();
> >>>> +
> >>>> +/**
> >>>> + * Deinitialize syncobj timeline test suite
> >>>> + */
> >>>> +int suite_syncobj_timeline_tests_clean();
> >>>> +
> >>>> +/**
> >>>> + * Decide if the suite is enabled by default or not.
> >>>> + */
> >>>> +CU_BOOL suite_syncobj_timeline_tests_enable(void);
> >>>> +
> >>>> +/**
> >>>> + * Tests in syncobj timeline test suite
> >>>> + */
> >>>> +extern CU_TestInfo syncobj_timeline_tests[];
> >>>> +
> >>>> +
> >>>>   /**
> >>>>    * Helper functions
> >>>>    */
> >>>> diff --git a/tests/amdgpu/meson.build b/tests/amdgpu/meson.build
> >>>> index 95ed9305..1726cb43 100644
> >>>> --- a/tests/amdgpu/meson.build
> >>>> +++ b/tests/amdgpu/meson.build
> >>>> @@ -24,7 +24,7 @@ if dep_cunit.found()
> >>>>       files(
> >>>>         'amdgpu_test.c', 'basic_tests.c', 'bo_tests.c', 'cs_tests.c',
> >>>>         'vce_tests.c', 'uvd_enc_tests.c', 'vcn_tests.c',
> >>>> 'deadlock_tests.c',
> >>>> -      'vm_tests.c', 'ras_tests.c',
> >>>> +      'vm_tests.c', 'ras_tests.c', 'syncobj_tests.c',
> >>>>       ),
> >>>>       dependencies : [dep_cunit, dep_threads],
> >>>>       include_directories : [inc_root, inc_drm,
> >>>> include_directories('../../amdgpu')],
> >>>> diff --git a/tests/amdgpu/syncobj_tests.c
> >>>> b/tests/amdgpu/syncobj_tests.c
> >>>> new file mode 100644
> >>>> index 00000000..a0c627d7
> >>>> --- /dev/null
> >>>> +++ b/tests/amdgpu/syncobj_tests.c
> >>>> @@ -0,0 +1,290 @@
> >>>> +/*
> >>>> + * Copyright 2017 Advanced Micro Devices, Inc.
> >>>> + *
> >>>> + * Permission is hereby granted, free of charge, to any person
> >>>> obtaining a
> >>>> + * copy of this software and associated documentation files (the
> >>>> "Software"),
> >>>> + * to deal in the Software without restriction, including without
> >>>> limitation
> >>>> + * the rights to use, copy, modify, merge, publish, distribute,
> >>>> sublicense,
> >>>> + * and/or sell copies of the Software, and to permit persons to whom
> >>>> the
> >>>> + * Software is furnished to do so, subject to the following
> >>>> conditions:
> >>>> + *
> >>>> + * The above copyright notice and this permission notice shall be
> >>>> included in
> >>>> + * all copies or substantial portions of the Software.
> >>>> + *
> >>>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> >>>> EXPRESS OR
> >>>> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
> >>>> MERCHANTABILITY,
> >>>> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO
> >>>> EVENT SHALL
> >>>> + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM,
> >>>> DAMAGES OR
> >>>> + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
> >>>> OTHERWISE,
> >>>> + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
> >>>> USE OR
> >>>> + * OTHER DEALINGS IN THE SOFTWARE.
> >>>> + *
> >>>> +*/
> >>>> +
> >>>> +#include "CUnit/Basic.h"
> >>>> +
> >>>> +#include "amdgpu_test.h"
> >>>> +#include "amdgpu_drm.h"
> >>>> +#include "amdgpu_internal.h"
> >>>> +#include <pthread.h>
> >>>> +
> >>>> +static  amdgpu_device_handle device_handle;
> >>>> +static  uint32_t  major_version;
> >>>> +static  uint32_t  minor_version;
> >>>> +
> >>>> +static void amdgpu_syncobj_timeline_test(void);
> >>>> +
> >>>> +CU_BOOL suite_syncobj_timeline_tests_enable(void)
> >>>> +{
> >>>> +    return CU_TRUE;
> >>>> +}
> >>>> +
> >>>> +int suite_syncobj_timeline_tests_init(void)
> >>>> +{
> >>>> +    int r;
> >>>> +
> >>>> +    r = amdgpu_device_initialize(drm_amdgpu[0], &major_version,
> >>>> +                   &minor_version, &device_handle);
> >>>> +
> >>>> +    if (r) {
> >>>> +        if ((r == -EACCES) && (errno == EACCES))
> >>>> +            printf("\n\nError:%s. "
> >>>> +                "Hint:Try to run this test program as root.",
> >>>> +                strerror(errno));
> >>>> +        return CUE_SINIT_FAILED;
> >>>> +    }
> >>>> +
> >>>> +    return CUE_SUCCESS;
> >>>> +}
> >>>> +
> >>>> +int suite_syncobj_timeline_tests_clean(void)
> >>>> +{
> >>>> +    int r = amdgpu_device_deinitialize(device_handle);
> >>>> +
> >>>> +    if (r == 0)
> >>>> +        return CUE_SUCCESS;
> >>>> +    else
> >>>> +        return CUE_SCLEAN_FAILED;
> >>>> +}
> >>>> +
> >>>> +
> >>>> +CU_TestInfo syncobj_timeline_tests[] = {
> >>>> +    { "syncobj timeline test", amdgpu_syncobj_timeline_test },
> >>>> +    CU_TEST_INFO_NULL,
> >>>> +};
> >>>> +
> >>>> +#define GFX_COMPUTE_NOP  0xffff1000
> >>>> +#define SDMA_NOP  0x0
> >>>> +static int syncobj_command_submission_helper(uint32_t
> >>>> syncobj_handle, bool
> >>>> +                         wait_or_signal, uint64_t point)
> >>>> +{
> >>>> +    amdgpu_context_handle context_handle;
> >>>> +    amdgpu_bo_handle ib_result_handle;
> >>>> +    void *ib_result_cpu;
> >>>> +    uint64_t ib_result_mc_address;
> >>>> +    struct drm_amdgpu_cs_chunk chunks[2];
> >>>> +    struct drm_amdgpu_cs_chunk_data chunk_data;
> >>>> +    struct drm_amdgpu_cs_chunk_syncobj syncobj_data;
> >>>> +    struct amdgpu_cs_fence fence_status;
> >>>> +    amdgpu_bo_list_handle bo_list;
> >>>> +    amdgpu_va_handle va_handle;
> >>>> +    uint32_t expired, flags;
> >>>> +    int i, r;
> >>>> +    uint64_t seq_no;
> >>>> +    static uint32_t *ptr;
> >>>> +
> >>>> +    r = amdgpu_cs_ctx_create(device_handle, &context_handle);
> >>>> +    CU_ASSERT_EQUAL(r, 0);
> >>>> +
> >>>> +    r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096,
> >>>> +                    AMDGPU_GEM_DOMAIN_GTT, 0,
> >>>> +                    &ib_result_handle, &ib_result_cpu,
> >>>> + &ib_result_mc_address, &va_handle);
> >>>> +    CU_ASSERT_EQUAL(r, 0);
> >>>> +
> >>>> +    r = amdgpu_get_bo_list(device_handle, ib_result_handle, NULL,
> >>>> +                   &bo_list);
> >>>> +    CU_ASSERT_EQUAL(r, 0);
> >>>> +
> >>>> +    ptr = ib_result_cpu;
> >>>> +
> >>>> +    for (i = 0; i < 16; ++i)
> >>>> +        ptr[i] = wait_or_signal ? GFX_COMPUTE_NOP: SDMA_NOP;
> >>>> +
> >>>> +    chunks[0].chunk_id = AMDGPU_CHUNK_ID_IB;
> >>>> +    chunks[0].length_dw = sizeof(struct drm_amdgpu_cs_chunk_ib) / 4;
> >>>> +    chunks[0].chunk_data = (uint64_t)(uintptr_t)&chunk_data;
> >>>> +    chunk_data.ib_data._pad = 0;
> >>>> +    chunk_data.ib_data.va_start = ib_result_mc_address;
> >>>> +    chunk_data.ib_data.ib_bytes = 16 * 4;
> >>>> +    chunk_data.ib_data.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX :
> >>>> +        AMDGPU_HW_IP_DMA;
> >>>> +    chunk_data.ib_data.ip_instance = 0;
> >>>> +    chunk_data.ib_data.ring = 0;
> >>>> +    chunk_data.ib_data.flags = 0;
> >>>> +
> >>>> +    chunks[1].chunk_id = wait_or_signal ?
> >>>> + AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT :
> >>>> + AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL;
> >>>> +    chunks[1].length_dw = sizeof(struct drm_amdgpu_cs_chunk_syncobj)
> >>>> / 4;
> >>>> +    chunks[1].chunk_data = (uint64_t)(uintptr_t)&syncobj_data;
> >>>> +    syncobj_data.handle = syncobj_handle;
> >>>> +    syncobj_data.point = point;
> >>>> +    syncobj_data.flags = DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT;
> >>>> +
> >>>> +    r = amdgpu_cs_submit_raw(device_handle,
> >>>> +                 context_handle,
> >>>> +                 bo_list,
> >>>> +                 2,
> >>>> +                 chunks,
> >>>> +                 &seq_no);
> >>>> +    CU_ASSERT_EQUAL(r, 0);
> >>>> +
> >>>> +
> >>>> +    memset(&fence_status, 0, sizeof(struct amdgpu_cs_fence));
> >>>> +    fence_status.context = context_handle;
> >>>> +    fence_status.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX:
> >>>> +        AMDGPU_HW_IP_DMA;
> >>>> +    fence_status.ip_instance = 0;
> >>>> +    fence_status.ring = 0;
> >>>> +    fence_status.fence = seq_no;
> >>>> +
> >>>> +    r = amdgpu_cs_query_fence_status(&fence_status,
> >>>> +            AMDGPU_TIMEOUT_INFINITE,0, &expired);
> >>>> +    CU_ASSERT_EQUAL(r, 0);
> >>>> +
> >>>> +    r = amdgpu_bo_list_destroy(bo_list);
> >>>> +    CU_ASSERT_EQUAL(r, 0);
> >>>> +
> >>>> +    r = amdgpu_bo_unmap_and_free(ib_result_handle, va_handle,
> >>>> +                     ib_result_mc_address, 4096);
> >>>> +    CU_ASSERT_EQUAL(r, 0);
> >>>> +
> >>>> +    r = amdgpu_cs_ctx_free(context_handle);
> >>>> +    CU_ASSERT_EQUAL(r, 0);
> >>>> +
> >>>> +    return r;
> >>>> +}
> >>>> +
> >>>> +struct syncobj_point {
> >>>> +    uint32_t syncobj_handle;
> >>>> +    uint64_t point;
> >>>> +};
> >>>> +
> >>>> +static void *syncobj_wait(void *data)
> >>>> +{
> >>>> +    struct syncobj_point *sp = (struct syncobj_point *)data;
> >>>> +    int r;
> >>>> +
> >>>> +    r = syncobj_command_submission_helper(sp->syncobj_handle, true,
> >>>> +                          sp->point);
> >>>> +    CU_ASSERT_EQUAL(r, 0);
> >>>> +
> >>>> +    return (void *)(long)r;
> >>>> +}
> >>>> +
> >>>> +static void *syncobj_signal(void *data)
> >>>> +{
> >>>> +    struct syncobj_point *sp = (struct syncobj_point *)data;
> >>>> +    int r;
> >>>> +
> >>>> +    r = syncobj_command_submission_helper(sp->syncobj_handle, false,
> >>>> +                          sp->point);
> >>>> +    CU_ASSERT_EQUAL(r, 0);
> >>>> +
> >>>> +    return (void *)(long)r;
> >>>> +}
> >>>> +
> >>>> +static void amdgpu_syncobj_timeline_test(void)
> >>>> +{
> >>>> +    static pthread_t wait_thread;
> >>>> +    static pthread_t signal_thread;
> >>>> +    static pthread_t c_thread;
> >>>> +    struct syncobj_point sp1, sp2, sp3;
> >>>> +    uint32_t syncobj_handle;
> >>>> +    uint64_t payload;
> >>>> +    uint64_t wait_point, signal_point;
> >>>> +    uint64_t timeout;
> >>>> +    struct timespec tp;
> >>>> +    int r, sync_fd;
> >>>> +    void *tmp;
> >>>> +
> >>>> +    r = amdgpu_cs_create_syncobj2(device_handle, 0,
> >>>> &syncobj_handle);
> >>>> +    CU_ASSERT_EQUAL(r, 0);
> >>>> +
> >>>> +    // wait on point 5
> >>>> +    sp1.syncobj_handle = syncobj_handle;
> >>>> +    sp1.point = 5;
> >>>> +    r = pthread_create(&wait_thread, NULL, syncobj_wait, &sp1);
> >>>> +    CU_ASSERT_EQUAL(r, 0);
> >>>> +
> >>>> +    // signal on point 10
> >>>> +    sp2.syncobj_handle = syncobj_handle;
> >>>> +    sp2.point = 10;
> >>>> +    r = pthread_create(&signal_thread, NULL, syncobj_signal, &sp2);
> >>>> +    CU_ASSERT_EQUAL(r, 0);
> >>>> +
> >>>> +    r = pthread_join(wait_thread, &tmp);
> >>>> +    CU_ASSERT_EQUAL(r, 0);
> >>>> +    CU_ASSERT_EQUAL(tmp, 0);
> >>>> +
> >>>> +    r = pthread_join(signal_thread, &tmp);
> >>>> +    CU_ASSERT_EQUAL(r, 0);
> >>>> +    CU_ASSERT_EQUAL(tmp, 0);
> >>>> +
> >>>> +    //query timeline payload
> >>>> +    r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
> >>>> +                    &payload, 1);
> >>>> +    CU_ASSERT_EQUAL(r, 0);
> >>>> +    CU_ASSERT_EQUAL(payload, 10);
> >>>> +
> >>>> +    //signal on point 16
> >>>> +    sp3.syncobj_handle = syncobj_handle;
> >>>> +    sp3.point = 16;
> >>>> +    r = pthread_create(&c_thread, NULL, syncobj_signal, &sp3);
> >>>> +    CU_ASSERT_EQUAL(r, 0);
> >>>> +    //CPU wait on point 16
> >>>> +    wait_point = 16;
> >>>> +    timeout = 0;
> >>>> +    clock_gettime(CLOCK_MONOTONIC, &tp);
> >>>> +    timeout = tp.tv_sec * 1000000000ULL + tp.tv_nsec;
> >>>> +    timeout += 0x10000000000; //10s
> >>>> +    r = amdgpu_cs_syncobj_timeline_wait(device_handle,
> >>>> &syncobj_handle,
> >>>> +                        &wait_point, 1, timeout,
> >>>> + DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL |
> >>>> + DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
> >>>> +                        NULL);
> >>>> +
> >>>> +    CU_ASSERT_EQUAL(r, 0);
> >>>> +    r = pthread_join(c_thread, &tmp);
> >>>> +    CU_ASSERT_EQUAL(r, 0);
> >>>> +    CU_ASSERT_EQUAL(tmp, 0);
> >>>> +
> >>>> +    // export point 16 and import to point 18
> >>>> +    r = amdgpu_cs_syncobj_export_sync_file2(device_handle,
> >>>> syncobj_handle,
> >>>> +                        16,
> >>>> + DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
> >>>> +                        &sync_fd);
> >>>> +    CU_ASSERT_EQUAL(r, 0);
> >>>> +    r = amdgpu_cs_syncobj_import_sync_file2(device_handle,
> >>>> syncobj_handle,
> >>>> +                        18, sync_fd);
> >>>> +    CU_ASSERT_EQUAL(r, 0);
> >>>> +    r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
> >>>> +                    &payload, 1);
> >>>> +    CU_ASSERT_EQUAL(r, 0);
> >>>> +    CU_ASSERT_EQUAL(payload, 18);
> >>>> +
> >>>> +    // CPU signal on point 20
> >>>> +    signal_point = 20;
> >>>> +    r = amdgpu_cs_syncobj_timeline_signal(device_handle,
> >>>> &syncobj_handle,
> >>>> + &signal_point, 1);
> >>>> +    CU_ASSERT_EQUAL(r, 0);
> >>>> +    r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
> >>>> +                    &payload, 1);
> >>>> +    CU_ASSERT_EQUAL(r, 0);
> >>>> +    CU_ASSERT_EQUAL(payload, 20);
> >>>> +
> >>>> +    r = amdgpu_cs_destroy_syncobj(device_handle, syncobj_handle);
> >>>> +    CU_ASSERT_EQUAL(r, 0);
> >>>> +
> >>>> +}
> >>>
> >>> _______________________________________________
> >>> dri-devel mailing list
> >>> dri-devel@lists.freedesktop.org
> >>> https://lists.freedesktop.org/mailman/listinfo/dri-devel
> >>
> >
> > _______________________________________________
> > dri-devel mailing list
> > dri-devel@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/dri-devel
>
>
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel


[-- Attachment #1.2: Type: text/html, Size: 35127 bytes --]

[-- Attachment #2: Type: text/plain, Size: 159 bytes --]

_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

Re: [PATCH libdrm 7/7] add syncobj timeline tests v3

[Michel Dänzer]

On 2019-05-16 12:09 p.m., Christian König wrote:
> Am 16.05.19 um 10:16 schrieb zhoucm1:
>> I was able to push changes to libdrm, but now seems after libdrm is
>> migrated to gitlab, I cannot yet. What step do I need to get back my
>> permission? I already can login into gitlab with old freedesktop account.
>>
>> @Christian, Can you help submit this patch set to libdrm first?
> 
> Done.

This broke amdgpu-symbol-check:
https://gitlab.freedesktop.org/mesa/drm/pipelines/37177


I pushed the trivial fix. Please consider using GitLab MRs, so that the
CI pipeline can catch issues like this before they can break the master
branch.


-- 
Earthling Michel Dänzer               |              https://www.amd.com
Libre software enthusiast             |             Mesa and X developer
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

Re: [PATCH libdrm 7/7] add syncobj timeline tests v3

[Daniel Vetter]

On Thu, May 16, 2019 at 2:46 PM Michel Dänzer <michel@daenzer.net> wrote:
>
> On 2019-05-16 12:09 p.m., Christian König wrote:
> > Am 16.05.19 um 10:16 schrieb zhoucm1:
> >> I was able to push changes to libdrm, but now seems after libdrm is
> >> migrated to gitlab, I cannot yet. What step do I need to get back my
> >> permission? I already can login into gitlab with old freedesktop account.
> >>
> >> @Christian, Can you help submit this patch set to libdrm first?
> >
> > Done.
>
> This broke amdgpu-symbol-check:
> https://gitlab.freedesktop.org/mesa/drm/pipelines/37177
>
>
> I pushed the trivial fix. Please consider using GitLab MRs, so that the
> CI pipeline can catch issues like this before they can break the master
> branch.

Should we switch docs to recommend MR? Make it the default? I guess
mesa hasn't made them mandatory yet, so doing that for libdrm is a bit
jumping ahread ...
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

Re: [PATCH libdrm 7/7] add syncobj timeline tests v3

[Michel Dänzer]

On 2019-05-16 2:47 p.m., Daniel Vetter wrote:
> On Thu, May 16, 2019 at 2:46 PM Michel Dänzer <michel@daenzer.net> wrote:
>> On 2019-05-16 12:09 p.m., Christian König wrote:
>>> Am 16.05.19 um 10:16 schrieb zhoucm1:
>>>> I was able to push changes to libdrm, but now seems after libdrm is
>>>> migrated to gitlab, I cannot yet. What step do I need to get back my
>>>> permission? I already can login into gitlab with old freedesktop account.
>>>>
>>>> @Christian, Can you help submit this patch set to libdrm first?
>>>
>>> Done.
>>
>> This broke amdgpu-symbol-check:
>> https://gitlab.freedesktop.org/mesa/drm/pipelines/37177
>>
>>
>> I pushed the trivial fix. Please consider using GitLab MRs, so that the
>> CI pipeline can catch issues like this before they can break the master
>> branch.
> 
> Should we switch docs to recommend MR? Make it the default? I guess
> mesa hasn't made them mandatory yet, so doing that for libdrm is a bit
> jumping ahread ...

Why can't libdrm go first?

With Mesa, it took some effort to get the CI pipeline to finish in an
acceptable amount of time, but that doesn't seem to be an issue with
libdrm (though it could probably still be sped up somewhat, e.g. by
using pre-generated docker images as in other projects, or just by
passing -j4 to make).


-- 
Earthling Michel Dänzer               |              https://www.amd.com
Libre software enthusiast             |             Mesa and X developer
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

Re: [PATCH libdrm 7/7] add syncobj timeline tests v3

[Daniel Vetter]

On Thu, May 16, 2019 at 6:33 PM Michel Dänzer <michel@daenzer.net> wrote:
> On 2019-05-16 2:47 p.m., Daniel Vetter wrote:
> > On Thu, May 16, 2019 at 2:46 PM Michel Dänzer <michel@daenzer.net> wrote:
> >> On 2019-05-16 12:09 p.m., Christian König wrote:
> >>> Am 16.05.19 um 10:16 schrieb zhoucm1:
> >>>> I was able to push changes to libdrm, but now seems after libdrm is
> >>>> migrated to gitlab, I cannot yet. What step do I need to get back my
> >>>> permission? I already can login into gitlab with old freedesktop account.
> >>>>
> >>>> @Christian, Can you help submit this patch set to libdrm first?
> >>>
> >>> Done.
> >>
> >> This broke amdgpu-symbol-check:
> >> https://gitlab.freedesktop.org/mesa/drm/pipelines/37177
> >>
> >>
> >> I pushed the trivial fix. Please consider using GitLab MRs, so that the
> >> CI pipeline can catch issues like this before they can break the master
> >> branch.
> >
> > Should we switch docs to recommend MR? Make it the default? I guess
> > mesa hasn't made them mandatory yet, so doing that for libdrm is a bit
> > jumping ahread ...
>
> Why can't libdrm go first?
>
> With Mesa, it took some effort to get the CI pipeline to finish in an
> acceptable amount of time, but that doesn't seem to be an issue with
> libdrm (though it could probably still be sped up somewhat, e.g. by
> using pre-generated docker images as in other projects, or just by
> passing -j4 to make).

tbh I'm all for doing that, just didn't want to mix things up too much
:-) And yeah libdrm is small enough that a quick MR-only experiment
wont upset anyone if it somehow goes wrong.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

[PATCH libdrm 1/7] addr cs chunk for syncobj timeline

[Chunming Zhou]

Signed-off-by: Chunming Zhou <david1.zhou@amd.com>
---
 include/drm/amdgpu_drm.h | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h
index d0701ffc..3d0318e6 100644
--- a/include/drm/amdgpu_drm.h
+++ b/include/drm/amdgpu_drm.h
@@ -528,6 +528,8 @@ struct drm_amdgpu_gem_va {
 #define AMDGPU_CHUNK_ID_SYNCOBJ_OUT     0x05
 #define AMDGPU_CHUNK_ID_BO_HANDLES      0x06
 #define AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES	0x07
+#define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT    0x08
+#define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL  0x09
 
 struct drm_amdgpu_cs_chunk {
 	__u32		chunk_id;
@@ -608,6 +610,13 @@ struct drm_amdgpu_cs_chunk_sem {
 	__u32 handle;
 };
 
+struct drm_amdgpu_cs_chunk_syncobj {
+	__u32 handle;
+	__u32 flags;
+	__u64 point;
+};
+
+
 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ	0
 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD	1
 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD	2
-- 
2.17.1

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH libdrm 7/7] add syncobj timeline tests v3

[Chunming Zhou]

v2: drop DRM_SYNCOBJ_CREATE_TYPE_TIMELINE, fix timeout calculation,
    fix some warnings
v3: add export/import and cpu signal testing cases

Signed-off-by: Chunming Zhou <david1.zhou@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
---
 tests/amdgpu/Makefile.am     |   3 +-
 tests/amdgpu/amdgpu_test.c   |  11 ++
 tests/amdgpu/amdgpu_test.h   |  21 +++
 tests/amdgpu/meson.build     |   2 +-
 tests/amdgpu/syncobj_tests.c | 290 +++++++++++++++++++++++++++++++++++
 5 files changed, 325 insertions(+), 2 deletions(-)
 create mode 100644 tests/amdgpu/syncobj_tests.c

diff --git a/tests/amdgpu/Makefile.am b/tests/amdgpu/Makefile.am
index 48278848..920882d0 100644
--- a/tests/amdgpu/Makefile.am
+++ b/tests/amdgpu/Makefile.am
@@ -34,4 +34,5 @@ amdgpu_test_SOURCES = \
 	uve_ib.h \
 	deadlock_tests.c \
 	vm_tests.c	\
-	ras_tests.c
+	ras_tests.c \
+	syncobj_tests.c
diff --git a/tests/amdgpu/amdgpu_test.c b/tests/amdgpu/amdgpu_test.c
index 35c8bf6c..73403fb4 100644
--- a/tests/amdgpu/amdgpu_test.c
+++ b/tests/amdgpu/amdgpu_test.c
@@ -57,6 +57,7 @@
 #define DEADLOCK_TESTS_STR "Deadlock Tests"
 #define VM_TESTS_STR "VM Tests"
 #define RAS_TESTS_STR "RAS Tests"
+#define SYNCOBJ_TIMELINE_TESTS_STR "SYNCOBJ TIMELINE Tests"
 
 /**
  *  Open handles for amdgpu devices
@@ -123,6 +124,12 @@ static CU_SuiteInfo suites[] = {
 		.pCleanupFunc = suite_ras_tests_clean,
 		.pTests = ras_tests,
 	},
+	{
+		.pName = SYNCOBJ_TIMELINE_TESTS_STR,
+		.pInitFunc = suite_syncobj_timeline_tests_init,
+		.pCleanupFunc = suite_syncobj_timeline_tests_clean,
+		.pTests = syncobj_timeline_tests,
+	},
 
 	CU_SUITE_INFO_NULL,
 };
@@ -176,6 +183,10 @@ static Suites_Active_Status suites_active_stat[] = {
 			.pName = RAS_TESTS_STR,
 			.pActive = suite_ras_tests_enable,
 		},
+		{
+			.pName = SYNCOBJ_TIMELINE_TESTS_STR,
+			.pActive = suite_syncobj_timeline_tests_enable,
+		},
 };
 
 
diff --git a/tests/amdgpu/amdgpu_test.h b/tests/amdgpu/amdgpu_test.h
index bcd0bc7e..36675ea3 100644
--- a/tests/amdgpu/amdgpu_test.h
+++ b/tests/amdgpu/amdgpu_test.h
@@ -216,6 +216,27 @@ CU_BOOL suite_ras_tests_enable(void);
 extern CU_TestInfo ras_tests[];
 
 
+/**
+ * Initialize syncobj timeline test suite
+ */
+int suite_syncobj_timeline_tests_init();
+
+/**
+ * Deinitialize syncobj timeline test suite
+ */
+int suite_syncobj_timeline_tests_clean();
+
+/**
+ * Decide if the suite is enabled by default or not.
+ */
+CU_BOOL suite_syncobj_timeline_tests_enable(void);
+
+/**
+ * Tests in syncobj timeline test suite
+ */
+extern CU_TestInfo syncobj_timeline_tests[];
+
+
 /**
  * Helper functions
  */
diff --git a/tests/amdgpu/meson.build b/tests/amdgpu/meson.build
index 95ed9305..1726cb43 100644
--- a/tests/amdgpu/meson.build
+++ b/tests/amdgpu/meson.build
@@ -24,7 +24,7 @@ if dep_cunit.found()
     files(
       'amdgpu_test.c', 'basic_tests.c', 'bo_tests.c', 'cs_tests.c',
       'vce_tests.c', 'uvd_enc_tests.c', 'vcn_tests.c', 'deadlock_tests.c',
-      'vm_tests.c', 'ras_tests.c',
+      'vm_tests.c', 'ras_tests.c', 'syncobj_tests.c',
     ),
     dependencies : [dep_cunit, dep_threads],
     include_directories : [inc_root, inc_drm, include_directories('../../amdgpu')],
diff --git a/tests/amdgpu/syncobj_tests.c b/tests/amdgpu/syncobj_tests.c
new file mode 100644
index 00000000..a0c627d7
--- /dev/null
+++ b/tests/amdgpu/syncobj_tests.c
@@ -0,0 +1,290 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+*/
+
+#include "CUnit/Basic.h"
+
+#include "amdgpu_test.h"
+#include "amdgpu_drm.h"
+#include "amdgpu_internal.h"
+#include <pthread.h>
+
+static  amdgpu_device_handle device_handle;
+static  uint32_t  major_version;
+static  uint32_t  minor_version;
+
+static void amdgpu_syncobj_timeline_test(void);
+
+CU_BOOL suite_syncobj_timeline_tests_enable(void)
+{
+	return CU_TRUE;
+}
+
+int suite_syncobj_timeline_tests_init(void)
+{
+	int r;
+
+	r = amdgpu_device_initialize(drm_amdgpu[0], &major_version,
+				   &minor_version, &device_handle);
+
+	if (r) {
+		if ((r == -EACCES) && (errno == EACCES))
+			printf("\n\nError:%s. "
+				"Hint:Try to run this test program as root.",
+				strerror(errno));
+		return CUE_SINIT_FAILED;
+	}
+
+	return CUE_SUCCESS;
+}
+
+int suite_syncobj_timeline_tests_clean(void)
+{
+	int r = amdgpu_device_deinitialize(device_handle);
+
+	if (r == 0)
+		return CUE_SUCCESS;
+	else
+		return CUE_SCLEAN_FAILED;
+}
+
+
+CU_TestInfo syncobj_timeline_tests[] = {
+	{ "syncobj timeline test",  amdgpu_syncobj_timeline_test },
+	CU_TEST_INFO_NULL,
+};
+
+#define GFX_COMPUTE_NOP  0xffff1000
+#define SDMA_NOP  0x0
+static int syncobj_command_submission_helper(uint32_t syncobj_handle, bool
+					     wait_or_signal, uint64_t point)
+{
+	amdgpu_context_handle context_handle;
+	amdgpu_bo_handle ib_result_handle;
+	void *ib_result_cpu;
+	uint64_t ib_result_mc_address;
+	struct drm_amdgpu_cs_chunk chunks[2];
+	struct drm_amdgpu_cs_chunk_data chunk_data;
+	struct drm_amdgpu_cs_chunk_syncobj syncobj_data;
+	struct amdgpu_cs_fence fence_status;
+	amdgpu_bo_list_handle bo_list;
+	amdgpu_va_handle va_handle;
+	uint32_t expired, flags;
+	int i, r;
+	uint64_t seq_no;
+	static uint32_t *ptr;
+
+	r = amdgpu_cs_ctx_create(device_handle, &context_handle);
+	CU_ASSERT_EQUAL(r, 0);
+
+	r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096,
+				    AMDGPU_GEM_DOMAIN_GTT, 0,
+				    &ib_result_handle, &ib_result_cpu,
+				    &ib_result_mc_address, &va_handle);
+	CU_ASSERT_EQUAL(r, 0);
+
+	r = amdgpu_get_bo_list(device_handle, ib_result_handle, NULL,
+			       &bo_list);
+	CU_ASSERT_EQUAL(r, 0);
+
+	ptr = ib_result_cpu;
+
+	for (i = 0; i < 16; ++i)
+		ptr[i] = wait_or_signal ? GFX_COMPUTE_NOP: SDMA_NOP;
+
+	chunks[0].chunk_id = AMDGPU_CHUNK_ID_IB;
+	chunks[0].length_dw = sizeof(struct drm_amdgpu_cs_chunk_ib) / 4;
+	chunks[0].chunk_data = (uint64_t)(uintptr_t)&chunk_data;
+	chunk_data.ib_data._pad = 0;
+	chunk_data.ib_data.va_start = ib_result_mc_address;
+	chunk_data.ib_data.ib_bytes = 16 * 4;
+	chunk_data.ib_data.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX :
+		AMDGPU_HW_IP_DMA;
+	chunk_data.ib_data.ip_instance = 0;
+	chunk_data.ib_data.ring = 0;
+	chunk_data.ib_data.flags = 0;
+
+	chunks[1].chunk_id = wait_or_signal ?
+		AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT :
+		AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL;
+	chunks[1].length_dw = sizeof(struct drm_amdgpu_cs_chunk_syncobj) / 4;
+	chunks[1].chunk_data = (uint64_t)(uintptr_t)&syncobj_data;
+	syncobj_data.handle = syncobj_handle;
+	syncobj_data.point = point;
+	syncobj_data.flags = DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT;
+
+	r = amdgpu_cs_submit_raw(device_handle,
+				 context_handle,
+				 bo_list,
+				 2,
+				 chunks,
+				 &seq_no);
+	CU_ASSERT_EQUAL(r, 0);
+
+
+	memset(&fence_status, 0, sizeof(struct amdgpu_cs_fence));
+	fence_status.context = context_handle;
+	fence_status.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX:
+		AMDGPU_HW_IP_DMA;
+	fence_status.ip_instance = 0;
+	fence_status.ring = 0;
+	fence_status.fence = seq_no;
+
+	r = amdgpu_cs_query_fence_status(&fence_status,
+			AMDGPU_TIMEOUT_INFINITE,0, &expired);
+	CU_ASSERT_EQUAL(r, 0);
+
+	r = amdgpu_bo_list_destroy(bo_list);
+	CU_ASSERT_EQUAL(r, 0);
+
+	r = amdgpu_bo_unmap_and_free(ib_result_handle, va_handle,
+				     ib_result_mc_address, 4096);
+	CU_ASSERT_EQUAL(r, 0);
+
+	r = amdgpu_cs_ctx_free(context_handle);
+	CU_ASSERT_EQUAL(r, 0);
+
+	return r;
+}
+
+struct syncobj_point {
+	uint32_t syncobj_handle;
+	uint64_t point;
+};
+
+static void *syncobj_wait(void *data)
+{
+	struct syncobj_point *sp = (struct syncobj_point *)data;
+	int r;
+
+	r = syncobj_command_submission_helper(sp->syncobj_handle, true,
+					      sp->point);
+	CU_ASSERT_EQUAL(r, 0);
+
+	return (void *)(long)r;
+}
+
+static void *syncobj_signal(void *data)
+{
+	struct syncobj_point *sp = (struct syncobj_point *)data;
+	int r;
+
+	r = syncobj_command_submission_helper(sp->syncobj_handle, false,
+					      sp->point);
+	CU_ASSERT_EQUAL(r, 0);
+
+	return (void *)(long)r;
+}
+
+static void amdgpu_syncobj_timeline_test(void)
+{
+	static pthread_t wait_thread;
+	static pthread_t signal_thread;
+	static pthread_t c_thread;
+	struct syncobj_point sp1, sp2, sp3;
+	uint32_t syncobj_handle;
+	uint64_t payload;
+	uint64_t wait_point, signal_point;
+	uint64_t timeout;
+	struct timespec tp;
+	int r, sync_fd;
+	void *tmp;
+
+	r =  amdgpu_cs_create_syncobj2(device_handle, 0, &syncobj_handle);
+	CU_ASSERT_EQUAL(r, 0);
+
+	// wait on point 5
+	sp1.syncobj_handle = syncobj_handle;
+	sp1.point = 5;
+	r = pthread_create(&wait_thread, NULL, syncobj_wait, &sp1);
+	CU_ASSERT_EQUAL(r, 0);
+
+	// signal on point 10
+	sp2.syncobj_handle = syncobj_handle;
+	sp2.point = 10;
+	r = pthread_create(&signal_thread, NULL, syncobj_signal, &sp2);
+	CU_ASSERT_EQUAL(r, 0);
+
+	r = pthread_join(wait_thread, &tmp);
+	CU_ASSERT_EQUAL(r, 0);
+	CU_ASSERT_EQUAL(tmp, 0);
+
+	r = pthread_join(signal_thread, &tmp);
+	CU_ASSERT_EQUAL(r, 0);
+	CU_ASSERT_EQUAL(tmp, 0);
+
+	//query timeline payload
+	r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
+				    &payload, 1);
+	CU_ASSERT_EQUAL(r, 0);
+	CU_ASSERT_EQUAL(payload, 10);
+
+	//signal on point 16
+	sp3.syncobj_handle = syncobj_handle;
+	sp3.point = 16;
+	r = pthread_create(&c_thread, NULL, syncobj_signal, &sp3);
+	CU_ASSERT_EQUAL(r, 0);
+	//CPU wait on point 16
+	wait_point = 16;
+	timeout = 0;
+	clock_gettime(CLOCK_MONOTONIC, &tp);
+	timeout = tp.tv_sec * 1000000000ULL + tp.tv_nsec;
+	timeout += 0x10000000000; //10s
+	r = amdgpu_cs_syncobj_timeline_wait(device_handle, &syncobj_handle,
+					    &wait_point, 1, timeout,
+					    DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL |
+					    DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
+					    NULL);
+
+	CU_ASSERT_EQUAL(r, 0);
+	r = pthread_join(c_thread, &tmp);
+	CU_ASSERT_EQUAL(r, 0);
+	CU_ASSERT_EQUAL(tmp, 0);
+
+	// export point 16 and import to point 18
+	r = amdgpu_cs_syncobj_export_sync_file2(device_handle, syncobj_handle,
+						16,
+						DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
+						&sync_fd);
+	CU_ASSERT_EQUAL(r, 0);
+	r = amdgpu_cs_syncobj_import_sync_file2(device_handle, syncobj_handle,
+						18, sync_fd);
+	CU_ASSERT_EQUAL(r, 0);
+	r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
+				    &payload, 1);
+	CU_ASSERT_EQUAL(r, 0);
+	CU_ASSERT_EQUAL(payload, 18);
+
+	// CPU signal on point 20
+	signal_point = 20;
+	r = amdgpu_cs_syncobj_timeline_signal(device_handle, &syncobj_handle,
+					      &signal_point, 1);
+	CU_ASSERT_EQUAL(r, 0);
+	r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
+				    &payload, 1);
+	CU_ASSERT_EQUAL(r, 0);
+	CU_ASSERT_EQUAL(payload, 20);
+
+	r = amdgpu_cs_destroy_syncobj(device_handle, syncobj_handle);
+	CU_ASSERT_EQUAL(r, 0);
+
+}
-- 
2.17.1

_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

[PATCH libdrm 1/7] addr cs chunk for syncobj timeline

[Chunming Zhou]

Signed-off-by: Chunming Zhou <david1.zhou@amd.com>
---
 include/drm/amdgpu_drm.h | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h
index d0701ffc..3d0318e6 100644
--- a/include/drm/amdgpu_drm.h
+++ b/include/drm/amdgpu_drm.h
@@ -528,6 +528,8 @@ struct drm_amdgpu_gem_va {
 #define AMDGPU_CHUNK_ID_SYNCOBJ_OUT     0x05
 #define AMDGPU_CHUNK_ID_BO_HANDLES      0x06
 #define AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES	0x07
+#define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT    0x08
+#define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL  0x09
 
 struct drm_amdgpu_cs_chunk {
 	__u32		chunk_id;
@@ -608,6 +610,13 @@ struct drm_amdgpu_cs_chunk_sem {
 	__u32 handle;
 };
 
+struct drm_amdgpu_cs_chunk_syncobj {
+	__u32 handle;
+	__u32 flags;
+	__u64 point;
+};
+
+
 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ	0
 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD	1
 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD	2
-- 
2.17.1

_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

[PATCH libdrm 7/7] add syncobj timeline tests v3

[Chunming Zhou]

v2: drop DRM_SYNCOBJ_CREATE_TYPE_TIMELINE, fix timeout calculation,
    fix some warnings
v3: add export/import and cpu signal testing cases

Signed-off-by: Chunming Zhou <david1.zhou@amd.com>
---
 tests/amdgpu/Makefile.am     |   3 +-
 tests/amdgpu/amdgpu_test.c   |  11 ++
 tests/amdgpu/amdgpu_test.h   |  21 +++
 tests/amdgpu/meson.build     |   2 +-
 tests/amdgpu/syncobj_tests.c | 290 +++++++++++++++++++++++++++++++++++
 5 files changed, 325 insertions(+), 2 deletions(-)
 create mode 100644 tests/amdgpu/syncobj_tests.c

diff --git a/tests/amdgpu/Makefile.am b/tests/amdgpu/Makefile.am
index 48278848..920882d0 100644
--- a/tests/amdgpu/Makefile.am
+++ b/tests/amdgpu/Makefile.am
@@ -34,4 +34,5 @@ amdgpu_test_SOURCES = \
 	uve_ib.h \
 	deadlock_tests.c \
 	vm_tests.c	\
-	ras_tests.c
+	ras_tests.c \
+	syncobj_tests.c
diff --git a/tests/amdgpu/amdgpu_test.c b/tests/amdgpu/amdgpu_test.c
index 35c8bf6c..73403fb4 100644
--- a/tests/amdgpu/amdgpu_test.c
+++ b/tests/amdgpu/amdgpu_test.c
@@ -57,6 +57,7 @@
 #define DEADLOCK_TESTS_STR "Deadlock Tests"
 #define VM_TESTS_STR "VM Tests"
 #define RAS_TESTS_STR "RAS Tests"
+#define SYNCOBJ_TIMELINE_TESTS_STR "SYNCOBJ TIMELINE Tests"
 
 /**
  *  Open handles for amdgpu devices
@@ -123,6 +124,12 @@ static CU_SuiteInfo suites[] = {
 		.pCleanupFunc = suite_ras_tests_clean,
 		.pTests = ras_tests,
 	},
+	{
+		.pName = SYNCOBJ_TIMELINE_TESTS_STR,
+		.pInitFunc = suite_syncobj_timeline_tests_init,
+		.pCleanupFunc = suite_syncobj_timeline_tests_clean,
+		.pTests = syncobj_timeline_tests,
+	},
 
 	CU_SUITE_INFO_NULL,
 };
@@ -176,6 +183,10 @@ static Suites_Active_Status suites_active_stat[] = {
 			.pName = RAS_TESTS_STR,
 			.pActive = suite_ras_tests_enable,
 		},
+		{
+			.pName = SYNCOBJ_TIMELINE_TESTS_STR,
+			.pActive = suite_syncobj_timeline_tests_enable,
+		},
 };
 
 
diff --git a/tests/amdgpu/amdgpu_test.h b/tests/amdgpu/amdgpu_test.h
index bcd0bc7e..36675ea3 100644
--- a/tests/amdgpu/amdgpu_test.h
+++ b/tests/amdgpu/amdgpu_test.h
@@ -216,6 +216,27 @@ CU_BOOL suite_ras_tests_enable(void);
 extern CU_TestInfo ras_tests[];
 
 
+/**
+ * Initialize syncobj timeline test suite
+ */
+int suite_syncobj_timeline_tests_init();
+
+/**
+ * Deinitialize syncobj timeline test suite
+ */
+int suite_syncobj_timeline_tests_clean();
+
+/**
+ * Decide if the suite is enabled by default or not.
+ */
+CU_BOOL suite_syncobj_timeline_tests_enable(void);
+
+/**
+ * Tests in syncobj timeline test suite
+ */
+extern CU_TestInfo syncobj_timeline_tests[];
+
+
 /**
  * Helper functions
  */
diff --git a/tests/amdgpu/meson.build b/tests/amdgpu/meson.build
index 95ed9305..1726cb43 100644
--- a/tests/amdgpu/meson.build
+++ b/tests/amdgpu/meson.build
@@ -24,7 +24,7 @@ if dep_cunit.found()
     files(
       'amdgpu_test.c', 'basic_tests.c', 'bo_tests.c', 'cs_tests.c',
       'vce_tests.c', 'uvd_enc_tests.c', 'vcn_tests.c', 'deadlock_tests.c',
-      'vm_tests.c', 'ras_tests.c',
+      'vm_tests.c', 'ras_tests.c', 'syncobj_tests.c',
     ),
     dependencies : [dep_cunit, dep_threads],
     include_directories : [inc_root, inc_drm, include_directories('../../amdgpu')],
diff --git a/tests/amdgpu/syncobj_tests.c b/tests/amdgpu/syncobj_tests.c
new file mode 100644
index 00000000..a0c627d7
--- /dev/null
+++ b/tests/amdgpu/syncobj_tests.c
@@ -0,0 +1,290 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+*/
+
+#include "CUnit/Basic.h"
+
+#include "amdgpu_test.h"
+#include "amdgpu_drm.h"
+#include "amdgpu_internal.h"
+#include <pthread.h>
+
+static  amdgpu_device_handle device_handle;
+static  uint32_t  major_version;
+static  uint32_t  minor_version;
+
+static void amdgpu_syncobj_timeline_test(void);
+
+CU_BOOL suite_syncobj_timeline_tests_enable(void)
+{
+	return CU_TRUE;
+}
+
+int suite_syncobj_timeline_tests_init(void)
+{
+	int r;
+
+	r = amdgpu_device_initialize(drm_amdgpu[0], &major_version,
+				   &minor_version, &device_handle);
+
+	if (r) {
+		if ((r == -EACCES) && (errno == EACCES))
+			printf("\n\nError:%s. "
+				"Hint:Try to run this test program as root.",
+				strerror(errno));
+		return CUE_SINIT_FAILED;
+	}
+
+	return CUE_SUCCESS;
+}
+
+int suite_syncobj_timeline_tests_clean(void)
+{
+	int r = amdgpu_device_deinitialize(device_handle);
+
+	if (r == 0)
+		return CUE_SUCCESS;
+	else
+		return CUE_SCLEAN_FAILED;
+}
+
+
+CU_TestInfo syncobj_timeline_tests[] = {
+	{ "syncobj timeline test",  amdgpu_syncobj_timeline_test },
+	CU_TEST_INFO_NULL,
+};
+
+#define GFX_COMPUTE_NOP  0xffff1000
+#define SDMA_NOP  0x0
+static int syncobj_command_submission_helper(uint32_t syncobj_handle, bool
+					     wait_or_signal, uint64_t point)
+{
+	amdgpu_context_handle context_handle;
+	amdgpu_bo_handle ib_result_handle;
+	void *ib_result_cpu;
+	uint64_t ib_result_mc_address;
+	struct drm_amdgpu_cs_chunk chunks[2];
+	struct drm_amdgpu_cs_chunk_data chunk_data;
+	struct drm_amdgpu_cs_chunk_syncobj syncobj_data;
+	struct amdgpu_cs_fence fence_status;
+	amdgpu_bo_list_handle bo_list;
+	amdgpu_va_handle va_handle;
+	uint32_t expired, flags;
+	int i, r;
+	uint64_t seq_no;
+	static uint32_t *ptr;
+
+	r = amdgpu_cs_ctx_create(device_handle, &context_handle);
+	CU_ASSERT_EQUAL(r, 0);
+
+	r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096,
+				    AMDGPU_GEM_DOMAIN_GTT, 0,
+				    &ib_result_handle, &ib_result_cpu,
+				    &ib_result_mc_address, &va_handle);
+	CU_ASSERT_EQUAL(r, 0);
+
+	r = amdgpu_get_bo_list(device_handle, ib_result_handle, NULL,
+			       &bo_list);
+	CU_ASSERT_EQUAL(r, 0);
+
+	ptr = ib_result_cpu;
+
+	for (i = 0; i < 16; ++i)
+		ptr[i] = wait_or_signal ? GFX_COMPUTE_NOP: SDMA_NOP;
+
+	chunks[0].chunk_id = AMDGPU_CHUNK_ID_IB;
+	chunks[0].length_dw = sizeof(struct drm_amdgpu_cs_chunk_ib) / 4;
+	chunks[0].chunk_data = (uint64_t)(uintptr_t)&chunk_data;
+	chunk_data.ib_data._pad = 0;
+	chunk_data.ib_data.va_start = ib_result_mc_address;
+	chunk_data.ib_data.ib_bytes = 16 * 4;
+	chunk_data.ib_data.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX :
+		AMDGPU_HW_IP_DMA;
+	chunk_data.ib_data.ip_instance = 0;
+	chunk_data.ib_data.ring = 0;
+	chunk_data.ib_data.flags = 0;
+
+	chunks[1].chunk_id = wait_or_signal ?
+		AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT :
+		AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL;
+	chunks[1].length_dw = sizeof(struct drm_amdgpu_cs_chunk_syncobj) / 4;
+	chunks[1].chunk_data = (uint64_t)(uintptr_t)&syncobj_data;
+	syncobj_data.handle = syncobj_handle;
+	syncobj_data.point = point;
+	syncobj_data.flags = DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT;
+
+	r = amdgpu_cs_submit_raw(device_handle,
+				 context_handle,
+				 bo_list,
+				 2,
+				 chunks,
+				 &seq_no);
+	CU_ASSERT_EQUAL(r, 0);
+
+
+	memset(&fence_status, 0, sizeof(struct amdgpu_cs_fence));
+	fence_status.context = context_handle;
+	fence_status.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX:
+		AMDGPU_HW_IP_DMA;
+	fence_status.ip_instance = 0;
+	fence_status.ring = 0;
+	fence_status.fence = seq_no;
+
+	r = amdgpu_cs_query_fence_status(&fence_status,
+			AMDGPU_TIMEOUT_INFINITE,0, &expired);
+	CU_ASSERT_EQUAL(r, 0);
+
+	r = amdgpu_bo_list_destroy(bo_list);
+	CU_ASSERT_EQUAL(r, 0);
+
+	r = amdgpu_bo_unmap_and_free(ib_result_handle, va_handle,
+				     ib_result_mc_address, 4096);
+	CU_ASSERT_EQUAL(r, 0);
+
+	r = amdgpu_cs_ctx_free(context_handle);
+	CU_ASSERT_EQUAL(r, 0);
+
+	return r;
+}
+
+struct syncobj_point {
+	uint32_t syncobj_handle;
+	uint64_t point;
+};
+
+static void *syncobj_wait(void *data)
+{
+	struct syncobj_point *sp = (struct syncobj_point *)data;
+	int r;
+
+	r = syncobj_command_submission_helper(sp->syncobj_handle, true,
+					      sp->point);
+	CU_ASSERT_EQUAL(r, 0);
+
+	return (void *)(long)r;
+}
+
+static void *syncobj_signal(void *data)
+{
+	struct syncobj_point *sp = (struct syncobj_point *)data;
+	int r;
+
+	r = syncobj_command_submission_helper(sp->syncobj_handle, false,
+					      sp->point);
+	CU_ASSERT_EQUAL(r, 0);
+
+	return (void *)(long)r;
+}
+
+static void amdgpu_syncobj_timeline_test(void)
+{
+	static pthread_t wait_thread;
+	static pthread_t signal_thread;
+	static pthread_t c_thread;
+	struct syncobj_point sp1, sp2, sp3;
+	uint32_t syncobj_handle;
+	uint64_t payload;
+	uint64_t wait_point, signal_point;
+	uint64_t timeout;
+	struct timespec tp;
+	int r, sync_fd;
+	void *tmp;
+
+	r =  amdgpu_cs_create_syncobj2(device_handle, 0, &syncobj_handle);
+	CU_ASSERT_EQUAL(r, 0);
+
+	// wait on point 5
+	sp1.syncobj_handle = syncobj_handle;
+	sp1.point = 5;
+	r = pthread_create(&wait_thread, NULL, syncobj_wait, &sp1);
+	CU_ASSERT_EQUAL(r, 0);
+
+	// signal on point 10
+	sp2.syncobj_handle = syncobj_handle;
+	sp2.point = 10;
+	r = pthread_create(&signal_thread, NULL, syncobj_signal, &sp2);
+	CU_ASSERT_EQUAL(r, 0);
+
+	r = pthread_join(wait_thread, &tmp);
+	CU_ASSERT_EQUAL(r, 0);
+	CU_ASSERT_EQUAL(tmp, 0);
+
+	r = pthread_join(signal_thread, &tmp);
+	CU_ASSERT_EQUAL(r, 0);
+	CU_ASSERT_EQUAL(tmp, 0);
+
+	//query timeline payload
+	r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
+				    &payload, 1);
+	CU_ASSERT_EQUAL(r, 0);
+	CU_ASSERT_EQUAL(payload, 10);
+
+	//signal on point 16
+	sp3.syncobj_handle = syncobj_handle;
+	sp3.point = 16;
+	r = pthread_create(&c_thread, NULL, syncobj_signal, &sp3);
+	CU_ASSERT_EQUAL(r, 0);
+	//CPU wait on point 16
+	wait_point = 16;
+	timeout = 0;
+	clock_gettime(CLOCK_MONOTONIC, &tp);
+	timeout = tp.tv_sec * 1000000000ULL + tp.tv_nsec;
+	timeout += 0x10000000000; //10s
+	r = amdgpu_cs_syncobj_timeline_wait(device_handle, &syncobj_handle,
+					    &wait_point, 1, timeout,
+					    DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL |
+					    DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
+					    NULL);
+
+	CU_ASSERT_EQUAL(r, 0);
+	r = pthread_join(c_thread, &tmp);
+	CU_ASSERT_EQUAL(r, 0);
+	CU_ASSERT_EQUAL(tmp, 0);
+
+	// export point 16 and import to point 18
+	r = amdgpu_cs_syncobj_export_sync_file2(device_handle, syncobj_handle,
+						16,
+						DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
+						&sync_fd);
+	CU_ASSERT_EQUAL(r, 0);
+	r = amdgpu_cs_syncobj_import_sync_file2(device_handle, syncobj_handle,
+						18, sync_fd);
+	CU_ASSERT_EQUAL(r, 0);
+	r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
+				    &payload, 1);
+	CU_ASSERT_EQUAL(r, 0);
+	CU_ASSERT_EQUAL(payload, 18);
+
+	// CPU signal on point 20
+	signal_point = 20;
+	r = amdgpu_cs_syncobj_timeline_signal(device_handle, &syncobj_handle,
+					      &signal_point, 1);
+	CU_ASSERT_EQUAL(r, 0);
+	r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
+				    &payload, 1);
+	CU_ASSERT_EQUAL(r, 0);
+	CU_ASSERT_EQUAL(payload, 20);
+
+	r = amdgpu_cs_destroy_syncobj(device_handle, syncobj_handle);
+	CU_ASSERT_EQUAL(r, 0);
+
+}
-- 
2.17.1

_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

[PATCH libdrm 1/7] new syncobj extension v2

[Chunming Zhou]

v2: drop not implemented IOCTLs and flags

Signed-off-by: Chunming Zhou <david1.zhou@amd.com>
Signed-off-by: Christian König <christian.koenig@amd.com>
---
 include/drm/drm.h | 35 +++++++++++++++++++++++++++++++++++
 1 file changed, 35 insertions(+)

diff --git a/include/drm/drm.h b/include/drm/drm.h
index 85c685a2..9ef6b9d0 100644
--- a/include/drm/drm.h
+++ b/include/drm/drm.h
@@ -729,8 +729,17 @@ struct drm_syncobj_handle {
 	__u32 pad;
 };
 
+struct drm_syncobj_transfer {
+        __u32 binary_handle;
+        __u32 timeline_handle;
+        __u64 point;
+        __u32 flags;
+        __u32 pad;
+};
+
 #define DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL (1 << 0)
 #define DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT (1 << 1)
+#define DRM_SYNCOBJ_WAIT_FLAGS_WAIT_AVAILABLE (1 << 2)
 struct drm_syncobj_wait {
 	__u64 handles;
 	/* absolute timeout */
@@ -741,12 +750,31 @@ struct drm_syncobj_wait {
 	__u32 pad;
 };
 
+struct drm_syncobj_timeline_wait {
+        __u64 handles;
+        /* wait on specific timeline point for every handles*/
+        __u64 points;
+        /* absolute timeout */
+        __s64 timeout_nsec;
+        __u32 count_handles;
+        __u32 flags;
+        __u32 first_signaled; /* only valid when not waiting all */
+        __u32 pad;
+};
+
 struct drm_syncobj_array {
 	__u64 handles;
 	__u32 count_handles;
 	__u32 pad;
 };
 
+struct drm_syncobj_timeline_array {
+        __u64 handles;
+        __u64 points;
+        __u32 count_handles;
+        __u32 pad;
+};
+
 /* Query current scanout sequence number */
 struct drm_crtc_get_sequence {
 	__u32 crtc_id;		/* requested crtc_id */
@@ -903,6 +931,13 @@ extern "C" {
 #define DRM_IOCTL_MODE_GET_LEASE	DRM_IOWR(0xC8, struct drm_mode_get_lease)
 #define DRM_IOCTL_MODE_REVOKE_LEASE	DRM_IOWR(0xC9, struct drm_mode_revoke_lease)
 
+#define DRM_IOCTL_SYNCOBJ_TIMELINE_WAIT DRM_IOWR(0xCA, struct drm_syncobj_timeline_wait)
+#define DRM_IOCTL_SYNCOBJ_QUERY         DRM_IOWR(0xCB, struct drm_syncobj_timeline_array)
+#define DRM_IOCTL_SYNCOBJ_BINARY_TO_TIMELINE    DRM_IOWR(0xCC, struct drm_syncobj_transfer)
+#define DRM_IOCTL_SYNCOBJ_TIMELINE_TO_BINARY    DRM_IOWR(0xCD, struct drm_syncobj_transfer)
+#define DRM_IOCTL_SYNCOBJ_TIMELINE_SIGNAL       DRM_IOWR(0xCE, struct drm_syncobj_timeline_array)
+
+
 /**
  * Device specific ioctls should only be in their respective headers
  * The device specific ioctl range is from 0x40 to 0x9f.
-- 
2.17.1

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH libdrm 7/7] add syncobj timeline tests v3

[Chunming Zhou]

v2: drop DRM_SYNCOBJ_CREATE_TYPE_TIMELINE, fix timeout calculation,
    fix some warnings
v3: add export/import and cpu signal testing cases

Signed-off-by: Chunming Zhou <david1.zhou@amd.com>
Signed-off-by: Christian König <christian.koenig@amd.com>
---
 tests/amdgpu/Makefile.am     |   3 +-
 tests/amdgpu/amdgpu_test.c   |  12 ++
 tests/amdgpu/amdgpu_test.h   |  21 +++
 tests/amdgpu/meson.build     |   2 +-
 tests/amdgpu/syncobj_tests.c | 290 +++++++++++++++++++++++++++++++++++
 5 files changed, 326 insertions(+), 2 deletions(-)
 create mode 100644 tests/amdgpu/syncobj_tests.c

diff --git a/tests/amdgpu/Makefile.am b/tests/amdgpu/Makefile.am
index 447ff217..d3fbe2bb 100644
--- a/tests/amdgpu/Makefile.am
+++ b/tests/amdgpu/Makefile.am
@@ -33,4 +33,5 @@ amdgpu_test_SOURCES = \
 	vcn_tests.c \
 	uve_ib.h \
 	deadlock_tests.c \
-	vm_tests.c
+	vm_tests.c \
+	syncobj_tests.c
diff --git a/tests/amdgpu/amdgpu_test.c b/tests/amdgpu/amdgpu_test.c
index ebf44098..ff1448f3 100644
--- a/tests/amdgpu/amdgpu_test.c
+++ b/tests/amdgpu/amdgpu_test.c
@@ -56,6 +56,7 @@
 #define UVD_ENC_TESTS_STR "UVD ENC Tests"
 #define DEADLOCK_TESTS_STR "Deadlock Tests"
 #define VM_TESTS_STR "VM Tests"
+#define SYNCOBJ_TIMELINE_TESTS_STR "SYNCOBJ TIMELINE Tests"
 
 /**
  *  Open handles for amdgpu devices
@@ -116,6 +117,12 @@ static CU_SuiteInfo suites[] = {
 		.pCleanupFunc = suite_vm_tests_clean,
 		.pTests = vm_tests,
 	},
+	{
+		.pName = SYNCOBJ_TIMELINE_TESTS_STR,
+		.pInitFunc = suite_syncobj_timeline_tests_init,
+		.pCleanupFunc = suite_syncobj_timeline_tests_clean,
+		.pTests = syncobj_timeline_tests,
+	},
 
 	CU_SUITE_INFO_NULL,
 };
@@ -165,6 +172,11 @@ static Suites_Active_Status suites_active_stat[] = {
 			.pName = VM_TESTS_STR,
 			.pActive = suite_vm_tests_enable,
 		},
+		{
+			.pName = SYNCOBJ_TIMELINE_TESTS_STR,
+			.pActive = suite_syncobj_timeline_tests_enable,
+		},
+
 };
 
 
diff --git a/tests/amdgpu/amdgpu_test.h b/tests/amdgpu/amdgpu_test.h
index af81eea8..24d64b64 100644
--- a/tests/amdgpu/amdgpu_test.h
+++ b/tests/amdgpu/amdgpu_test.h
@@ -194,6 +194,27 @@ CU_BOOL suite_vm_tests_enable(void);
  */
 extern CU_TestInfo vm_tests[];
 
+/**
+ * Initialize syncobj timeline test suite
+ */
+int suite_syncobj_timeline_tests_init();
+
+/**
+ * Deinitialize syncobj timeline test suite
+ */
+int suite_syncobj_timeline_tests_clean();
+
+/**
+ * Decide if the suite is enabled by default or not.
+ */
+CU_BOOL suite_syncobj_timeline_tests_enable(void);
+
+/**
+ * Tests in syncobj timeline test suite
+ */
+extern CU_TestInfo syncobj_timeline_tests[];
+
+
 /**
  * Helper functions
  */
diff --git a/tests/amdgpu/meson.build b/tests/amdgpu/meson.build
index 4c1237c6..3ceec715 100644
--- a/tests/amdgpu/meson.build
+++ b/tests/amdgpu/meson.build
@@ -24,7 +24,7 @@ if dep_cunit.found()
     files(
       'amdgpu_test.c', 'basic_tests.c', 'bo_tests.c', 'cs_tests.c',
       'vce_tests.c', 'uvd_enc_tests.c', 'vcn_tests.c', 'deadlock_tests.c',
-      'vm_tests.c',
+      'vm_tests.c', 'syncobj_tests.c',
     ),
     dependencies : [dep_cunit, dep_threads],
     include_directories : [inc_root, inc_drm, include_directories('../../amdgpu')],
diff --git a/tests/amdgpu/syncobj_tests.c b/tests/amdgpu/syncobj_tests.c
new file mode 100644
index 00000000..a0c627d7
--- /dev/null
+++ b/tests/amdgpu/syncobj_tests.c
@@ -0,0 +1,290 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+*/
+
+#include "CUnit/Basic.h"
+
+#include "amdgpu_test.h"
+#include "amdgpu_drm.h"
+#include "amdgpu_internal.h"
+#include <pthread.h>
+
+static  amdgpu_device_handle device_handle;
+static  uint32_t  major_version;
+static  uint32_t  minor_version;
+
+static void amdgpu_syncobj_timeline_test(void);
+
+CU_BOOL suite_syncobj_timeline_tests_enable(void)
+{
+	return CU_TRUE;
+}
+
+int suite_syncobj_timeline_tests_init(void)
+{
+	int r;
+
+	r = amdgpu_device_initialize(drm_amdgpu[0], &major_version,
+				   &minor_version, &device_handle);
+
+	if (r) {
+		if ((r == -EACCES) && (errno == EACCES))
+			printf("\n\nError:%s. "
+				"Hint:Try to run this test program as root.",
+				strerror(errno));
+		return CUE_SINIT_FAILED;
+	}
+
+	return CUE_SUCCESS;
+}
+
+int suite_syncobj_timeline_tests_clean(void)
+{
+	int r = amdgpu_device_deinitialize(device_handle);
+
+	if (r == 0)
+		return CUE_SUCCESS;
+	else
+		return CUE_SCLEAN_FAILED;
+}
+
+
+CU_TestInfo syncobj_timeline_tests[] = {
+	{ "syncobj timeline test",  amdgpu_syncobj_timeline_test },
+	CU_TEST_INFO_NULL,
+};
+
+#define GFX_COMPUTE_NOP  0xffff1000
+#define SDMA_NOP  0x0
+static int syncobj_command_submission_helper(uint32_t syncobj_handle, bool
+					     wait_or_signal, uint64_t point)
+{
+	amdgpu_context_handle context_handle;
+	amdgpu_bo_handle ib_result_handle;
+	void *ib_result_cpu;
+	uint64_t ib_result_mc_address;
+	struct drm_amdgpu_cs_chunk chunks[2];
+	struct drm_amdgpu_cs_chunk_data chunk_data;
+	struct drm_amdgpu_cs_chunk_syncobj syncobj_data;
+	struct amdgpu_cs_fence fence_status;
+	amdgpu_bo_list_handle bo_list;
+	amdgpu_va_handle va_handle;
+	uint32_t expired, flags;
+	int i, r;
+	uint64_t seq_no;
+	static uint32_t *ptr;
+
+	r = amdgpu_cs_ctx_create(device_handle, &context_handle);
+	CU_ASSERT_EQUAL(r, 0);
+
+	r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096,
+				    AMDGPU_GEM_DOMAIN_GTT, 0,
+				    &ib_result_handle, &ib_result_cpu,
+				    &ib_result_mc_address, &va_handle);
+	CU_ASSERT_EQUAL(r, 0);
+
+	r = amdgpu_get_bo_list(device_handle, ib_result_handle, NULL,
+			       &bo_list);
+	CU_ASSERT_EQUAL(r, 0);
+
+	ptr = ib_result_cpu;
+
+	for (i = 0; i < 16; ++i)
+		ptr[i] = wait_or_signal ? GFX_COMPUTE_NOP: SDMA_NOP;
+
+	chunks[0].chunk_id = AMDGPU_CHUNK_ID_IB;
+	chunks[0].length_dw = sizeof(struct drm_amdgpu_cs_chunk_ib) / 4;
+	chunks[0].chunk_data = (uint64_t)(uintptr_t)&chunk_data;
+	chunk_data.ib_data._pad = 0;
+	chunk_data.ib_data.va_start = ib_result_mc_address;
+	chunk_data.ib_data.ib_bytes = 16 * 4;
+	chunk_data.ib_data.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX :
+		AMDGPU_HW_IP_DMA;
+	chunk_data.ib_data.ip_instance = 0;
+	chunk_data.ib_data.ring = 0;
+	chunk_data.ib_data.flags = 0;
+
+	chunks[1].chunk_id = wait_or_signal ?
+		AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT :
+		AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL;
+	chunks[1].length_dw = sizeof(struct drm_amdgpu_cs_chunk_syncobj) / 4;
+	chunks[1].chunk_data = (uint64_t)(uintptr_t)&syncobj_data;
+	syncobj_data.handle = syncobj_handle;
+	syncobj_data.point = point;
+	syncobj_data.flags = DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT;
+
+	r = amdgpu_cs_submit_raw(device_handle,
+				 context_handle,
+				 bo_list,
+				 2,
+				 chunks,
+				 &seq_no);
+	CU_ASSERT_EQUAL(r, 0);
+
+
+	memset(&fence_status, 0, sizeof(struct amdgpu_cs_fence));
+	fence_status.context = context_handle;
+	fence_status.ip_type = wait_or_signal ? AMDGPU_HW_IP_GFX:
+		AMDGPU_HW_IP_DMA;
+	fence_status.ip_instance = 0;
+	fence_status.ring = 0;
+	fence_status.fence = seq_no;
+
+	r = amdgpu_cs_query_fence_status(&fence_status,
+			AMDGPU_TIMEOUT_INFINITE,0, &expired);
+	CU_ASSERT_EQUAL(r, 0);
+
+	r = amdgpu_bo_list_destroy(bo_list);
+	CU_ASSERT_EQUAL(r, 0);
+
+	r = amdgpu_bo_unmap_and_free(ib_result_handle, va_handle,
+				     ib_result_mc_address, 4096);
+	CU_ASSERT_EQUAL(r, 0);
+
+	r = amdgpu_cs_ctx_free(context_handle);
+	CU_ASSERT_EQUAL(r, 0);
+
+	return r;
+}
+
+struct syncobj_point {
+	uint32_t syncobj_handle;
+	uint64_t point;
+};
+
+static void *syncobj_wait(void *data)
+{
+	struct syncobj_point *sp = (struct syncobj_point *)data;
+	int r;
+
+	r = syncobj_command_submission_helper(sp->syncobj_handle, true,
+					      sp->point);
+	CU_ASSERT_EQUAL(r, 0);
+
+	return (void *)(long)r;
+}
+
+static void *syncobj_signal(void *data)
+{
+	struct syncobj_point *sp = (struct syncobj_point *)data;
+	int r;
+
+	r = syncobj_command_submission_helper(sp->syncobj_handle, false,
+					      sp->point);
+	CU_ASSERT_EQUAL(r, 0);
+
+	return (void *)(long)r;
+}
+
+static void amdgpu_syncobj_timeline_test(void)
+{
+	static pthread_t wait_thread;
+	static pthread_t signal_thread;
+	static pthread_t c_thread;
+	struct syncobj_point sp1, sp2, sp3;
+	uint32_t syncobj_handle;
+	uint64_t payload;
+	uint64_t wait_point, signal_point;
+	uint64_t timeout;
+	struct timespec tp;
+	int r, sync_fd;
+	void *tmp;
+
+	r =  amdgpu_cs_create_syncobj2(device_handle, 0, &syncobj_handle);
+	CU_ASSERT_EQUAL(r, 0);
+
+	// wait on point 5
+	sp1.syncobj_handle = syncobj_handle;
+	sp1.point = 5;
+	r = pthread_create(&wait_thread, NULL, syncobj_wait, &sp1);
+	CU_ASSERT_EQUAL(r, 0);
+
+	// signal on point 10
+	sp2.syncobj_handle = syncobj_handle;
+	sp2.point = 10;
+	r = pthread_create(&signal_thread, NULL, syncobj_signal, &sp2);
+	CU_ASSERT_EQUAL(r, 0);
+
+	r = pthread_join(wait_thread, &tmp);
+	CU_ASSERT_EQUAL(r, 0);
+	CU_ASSERT_EQUAL(tmp, 0);
+
+	r = pthread_join(signal_thread, &tmp);
+	CU_ASSERT_EQUAL(r, 0);
+	CU_ASSERT_EQUAL(tmp, 0);
+
+	//query timeline payload
+	r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
+				    &payload, 1);
+	CU_ASSERT_EQUAL(r, 0);
+	CU_ASSERT_EQUAL(payload, 10);
+
+	//signal on point 16
+	sp3.syncobj_handle = syncobj_handle;
+	sp3.point = 16;
+	r = pthread_create(&c_thread, NULL, syncobj_signal, &sp3);
+	CU_ASSERT_EQUAL(r, 0);
+	//CPU wait on point 16
+	wait_point = 16;
+	timeout = 0;
+	clock_gettime(CLOCK_MONOTONIC, &tp);
+	timeout = tp.tv_sec * 1000000000ULL + tp.tv_nsec;
+	timeout += 0x10000000000; //10s
+	r = amdgpu_cs_syncobj_timeline_wait(device_handle, &syncobj_handle,
+					    &wait_point, 1, timeout,
+					    DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL |
+					    DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
+					    NULL);
+
+	CU_ASSERT_EQUAL(r, 0);
+	r = pthread_join(c_thread, &tmp);
+	CU_ASSERT_EQUAL(r, 0);
+	CU_ASSERT_EQUAL(tmp, 0);
+
+	// export point 16 and import to point 18
+	r = amdgpu_cs_syncobj_export_sync_file2(device_handle, syncobj_handle,
+						16,
+						DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT,
+						&sync_fd);
+	CU_ASSERT_EQUAL(r, 0);
+	r = amdgpu_cs_syncobj_import_sync_file2(device_handle, syncobj_handle,
+						18, sync_fd);
+	CU_ASSERT_EQUAL(r, 0);
+	r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
+				    &payload, 1);
+	CU_ASSERT_EQUAL(r, 0);
+	CU_ASSERT_EQUAL(payload, 18);
+
+	// CPU signal on point 20
+	signal_point = 20;
+	r = amdgpu_cs_syncobj_timeline_signal(device_handle, &syncobj_handle,
+					      &signal_point, 1);
+	CU_ASSERT_EQUAL(r, 0);
+	r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle,
+				    &payload, 1);
+	CU_ASSERT_EQUAL(r, 0);
+	CU_ASSERT_EQUAL(payload, 20);
+
+	r = amdgpu_cs_destroy_syncobj(device_handle, syncobj_handle);
+	CU_ASSERT_EQUAL(r, 0);
+
+}
-- 
2.17.1

_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel