dri-devel Archive on lore.kernel.org
 help / color / mirror / Atom feed
From: Jonathan Gray <jsg@jsg.id.au>
To: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-dev@lists.freedesktop.org,
	Kenneth Graunke <kenneth@whitecape.org>,
	Jos?? Roberto de Souza <jose.souza@intel.com>,
	dri-devel@lists.freedesktop.org,
	Rodrigo Vivi <rodrigo.vivi@intel.com>
Subject: Re: [PATCH] intel: Add more PCI Device IDs for Coffee Lake and Ice Lake.
Date: Mon, 18 Feb 2019 16:54:34 +1100	[thread overview]
Message-ID: <20190218055434.GA65436@largo.jsg.id.au> (raw)
In-Reply-To: <bf39ff72-a660-b0ac-295e-d86a6a75f257@intel.com>

Compared to linux and libdrm Mesa is missing a VLV and ICL id.

0x0f30
ff049b6ce21d2814451afd4a116d001712e0116b
drm/i915: bind driver to ValleyView chipsets

0x8A70
d55cb4fa2cf0105bfb16b60a2846737b91fdc173
drm/i915/icl: Add the ICL PCI IDs

The Intel Media SDK describes these as

    /* VLV */
    { 0x0f30, MFX_HW_VLV, MFX_GT1 },   /* VLV mobile */

    /* ICL LP */
    { 0x8A70, MFX_HW_ICL_LP, MFX_GT1 }

and libdrm's intel_chipset.h describes the VLV id as

#define PCI_CHIP_VALLEYVIEW_PO		0x0f30 /* VLV PO board */

It isn't clear what the ICL configuration should be from public
information.

diff --git a/include/pci_ids/i965_pci_ids.h b/include/pci_ids/i965_pci_ids.h
index b91abd7a3f9..3568007b1ef 100644
--- a/include/pci_ids/i965_pci_ids.h
+++ b/include/pci_ids/i965_pci_ids.h
@@ -86,6 +86,7 @@ CHIPSET(0x0D2B, hsw_gt3, "Intel(R) Haswell")
 CHIPSET(0x0D0E, hsw_gt1, "Intel(R) Haswell")
 CHIPSET(0x0D1E, hsw_gt2, "Intel(R) Haswell")
 CHIPSET(0x0D2E, hsw_gt3, "Intel(R) Haswell")
+CHIPSET(0x0F30, byt,     "Intel(R) Bay Trail")
 CHIPSET(0x0F31, byt,     "Intel(R) Bay Trail")
 CHIPSET(0x0F32, byt,     "Intel(R) Bay Trail")
 CHIPSET(0x0F33, byt,     "Intel(R) Bay Trail")
@@ -212,4 +213,5 @@ CHIPSET(0x8A5A, icl_6x8, "Intel(R) HD Graphics (Ice Lake 6x8 GT1.5)")
 CHIPSET(0x8A5B, icl_4x8, "Intel(R) HD Graphics (Ice Lake 4x8 GT1)")
 CHIPSET(0x8A5C, icl_6x8, "Intel(R) HD Graphics (Ice Lake 6x8 GT1.5)")
 CHIPSET(0x8A5D, icl_4x8, "Intel(R) HD Graphics (Ice Lake 4x8 GT1)")
+CHIPSET(0x8A70, icl_4x8, "Intel(R) HD Graphics (Ice Lake 4x8 GT1)")
 CHIPSET(0x8A71, icl_1x8, "Intel(R) HD Graphics (Ice Lake 1x8 GT0.5)")
_______________________________________________
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

  reply	other threads:[~2019-02-18  5:54 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-02-02  8:07 [PATCH] intel: Add more PCI Device IDs for Coffee Lake and Ice Lake Rodrigo Vivi
2019-02-04 15:08 ` Lionel Landwerlin
2019-02-18  5:54   ` Jonathan Gray [this message]
2019-02-19 17:36     ` [Mesa-dev] " Rodrigo Vivi
2019-02-19 18:08       ` Ville Syrjälä
2019-02-19 18:13         ` Kenneth Graunke

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20190218055434.GA65436@largo.jsg.id.au \
    --to=jsg@jsg.id.au \
    --cc=dri-devel@lists.freedesktop.org \
    --cc=jose.souza@intel.com \
    --cc=kenneth@whitecape.org \
    --cc=lionel.g.landwerlin@intel.com \
    --cc=mesa-dev@lists.freedesktop.org \
    --cc=rodrigo.vivi@intel.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox