* [PATCH 0/2] drm/i915: Add MOCS tables for XeHP SDV and DG2 @ 2021-09-04 0:35 Matt Roper 2021-09-04 0:35 ` [PATCH 1/2] drm/i915/xehpsdv: Define MOCS table for XeHP SDV Matt Roper 2021-09-04 0:35 ` [PATCH 2/2] drm/i915/dg2: Define MOCS table for DG2 Matt Roper 0 siblings, 2 replies; 4+ messages in thread From: Matt Roper @ 2021-09-04 0:35 UTC (permalink / raw) To: intel-gfx; +Cc: dri-devel, Matt Roper Now that Ayaz's MOCS initialization series has landed on drm-intel-gt-next, we can add the new MOCS tables for XeHP SDV and DG2. [1] https://patchwork.freedesktop.org/series/94315/ Lucas De Marchi (1): drm/i915/xehpsdv: Define MOCS table for XeHP SDV Matt Roper (1): drm/i915/dg2: Define MOCS table for DG2 drivers/gpu/drm/i915/gt/intel_mocs.c | 70 +++++++++++++++++++++++++++- 1 file changed, 69 insertions(+), 1 deletion(-) -- 2.25.4 ^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH 1/2] drm/i915/xehpsdv: Define MOCS table for XeHP SDV 2021-09-04 0:35 [PATCH 0/2] drm/i915: Add MOCS tables for XeHP SDV and DG2 Matt Roper @ 2021-09-04 0:35 ` Matt Roper 2021-09-14 18:07 ` Clint Taylor 2021-09-04 0:35 ` [PATCH 2/2] drm/i915/dg2: Define MOCS table for DG2 Matt Roper 1 sibling, 1 reply; 4+ messages in thread From: Matt Roper @ 2021-09-04 0:35 UTC (permalink / raw) To: intel-gfx Cc: dri-devel, Lucas De Marchi, Daniele Ceraolo Spurio, Stuart Summers, Matt Roper From: Lucas De Marchi <lucas.demarchi@intel.com> Like DG1, XeHP SDV doesn't have LLC/eDRAM control values due to being a dgfx card. XeHP SDV adds 2 more bits: L3_GLBGO to "push the Go point to memory for L3 destined transaction" and L3_LKP to "enable Lookup for uncacheable accesses". Bspec: 45101 Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Stuart Summers <stuart.summers@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> --- drivers/gpu/drm/i915/gt/intel_mocs.c | 35 +++++++++++++++++++++++++++- 1 file changed, 34 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c index e96afd7beb49..133cfe07cb9f 100644 --- a/drivers/gpu/drm/i915/gt/intel_mocs.c +++ b/drivers/gpu/drm/i915/gt/intel_mocs.c @@ -42,6 +42,8 @@ struct drm_i915_mocs_table { #define L3_ESC(value) ((value) << 0) #define L3_SCC(value) ((value) << 1) #define _L3_CACHEABILITY(value) ((value) << 4) +#define L3_GLBGO(value) ((value) << 6) +#define L3_LKUP(value) ((value) << 7) /* Helper defines */ #define GEN9_NUM_MOCS_ENTRIES 64 /* 63-64 are reserved, but configured. */ @@ -315,6 +317,31 @@ static const struct drm_i915_mocs_entry dg1_mocs_table[] = { MOCS_ENTRY(63, 0, L3_1_UC), }; +static const struct drm_i915_mocs_entry xehpsdv_mocs_table[] = { + /* wa_1608975824 */ + MOCS_ENTRY(0, 0, L3_3_WB | L3_LKUP(1)), + + /* UC - Coherent; GO:L3 */ + MOCS_ENTRY(1, 0, L3_1_UC | L3_LKUP(1)), + /* UC - Coherent; GO:Memory */ + MOCS_ENTRY(2, 0, L3_1_UC | L3_GLBGO(1) | L3_LKUP(1)), + /* UC - Non-Coherent; GO:Memory */ + MOCS_ENTRY(3, 0, L3_1_UC | L3_GLBGO(1)), + /* UC - Non-Coherent; GO:L3 */ + MOCS_ENTRY(4, 0, L3_1_UC), + + /* WB */ + MOCS_ENTRY(5, 0, L3_3_WB | L3_LKUP(1)), + + /* HW Reserved - SW program but never use. */ + MOCS_ENTRY(48, 0, L3_3_WB | L3_LKUP(1)), + MOCS_ENTRY(49, 0, L3_1_UC | L3_LKUP(1)), + MOCS_ENTRY(60, 0, L3_1_UC), + MOCS_ENTRY(61, 0, L3_1_UC), + MOCS_ENTRY(62, 0, L3_1_UC), + MOCS_ENTRY(63, 0, L3_1_UC), +}; + enum { HAS_GLOBAL_MOCS = BIT(0), HAS_ENGINE_MOCS = BIT(1), @@ -344,7 +371,13 @@ static unsigned int get_mocs_settings(const struct drm_i915_private *i915, memset(table, 0, sizeof(struct drm_i915_mocs_table)); table->unused_entries_index = I915_MOCS_PTE; - if (IS_DG1(i915)) { + if (IS_XEHPSDV(i915)) { + table->size = ARRAY_SIZE(xehpsdv_mocs_table); + table->table = xehpsdv_mocs_table; + table->uc_index = 2; + table->n_entries = GEN9_NUM_MOCS_ENTRIES; + table->unused_entries_index = 5; + } else if (IS_DG1(i915)) { table->size = ARRAY_SIZE(dg1_mocs_table); table->table = dg1_mocs_table; table->uc_index = 1; -- 2.25.4 ^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH 1/2] drm/i915/xehpsdv: Define MOCS table for XeHP SDV 2021-09-04 0:35 ` [PATCH 1/2] drm/i915/xehpsdv: Define MOCS table for XeHP SDV Matt Roper @ 2021-09-14 18:07 ` Clint Taylor 0 siblings, 0 replies; 4+ messages in thread From: Clint Taylor @ 2021-09-14 18:07 UTC (permalink / raw) To: Matt Roper, intel-gfx Cc: dri-devel, Lucas De Marchi, Daniele Ceraolo Spurio, Stuart Summers Appears to match latest BSPEC Reviewed-by: Clint Taylor <Clinton.A.Taylor@intel.com> -Clint On 9/3/21 5:35 PM, Matt Roper wrote: > From: Lucas De Marchi <lucas.demarchi@intel.com> > > Like DG1, XeHP SDV doesn't have LLC/eDRAM control values due to being a > dgfx card. XeHP SDV adds 2 more bits: L3_GLBGO to "push the Go point to > memory for L3 destined transaction" and L3_LKP to "enable Lookup for > uncacheable accesses". > > Bspec: 45101 > Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> > Signed-off-by: Stuart Summers <stuart.summers@intel.com> > Signed-off-by: Matt Roper <matthew.d.roper@intel.com> > --- > drivers/gpu/drm/i915/gt/intel_mocs.c | 35 +++++++++++++++++++++++++++- > 1 file changed, 34 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c > index e96afd7beb49..133cfe07cb9f 100644 > --- a/drivers/gpu/drm/i915/gt/intel_mocs.c > +++ b/drivers/gpu/drm/i915/gt/intel_mocs.c > @@ -42,6 +42,8 @@ struct drm_i915_mocs_table { > #define L3_ESC(value) ((value) << 0) > #define L3_SCC(value) ((value) << 1) > #define _L3_CACHEABILITY(value) ((value) << 4) > +#define L3_GLBGO(value) ((value) << 6) > +#define L3_LKUP(value) ((value) << 7) > > /* Helper defines */ > #define GEN9_NUM_MOCS_ENTRIES 64 /* 63-64 are reserved, but configured. */ > @@ -315,6 +317,31 @@ static const struct drm_i915_mocs_entry dg1_mocs_table[] = { > MOCS_ENTRY(63, 0, L3_1_UC), > }; > > +static const struct drm_i915_mocs_entry xehpsdv_mocs_table[] = { > + /* wa_1608975824 */ > + MOCS_ENTRY(0, 0, L3_3_WB | L3_LKUP(1)), > + > + /* UC - Coherent; GO:L3 */ > + MOCS_ENTRY(1, 0, L3_1_UC | L3_LKUP(1)), > + /* UC - Coherent; GO:Memory */ > + MOCS_ENTRY(2, 0, L3_1_UC | L3_GLBGO(1) | L3_LKUP(1)), > + /* UC - Non-Coherent; GO:Memory */ > + MOCS_ENTRY(3, 0, L3_1_UC | L3_GLBGO(1)), > + /* UC - Non-Coherent; GO:L3 */ > + MOCS_ENTRY(4, 0, L3_1_UC), > + > + /* WB */ > + MOCS_ENTRY(5, 0, L3_3_WB | L3_LKUP(1)), > + > + /* HW Reserved - SW program but never use. */ > + MOCS_ENTRY(48, 0, L3_3_WB | L3_LKUP(1)), > + MOCS_ENTRY(49, 0, L3_1_UC | L3_LKUP(1)), > + MOCS_ENTRY(60, 0, L3_1_UC), > + MOCS_ENTRY(61, 0, L3_1_UC), > + MOCS_ENTRY(62, 0, L3_1_UC), > + MOCS_ENTRY(63, 0, L3_1_UC), > +}; > + > enum { > HAS_GLOBAL_MOCS = BIT(0), > HAS_ENGINE_MOCS = BIT(1), > @@ -344,7 +371,13 @@ static unsigned int get_mocs_settings(const struct drm_i915_private *i915, > memset(table, 0, sizeof(struct drm_i915_mocs_table)); > > table->unused_entries_index = I915_MOCS_PTE; > - if (IS_DG1(i915)) { > + if (IS_XEHPSDV(i915)) { > + table->size = ARRAY_SIZE(xehpsdv_mocs_table); > + table->table = xehpsdv_mocs_table; > + table->uc_index = 2; > + table->n_entries = GEN9_NUM_MOCS_ENTRIES; > + table->unused_entries_index = 5; > + } else if (IS_DG1(i915)) { > table->size = ARRAY_SIZE(dg1_mocs_table); > table->table = dg1_mocs_table; > table->uc_index = 1; ^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH 2/2] drm/i915/dg2: Define MOCS table for DG2 2021-09-04 0:35 [PATCH 0/2] drm/i915: Add MOCS tables for XeHP SDV and DG2 Matt Roper 2021-09-04 0:35 ` [PATCH 1/2] drm/i915/xehpsdv: Define MOCS table for XeHP SDV Matt Roper @ 2021-09-04 0:35 ` Matt Roper 1 sibling, 0 replies; 4+ messages in thread From: Matt Roper @ 2021-09-04 0:35 UTC (permalink / raw) To: intel-gfx; +Cc: dri-devel, Matt Roper, Ramalingam C, Matt Atwood Bspec: 45101, 45427 Cc: Ramalingam C <ramalingam.c@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com> --- drivers/gpu/drm/i915/gt/intel_mocs.c | 37 +++++++++++++++++++++++++++- 1 file changed, 36 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c index 133cfe07cb9f..d66be8457d26 100644 --- a/drivers/gpu/drm/i915/gt/intel_mocs.c +++ b/drivers/gpu/drm/i915/gt/intel_mocs.c @@ -342,6 +342,30 @@ static const struct drm_i915_mocs_entry xehpsdv_mocs_table[] = { MOCS_ENTRY(63, 0, L3_1_UC), }; +static const struct drm_i915_mocs_entry dg2_mocs_table[] = { + /* UC - Coherent; GO:L3 */ + MOCS_ENTRY(0, 0, L3_1_UC | L3_LKUP(1)), + /* UC - Coherent; GO:Memory */ + MOCS_ENTRY(1, 0, L3_1_UC | L3_GLBGO(1) | L3_LKUP(1)), + /* UC - Non-Coherent; GO:Memory */ + MOCS_ENTRY(2, 0, L3_1_UC | L3_GLBGO(1)), + + /* WB - LC */ + MOCS_ENTRY(3, 0, L3_3_WB | L3_LKUP(1)), +}; + +static const struct drm_i915_mocs_entry dg2_mocs_table_g10_ax[] = { + /* Wa_14011441408: Set Go to Memory for MOCS#0 */ + MOCS_ENTRY(0, 0, L3_1_UC | L3_GLBGO(1) | L3_LKUP(1)), + /* UC - Coherent; GO:Memory */ + MOCS_ENTRY(1, 0, L3_1_UC | L3_GLBGO(1) | L3_LKUP(1)), + /* UC - Non-Coherent; GO:Memory */ + MOCS_ENTRY(2, 0, L3_1_UC | L3_GLBGO(1)), + + /* WB - LC */ + MOCS_ENTRY(3, 0, L3_3_WB | L3_LKUP(1)), +}; + enum { HAS_GLOBAL_MOCS = BIT(0), HAS_ENGINE_MOCS = BIT(1), @@ -371,7 +395,18 @@ static unsigned int get_mocs_settings(const struct drm_i915_private *i915, memset(table, 0, sizeof(struct drm_i915_mocs_table)); table->unused_entries_index = I915_MOCS_PTE; - if (IS_XEHPSDV(i915)) { + if (IS_DG2(i915)) { + if (IS_DG2_GT_STEP(i915, G10, STEP_A0, STEP_B0)) { + table->size = ARRAY_SIZE(dg2_mocs_table_g10_ax); + table->table = dg2_mocs_table_g10_ax; + } else { + table->size = ARRAY_SIZE(dg2_mocs_table); + table->table = dg2_mocs_table; + } + table->uc_index = 1; + table->n_entries = GEN9_NUM_MOCS_ENTRIES; + table->unused_entries_index = 3; + } else if (IS_XEHPSDV(i915)) { table->size = ARRAY_SIZE(xehpsdv_mocs_table); table->table = xehpsdv_mocs_table; table->uc_index = 2; -- 2.25.4 ^ permalink raw reply related [flat|nested] 4+ messages in thread
end of thread, other threads:[~2021-09-14 18:11 UTC | newest] Thread overview: 4+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2021-09-04 0:35 [PATCH 0/2] drm/i915: Add MOCS tables for XeHP SDV and DG2 Matt Roper 2021-09-04 0:35 ` [PATCH 1/2] drm/i915/xehpsdv: Define MOCS table for XeHP SDV Matt Roper 2021-09-14 18:07 ` Clint Taylor 2021-09-04 0:35 ` [PATCH 2/2] drm/i915/dg2: Define MOCS table for DG2 Matt Roper
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