[PATCH 0/2] drm/msm/a6xx: use correct timestamp counter on A750 GPU

[PATCH 0/2] drm/msm/a6xx: use correct timestamp counter on A750 GPU

[Neil Armstrong]

The A750 uses a different counter register as used on the downstream
driver:

static u64 gen7_9_0_read_alwayson(struct adreno_device *adreno_dev)
{
...
	/* Always use the GMU AO counter when doing a AHB read */
	gmu_core_regread(device, GEN7_GMU_CX_AO_COUNTER_HI, &hi);
	gmu_core_regread(device, GEN7_GMU_CX_AO_COUNTER_LO, &lo);
...
}

gen7_reg.h:#define GEN7_GMU_CX_AO_COUNTER_LO		0x1f880
gen7_reg.h:#define GEN7_GMU_CX_AO_COUNTER_HI		0x1f881

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
---
Neil Armstrong (2):
      drm/msm/a6xx: Add CX AO Counter registers used for a750 GPUs
      drm/msm/a6xx: Use CX AO Counter register for timestamp on a750 GPUs

 drivers/gpu/drm/msm/adreno/a6xx_gpu.c             | 12 +++++++++---
 drivers/gpu/drm/msm/registers/adreno/a6xx_gmu.xml |  2 ++
 2 files changed, 11 insertions(+), 3 deletions(-)
---
base-commit: df2908090cda368b01ff43709f51890076c56157
change-id: 20260908-topic-sm8650-gmu-a750-timestamp-reg-2e7575e6279d

Best regards,
--  
Neil Armstrong <neil.armstrong@linaro.org>

[PATCH 1/2] drm/msm/a6xx: Add CX AO Counter registers used for a750 GPUs

[Neil Armstrong]

The a750 uses the CX AO Counters instead of the GMU_ALWAYS_ON_COUNTER
register on A6xx and other A7xx GPUs.

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
---
 drivers/gpu/drm/msm/registers/adreno/a6xx_gmu.xml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/msm/registers/adreno/a6xx_gmu.xml b/drivers/gpu/drm/msm/registers/adreno/a6xx_gmu.xml
index 33404eb18fd0..3fe7bc3ea93d 100644
--- a/drivers/gpu/drm/msm/registers/adreno/a6xx_gmu.xml
+++ b/drivers/gpu/drm/msm/registers/adreno/a6xx_gmu.xml
@@ -141,6 +141,8 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
 	<reg32 offset="0x1f9f0" name="GMU_BOOT_KMD_LM_HANDSHAKE"/>
 	<reg32 offset="0x1f957" name="GMU_LLM_GLM_SLEEP_CTRL"/>
 	<reg32 offset="0x1f958" name="GMU_LLM_GLM_SLEEP_STATUS"/>
+	<reg32 offset="0x1f880" name="GMU_CX_AO_COUNTER_H" variants="A7XX"/>
+	<reg32 offset="0x1f881" name="GMU_CX_AO_COUNTER_L" variants="A7XX"/>
 	<reg32 offset="0x1f888" name="GMU_ALWAYS_ON_COUNTER_L" variants="A6XX-A7XX"/>
 	<reg32 offset="0x1f840" name="GMU_ALWAYS_ON_COUNTER_L" variants="A8XX-"/>
 	<reg32 offset="0x1f889" name="GMU_ALWAYS_ON_COUNTER_H" variants="A6XX-A7XX"/>

-- 
2.34.1

[PATCH 2/2] drm/msm/a6xx: Use CX AO Counter register for timestamp on a750 GPUs

[Neil Armstrong]

The a750 uses the CX AO Counters instead of the GMU_ALWAYS_ON_COUNTER
register on A6xx and other A7xx GPUs, use it when running a A750 GPU.

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
---
 drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 12 +++++++++---
 1 file changed, 9 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index f9de9329dee3..081e79ea4652 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -23,9 +23,15 @@ static u64 a6xx_gmu_get_timestamp(struct msm_gpu *gpu)
 	u64 count_hi, count_lo, temp;
 
 	do {
-		count_hi = gmu_read(&a6xx_gpu->gmu, REG_A6XX_GMU_ALWAYS_ON_COUNTER_H);
-		count_lo = gmu_read(&a6xx_gpu->gmu, REG_A6XX_GMU_ALWAYS_ON_COUNTER_L);
-		temp = gmu_read(&a6xx_gpu->gmu, REG_A6XX_GMU_ALWAYS_ON_COUNTER_H);
+		if (adreno_is_a750_family(adreno_gpu)) {
+			count_hi = gmu_read(&a6xx_gpu->gmu, REG_A7XX_GMU_CX_AO_COUNTER_H);
+			count_lo = gmu_read(&a6xx_gpu->gmu, REG_A7XX_GMU_CX_AO_COUNTER_L);
+			temp = gmu_read(&a6xx_gpu->gmu, REG_A7XX_GMU_CX_AO_COUNTER_H);
+		} else {
+			count_hi = gmu_read(&a6xx_gpu->gmu, REG_A6XX_GMU_ALWAYS_ON_COUNTER_H);
+			count_lo = gmu_read(&a6xx_gpu->gmu, REG_A6XX_GMU_ALWAYS_ON_COUNTER_L);
+			temp = gmu_read(&a6xx_gpu->gmu, REG_A6XX_GMU_ALWAYS_ON_COUNTER_H);
+		}
 	} while (unlikely(count_hi != temp));
 
 	return (count_hi << 32) | count_lo;

-- 
2.34.1

Re: [PATCH 2/2] drm/msm/a6xx: Use CX AO Counter register for timestamp on a750 GPUs

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Critical] The lockless 64-bit counter read loop will spin indefinitely on A750 GPUs, causing a hard CPU hang, because the high and low register offsets for the CX AO counter are swapped in their XML definitions.
--

commit cf31c6e4a536e6c06c20aa83c73f0af1762a7d51
Author: Neil Armstrong <neil.armstrong@linaro.org>

drm/msm/a6xx: Use CX AO Counter register for timestamp on a750 GPUs

The a750 uses the CX AO Counters instead of the GMU_ALWAYS_ON_COUNTER
register on A6xx and other A7xx GPUs, use it when running a A750 GPU.

> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> index f9de9329dee39..081e79ea46528 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> @@ -23,9 +23,15 @@ static u64 a6xx_gmu_get_timestamp(struct msm_gpu *gpu)
>  	u64 count_hi, count_lo, temp;
>  
>  	do {
> -		count_hi = gmu_read(&a6xx_gpu->gmu, REG_A6XX_GMU_ALWAYS_ON_COUNTER_H);
> -		count_lo = gmu_read(&a6xx_gpu->gmu, REG_A6XX_GMU_ALWAYS_ON_COUNTER_L);
> -		temp = gmu_read(&a6xx_gpu->gmu, REG_A6XX_GMU_ALWAYS_ON_COUNTER_H);
> +		if (adreno_is_a750_family(adreno_gpu)) {
> +			count_hi = gmu_read(&a6xx_gpu->gmu, REG_A7XX_GMU_CX_AO_COUNTER_H);
> +			count_lo = gmu_read(&a6xx_gpu->gmu, REG_A7XX_GMU_CX_AO_COUNTER_L);
> +			temp = gmu_read(&a6xx_gpu->gmu, REG_A7XX_GMU_CX_AO_COUNTER_H);
> +		} else {
> +			count_hi = gmu_read(&a6xx_gpu->gmu, REG_A6XX_GMU_ALWAYS_ON_COUNTER_H);
> +			count_lo = gmu_read(&a6xx_gpu->gmu, REG_A6XX_GMU_ALWAYS_ON_COUNTER_L);
> +			temp = gmu_read(&a6xx_gpu->gmu, REG_A6XX_GMU_ALWAYS_ON_COUNTER_H);
> +		}
>  	} while (unlikely(count_hi != temp));
        ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

[Severity: Critical]
Could this cause an infinite loop on A750 GPUs?

In drivers/gpu/drm/msm/registers/adreno/a6xx_gmu.xml, the register offsets
for the A750 CX AO counter appear to be swapped:

	<reg32 offset="0x1f880" name="GMU_CX_AO_COUNTER_H" variants="A7XX"/>
	<reg32 offset="0x1f881" name="GMU_CX_AO_COUNTER_L" variants="A7XX"/>

Since the H offset points to the lower 32 bits (0x1f880), this loop will
read the fast-changing lower 32 bits into count_hi and temp. Because these
bits change rapidly, won't the comparison (count_hi != temp) almost always
evaluate to true, causing a hard CPU hang in a6xx_gmu_get_timestamp()?

>  
>  	return (count_hi << 32) | count_lo;

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260908-topic-sm8650-gmu-a750-timestamp-reg-v1-0-284880d6e68b@linaro.org?part=2

Re: [PATCH 1/2] drm/msm/a6xx: Add CX AO Counter registers used for a750 GPUs

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] Swapped _H and _L register offsets for GMU_CX_AO_COUNTER cause incorrect timestamp calculation and potential infinite loop.
--

commit 6a7904eb81671357880e41c095c0516fdc10e669
Author: Neil Armstrong <neil.armstrong@linaro.org>

drm/msm/a6xx: Add CX AO Counter registers used for a750 GPUs

This commit adds the CX AO Counters to the a6xx GMU XML definitions for
use on a750 GPUs. These replace the GMU_ALWAYS_ON_COUNTER register used
on other A6xx and A7xx variants.

> diff --git a/drivers/gpu/drm/msm/registers/adreno/a6xx_gmu.xml b/drivers/gpu/drm/msm/registers/adreno/a6xx_gmu.xml
> index 33404eb18fd02..3fe7bc3ea93d1 100644
> --- a/drivers/gpu/drm/msm/registers/adreno/a6xx_gmu.xml
> +++ b/drivers/gpu/drm/msm/registers/adreno/a6xx_gmu.xml
> @@ -141,6 +141,8 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
>  	<reg32 offset="0x1f9f0" name="GMU_BOOT_KMD_LM_HANDSHAKE"/>
>  	<reg32 offset="0x1f957" name="GMU_LLM_GLM_SLEEP_CTRL"/>
>  	<reg32 offset="0x1f958" name="GMU_LLM_GLM_SLEEP_STATUS"/>
> +	<reg32 offset="0x1f880" name="GMU_CX_AO_COUNTER_H" variants="A7XX"/>
> +	<reg32 offset="0x1f881" name="GMU_CX_AO_COUNTER_L" variants="A7XX"/>

[Severity: High]
Are the offsets for GMU_CX_AO_COUNTER_H and GMU_CX_AO_COUNTER_L swapped
here? 

Usually, standard little-endian hardware counters place the lower 32 bits
(_L) at the lower offset (0x1f880) and the upper 32 bits (_H) at the higher
offset (0x1f881).

If GMU_CX_AO_COUNTER_H points to the fast-changing lower 32 bits of the
counter, it could cause an infinite loop in a6xx_gmu_get_timestamp(). That
function relies on a read-retry loop to ensure the high bits haven't rolled
over:

    do {
        count_hi = read(_H);
        count_lo = read(_L);
        temp = read(_H);
    } while (unlikely(count_hi != temp));

If _H is mapped to the lower bits, which increment rapidly at 19.2 MHz, the
two reads of _H will almost always yield different values due to MMIO
latency. This would cause the loop to spin indefinitely and potentially lock
up the CPU, returning corrupted timestamps if it ever manages to exit.

>  	<reg32 offset="0x1f888" name="GMU_ALWAYS_ON_COUNTER_L" variants="A6XX-A7XX"/>
>  	<reg32 offset="0x1f840" name="GMU_ALWAYS_ON_COUNTER_L" variants="A8XX-"/>
>  	<reg32 offset="0x1f889" name="GMU_ALWAYS_ON_COUNTER_H" variants="A6XX-A7XX"/>

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260908-topic-sm8650-gmu-a750-timestamp-reg-v1-0-284880d6e68b@linaro.org?part=1

Re: [PATCH 1/2] drm/msm/a6xx: Add CX AO Counter registers used for a750 GPUs

[Neil Armstrong]

On 9/8/26 15:24, Neil Armstrong wrote:
> The a750 uses the CX AO Counters instead of the GMU_ALWAYS_ON_COUNTER
> register on A6xx and other A7xx GPUs.
> 
> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
> ---
>   drivers/gpu/drm/msm/registers/adreno/a6xx_gmu.xml | 2 ++
>   1 file changed, 2 insertions(+)
> 
> diff --git a/drivers/gpu/drm/msm/registers/adreno/a6xx_gmu.xml b/drivers/gpu/drm/msm/registers/adreno/a6xx_gmu.xml
> index 33404eb18fd0..3fe7bc3ea93d 100644
> --- a/drivers/gpu/drm/msm/registers/adreno/a6xx_gmu.xml
> +++ b/drivers/gpu/drm/msm/registers/adreno/a6xx_gmu.xml
> @@ -141,6 +141,8 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
>   	<reg32 offset="0x1f9f0" name="GMU_BOOT_KMD_LM_HANDSHAKE"/>
>   	<reg32 offset="0x1f957" name="GMU_LLM_GLM_SLEEP_CTRL"/>
>   	<reg32 offset="0x1f958" name="GMU_LLM_GLM_SLEEP_STATUS"/>
> +	<reg32 offset="0x1f880" name="GMU_CX_AO_COUNTER_H" variants="A7XX"/>
> +	<reg32 offset="0x1f881" name="GMU_CX_AO_COUNTER_L" variants="A7XX"/>

It's swapped.... please ignore this patchset I'll send a v2 with the proper offsets

>   	<reg32 offset="0x1f888" name="GMU_ALWAYS_ON_COUNTER_L" variants="A6XX-A7XX"/>
>   	<reg32 offset="0x1f840" name="GMU_ALWAYS_ON_COUNTER_L" variants="A8XX-"/>
>   	<reg32 offset="0x1f889" name="GMU_ALWAYS_ON_COUNTER_H" variants="A6XX-A7XX"/>
> 

Neil

Re: [PATCH 2/2] drm/msm/a6xx: Use CX AO Counter register for timestamp on a750 GPUs

[Konrad Dybcio]

On 9/8/26 3:24 PM, Neil Armstrong wrote:
> The a750 uses the CX AO Counters instead of the GMU_ALWAYS_ON_COUNTER
> register on A6xx and other A7xx GPUs, use it when running a A750 GPU.
> 
> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
> ---
>  drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 12 +++++++++---
>  1 file changed, 9 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> index f9de9329dee3..081e79ea4652 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> @@ -23,9 +23,15 @@ static u64 a6xx_gmu_get_timestamp(struct msm_gpu *gpu)
>  	u64 count_hi, count_lo, temp;
>  
>  	do {
> -		count_hi = gmu_read(&a6xx_gpu->gmu, REG_A6XX_GMU_ALWAYS_ON_COUNTER_H);
> -		count_lo = gmu_read(&a6xx_gpu->gmu, REG_A6XX_GMU_ALWAYS_ON_COUNTER_L);
> -		temp = gmu_read(&a6xx_gpu->gmu, REG_A6XX_GMU_ALWAYS_ON_COUNTER_H);
> +		if (adreno_is_a750_family(adreno_gpu)) {
> +			count_hi = gmu_read(&a6xx_gpu->gmu, REG_A7XX_GMU_CX_AO_COUNTER_H);
> +			count_lo = gmu_read(&a6xx_gpu->gmu, REG_A7XX_GMU_CX_AO_COUNTER_L);
> +			temp = gmu_read(&a6xx_gpu->gmu, REG_A7XX_GMU_CX_AO_COUNTER_H);

KGSL apparently *writes* the system time to these registers, is that
an idiosyncrasy regarding how the vendor userland drivers then use
this counter?

Konrad

P.S. looks like a8xx also has this counter

Re: [PATCH 2/2] drm/msm/a6xx: Use CX AO Counter register for timestamp on a750 GPUs

[Neil Armstrong]

On 9/9/26 11:06, Konrad Dybcio wrote:
> On 9/8/26 3:24 PM, Neil Armstrong wrote:
>> The a750 uses the CX AO Counters instead of the GMU_ALWAYS_ON_COUNTER
>> register on A6xx and other A7xx GPUs, use it when running a A750 GPU.
>>
>> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
>> ---
>>   drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 12 +++++++++---
>>   1 file changed, 9 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
>> index f9de9329dee3..081e79ea4652 100644
>> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
>> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
>> @@ -23,9 +23,15 @@ static u64 a6xx_gmu_get_timestamp(struct msm_gpu *gpu)
>>   	u64 count_hi, count_lo, temp;
>>   
>>   	do {
>> -		count_hi = gmu_read(&a6xx_gpu->gmu, REG_A6XX_GMU_ALWAYS_ON_COUNTER_H);
>> -		count_lo = gmu_read(&a6xx_gpu->gmu, REG_A6XX_GMU_ALWAYS_ON_COUNTER_L);
>> -		temp = gmu_read(&a6xx_gpu->gmu, REG_A6XX_GMU_ALWAYS_ON_COUNTER_H);
>> +		if (adreno_is_a750_family(adreno_gpu)) {
>> +			count_hi = gmu_read(&a6xx_gpu->gmu, REG_A7XX_GMU_CX_AO_COUNTER_H);
>> +			count_lo = gmu_read(&a6xx_gpu->gmu, REG_A7XX_GMU_CX_AO_COUNTER_L);
>> +			temp = gmu_read(&a6xx_gpu->gmu, REG_A7XX_GMU_CX_AO_COUNTER_H);
> 
> KGSL apparently *writes* the system time to these registers, is that
> an idiosyncrasy regarding how the vendor userland drivers then use
> this counter?

This is a GMU counter, no sure why & how KGSL or freedreno would write anything to it...

> 
> Konrad
> 
> P.S. looks like a8xx also has this counter
> 

Re: [PATCH 2/2] drm/msm/a6xx: Use CX AO Counter register for timestamp on a750 GPUs

[Connor Abbott]

On Wed, Sep 9, 2026 at 5:32 AM Neil Armstrong <neil.armstrong@linaro.org> wrote:
>
> On 9/9/26 11:06, Konrad Dybcio wrote:
> > On 9/8/26 3:24 PM, Neil Armstrong wrote:
> >> The a750 uses the CX AO Counters instead of the GMU_ALWAYS_ON_COUNTER
> >> register on A6xx and other A7xx GPUs, use it when running a A750 GPU.
> >>
> >> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
> >> ---
> >>   drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 12 +++++++++---
> >>   1 file changed, 9 insertions(+), 3 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> >> index f9de9329dee3..081e79ea4652 100644
> >> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> >> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> >> @@ -23,9 +23,15 @@ static u64 a6xx_gmu_get_timestamp(struct msm_gpu *gpu)
> >>      u64 count_hi, count_lo, temp;
> >>
> >>      do {
> >> -            count_hi = gmu_read(&a6xx_gpu->gmu, REG_A6XX_GMU_ALWAYS_ON_COUNTER_H);
> >> -            count_lo = gmu_read(&a6xx_gpu->gmu, REG_A6XX_GMU_ALWAYS_ON_COUNTER_L);
> >> -            temp = gmu_read(&a6xx_gpu->gmu, REG_A6XX_GMU_ALWAYS_ON_COUNTER_H);
> >> +            if (adreno_is_a750_family(adreno_gpu)) {
> >> +                    count_hi = gmu_read(&a6xx_gpu->gmu, REG_A7XX_GMU_CX_AO_COUNTER_H);
> >> +                    count_lo = gmu_read(&a6xx_gpu->gmu, REG_A7XX_GMU_CX_AO_COUNTER_L);
> >> +                    temp = gmu_read(&a6xx_gpu->gmu, REG_A7XX_GMU_CX_AO_COUNTER_H);
> >
> > KGSL apparently *writes* the system time to these registers, is that
> > an idiosyncrasy regarding how the vendor userland drivers then use
> > this counter?
>
> This is a GMU counter, no sure why & how KGSL or freedreno would write anything to it...

It is writeable. This is part of implementing
VK_KHR_calibrated_timestamps. The idea is that when the GPU suspends
and resumes, we keep track of how many ticks it would've taken and
then pretend to advance the counter by writing the CX counter (after
powering on CX but before powering on GX which initializes the normal
GMU counter).

Note that VK_KHR_calibrated_timestamps worked initially on turnip but
the tests started failing with v6.19. I haven't bisected yet but my
guess is CX was never actually collapsing for whatever reason and we
made it collapse hence breaking the tests. So we probably do need
this.

Connor

>
> >
> > Konrad
> >
> > P.S. looks like a8xx also has this counter
> >
>

Re: [PATCH 2/2] drm/msm/a6xx: Use CX AO Counter register for timestamp on a750 GPUs

[Neil Armstrong]

On 9/9/26 15:24, Connor Abbott wrote:
> On Wed, Sep 9, 2026 at 5:32 AM Neil Armstrong <neil.armstrong@linaro.org> wrote:
>>
>> On 9/9/26 11:06, Konrad Dybcio wrote:
>>> On 9/8/26 3:24 PM, Neil Armstrong wrote:
>>>> The a750 uses the CX AO Counters instead of the GMU_ALWAYS_ON_COUNTER
>>>> register on A6xx and other A7xx GPUs, use it when running a A750 GPU.
>>>>
>>>> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
>>>> ---
>>>>    drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 12 +++++++++---
>>>>    1 file changed, 9 insertions(+), 3 deletions(-)
>>>>
>>>> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
>>>> index f9de9329dee3..081e79ea4652 100644
>>>> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
>>>> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
>>>> @@ -23,9 +23,15 @@ static u64 a6xx_gmu_get_timestamp(struct msm_gpu *gpu)
>>>>       u64 count_hi, count_lo, temp;
>>>>
>>>>       do {
>>>> -            count_hi = gmu_read(&a6xx_gpu->gmu, REG_A6XX_GMU_ALWAYS_ON_COUNTER_H);
>>>> -            count_lo = gmu_read(&a6xx_gpu->gmu, REG_A6XX_GMU_ALWAYS_ON_COUNTER_L);
>>>> -            temp = gmu_read(&a6xx_gpu->gmu, REG_A6XX_GMU_ALWAYS_ON_COUNTER_H);
>>>> +            if (adreno_is_a750_family(adreno_gpu)) {
>>>> +                    count_hi = gmu_read(&a6xx_gpu->gmu, REG_A7XX_GMU_CX_AO_COUNTER_H);
>>>> +                    count_lo = gmu_read(&a6xx_gpu->gmu, REG_A7XX_GMU_CX_AO_COUNTER_L);
>>>> +                    temp = gmu_read(&a6xx_gpu->gmu, REG_A7XX_GMU_CX_AO_COUNTER_H);
>>>
>>> KGSL apparently *writes* the system time to these registers, is that
>>> an idiosyncrasy regarding how the vendor userland drivers then use
>>> this counter?
>>
>> This is a GMU counter, no sure why & how KGSL or freedreno would write anything to it...
> 
> It is writeable. This is part of implementing
> VK_KHR_calibrated_timestamps. The idea is that when the GPU suspends
> and resumes, we keep track of how many ticks it would've taken and
> then pretend to advance the counter by writing the CX counter (after
> powering on CX but before powering on GX which initializes the normal
> GMU counter).
> 
> Note that VK_KHR_calibrated_timestamps worked initially on turnip but
> the tests started failing with v6.19. I haven't bisected yet but my
> guess is CX was never actually collapsing for whatever reason and we
> made it collapse hence breaking the tests. So we probably do need
> this.

OK thanks for the detail! Today it's only used for perfetto, but still
on A750 a different register is used for this purpose.

Neil

> 
> Connor
> 
>>
>>>
>>> Konrad
>>>
>>> P.S. looks like a8xx also has this counter
>>>
>>

Re: [PATCH 2/2] drm/msm/a6xx: Use CX AO Counter register for timestamp on a750 GPUs

[Connor Abbott]

On Wed, Sep 9, 2026 at 10:29 AM Neil Armstrong
<neil.armstrong@linaro.org> wrote:
>
> On 9/9/26 15:24, Connor Abbott wrote:
> > On Wed, Sep 9, 2026 at 5:32 AM Neil Armstrong <neil.armstrong@linaro.org> wrote:
> >>
> >> On 9/9/26 11:06, Konrad Dybcio wrote:
> >>> On 9/8/26 3:24 PM, Neil Armstrong wrote:
> >>>> The a750 uses the CX AO Counters instead of the GMU_ALWAYS_ON_COUNTER
> >>>> register on A6xx and other A7xx GPUs, use it when running a A750 GPU.
> >>>>
> >>>> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
> >>>> ---
> >>>>    drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 12 +++++++++---
> >>>>    1 file changed, 9 insertions(+), 3 deletions(-)
> >>>>
> >>>> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> >>>> index f9de9329dee3..081e79ea4652 100644
> >>>> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> >>>> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> >>>> @@ -23,9 +23,15 @@ static u64 a6xx_gmu_get_timestamp(struct msm_gpu *gpu)
> >>>>       u64 count_hi, count_lo, temp;
> >>>>
> >>>>       do {
> >>>> -            count_hi = gmu_read(&a6xx_gpu->gmu, REG_A6XX_GMU_ALWAYS_ON_COUNTER_H);
> >>>> -            count_lo = gmu_read(&a6xx_gpu->gmu, REG_A6XX_GMU_ALWAYS_ON_COUNTER_L);
> >>>> -            temp = gmu_read(&a6xx_gpu->gmu, REG_A6XX_GMU_ALWAYS_ON_COUNTER_H);
> >>>> +            if (adreno_is_a750_family(adreno_gpu)) {
> >>>> +                    count_hi = gmu_read(&a6xx_gpu->gmu, REG_A7XX_GMU_CX_AO_COUNTER_H);
> >>>> +                    count_lo = gmu_read(&a6xx_gpu->gmu, REG_A7XX_GMU_CX_AO_COUNTER_L);
> >>>> +                    temp = gmu_read(&a6xx_gpu->gmu, REG_A7XX_GMU_CX_AO_COUNTER_H);
> >>>
> >>> KGSL apparently *writes* the system time to these registers, is that
> >>> an idiosyncrasy regarding how the vendor userland drivers then use
> >>> this counter?
> >>
> >> This is a GMU counter, no sure why & how KGSL or freedreno would write anything to it...
> >
> > It is writeable. This is part of implementing
> > VK_KHR_calibrated_timestamps. The idea is that when the GPU suspends
> > and resumes, we keep track of how many ticks it would've taken and
> > then pretend to advance the counter by writing the CX counter (after
> > powering on CX but before powering on GX which initializes the normal
> > GMU counter).
> >
> > Note that VK_KHR_calibrated_timestamps worked initially on turnip but
> > the tests started failing with v6.19. I haven't bisected yet but my
> > guess is CX was never actually collapsing for whatever reason and we
> > made it collapse hence breaking the tests. So we probably do need
> > this.
>
> OK thanks for the detail! Today it's only used for perfetto, but still
> on A750 a different register is used for this purpose.
>
> Neil

Well technically no, today this function is also used by
VK_KHR_calibrated_timestamps on turnip and today it's broken because
of a kernel regression...

Connor

>
> >
> > Connor
> >
> >>
> >>>
> >>> Konrad
> >>>
> >>> P.S. looks like a8xx also has this counter
> >>>
> >>
>

Re: [PATCH 2/2] drm/msm/a6xx: Use CX AO Counter register for timestamp on a750 GPUs

[Akhil P Oommen]

On 9/8/2026 6:54 PM, Neil Armstrong wrote:
> The a750 uses the CX AO Counters instead of the GMU_ALWAYS_ON_COUNTER
> register on A6xx and other A7xx GPUs, use it when running a A750 GPU.

Do you see any difference in behavior? Both counters are synchronized.

-Akhil.

> 
> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
> ---
>  drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 12 +++++++++---
>  1 file changed, 9 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> index f9de9329dee3..081e79ea4652 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> @@ -23,9 +23,15 @@ static u64 a6xx_gmu_get_timestamp(struct msm_gpu *gpu)
>  	u64 count_hi, count_lo, temp;
>  
>  	do {
> -		count_hi = gmu_read(&a6xx_gpu->gmu, REG_A6XX_GMU_ALWAYS_ON_COUNTER_H);
> -		count_lo = gmu_read(&a6xx_gpu->gmu, REG_A6XX_GMU_ALWAYS_ON_COUNTER_L);
> -		temp = gmu_read(&a6xx_gpu->gmu, REG_A6XX_GMU_ALWAYS_ON_COUNTER_H);
> +		if (adreno_is_a750_family(adreno_gpu)) {
> +			count_hi = gmu_read(&a6xx_gpu->gmu, REG_A7XX_GMU_CX_AO_COUNTER_H);
> +			count_lo = gmu_read(&a6xx_gpu->gmu, REG_A7XX_GMU_CX_AO_COUNTER_L);
> +			temp = gmu_read(&a6xx_gpu->gmu, REG_A7XX_GMU_CX_AO_COUNTER_H);
> +		} else {
> +			count_hi = gmu_read(&a6xx_gpu->gmu, REG_A6XX_GMU_ALWAYS_ON_COUNTER_H);
> +			count_lo = gmu_read(&a6xx_gpu->gmu, REG_A6XX_GMU_ALWAYS_ON_COUNTER_L);
> +			temp = gmu_read(&a6xx_gpu->gmu, REG_A6XX_GMU_ALWAYS_ON_COUNTER_H);
> +		}
>  	} while (unlikely(count_hi != temp));
>  
>  	return (count_hi << 32) | count_lo;
> 

Re: [PATCH 2/2] drm/msm/a6xx: Use CX AO Counter register for timestamp on a750 GPUs

[Neil Armstrong]

On 9/9/26 20:31, Akhil P Oommen wrote:
> 
> 
> On 9/8/2026 6:54 PM, Neil Armstrong wrote:
>> The a750 uses the CX AO Counters instead of the GMU_ALWAYS_ON_COUNTER
>> register on A6xx and other A7xx GPUs, use it when running a A750 GPU.
> 
> Do you see any difference in behavior? Both counters are synchronized.

GMU_ALWAYS_ON_COUNTER_H/L returns 0 on SM8650

Neil

> 
> -Akhil.
> 
>>
>> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
>> ---
>>   drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 12 +++++++++---
>>   1 file changed, 9 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
>> index f9de9329dee3..081e79ea4652 100644
>> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
>> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
>> @@ -23,9 +23,15 @@ static u64 a6xx_gmu_get_timestamp(struct msm_gpu *gpu)
>>   	u64 count_hi, count_lo, temp;
>>   
>>   	do {
>> -		count_hi = gmu_read(&a6xx_gpu->gmu, REG_A6XX_GMU_ALWAYS_ON_COUNTER_H);
>> -		count_lo = gmu_read(&a6xx_gpu->gmu, REG_A6XX_GMU_ALWAYS_ON_COUNTER_L);
>> -		temp = gmu_read(&a6xx_gpu->gmu, REG_A6XX_GMU_ALWAYS_ON_COUNTER_H);
>> +		if (adreno_is_a750_family(adreno_gpu)) {
>> +			count_hi = gmu_read(&a6xx_gpu->gmu, REG_A7XX_GMU_CX_AO_COUNTER_H);
>> +			count_lo = gmu_read(&a6xx_gpu->gmu, REG_A7XX_GMU_CX_AO_COUNTER_L);
>> +			temp = gmu_read(&a6xx_gpu->gmu, REG_A7XX_GMU_CX_AO_COUNTER_H);
>> +		} else {
>> +			count_hi = gmu_read(&a6xx_gpu->gmu, REG_A6XX_GMU_ALWAYS_ON_COUNTER_H);
>> +			count_lo = gmu_read(&a6xx_gpu->gmu, REG_A6XX_GMU_ALWAYS_ON_COUNTER_L);
>> +			temp = gmu_read(&a6xx_gpu->gmu, REG_A6XX_GMU_ALWAYS_ON_COUNTER_H);
>> +		}
>>   	} while (unlikely(count_hi != temp));
>>   
>>   	return (count_hi << 32) | count_lo;
>>
>