[PATCH 0/3] drm/nouveau: HDMI Deep Color link depth (30/36/48 bpp)

[PATCH 0/3] drm/nouveau: HDMI Deep Color link depth (30/36/48 bpp)

[Daniel Campos Ramos]

This series wires up HDMI Deep Color on nouveau.  The connector gains the
"max bpc" property, the atomic check selects a link depth that both the
sink EDID (HDMI VSDB DC_30/36/48) and the TMDS character-rate budget
admit, the head is programmed for 30/36/48 bpp RGB, and the TMDS General
Control Packet carries the matching CD/PP fields.

Patch 3 is what makes the link physically work on GSP boards.  The
GV100-class GCP writers emitted a depth-less packet, and on GSP systems
the HDMI audio enable runs after the display commit and emits it again,
erasing the deep-color declaration (sor->disp->func->gsp.hdmi_gcp).  The
proprietary NVIDIA stack performs the same audio operation and then
rebuilds the GCP from the committed head depth.  Threading CD/PP through
the OUTP HDMI ctrl method (patch 2), caching them on the ior, and writing
them with a 0x00ffffff mask gives nouveau the same ordering; the mask also
keeps generation-specific bits sharing the register intact (GB20x
SB1_CTRL).

Tested on a GA106 (RTX 3060) driving a Sony KDL-46HX855 (HDMI 1.4 sink,
EDID DC_30/DC_36, 225 MHz TMDS ceiling): 1920x1080p60 RGB at 36 bpp,
i.e. a 222.75 MHz character rate.  Without the series the sink rejects
the modeset with an incompatible-signal OSD; with it the set accepts the
signal, reports a 12-bit input, and renders correctly.  30 bpp follows
the same code paths.

Scope and non-goals, so nobody has to guess:

- Only RGB is selected.  YCbCr output additionally needs a connector
  color-format selection path that nouveau does not have today, plus AVI
  InfoFrame colorspace/range handling and format-aware bandwidth and
  packing.  That is the next series, building on the DRM connector
  color-format property work.
- 48 bpp (16 bpc) is implemented from DC_48, BPP_48_444 and GCP CD=7 but
  is untested: the bench has no DC_48 sink.  It might enable professional
  16-bit displays; the mechanism is the same, but we do not own the
  hardware to test or claim it.
- HDR might benefit: HDR10's baseline transport is 10-bpc YCbCr 4:2:2
  carried in a 12-bpc container, and link-depth failures feature in HDR
  reports.  The transport mechanism is the same, but we do not have
  hardware to test or claim native HDR here (static metadata and
  colorspace are separate pieces nouveau does not yet emit for HDMI).

For context: on this same bench the installed proprietary NVIDIA driver
(615.71.09, hdmi_deepcolor=Y, max_output_color_depth=10) caps this sink
at 10 bpc by default policy, while Windows on the same card reports
12 bpc.  A companion one-line default-cap change for the open NVIDIA
kernel modules is being submitted to its own repository as the
closed-source counterpart of this series.

AI partners were leveraged in the production of this work.

Daniel Campos Ramos (3):
  drm/nouveau: select HDMI deep-color link depth
  drm/nouveau: pass HDMI GCP deep-color state through NVIF
  drm/nouveau: program HDMI deep-color GCP fields

 drivers/gpu/drm/nouveau/dispnv50/disp.c       | 80 +++++++++++++++++--
 drivers/gpu/drm/nouveau/dispnv50/headc37d.c   |  6 ++
 drivers/gpu/drm/nouveau/dispnv50/headc57d.c   |  6 ++
 drivers/gpu/drm/nouveau/dispnv50/headca7d.c   |  6 ++
 drivers/gpu/drm/nouveau/include/nvif/if0012.h |  3 +
 drivers/gpu/drm/nouveau/include/nvif/outp.h   |  2 +-
 drivers/gpu/drm/nouveau/nouveau_connector.c   |  9 ++-
 drivers/gpu/drm/nouveau/nouveau_connector.h   |  1 +
 drivers/gpu/drm/nouveau/nvif/outp.c           |  7 +-
 .../gpu/drm/nouveau/nvkm/engine/disp/gb202.c  | 12 +--
 .../gpu/drm/nouveau/nvkm/engine/disp/gv100.c  |  4 +-
 .../gpu/drm/nouveau/nvkm/engine/disp/ior.h    |  2 +
 .../gpu/drm/nouveau/nvkm/engine/disp/tu102.c  |  4 +-
 .../gpu/drm/nouveau/nvkm/engine/disp/uoutp.c  |  6 ++
 14 files changed, 128 insertions(+), 20 deletions(-)

-- 
2.53.0

[PATCH 1/3] drm/nouveau: select HDMI deep-color link depth

[Daniel Campos Ramos]

Nouveau currently initializes the output depth from the EDID basic display
parameters and does not expose a max bpc property on HDMI connectors.  As a
result, HDMI deep-color modes advertised by the VSDB are never selected.

Attach an 8..16 max bpc property.  Select 10, 12 or 16 bpc only when
the sink advertises the corresponding RGB 4:4:4 deep-color mode and the
resulting TMDS character rate fits the existing link limit.  Program the
matching head output-resource depth on NVDisplay.

Share the existing TMDS bandwidth helper with the atomic check so the depth
selection observes both sink and GPU limits.

Signed-off-by: Daniel Campos Ramos <Capitain_Jack@yahoo.com>
---
 drivers/gpu/drm/nouveau/dispnv50/disp.c     | 57 ++++++++++++++++++++-
 drivers/gpu/drm/nouveau/dispnv50/headc37d.c |  6 +++
 drivers/gpu/drm/nouveau/dispnv50/headc57d.c |  6 +++
 drivers/gpu/drm/nouveau/dispnv50/headca7d.c |  6 +++
 drivers/gpu/drm/nouveau/nouveau_connector.c |  9 ++--
 drivers/gpu/drm/nouveau/nouveau_connector.h |  1 +
 6 files changed, 80 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/nouveau/dispnv50/disp.c b/drivers/gpu/drm/nouveau/dispnv50/disp.c
index add19d47..6410b96b 100644
--- a/drivers/gpu/drm/nouveau/dispnv50/disp.c
+++ b/drivers/gpu/drm/nouveau/dispnv50/disp.c
@@ -375,10 +375,12 @@ nv50_outp_atomic_check_view(struct drm_encoder *encoder,
 }
 
 static void
-nv50_outp_atomic_fix_depth(struct drm_encoder *encoder, struct drm_crtc_state *crtc_state)
+nv50_outp_atomic_fix_depth(struct drm_encoder *encoder, struct drm_crtc_state *crtc_state,
+			   struct drm_connector_state *conn_state)
 {
 	struct nv50_head_atom *asyh = nv50_head_atom(crtc_state);
 	struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
+	struct drm_connector *connector = conn_state->connector;
 	struct drm_display_mode *mode = &asyh->state.adjusted_mode;
 	unsigned int max_rate, mode_rate;
 
@@ -398,6 +400,36 @@ nv50_outp_atomic_fix_depth(struct drm_encoder *encoder, struct drm_crtc_state *c
 			asyh->or.bpc -= 2;
 		}
 		break;
+	case DCB_OUTPUT_TMDS:
+		if (!connector->display_info.is_hdmi)
+			break;
+
+		max_rate = nouveau_connector_get_tmds_link_bandwidth(connector);
+		asyh->or.bpc = 8;
+
+		if (conn_state->max_requested_bpc >= 16 &&
+		    connector->display_info.edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_48) {
+			mode_rate = DIV_ROUND_UP(mode->clock * 16, 8);
+			if (mode_rate <= max_rate)
+				asyh->or.bpc = 16;
+		}
+
+		if (asyh->or.bpc == 8 && conn_state->max_requested_bpc >= 12 &&
+		    connector->display_info.edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_36) {
+			mode_rate = DIV_ROUND_UP(mode->clock * 12, 8);
+			if (mode_rate <= max_rate)
+				asyh->or.bpc = 12;
+		}
+
+		if (asyh->or.bpc == 8 && conn_state->max_requested_bpc >= 10 &&
+		    connector->display_info.edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_30) {
+			mode_rate = DIV_ROUND_UP(mode->clock * 10, 8);
+			if (mode_rate <= max_rate)
+				asyh->or.bpc = 10;
+		}
+
+		conn_state->max_bpc = asyh->or.bpc;
+		break;
 	default:
 		break;
 	}
@@ -422,7 +454,7 @@ nv50_outp_atomic_check(struct drm_encoder *encoder,
 		asyh->or.bpc = connector->display_info.bpc;
 
 	/* We might have to reduce the bpc */
-	nv50_outp_atomic_fix_depth(encoder, crtc_state);
+	nv50_outp_atomic_fix_depth(encoder, crtc_state, conn_state);
 
 	return 0;
 }
@@ -1776,6 +1808,27 @@ nv50_sor_atomic_enable(struct drm_encoder *encoder, struct drm_atomic_commit *st
 
 	switch (nv_encoder->dcb->type) {
 	case DCB_OUTPUT_TMDS:
+		switch (asyh->or.bpc) {
+		case 16:
+			depth = NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_48_444;
+			break;
+		case 12:
+			depth = NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_36_444;
+			break;
+		case 10:
+			depth = NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_30_444;
+			break;
+		case 8:
+			depth = NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_24_444;
+			break;
+		case 6:
+			depth = NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_18_444;
+			break;
+		default:
+			depth = NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_DEFAULT;
+			break;
+		}
+
 		if (disp->disp->object.oclass != NV50_DISP &&
 		    nv_connector->base.display_info.is_hdmi)
 			nv50_hdmi_enable(encoder, nv_crtc, nv_connector, state, mode, hda);
diff --git a/drivers/gpu/drm/nouveau/dispnv50/headc37d.c b/drivers/gpu/drm/nouveau/dispnv50/headc37d.c
index 2bcb3790..f42d6642 100644
--- a/drivers/gpu/drm/nouveau/dispnv50/headc37d.c
+++ b/drivers/gpu/drm/nouveau/dispnv50/headc37d.c
@@ -39,6 +39,12 @@ headc37d_or(struct nv50_head *head, struct nv50_head_atom *asyh)
 	 *     improved later for deep colour etc.
 	 */
 	switch (asyh->or.depth) {
+	case 9:
+		depth = 8;
+		break;
+	case 8:
+		depth = 7;
+		break;
 	case 6: depth = 5; break;
 	case 5: depth = 4; break;
 	case 2: depth = 1; break;
diff --git a/drivers/gpu/drm/nouveau/dispnv50/headc57d.c b/drivers/gpu/drm/nouveau/dispnv50/headc57d.c
index 3f8ba495..f1e9f02d 100644
--- a/drivers/gpu/drm/nouveau/dispnv50/headc57d.c
+++ b/drivers/gpu/drm/nouveau/dispnv50/headc57d.c
@@ -52,6 +52,12 @@ headc57d_or(struct nv50_head *head, struct nv50_head_atom *asyh)
 	 *     improved later for deep colour etc.
 	 */
 	switch (asyh->or.depth) {
+	case 9:
+		depth = 8;
+		break;
+	case 8:
+		depth = 7;
+		break;
 	case 6: depth = 5; break;
 	case 5: depth = 4; break;
 	case 2: depth = 1; break;
diff --git a/drivers/gpu/drm/nouveau/dispnv50/headca7d.c b/drivers/gpu/drm/nouveau/dispnv50/headca7d.c
index 678cbc78..437633ff 100644
--- a/drivers/gpu/drm/nouveau/dispnv50/headca7d.c
+++ b/drivers/gpu/drm/nouveau/dispnv50/headca7d.c
@@ -35,6 +35,12 @@ headca7d_or(struct nv50_head *head, struct nv50_head_atom *asyh)
 	int ret;
 
 	switch (asyh->or.depth) {
+	case 9:
+		depth = NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_48_444;
+		break;
+	case 8:
+		depth = NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_36_444;
+		break;
 	case 6:
 		depth = NVCA7D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_30_444;
 		break;
diff --git a/drivers/gpu/drm/nouveau/nouveau_connector.c b/drivers/gpu/drm/nouveau/nouveau_connector.c
index cc3caf8d..b452e73f 100644
--- a/drivers/gpu/drm/nouveau/nouveau_connector.c
+++ b/drivers/gpu/drm/nouveau/nouveau_connector.c
@@ -298,6 +298,9 @@ nouveau_conn_attach_properties(struct drm_connector *connector)
 		drm_object_attach_property(&connector->base, dev->mode_config.
 					   dvi_i_subconnector_property, 0);
 
+	if (connector->connector_type == DRM_MODE_CONNECTOR_HDMIA)
+		drm_connector_attach_max_bpc_property(connector, 8, 16);
+
 	/* Add overscan compensation options to digital outputs. */
 	if (disp->underscan_property &&
 	    (connector->connector_type == DRM_MODE_CONNECTOR_DVID ||
@@ -1101,8 +1104,8 @@ nouveau_connector_get_modes(struct drm_connector *connector)
 	return ret;
 }
 
-static unsigned
-get_tmds_link_bandwidth(struct drm_connector *connector)
+unsigned int
+nouveau_connector_get_tmds_link_bandwidth(struct drm_connector *connector)
 {
 	struct nouveau_connector *nv_connector = nouveau_connector(connector);
 	struct nouveau_encoder *nv_encoder = nv_connector->detected_encoder;
@@ -1168,7 +1171,7 @@ nouveau_connector_mode_valid(struct drm_connector *connector,
 		max_clock = 400000;
 		break;
 	case DCB_OUTPUT_TMDS:
-		max_clock = get_tmds_link_bandwidth(connector);
+		max_clock = nouveau_connector_get_tmds_link_bandwidth(connector);
 		break;
 	case DCB_OUTPUT_ANALOG:
 		max_clock = nv_encoder->dcb->crtconf.maxfreq;
diff --git a/drivers/gpu/drm/nouveau/nouveau_connector.h b/drivers/gpu/drm/nouveau/nouveau_connector.h
index eb292d2b..6623b5e1 100644
--- a/drivers/gpu/drm/nouveau/nouveau_connector.h
+++ b/drivers/gpu/drm/nouveau/nouveau_connector.h
@@ -216,6 +216,7 @@ extern int nouveau_duallink;
 extern int nouveau_hdmimhz;
 
 void nouveau_conn_attach_properties(struct drm_connector *);
+unsigned int nouveau_connector_get_tmds_link_bandwidth(struct drm_connector *connector);
 void nouveau_conn_reset(struct drm_connector *);
 struct drm_connector_state *
 nouveau_conn_atomic_duplicate_state(struct drm_connector *);
-- 
2.53.0

Re: [PATCH 1/3] drm/nouveau: select HDMI deep-color link depth

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [High] drm/nouveau: incorrect TMDS character rate calculation for HDMI deep color breaks SCDC scrambling
- [Medium] drm/nouveau: HDMI deep color permanently disabled on non-HDMI connectors
--

commit e40b56c72a75d42642f11bb0711a44b65e65a10b
Author: Daniel Campos Ramos <Capitain_Jack@yahoo.com>

drm/nouveau: select HDMI deep-color link depth

The patch enables HDMI deep-color modes by attaching an 8 to 16 max bpc
property to HDMI connectors. It then selects the appropriate 10, 12, or
16 bpc output depth if the sink advertises support and the resulting TMDS
character rate fits within the existing link limits.

> diff --git a/drivers/gpu/drm/nouveau/nouveau_connector.c b/drivers/gpu/drm/nouveau/nouveau_connector.c
> index b0b0ad9a0c248..240a7b96cc519 100644
> --- a/drivers/gpu/drm/nouveau/nouveau_connector.c
> +++ b/drivers/gpu/drm/nouveau/nouveau_connector.c
[ ... ]
> @@ -298,6 +298,9 @@ nouveau_conn_attach_properties(struct drm_connector *connector)
>  		drm_object_attach_property(&connector->base, dev->mode_config.
>  					   dvi_i_subconnector_property, 0);
>  
> +	if (connector->connector_type == DRM_MODE_CONNECTOR_HDMIA)
> +		drm_connector_attach_max_bpc_property(connector, 8, 16);

[Severity: Medium]
Does this prevent HDMI deep color from being enabled on DVI or DP connectors
that are driving an HDMI sink via a passive adapter?

If the max bpc property is only attached for HDMIA connectors, then for other
connector types driving an HDMI sink, the max_requested_bpc state remains 0.
Later in nv50_outp_atomic_fix_depth(), the deep color promotion checks
(like conn_state->max_requested_bpc >= 12) will fail, locking these
configurations to 8 bpc despite both sink and GPU supporting higher depths.

> diff --git a/drivers/gpu/drm/nouveau/dispnv50/disp.c b/drivers/gpu/drm/nouveau/dispnv50/disp.c
> index 2c66e480b5116..9e8bfd6b78ec0 100644
> --- a/drivers/gpu/drm/nouveau/dispnv50/disp.c
> +++ b/drivers/gpu/drm/nouveau/dispnv50/disp.c
[ ... ]
> @@ -1776,6 +1808,27 @@ nv50_sor_atomic_enable(struct drm_encoder *encoder, struct drm_atomic_commit *st
>  
>  	switch (nv_encoder->dcb->type) {
>  	case DCB_OUTPUT_TMDS:
> +		switch (asyh->or.bpc) {
> +		case 16:
> +			depth = NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_48_444;
> +			break;
> +		case 12:
> +			depth = NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_36_444;
> +			break;
> +		case 10:
> +			depth = NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_30_444;
> +			break;
> +		case 8:
> +			depth = NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_24_444;
> +			break;
> +		case 6:
> +			depth = NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_18_444;
> +			break;
> +		default:
> +			depth = NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_DEFAULT;
> +			break;
> +		}
> +
>  		if (disp->disp->object.oclass != NV50_DISP &&
>  		    nv_connector->base.display_info.is_hdmi)
>  			nv50_hdmi_enable(encoder, nv_crtc, nv_connector, state, mode, hda);

[Severity: High]
Will enabling deep color here cause SCDC scrambling to fail for high-bandwidth
modes?

The HDMI 2.0 specification requires TMDS scrambling and a 1/40 bit clock
ratio when the TMDS character rate exceeds 340 MHz. However, when calling
nv50_hdmi_enable(), the existing code calculates the high TMDS clock
ratio using the pixel clock rather than the new TMDS character rate:

drivers/gpu/drm/nouveau/dispnv50/disp.c:nv50_hdmi_enable() {
    ...
    const bool high_tmds_clock_ratio = mode->clock > 340000;
    ...
    ret = nvif_outp_hdmi(&nv_encoder->outp, nv_crtc->index, true,
                         max_ac_packet, rekey, mode->clock, ...);
    ...
}

For high-bandwidth modes like 4K 30Hz at 12 bpc, the pixel clock is 297 MHz
but the TMDS rate is 445.5 MHz. In this scenario, high_tmds_clock_ratio
evaluates to false and the unscaled pixel clock is passed to the hardware
sequencer.

Could this cause the driver to fail to enable SCDC scrambling and the required
clock ratio, resulting in a display link training failure and a black screen?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260922192132.114546-1-Capitain_Jack@yahoo.com?part=1

Re: [PATCH 1/3] drm/nouveau: select HDMI deep-color link depth

[Daniel Campos Ramos]

Thank you, this one was right, and it helped.
The SCDC gate half was already fixed in v2, but the second half was not: v2 still passes the pixel clock as khz to nvif_outp_hdmi().
On GSP boards that value is ignored, which is why our GA106 bench never showed it, and why the v2 cover letter's claim that the pixel clock is correct there only holds for GSP.
Without GSP, gm200_sor_hdmi_scdc() derives tmds.high_speed from it, and that sets the SOR scrambler, the 1/40 clock ratio and the clock divider.
So when Deep Color pushes the character rate past 340 MHz while the pixel clock stays under it, v2 would tell the sink to scramble at 1/40 while the SOR stays at 1/10.
The next revision passes the TMDS character rate there; it is ready, and will go out once the maintainers have had a chance to look at v2.
The max bpc attach on DVI connectors is handled in the colour format series, where patch 6 closes this report.

AI partners were leveraged in the production of this work.

Daniel

[PATCH 2/3] drm/nouveau: pass HDMI GCP deep-color state through NVIF

[Daniel Campos Ramos]

The HDMI GCP carries color depth and pixel packing phase.  These fields
are required for 30-, 36- and 48-bpp RGB links.  Nouveau has no way to
pass them from the atomic state to the display engine.

Build CD and PP using NVIDIA NVKMS's 36-bpp rule and the HDMI 48-bpp
encoding.
Extend the internal HDMI NVIF method and cache the values in the armed TMDS
state.  The following change uses that state in the generation-specific GCP
writers.

Signed-off-by: Daniel Campos Ramos <Capitain_Jack@yahoo.com>
---
 drivers/gpu/drm/nouveau/dispnv50/disp.c       | 23 +++++++++++++++----
 drivers/gpu/drm/nouveau/include/nvif/if0012.h |  3 +++
 drivers/gpu/drm/nouveau/include/nvif/outp.h   |  2 +-
 drivers/gpu/drm/nouveau/nvif/outp.c           |  7 ++++--
 .../gpu/drm/nouveau/nvkm/engine/disp/ior.h    |  2 ++
 .../gpu/drm/nouveau/nvkm/engine/disp/uoutp.c  |  6 +++++
 6 files changed, 36 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/nouveau/dispnv50/disp.c b/drivers/gpu/drm/nouveau/dispnv50/disp.c
index 6410b96b..6d8fee1b 100644
--- a/drivers/gpu/drm/nouveau/dispnv50/disp.c
+++ b/drivers/gpu/drm/nouveau/dispnv50/disp.c
@@ -809,13 +809,14 @@ nv50_audio_enable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc,
 static void
 nv50_hdmi_enable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc,
 		 struct nouveau_connector *nv_connector, struct drm_atomic_commit *state,
-		 struct drm_display_mode *mode, bool hda)
+		 struct drm_display_mode *mode, bool hda, u8 bpc)
 {
 	struct nouveau_drm *drm = nouveau_drm(encoder->dev);
 	struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 	struct drm_hdmi_info *hdmi = &nv_connector->base.display_info.hdmi;
 	union hdmi_infoframe infoframe = { 0 };
 	const u8 rekey = 56; /* binary driver, and tegra, constant */
+	u8 gcp_cd = 0, gcp_pp = 0;
 	u32 max_ac_packet;
 	DEFINE_RAW_FLEX(struct nvif_outp_infoframe_v0, args, data, 17);
 	const u8 data_len = __member_size(args->data);
@@ -826,6 +827,19 @@ nv50_hdmi_enable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc,
 	max_ac_packet -= 18; /* constant from tegra */
 	max_ac_packet /= 32;
 
+	/* Match NVIDIA's 36-bpp GCP construction and extend the same HDMI
+	 * color-depth encoding to 48-bpp.  48-bpp groups contain one pixel,
+	 * so their last packing phase is phase 4 (zero).
+	 */
+	if (bpc == 16) {
+		gcp_cd = 7;
+	} else if (bpc == 12) {
+		const u32 hbp = mode->crtc_hblank_end - mode->crtc_hsync_end;
+
+		gcp_cd = 6;
+		gcp_pp = ((mode->crtc_hdisplay + hbp) & 1) ? 1 : 2;
+	}
+
 	if (nv_encoder->i2c && hdmi->scdc.scrambling.supported) {
 		const bool high_tmds_clock_ratio = mode->clock > 340000;
 		u8 scdc;
@@ -850,7 +864,7 @@ nv50_hdmi_enable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc,
 
 	ret = nvif_outp_hdmi(&nv_encoder->outp, nv_crtc->index, true, max_ac_packet, rekey,
 			     mode->clock, hdmi->scdc.supported, hdmi->scdc.scrambling.supported,
-			     hdmi->scdc.scrambling.low_rates);
+			     hdmi->scdc.scrambling.low_rates, gcp_cd, gcp_pp);
 	if (ret)
 		return;
 
@@ -1615,7 +1629,7 @@ nv50_sor_atomic_disable(struct drm_encoder *encoder, struct drm_atomic_commit *s
 
 	if (nv_encoder->dcb->type == DCB_OUTPUT_TMDS && nv_encoder->hdmi.enabled) {
 		nvif_outp_hdmi(&nv_encoder->outp, head->base.index,
-			       false, 0, 0, 0, false, false, false);
+			       false, 0, 0, 0, false, false, false, 0, 0);
 		nv_encoder->hdmi.enabled = false;
 	}
 
@@ -1831,7 +1845,8 @@ nv50_sor_atomic_enable(struct drm_encoder *encoder, struct drm_atomic_commit *st
 
 		if (disp->disp->object.oclass != NV50_DISP &&
 		    nv_connector->base.display_info.is_hdmi)
-			nv50_hdmi_enable(encoder, nv_crtc, nv_connector, state, mode, hda);
+			nv50_hdmi_enable(encoder, nv_crtc, nv_connector, state, mode, hda,
+					 asyh->or.bpc);
 
 		if (nv_encoder->outp.or.link & 1) {
 			proto = NV507D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_A;
diff --git a/drivers/gpu/drm/nouveau/include/nvif/if0012.h b/drivers/gpu/drm/nouveau/include/nvif/if0012.h
index bde9bfae..ebfa60f9 100644
--- a/drivers/gpu/drm/nouveau/include/nvif/if0012.h
+++ b/drivers/gpu/drm/nouveau/include/nvif/if0012.h
@@ -176,6 +176,9 @@ union nvif_outp_hdmi_args {
 		__u8 scdc_scrambling;
 		__u8 scdc_low_rates;
 		__u32 khz;
+		__u8 gcp_cd;
+		__u8 gcp_pp;
+		__u8 pad14[2];
 	} v0;
 };
 
diff --git a/drivers/gpu/drm/nouveau/include/nvif/outp.h b/drivers/gpu/drm/nouveau/include/nvif/outp.h
index bc122a5b..3d5ed53f 100644
--- a/drivers/gpu/drm/nouveau/include/nvif/outp.h
+++ b/drivers/gpu/drm/nouveau/include/nvif/outp.h
@@ -90,7 +90,7 @@ int nvif_outp_bl_set(struct nvif_outp *, int level);
 int nvif_outp_lvds(struct nvif_outp *, bool dual, bool bpc8);
 
 int nvif_outp_hdmi(struct nvif_outp *, int head, bool enable, u8 max_ac_packet, u8 rekey, u32 khz,
-		   bool scdc, bool scdc_scrambling, bool scdc_low_rates);
+		   bool scdc, bool scdc_scrambling, bool scdc_low_rates, u8 gcp_cd, u8 gcp_pp);
 
 int nvif_outp_infoframe(struct nvif_outp *, u8 type, struct nvif_outp_infoframe_v0 *, u32 size);
 int nvif_outp_hda_eld(struct nvif_outp *, int head, void *data, u32 size);
diff --git a/drivers/gpu/drm/nouveau/nvif/outp.c b/drivers/gpu/drm/nouveau/nvif/outp.c
index 8cf4775a..44562645 100644
--- a/drivers/gpu/drm/nouveau/nvif/outp.c
+++ b/drivers/gpu/drm/nouveau/nvif/outp.c
@@ -224,9 +224,10 @@ nvif_outp_infoframe(struct nvif_outp *outp, u8 type, struct nvif_outp_infoframe_
 
 int
 nvif_outp_hdmi(struct nvif_outp *outp, int head, bool enable, u8 max_ac_packet, u8 rekey,
-	       u32 khz, bool scdc, bool scdc_scrambling, bool scdc_low_rates)
+	       u32 khz, bool scdc, bool scdc_scrambling, bool scdc_low_rates,
+	       u8 gcp_cd, u8 gcp_pp)
 {
-	struct nvif_outp_hdmi_v0 args;
+	struct nvif_outp_hdmi_v0 args = {};
 	int ret;
 
 	args.version = 0;
@@ -238,6 +239,8 @@ nvif_outp_hdmi(struct nvif_outp *outp, int head, bool enable, u8 max_ac_packet,
 	args.scdc = scdc;
 	args.scdc_scrambling = scdc_scrambling;
 	args.scdc_low_rates = scdc_low_rates;
+	args.gcp_cd = gcp_cd;
+	args.gcp_pp = gcp_pp;
 
 	ret = nvif_mthd(&outp->object, NVIF_OUTP_V0_HDMI, &args, sizeof(args));
 	NVIF_ERRON(ret, &outp->object,
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/ior.h b/drivers/gpu/drm/nouveau/nvkm/engine/disp/ior.h
index 5d682a77..fcf624cf 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/ior.h
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/ior.h
@@ -46,6 +46,8 @@ struct nvkm_ior {
 	/* Armed TMDS state. */
 	struct {
 		bool high_speed;
+		u8 gcp_cd;
+		u8 gcp_pp;
 	} tmds;
 };
 
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c
index 377d0e0c..dff75d72 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.c
@@ -254,16 +254,22 @@ nvkm_uoutp_mthd_hdmi(struct nvkm_outp *outp, void *argv, u32 argc)
 	if (!ior->func->hdmi ||
 	    args->v0.max_ac_packet > 0x1f ||
 	    args->v0.rekey > 0x7f ||
+	    args->v0.gcp_cd > 0x0f ||
+	    args->v0.gcp_pp > 0x0f ||
 	    (args->v0.scdc && !ior->func->hdmi->scdc))
 		return -EINVAL;
 
 	if (!args->v0.enable) {
+		ior->tmds.gcp_cd = 0;
+		ior->tmds.gcp_pp = 0;
 		ior->func->hdmi->infoframe_avi(ior, args->v0.head, NULL, 0);
 		ior->func->hdmi->infoframe_vsi(ior, args->v0.head, NULL, 0);
 		ior->func->hdmi->ctrl(ior, args->v0.head, false, 0, 0);
 		return 0;
 	}
 
+	ior->tmds.gcp_cd = args->v0.gcp_cd;
+	ior->tmds.gcp_pp = args->v0.gcp_pp;
 	ior->func->hdmi->ctrl(ior, args->v0.head, args->v0.enable,
 			      args->v0.max_ac_packet, args->v0.rekey);
 	if (ior->func->hdmi->scdc)
-- 
2.53.0

Re: [PATCH 2/3] drm/nouveau: pass HDMI GCP deep-color state through NVIF

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] drm/nouveau: missing 30-bpp GCP configuration in nv50_hdmi_enable()
--

commit a5a312ee20dba0d1f27e5316dc3d7c1c29070995
Author: Daniel Campos Ramos <Capitain_Jack@yahoo.com>
Subject: drm/nouveau: pass HDMI GCP deep-color state through NVIF

This commit adds HDMI GCP color depth and pixel packing phase configuration
to Nouveau to support 30, 36, and 48-bpp RGB links. It extends the NVIF
HDMI method to pass and cache these values for generation-specific writers.

> diff --git a/drivers/gpu/drm/nouveau/dispnv50/disp.c b/drivers/gpu/drm/nouveau/dispnv50/disp.c
> --- a/drivers/gpu/drm/nouveau/dispnv50/disp.c
> +++ b/drivers/gpu/drm/nouveau/dispnv50/disp.c
[ ... ]
> @@ -826,6 +827,19 @@ nv50_hdmi_enable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc,
>  	max_ac_packet -= 18; /* constant from tegra */
>  	max_ac_packet /= 32;
>  
> +	/* Match NVIDIA's 36-bpp GCP construction and extend the same HDMI
> +	 * color-depth encoding to 48-bpp.  48-bpp groups contain one pixel,
> +	 * so their last packing phase is phase 4 (zero).
> +	 */
> +	if (bpc == 16) {
> +		gcp_cd = 7;
> +	} else if (bpc == 12) {
> +		const u32 hbp = mode->crtc_hblank_end - mode->crtc_hsync_end;
> +
> +		gcp_cd = 6;
> +		gcp_pp = ((mode->crtc_hdisplay + hbp) & 1) ? 1 : 2;
> +	}
> +

[Severity: High]
Does this code omit the configuration for 30-bpp (10 bpc) HDMI streams?

If a monitor supports 30-bit deep color (DRM_EDID_HDMI_DC_30), asyh->or.bpc
is set to 10 in nv50_sor_atomic_enable() and passed here as bpc = 10. 
When bpc == 10, gcp_cd and gcp_pp are left as 0, which means "not indicated" 
and assumes a 24-bpp standard color depth.

Could this cause a corrupted or unreadable display output on 10-bit color 
monitors by violating the HDMI specification for Deep Color?

>  	if (nv_encoder->i2c && hdmi->scdc.scrambling.supported) {
>  		const bool high_tmds_clock_ratio = mode->clock > 340000;
>  		u8 scdc;

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260922192132.114546-1-Capitain_Jack@yahoo.com?part=2

[PATCH 3/3] drm/nouveau: program HDMI deep-color GCP fields

[Daniel Campos Ramos]

The GV100-class GCP writers always program a depth-less packet.  On GSP
systems the HDMI audio setup runs after the display commit and writes that
packet again, replacing any earlier deep-color declaration.

Program cached CD and PP in the direct and GSP GCP paths.  Update only
SB0..SB2 so generation-specific bits sharing the register remain intact,
including GB20x SB1_CTRL.

On a GA106 driving a Sony KDL-46HX855, the depth-less packet produced an
incompatible-signal OSD at 1920x1080p60.  Restoring CD=6 and PP=2 after
audio setup made the same sink accept the image and report 12-bit input.

Signed-off-by: Daniel Campos Ramos <Capitain_Jack@yahoo.com>
---
 drivers/gpu/drm/nouveau/nvkm/engine/disp/gb202.c | 12 ++++++------
 drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c |  4 +++-
 drivers/gpu/drm/nouveau/nvkm/engine/disp/tu102.c |  4 +++-
 3 files changed, 12 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/gb202.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/gb202.c
index d0360610..517a51ca 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/gb202.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/gb202.c
@@ -66,20 +66,20 @@ gb202_sor_hdmi_infoframe_vsi(struct nvkm_ior *ior, int head, void *data, u32 siz
 }
 
 /* General Control Packet AVMute bracket. The GCP unit moved to slot 1 on
- * NVD5.0. Only SB0 (the AVMute bit) is ours to write so we must not do a
- * full write here: SB1 carries the deep-color CD/PP fields, and SB1_CTRL
- * (bit 24, new with clc871.h) controls where their generation happens (HW
- * or driver) on these chips, with the default being HW.
+ * NVD5.0. SB0 carries AVMute, SB1 carries the deep-color CD/PP fields, and
+ * SB1_CTRL (bit 24, new with clc871.h) controls where their generation
+ * happens (HW or driver). Preserve SB1_CTRL while updating SB0..SB2.
  */
 static void
 gb202_sor_hdmi_gcp(struct nvkm_ior *sor, int head, bool enable)
 {
 	struct nvkm_device *device = sor->disp->engine.subdev.device;
 	const u32 hdmi = head * 0x400;
+	const u32 gcp = (!enable ? 0x00000001 : 0x00000010) |
+			 sor->tmds.gcp_cd << 8 | sor->tmds.gcp_pp << 12;
 
 	nvkm_mask(device, 0x6f0040 + hdmi, 0x00000001, 0x00000000);
-	nvkm_mask(device, 0x6f004c + hdmi, 0x000000ff, !enable ? 0x00000001 :
-								 0x00000010);
+	nvkm_mask(device, 0x6f004c + hdmi, 0x00ffffff, gcp);
 	nvkm_mask(device, 0x6f0040 + hdmi, 0x00000001, 0x00000001);
 }
 
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c
index 06082661..d1e4b38b 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.c
@@ -149,6 +149,8 @@ gv100_sor_hdmi_ctrl(struct nvkm_ior *ior, int head, bool enable, u8 max_ac_packe
 	const u32 ctrl = 0x40000000 * enable |
 			 max_ac_packet << 16 |
 			 rekey;
+	const u32 gcp = 0x00000010 | ior->tmds.gcp_cd << 8 |
+					   ior->tmds.gcp_pp << 12;
 	const u32 hoff = head * 0x800;
 	const u32 hdmi = head * 0x400;
 
@@ -162,7 +164,7 @@ gv100_sor_hdmi_ctrl(struct nvkm_ior *ior, int head, bool enable, u8 max_ac_packe
 
 	/* General Control (GCP). */
 	nvkm_mask(device, 0x6f00c0 + hdmi, 0x00000001, 0x00000000);
-	nvkm_wr32(device, 0x6f00cc + hdmi, 0x00000010);
+	nvkm_mask(device, 0x6f00cc + hdmi, 0x00ffffff, gcp);
 	nvkm_mask(device, 0x6f00c0 + hdmi, 0x00000001, 0x00000001);
 
 	/* Audio Clock Regeneration (ACR). */
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/tu102.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/tu102.c
index f6c16307..49c84927 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/tu102.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/tu102.c
@@ -39,9 +39,11 @@ tu102_sor_hdmi_gcp(struct nvkm_ior *sor, int head, bool enable)
 {
 	struct nvkm_device *device = sor->disp->engine.subdev.device;
 	const u32 hdmi = head * 0x400;
+	const u32 gcp = (!enable ? 0x00000001 : 0x00000010) |
+			 sor->tmds.gcp_cd << 8 | sor->tmds.gcp_pp << 12;
 
 	nvkm_mask(device, 0x6f00c0 + hdmi, 0x00000001, 0x00000000);
-	nvkm_wr32(device, 0x6f00cc + hdmi, !enable ? 0x00000001 : 0x00000010);
+	nvkm_mask(device, 0x6f00cc + hdmi, 0x00ffffff, gcp);
 	nvkm_mask(device, 0x6f00c0 + hdmi, 0x00000001, 0x00000001);
 }
 
-- 
2.53.0

Re: [PATCH 0/3] drm/nouveau: HDMI Deep Color link depth (30/36/48 bpp)

[Daniel Campos Ramos]

None of these compliance gaps were introduced by the series; they were already there, and the series exists to patch exactly that.
Before it, nouveau sent 8-bpc output with a depth-less GCP to sinks declaring Deep Color, and full-range RGB on CE formats without signalling it.
The SCDC gate compared the pixel clock because, without Deep Color, the pixel clock was the character rate; the series made that no longer true, so v2 gates on the character rate.
The missing 30-bpp GCP arm was v1 not yet covering the whole gap: it followed NVIDIA's own reference rule, which only declares 36 bpp. v2 encodes 30, 36 and 48 bpp per HDMI 1.4b 6.5.3, and the 10-bit path is now bench-tested on the same sink.
The HDMI-A-only attach is closed in the follow-on colour format series, which also brings limited-range RGB and YCbCr.
Our own bench logs found one more, frame packing rated at the per-eye clock, and v2 fixes that too.
The current implementation is the one breaking the HDMI specs; we're attempting to medicine that disease.

v2: https://lore.kernel.org/dri-devel/20260922215317.611388-1-Capitain_Jack@yahoo.com/
Colour format series: https://lore.kernel.org/dri-devel/20260922215336.612239-1-Capitain_Jack@yahoo.com/

AI partners were leveraged in the production of this work.

Daniel

Re: [PATCH 0/3] drm/nouveau: HDMI Deep Color link depth (30/36/48 bpp)

[lyude]

On Tue, 2026-09-22 at 16:21 -0300, Daniel Campos Ramos wrote:
> 
> 
> AI partners were leveraged in the production of this work.

Can you please clarify how LLM tooling was used in the production of
this work? If you actually generated code with it that is part of this
submission, then you need to append a Assisted-by: tag to each commit
indicating that it was generated by an LLM. If it was only used for
research or analysis and the code is written by hand (also, this is
_vastly_ preferable to getting LLM submissions. consider trying it or
even better - try not using them at all.) then leaving the tags out is
fine.

> 
> Daniel Campos Ramos (3):
>   drm/nouveau: select HDMI deep-color link depth
>   drm/nouveau: pass HDMI GCP deep-color state through NVIF
>   drm/nouveau: program HDMI deep-color GCP fields
> 
>  drivers/gpu/drm/nouveau/dispnv50/disp.c       | 80
> +++++++++++++++++--
>  drivers/gpu/drm/nouveau/dispnv50/headc37d.c   |  6 ++
>  drivers/gpu/drm/nouveau/dispnv50/headc57d.c   |  6 ++
>  drivers/gpu/drm/nouveau/dispnv50/headca7d.c   |  6 ++
>  drivers/gpu/drm/nouveau/include/nvif/if0012.h |  3 +
>  drivers/gpu/drm/nouveau/include/nvif/outp.h   |  2 +-
>  drivers/gpu/drm/nouveau/nouveau_connector.c   |  9 ++-
>  drivers/gpu/drm/nouveau/nouveau_connector.h   |  1 +
>  drivers/gpu/drm/nouveau/nvif/outp.c           |  7 +-
>  .../gpu/drm/nouveau/nvkm/engine/disp/gb202.c  | 12 +--
>  .../gpu/drm/nouveau/nvkm/engine/disp/gv100.c  |  4 +-
>  .../gpu/drm/nouveau/nvkm/engine/disp/ior.h    |  2 +
>  .../gpu/drm/nouveau/nvkm/engine/disp/tu102.c  |  4 +-
>  .../gpu/drm/nouveau/nvkm/engine/disp/uoutp.c  |  6 ++
>  14 files changed, 128 insertions(+), 20 deletions(-)

Re: [PATCH 0/3] drm/nouveau: HDMI Deep Color link depth (30/36/48 bpp)

[Daniel Campos Ramos]

On Wed, 2026-09-23, lyude@redhat.com wrote:
> Can you please clarify how LLM tooling was used in the production of
> this work? If you actually generated code with it that is part of this
> submission, then you need to append a Assisted-by: tag to each commit
> indicating that it was generated by an LLM.

Yes, the code was generated with AI partners under my direction, so every patch needs the tag.
I answered in detail on the colour format thread: https://lore.kernel.org/all/20260923162348.1037898-1-Capitain_Jack@yahoo.com/
The next version of this series (v2 is already on the list) will carry Assisted-by: on each patch.

Daniel