[PATCH v1 00/27] drm/panthor: Add Mali v15 virtualization support

[PATCH v1 00/27] drm/panthor: Add Mali v15 virtualization support

[Karunika Choo]

This series adds HW-assisted para-virtualization support for Mali v15
GPUs. v15 GPUs provide 16 register sets for job submission known as
access windows (AWs). The GPU hardware itself is then time-sliced across
each requesting access window.

Patches 1-6 make panthor less dependent on fixed register layouts by
caching decoded GPU_ID fields and moving register offsets into the HW
description.

Patches 7-9 update dt-bindings and add basic support for v15 GPUs.

Patches 10-11 introduce the GPU-wide configuration driver.

Patches 12-21 implement the time-slicing driver with a simple
interrupt-driven round robin scheduler.

Patches 22-27 update panthor to be time-slice aware as well as
being resilient against the GPU being yielded at any time.

v1:
- Rebased on drm-misc-next.
- Added device-tree bindings for the GPU and virtualization components.
- Improved GPU identification and register handling.
- Updated AM messaging to protocol v2.
- Improved GPU scheduling and recovery from timeouts and failed
  commands.
- Added access-window assignments through device tree and earlier GPU
  release when another window is waiting.
- Improved power management, driver setup and cleanup.
- Fixed races involving GPU resets, loss of access and late grants.
- Kept frequency reporting available without devfreq and documented
  scheduler timeout settings.
- Link to RFC: https://lore.kernel.org/all/20260528150546.3168527-1-karunika.choo@arm.com/

Kind regards,
Karunika Choo

Karunika Choo (27):
  drm/panthor: Ignore -EOPNOTSUPP for shader-present nvmem lookup
  drm/panthor: Move register access helpers out of panthor_device.h
  drm/panthor: Parse and store GPU_ID fields
  drm/panthor: Add 64-bit GPU_ID decoding for v15 GPUs
  drm/panthor: Move register base offsets to the HW description
  drm/panthor: Derive MMU AS register addresses from base and stride
  dt-bindings: gpu: mali-valhall-csf: Add Mali Gen5 AM compatible
  drm/panthor: Add Mali v15 hardware support
  drm/panthor: Skip devfreq when no OPP table is present
  dt-bindings: gpu: panthor: Document panthor-system bindings
  drm/panthor: Add AM_SYSTEM platform driver
  dt-bindings: gpu: panthor: Document panthor-arbitration bindings
  drm/panthor: Add AM_PARTITION_CONTROL support
  drm/panthor: Add AM message helpers
  drm/panthor: Add AM_RESOURCE_GROUP support
  drm/panthor: Add arbitration scheduler
  drm/panthor: Route arbitration events
  dt-bindings: gpu: panthor: Document AW assignment DT property
  drm/panthor: Add AW assignment tracking
  drm/panthor: Handle partition control INVALID_COMMAND interrupt
  drm/panthor: Request AW to yield GPU access on idle
  drm/panthor: Add access-window support
  drm/panthor: Synchronize HW component PM transitions
  drm/panthor: Route HW component PM through access windows
  drm/panthor: Tolerate access-window loss during HW waits
  drm/panthor: Prevent missed post-yield cleanup due to reset
  drm/panthor: Release GPU access immediately for out-of-band grants

 .../testing/sysfs-driver-panthor-arbitration  |  18 +
 .../gpu/arm,mali-gen5-am-arbitration.yaml     | 135 ++++
 .../bindings/gpu/arm,mali-gen5-am-system.yaml |  76 ++
 .../bindings/gpu/arm,mali-valhall-csf.yaml    |  26 +-
 MAINTAINERS                                   |   2 +
 drivers/gpu/drm/panthor/Kconfig               |  20 +
 drivers/gpu/drm/panthor/Makefile              |   3 +
 drivers/gpu/drm/panthor/arbitration/Makefile  |  15 +
 .../panthor/arbitration/panthor_arbitration.h |  81 ++
 .../arbitration/panthor_arbitration_drv.c     | 451 +++++++++++
 .../arbitration/panthor_arbitration_sched.c   | 755 ++++++++++++++++++
 .../arbitration/panthor_arbitration_sched.h   |  46 ++
 .../arbitration/panthor_partition_control.c   | 428 ++++++++++
 .../arbitration/panthor_partition_control.h   |  29 +
 .../arbitration/panthor_resource_group.c      | 323 ++++++++
 .../arbitration/panthor_resource_group.h      |  22 +
 drivers/gpu/drm/panthor/panthor_am_msg.h      | 159 ++++
 drivers/gpu/drm/panthor/panthor_aw.c          | 628 +++++++++++++++
 drivers/gpu/drm/panthor/panthor_aw.h          |  53 ++
 drivers/gpu/drm/panthor/panthor_devfreq.c     |  31 +-
 drivers/gpu/drm/panthor/panthor_device.c      |  82 +-
 drivers/gpu/drm/panthor/panthor_device.h      | 131 ++-
 drivers/gpu/drm/panthor/panthor_device_io.h   |  83 ++
 drivers/gpu/drm/panthor/panthor_drv.c         |   1 +
 drivers/gpu/drm/panthor/panthor_fw.c          |  12 +-
 drivers/gpu/drm/panthor/panthor_fw_regs.h     |   2 -
 drivers/gpu/drm/panthor/panthor_gpu.c         |  13 +-
 .../drm/panthor/panthor_gpu_discover_regs.h   |  44 +
 drivers/gpu/drm/panthor/panthor_gpu_regs.h    |   3 +-
 drivers/gpu/drm/panthor/panthor_heap.c        |   3 +-
 drivers/gpu/drm/panthor/panthor_hw.c          | 193 ++++-
 drivers/gpu/drm/panthor/panthor_hw.h          |  56 +-
 drivers/gpu/drm/panthor/panthor_mmu.c         |  45 +-
 drivers/gpu/drm/panthor/panthor_mmu_regs.h    |  23 +-
 drivers/gpu/drm/panthor/panthor_pwr.c         |  29 +-
 drivers/gpu/drm/panthor/panthor_pwr_regs.h    |   2 -
 drivers/gpu/drm/panthor/panthor_sched.c       |   5 +
 drivers/gpu/drm/panthor/system/Makefile       |  13 +
 .../drm/panthor/system/panthor_system_drv.c   | 304 +++++++
 include/uapi/drm/panthor_drm.h                |  23 +-
 40 files changed, 4193 insertions(+), 175 deletions(-)
 create mode 100644 Documentation/ABI/testing/sysfs-driver-panthor-arbitration
 create mode 100644 Documentation/devicetree/bindings/gpu/arm,mali-gen5-am-arbitration.yaml
 create mode 100644 Documentation/devicetree/bindings/gpu/arm,mali-gen5-am-system.yaml
 create mode 100644 drivers/gpu/drm/panthor/arbitration/Makefile
 create mode 100644 drivers/gpu/drm/panthor/arbitration/panthor_arbitration.h
 create mode 100644 drivers/gpu/drm/panthor/arbitration/panthor_arbitration_drv.c
 create mode 100644 drivers/gpu/drm/panthor/arbitration/panthor_arbitration_sched.c
 create mode 100644 drivers/gpu/drm/panthor/arbitration/panthor_arbitration_sched.h
 create mode 100644 drivers/gpu/drm/panthor/arbitration/panthor_partition_control.c
 create mode 100644 drivers/gpu/drm/panthor/arbitration/panthor_partition_control.h
 create mode 100644 drivers/gpu/drm/panthor/arbitration/panthor_resource_group.c
 create mode 100644 drivers/gpu/drm/panthor/arbitration/panthor_resource_group.h
 create mode 100644 drivers/gpu/drm/panthor/panthor_am_msg.h
 create mode 100644 drivers/gpu/drm/panthor/panthor_aw.c
 create mode 100644 drivers/gpu/drm/panthor/panthor_aw.h
 create mode 100644 drivers/gpu/drm/panthor/panthor_device_io.h
 create mode 100644 drivers/gpu/drm/panthor/panthor_gpu_discover_regs.h
 create mode 100644 drivers/gpu/drm/panthor/system/Makefile
 create mode 100644 drivers/gpu/drm/panthor/system/panthor_system_drv.c

--
2.43.0

[PATCH v1 01/27] drm/panthor: Ignore -EOPNOTSUPP for shader-present nvmem lookup

[Karunika Choo]

When CONFIG_NVMEM is disabled, reading the optional "shader-present"
nvmem cell can return -EOPNOTSUPP.

Treat this the same as the cell being absent so panthor can continue
probing on platforms that do not provide shader-present fuses through
nvmem.

Fixes: c40b50c3cfbe ("drm/panthor: Implement reading shader_present from nvmem")
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Steven Price <steven.price@arm.com>
Signed-off-by: Karunika Choo <karunika.choo@arm.com>
---
v1:
- Picked up R-bs from Boris and Steve
- Added Fixes tag

 drivers/gpu/drm/panthor/panthor_hw.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/panthor/panthor_hw.c b/drivers/gpu/drm/panthor/panthor_hw.c
index 7e315708ca7ca..4c96573b649a1 100644
--- a/drivers/gpu/drm/panthor/panthor_hw.c
+++ b/drivers/gpu/drm/panthor/panthor_hw.c
@@ -182,7 +182,7 @@ static int overload_shader_present(struct panthor_device *ptdev)
 					      &contents);
 	if (!ret)
 		ptdev->gpu_info.shader_present = contents;
-	else if (ret == -ENOENT)
+	else if (ret == -ENOENT || ret == -EOPNOTSUPP)
 		return 0;
 	else
 		return dev_err_probe(ptdev->base.dev, ret,
--
2.43.0

[PATCH v1 02/27] drm/panthor: Move register access helpers out of panthor_device.h

[Karunika Choo]

Move register access helpers out of panthor_device.h to allow reuse by
other panthor drivers that will be added to enable v15 support.

Signed-off-by: Karunika Choo <karunika.choo@arm.com>
---
v1:
- Includes "panthor_device_io.h" directly in "panthor_device.h" instead
  of peppering multiple files with the header.

 drivers/gpu/drm/panthor/panthor_device.h    | 74 +-----------------
 drivers/gpu/drm/panthor/panthor_device_io.h | 83 +++++++++++++++++++++
 2 files changed, 85 insertions(+), 72 deletions(-)
 create mode 100644 drivers/gpu/drm/panthor/panthor_device_io.h

diff --git a/drivers/gpu/drm/panthor/panthor_device.h b/drivers/gpu/drm/panthor/panthor_device.h
index b55a3f9edd414..54031c5252473 100644
--- a/drivers/gpu/drm/panthor/panthor_device.h
+++ b/drivers/gpu/drm/panthor/panthor_device.h
@@ -6,7 +6,6 @@
 #ifndef __PANTHOR_DEVICE_H__
 #define __PANTHOR_DEVICE_H__

-#include <linux/atomic.h>
 #include <linux/io-pgtable.h>
 #include <linux/regulator/consumer.h>
 #include <linux/pm_runtime.h>
@@ -19,6 +18,8 @@
 #include <drm/gpu_scheduler.h>
 #include <drm/panthor_drm.h>

+#include "panthor_device_io.h"
+
 struct panthor_csf;
 struct panthor_csf_ctx;
 struct panthor_device;
@@ -495,77 +496,6 @@ panthor_exception_is_fault(u32 exception_code)
 const char *panthor_exception_name(struct panthor_device *ptdev,
 				   u32 exception_code);

-static inline void gpu_write(void __iomem *iomem, u32 reg, u32 data)
-{
-	writel(data, iomem + reg);
-}
-
-static inline u32 gpu_read(void __iomem *iomem, u32 reg)
-{
-	return readl(iomem + reg);
-}
-
-static inline u32 gpu_read_relaxed(void __iomem *iomem, u32 reg)
-{
-	return readl_relaxed(iomem + reg);
-}
-
-static inline void gpu_write64(void __iomem *iomem, u32 reg, u64 data)
-{
-	gpu_write(iomem, reg, lower_32_bits(data));
-	gpu_write(iomem, reg + 4, upper_32_bits(data));
-}
-
-static inline u64 gpu_read64(void __iomem *iomem, u32 reg)
-{
-	return (gpu_read(iomem, reg) | ((u64)gpu_read(iomem, reg + 4) << 32));
-}
-
-static inline u64 gpu_read64_relaxed(void __iomem *iomem, u32 reg)
-{
-	return (gpu_read_relaxed(iomem, reg) |
-		((u64)gpu_read_relaxed(iomem, reg + 4) << 32));
-}
-
-static inline u64 gpu_read64_counter(void __iomem *iomem, u32 reg)
-{
-	u32 lo, hi1, hi2;
-	do {
-		hi1 = gpu_read(iomem, reg + 4);
-		lo = gpu_read(iomem, reg);
-		hi2 = gpu_read(iomem, reg + 4);
-	} while (hi1 != hi2);
-	return lo | ((u64)hi2 << 32);
-}
-
-#define gpu_read_poll_timeout(iomem, reg, val, cond, delay_us, timeout_us)	\
-	read_poll_timeout(gpu_read, val, cond, delay_us, timeout_us, false,	\
-			  iomem, reg)
-
-#define gpu_read_poll_timeout_atomic(iomem, reg, val, cond, delay_us,		\
-				     timeout_us)				\
-	read_poll_timeout_atomic(gpu_read, val, cond, delay_us, timeout_us,	\
-				 false, iomem, reg)
-
-#define gpu_read64_poll_timeout(iomem, reg, val, cond, delay_us, timeout_us)	\
-	read_poll_timeout(gpu_read64, val, cond, delay_us, timeout_us, false,	\
-			  iomem, reg)
-
-#define gpu_read64_poll_timeout_atomic(iomem, reg, val, cond, delay_us,		\
-				       timeout_us)				\
-	read_poll_timeout_atomic(gpu_read64, val, cond, delay_us, timeout_us,	\
-				 false, iomem, reg)
-
-#define gpu_read_relaxed_poll_timeout_atomic(iomem, reg, val, cond, delay_us,	\
-					     timeout_us)			\
-	read_poll_timeout_atomic(gpu_read_relaxed, val, cond, delay_us,		\
-				 timeout_us, false, iomem, reg)
-
-#define gpu_read64_relaxed_poll_timeout(iomem, reg, val, cond, delay_us,	\
-					timeout_us)				\
-	read_poll_timeout(gpu_read64_relaxed, val, cond, delay_us, timeout_us,	\
-			  false, iomem, reg)
-
 #define INT_RAWSTAT 0x0
 #define INT_CLEAR   0x4
 #define INT_MASK    0x8
diff --git a/drivers/gpu/drm/panthor/panthor_device_io.h b/drivers/gpu/drm/panthor/panthor_device_io.h
new file mode 100644
index 0000000000000..2287a0d9f86c2
--- /dev/null
+++ b/drivers/gpu/drm/panthor/panthor_device_io.h
@@ -0,0 +1,83 @@
+/* SPDX-License-Identifier: GPL-2.0 or MIT */
+/* Copyright 2026 ARM Limited. All rights reserved. */
+
+#ifndef __PANTHOR_DEVICE_IO_H__
+#define __PANTHOR_DEVICE_IO_H__
+
+#include <linux/atomic.h>
+#include <linux/io.h>
+
+
+static inline void gpu_write(void __iomem *iomem, u32 reg, u32 data)
+{
+	writel(data, iomem + reg);
+}
+
+static inline u32 gpu_read(void __iomem *iomem, u32 reg)
+{
+	return readl(iomem + reg);
+}
+
+static inline u32 gpu_read_relaxed(void __iomem *iomem, u32 reg)
+{
+	return readl_relaxed(iomem + reg);
+}
+
+static inline void gpu_write64(void __iomem *iomem, u32 reg, u64 data)
+{
+	gpu_write(iomem, reg, lower_32_bits(data));
+	gpu_write(iomem, reg + 4, upper_32_bits(data));
+}
+
+static inline u64 gpu_read64(void __iomem *iomem, u32 reg)
+{
+	return (gpu_read(iomem, reg) | ((u64)gpu_read(iomem, reg + 4) << 32));
+}
+
+static inline u64 gpu_read64_relaxed(void __iomem *iomem, u32 reg)
+{
+	return (gpu_read_relaxed(iomem, reg) |
+		((u64)gpu_read_relaxed(iomem, reg + 4) << 32));
+}
+
+static inline u64 gpu_read64_counter(void __iomem *iomem, u32 reg)
+{
+	u32 lo, hi1, hi2;
+	do {
+		hi1 = gpu_read(iomem, reg + 4);
+		lo = gpu_read(iomem, reg);
+		hi2 = gpu_read(iomem, reg + 4);
+	} while (hi1 != hi2);
+	return lo | ((u64)hi2 << 32);
+}
+
+#define gpu_read_poll_timeout(iomem, reg, val, cond, delay_us, timeout_us)	\
+	read_poll_timeout(gpu_read, val, cond, delay_us, timeout_us, false,	\
+			  iomem, reg)
+
+#define gpu_read_poll_timeout_atomic(iomem, reg, val, cond, delay_us,		\
+				     timeout_us)				\
+	read_poll_timeout_atomic(gpu_read, val, cond, delay_us, timeout_us,	\
+				 false, iomem, reg)
+
+#define gpu_read64_poll_timeout(iomem, reg, val, cond, delay_us, timeout_us)	\
+	read_poll_timeout(gpu_read64, val, cond, delay_us, timeout_us, false,	\
+			  iomem, reg)
+
+#define gpu_read64_poll_timeout_atomic(iomem, reg, val, cond, delay_us,		\
+				       timeout_us)				\
+	read_poll_timeout_atomic(gpu_read64, val, cond, delay_us, timeout_us,	\
+				 false, iomem, reg)
+
+#define gpu_read_relaxed_poll_timeout_atomic(iomem, reg, val, cond, delay_us,	\
+					     timeout_us)			\
+	read_poll_timeout_atomic(gpu_read_relaxed, val, cond, delay_us,		\
+				 timeout_us, false, iomem, reg)
+
+#define gpu_read64_relaxed_poll_timeout(iomem, reg, val, cond, delay_us,	\
+					timeout_us)				\
+	read_poll_timeout(gpu_read64_relaxed, val, cond, delay_us, timeout_us,	\
+			  false, iomem, reg)
+
+
+#endif /* __PANTHOR_DEVICE_IO_H__ */
--
2.43.0

[PATCH v1 03/27] drm/panthor: Parse and store GPU_ID fields

[Karunika Choo]

Prepare for Mali v15, where GPU_ID expands to 64 bits and its field
layout changes.

Introduce a small panthor_gpu_id structure and parse the GPU_ID fields
once during hardware initialization. Convert existing users to consume
the cached fields instead of extracting them repeatedly from the raw
register value.

This centralizes GPU_ID decoding and makes it easier to support both the
existing and v15 formats.

Signed-off-by: Karunika Choo <karunika.choo@arm.com>
---
v1:
- changed struct panthor_gpu_id into a flat structure instead of
  inconsistent groupings.

 drivers/gpu/drm/panthor/panthor_device.h | 29 ++++++++++++++++++++++++
 drivers/gpu/drm/panthor/panthor_fw.c     |  4 ++--
 drivers/gpu/drm/panthor/panthor_gpu.c    |  2 +-
 drivers/gpu/drm/panthor/panthor_hw.c     | 26 ++++++++++++++-------
 drivers/gpu/drm/panthor/panthor_hw.h     |  3 +--
 5 files changed, 51 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/panthor/panthor_device.h b/drivers/gpu/drm/panthor/panthor_device.h
index 54031c5252473..ba93a100ceda2 100644
--- a/drivers/gpu/drm/panthor/panthor_device.h
+++ b/drivers/gpu/drm/panthor/panthor_device.h
@@ -110,6 +110,32 @@ struct panthor_irq {
 	enum panthor_irq_state state;
 };
 
+/**
+ * struct panthor_gpu_id - Parsed GPU_ID fields
+ */
+struct panthor_gpu_id {
+	/** @arch_major: Architecture major revision */
+	u8 arch_major;
+
+	/** @arch_minor: Architecture minor revision */
+	u8 arch_minor;
+
+	/** @arch_rev: Architecture patch revision */
+	u8 arch_rev;
+
+	/** @prod_major: Product identifier */
+	u8 prod_major;
+
+	/** @ver_major: Major release version number */
+	u8 ver_major;
+
+	/** @ver_minor: Minor release version number */
+	u8 ver_minor;
+
+	/** @ver_status: Status of GPU release */
+	u8 ver_status;
+};
+
 /**
  * enum panthor_device_profiling_mode - Profiling state
  */
@@ -169,6 +195,9 @@ struct panthor_device {
 	/** @mmu_info: MMU info */
 	struct drm_panthor_mmu_info mmu_info;
 
+	/** @gpu_id: Parsed GPU_ID fields */
+	struct panthor_gpu_id gpu_id;
+
 	/** @hw: GPU-specific data. */
 	struct panthor_hw *hw;
 
diff --git a/drivers/gpu/drm/panthor/panthor_fw.c b/drivers/gpu/drm/panthor/panthor_fw.c
index 4f1fab66a13bf..13efed3a2ea72 100644
--- a/drivers/gpu/drm/panthor/panthor_fw.c
+++ b/drivers/gpu/drm/panthor/panthor_fw.c
@@ -809,8 +809,8 @@ static int panthor_fw_load(struct panthor_device *ptdev)
 	int ret;
 
 	snprintf(fw_path, sizeof(fw_path), "arm/mali/arch%d.%d/%s",
-		 (u32)GPU_ARCH_MAJOR(ptdev->gpu_info.gpu_id),
-		 (u32)GPU_ARCH_MINOR(ptdev->gpu_info.gpu_id),
+		 (u32)ptdev->gpu_id.arch_major,
+		 (u32)ptdev->gpu_id.arch_minor,
 		 CSF_FW_NAME);
 
 	ret = request_firmware(&fw, fw_path, ptdev->base.dev);
diff --git a/drivers/gpu/drm/panthor/panthor_gpu.c b/drivers/gpu/drm/panthor/panthor_gpu.c
index a383b04f101ed..ade2646e2caf6 100644
--- a/drivers/gpu/drm/panthor/panthor_gpu.c
+++ b/drivers/gpu/drm/panthor/panthor_gpu.c
@@ -73,7 +73,7 @@ static void panthor_gpu_l2_config_set(struct panthor_device *ptdev)
 	if (!data || !data->asn_hash_enable)
 		return;
 
-	if (GPU_ARCH_MAJOR(ptdev->gpu_info.gpu_id) < 11) {
+	if (ptdev->gpu_id.arch_major < 11) {
 		drm_err(&ptdev->base, "Custom ASN hash not supported by the device");
 		return;
 	}
diff --git a/drivers/gpu/drm/panthor/panthor_hw.c b/drivers/gpu/drm/panthor/panthor_hw.c
index 4c96573b649a1..2143e57d48106 100644
--- a/drivers/gpu/drm/panthor/panthor_hw.c
+++ b/drivers/gpu/drm/panthor/panthor_hw.c
@@ -119,9 +119,9 @@ void panthor_hw_power_status_unregister(void)
 
 static char *get_gpu_model_name(struct panthor_device *ptdev)
 {
-	const u32 gpu_id = ptdev->gpu_info.gpu_id;
-	const u32 product_id = GPU_PROD_ID_MAKE(GPU_ARCH_MAJOR(gpu_id),
-						GPU_PROD_MAJOR(gpu_id));
+	const struct panthor_gpu_id *gpu_id = &ptdev->gpu_id;
+	const u32 product_id = GPU_PROD_ID_MAKE(gpu_id->arch_major,
+						gpu_id->prod_major);
 	const bool ray_intersection = !!(ptdev->gpu_info.gpu_features &
 					 GPU_FEATURES_RAY_INTERSECTION);
 	const u8 shader_core_count = hweight64(ptdev->gpu_info.shader_present);
@@ -245,13 +245,13 @@ static int panthor_hw_info_init(struct panthor_device *ptdev)
 	if (ret)
 		return ret;
 
-	major = GPU_VER_MAJOR(ptdev->gpu_info.gpu_id);
-	minor = GPU_VER_MINOR(ptdev->gpu_info.gpu_id);
-	status = GPU_VER_STATUS(ptdev->gpu_info.gpu_id);
+	major = ptdev->gpu_id.ver_major;
+	minor = ptdev->gpu_id.ver_minor;
+	status = ptdev->gpu_id.ver_status;
 
 	drm_info(&ptdev->base,
 		 "%s id 0x%x major 0x%x minor 0x%x status 0x%x",
-		 get_gpu_model_name(ptdev), ptdev->gpu_info.gpu_id >> 16,
+		 get_gpu_model_name(ptdev), ptdev->gpu_id.prod_major,
 		 major, minor, status);
 
 	drm_info(&ptdev->base,
@@ -273,7 +273,7 @@ static int panthor_hw_info_init(struct panthor_device *ptdev)
 static int panthor_hw_bind_device(struct panthor_device *ptdev)
 {
 	struct panthor_hw *hdev = NULL;
-	const u32 arch_major = GPU_ARCH_MAJOR(ptdev->gpu_info.gpu_id);
+	const u32 arch_major = ptdev->gpu_id.arch_major;
 	int i = 0;
 
 	for (i = 0; i < ARRAY_SIZE(panthor_hw_match); i++) {
@@ -295,10 +295,20 @@ static int panthor_hw_bind_device(struct panthor_device *ptdev)
 
 static int panthor_hw_gpu_id_init(struct panthor_device *ptdev)
 {
+	struct panthor_gpu_id *gpu_id = &ptdev->gpu_id;
 	ptdev->gpu_info.gpu_id = gpu_read(ptdev->iomem, GPU_ID);
+
 	if (!ptdev->gpu_info.gpu_id)
 		return -ENXIO;
 
+	gpu_id->arch_major = GPU_ARCH_MAJOR(ptdev->gpu_info.gpu_id);
+	gpu_id->arch_minor = GPU_ARCH_MINOR(ptdev->gpu_info.gpu_id);
+	gpu_id->arch_rev = GPU_ARCH_REV(ptdev->gpu_info.gpu_id);
+	gpu_id->prod_major = GPU_PROD_MAJOR(ptdev->gpu_info.gpu_id);
+	gpu_id->ver_major = GPU_VER_MAJOR(ptdev->gpu_info.gpu_id);
+	gpu_id->ver_minor = GPU_VER_MINOR(ptdev->gpu_info.gpu_id);
+	gpu_id->ver_status = GPU_VER_STATUS(ptdev->gpu_info.gpu_id);
+
 	return 0;
 }
 
diff --git a/drivers/gpu/drm/panthor/panthor_hw.h b/drivers/gpu/drm/panthor/panthor_hw.h
index f797663893b2d..bdda3b10e660a 100644
--- a/drivers/gpu/drm/panthor/panthor_hw.h
+++ b/drivers/gpu/drm/panthor/panthor_hw.h
@@ -5,7 +5,6 @@
 #define __PANTHOR_HW_H__
 
 #include "panthor_device.h"
-#include "panthor_gpu_regs.h"
 
 /**
  * struct panthor_hw_ops - HW operations that are specific to a GPU
@@ -58,7 +57,7 @@ static inline void panthor_hw_l2_power_off(struct panthor_device *ptdev)
 
 static inline bool panthor_hw_has_pwr_ctrl(struct panthor_device *ptdev)
 {
-	return GPU_ARCH_MAJOR(ptdev->gpu_info.gpu_id) >= 14;
+	return ptdev->gpu_id.arch_major >= 14;
 }
 
 #endif /* __PANTHOR_HW_H__ */
-- 
2.43.0

[PATCH v1 04/27] drm/panthor: Add 64-bit GPU_ID decoding for v15 GPUs

[Karunika Choo]

Mali v15 exposes a 64-bit GPU_ID register with a different field layout
from earlier GPUs.

Add the register definitions and decoding helpers for the new format,
read GPU_WIDE_ID when the compatibility value indicates a v15 GPU, and
populate both the cached GPU_ID fields and the uAPI gpu_wide_id field.

This allows userspace and the driver to identify v15 GPUs correctly.

Signed-off-by: Karunika Choo <karunika.choo@arm.com>
---
v1:
- Decode selected GPU_ID format after checking compatibility value.
- Document GPU_DISCOVER and GPU_CONTROL register offset differences
  between GPUs.
- Fix mask generation in panthor_gpu_discover_regs.h

 .../drm/panthor/panthor_gpu_discover_regs.h   | 19 +++++++++
 drivers/gpu/drm/panthor/panthor_hw.c          | 42 +++++++++++++++----
 include/uapi/drm/panthor_drm.h                | 13 ++++++
 3 files changed, 65 insertions(+), 9 deletions(-)
 create mode 100644 drivers/gpu/drm/panthor/panthor_gpu_discover_regs.h

diff --git a/drivers/gpu/drm/panthor/panthor_gpu_discover_regs.h b/drivers/gpu/drm/panthor/panthor_gpu_discover_regs.h
new file mode 100644
index 0000000000000..e6bfe1fe2c68a
--- /dev/null
+++ b/drivers/gpu/drm/panthor/panthor_gpu_discover_regs.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0 or MIT */
+/* Copyright 2026 ARM Limited. All rights reserved. */
+
+#ifndef __PANTHOR_GPU_DISCOVER_REGS_H__
+#define __PANTHOR_GPU_DISCOVER_REGS_H__
+
+#include <linux/bits.h>
+
+#define GPU_WIDE_ID					0x0
+#define   GPU_WIDE_COMPAT				0xF
+#define   GPU_WIDE_ARCH_MAJOR(x)			(((x) & GENMASK_U64(63, 56)) >> 56)
+#define   GPU_WIDE_ARCH_MINOR(x)			(((x) & GENMASK_U64(55, 48)) >> 48)
+#define   GPU_WIDE_ARCH_REV(x)				(((x) & GENMASK_U64(47, 40)) >> 40)
+#define   GPU_WIDE_PROD_MAJOR(x)			(((x) & GENMASK_U64(39, 32)) >> 32)
+#define   GPU_WIDE_VER_MAJOR(x)				(((x) & GENMASK_U64(23, 16)) >> 16)
+#define   GPU_WIDE_VER_MINOR(x)				(((x) & GENMASK_U64(15, 8)) >> 8)
+#define   GPU_WIDE_VER_STATUS(x)			((x) & GENMASK_U64(7, 0))
+
+#endif /* __PANTHOR_GPU_DISCOVER_REGS_H__ */
diff --git a/drivers/gpu/drm/panthor/panthor_hw.c b/drivers/gpu/drm/panthor/panthor_hw.c
index 2143e57d48106..40012ba7e23ca 100644
--- a/drivers/gpu/drm/panthor/panthor_hw.c
+++ b/drivers/gpu/drm/panthor/panthor_hw.c
@@ -8,6 +8,7 @@
 
 #include "panthor_device.h"
 #include "panthor_gpu.h"
+#include "panthor_gpu_discover_regs.h"
 #include "panthor_gpu_regs.h"
 #include "panthor_hw.h"
 #include "panthor_pwr.h"
@@ -296,18 +297,41 @@ static int panthor_hw_bind_device(struct panthor_device *ptdev)
 static int panthor_hw_gpu_id_init(struct panthor_device *ptdev)
 {
 	struct panthor_gpu_id *gpu_id = &ptdev->gpu_id;
-	ptdev->gpu_info.gpu_id = gpu_read(ptdev->iomem, GPU_ID);
+	u32 gpu_id32 = gpu_read(ptdev->iomem, GPU_ID);
 
-	if (!ptdev->gpu_info.gpu_id)
+	if (!gpu_id32)
 		return -ENXIO;
 
-	gpu_id->arch_major = GPU_ARCH_MAJOR(ptdev->gpu_info.gpu_id);
-	gpu_id->arch_minor = GPU_ARCH_MINOR(ptdev->gpu_info.gpu_id);
-	gpu_id->arch_rev = GPU_ARCH_REV(ptdev->gpu_info.gpu_id);
-	gpu_id->prod_major = GPU_PROD_MAJOR(ptdev->gpu_info.gpu_id);
-	gpu_id->ver_major = GPU_VER_MAJOR(ptdev->gpu_info.gpu_id);
-	gpu_id->ver_minor = GPU_VER_MINOR(ptdev->gpu_info.gpu_id);
-	gpu_id->ver_status = GPU_VER_STATUS(ptdev->gpu_info.gpu_id);
+	if (GPU_ARCH_MAJOR(gpu_id32) == GPU_WIDE_COMPAT) {
+		/*
+		 * GPU_DISCOVER register block always starts at offset zero,
+		 * so does the GPU_CONTROL register block on pre-v15 GPUs.
+		 */
+		void __iomem *discover = ptdev->iomem;
+		u64 gpu_id64 = gpu_read64(discover, GPU_WIDE_ID);
+		if (!gpu_id64)
+			return -ENXIO;
+
+		ptdev->gpu_info.gpu_wide_id = gpu_id64;
+
+		gpu_id->arch_major = GPU_WIDE_ARCH_MAJOR(gpu_id64);
+		gpu_id->arch_minor = GPU_WIDE_ARCH_MINOR(gpu_id64);
+		gpu_id->arch_rev = GPU_WIDE_ARCH_REV(gpu_id64);
+		gpu_id->prod_major = GPU_WIDE_PROD_MAJOR(gpu_id64);
+		gpu_id->ver_major = GPU_WIDE_VER_MAJOR(gpu_id64);
+		gpu_id->ver_minor = GPU_WIDE_VER_MINOR(gpu_id64);
+		gpu_id->ver_status = GPU_WIDE_VER_STATUS(gpu_id64);
+	} else {
+		ptdev->gpu_info.gpu_id = gpu_id32;
+
+		gpu_id->arch_major = GPU_ARCH_MAJOR(gpu_id32);
+		gpu_id->arch_minor = GPU_ARCH_MINOR(gpu_id32);
+		gpu_id->arch_rev = GPU_ARCH_REV(gpu_id32);
+		gpu_id->prod_major = GPU_PROD_MAJOR(gpu_id32);
+		gpu_id->ver_major = GPU_VER_MAJOR(gpu_id32);
+		gpu_id->ver_minor = GPU_VER_MINOR(gpu_id32);
+		gpu_id->ver_status = GPU_VER_STATUS(gpu_id32);
+	}
 
 	return 0;
 }
diff --git a/include/uapi/drm/panthor_drm.h b/include/uapi/drm/panthor_drm.h
index a2ff0f4ec6915..843a0b40e1d36 100644
--- a/include/uapi/drm/panthor_drm.h
+++ b/include/uapi/drm/panthor_drm.h
@@ -376,6 +376,19 @@ struct drm_panthor_gpu_info {
 
 	/** @gpu_features: Bitmask describing supported GPU-wide features */
 	__u64 gpu_features;
+
+	/**
+	 * @gpu_wide_id: 64-bit GPU ID for v15 and later GPUs. @gpu_id is 0 when
+	 * this is populated.
+	 */
+	__u64 gpu_wide_id;
+#define DRM_PANTHOR_WIDE_ARCH_MAJOR(x)		(((x) >> 56) & 0xff)
+#define DRM_PANTHOR_WIDE_ARCH_MINOR(x)		(((x) >> 48) & 0xff)
+#define DRM_PANTHOR_WIDE_ARCH_REV(x)		(((x) >> 40) & 0xff)
+#define DRM_PANTHOR_WIDE_PRODUCT_MAJOR(x)	(((x) >> 32) & 0xff)
+#define DRM_PANTHOR_WIDE_VERSION_MAJOR(x)	(((x) >> 16) & 0xff)
+#define DRM_PANTHOR_WIDE_VERSION_MINOR(x)	(((x) >> 8) & 0xff)
+#define DRM_PANTHOR_WIDE_VERSION_STATUS(x)	((x) & 0xff)
 };
 
 /**
-- 
2.43.0

[PATCH v1 05/27] drm/panthor: Move register base offsets to the HW description

[Karunika Choo]

Mali v15 reorders several register regions, including GPU_CONTROL,
MCU_CONTROL and PWR_CONTROL, so the driver can no longer assume a single
fixed base layout across all supported GPUs.

Add per-GPU register base offsets to the panthor hardware description
and switch the GPU, FW and PWR local iomem setup to use those stored
values. With the base addresses now owned by the hardware description,
drop the corresponding fixed base-offset definitions from the register
headers.

This prepares the driver for GPUs with different register layouts
without changing the existing behaviour on currently supported parts.

Signed-off-by: Karunika Choo <karunika.choo@arm.com>
---
v1:
- rebased on drm-misc-next
- use a generic panthor_hw_regbank structure for all register offsets.

 drivers/gpu/drm/panthor/panthor_fw.c       |  2 +-
 drivers/gpu/drm/panthor/panthor_fw_regs.h  |  2 --
 drivers/gpu/drm/panthor/panthor_gpu.c      |  4 +--
 drivers/gpu/drm/panthor/panthor_gpu_regs.h |  2 --
 drivers/gpu/drm/panthor/panthor_hw.c       | 23 +++++++++++++++--
 drivers/gpu/drm/panthor/panthor_hw.h       | 29 ++++++++++++++++++++--
 drivers/gpu/drm/panthor/panthor_pwr.c      |  2 +-
 drivers/gpu/drm/panthor/panthor_pwr_regs.h |  2 --
 8 files changed, 52 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/panthor/panthor_fw.c b/drivers/gpu/drm/panthor/panthor_fw.c
index 13efed3a2ea72..679ea1d233d53 100644
--- a/drivers/gpu/drm/panthor/panthor_fw.c
+++ b/drivers/gpu/drm/panthor/panthor_fw.c
@@ -1500,7 +1500,7 @@ int panthor_fw_init(struct panthor_device *ptdev)
 	if (!fw)
 		return -ENOMEM;
 
-	fw->iomem = ptdev->iomem + MCU_CONTROL_BASE;
+	fw->iomem = ptdev->iomem + ptdev->hw->regs.mcu_control.offset;
 	ptdev->fw = fw;
 	init_waitqueue_head(&fw->req_waitqueue);
 	INIT_LIST_HEAD(&fw->sections);
diff --git a/drivers/gpu/drm/panthor/panthor_fw_regs.h b/drivers/gpu/drm/panthor/panthor_fw_regs.h
index b2e59cfc22b00..a3492f7f913f9 100644
--- a/drivers/gpu/drm/panthor/panthor_fw_regs.h
+++ b/drivers/gpu/drm/panthor/panthor_fw_regs.h
@@ -4,8 +4,6 @@
 #ifndef __PANTHOR_FW_REGS_H__
 #define __PANTHOR_FW_REGS_H__
 
-#define MCU_CONTROL_BASE				0x700
-
 #define MCU_CONTROL					0x0
 #define   MCU_CONTROL_ENABLE				1
 #define   MCU_CONTROL_AUTO				2
diff --git a/drivers/gpu/drm/panthor/panthor_gpu.c b/drivers/gpu/drm/panthor/panthor_gpu.c
index ade2646e2caf6..d6534fabc682e 100644
--- a/drivers/gpu/drm/panthor/panthor_gpu.c
+++ b/drivers/gpu/drm/panthor/panthor_gpu.c
@@ -158,7 +158,7 @@ int panthor_gpu_init(struct panthor_device *ptdev)
 	if (!gpu)
 		return -ENOMEM;
 
-	gpu->iomem = ptdev->iomem + GPU_CONTROL_BASE;
+	gpu->iomem = ptdev->iomem + ptdev->hw->regs.gpu_control.offset;
 	spin_lock_init(&gpu->reqs_lock);
 	init_waitqueue_head(&gpu->reqs_acked);
 	mutex_init(&gpu->cache_flush_lock);
@@ -175,7 +175,7 @@ int panthor_gpu_init(struct panthor_device *ptdev)
 		return irq;
 
 	ret = panthor_irq_request(ptdev, &ptdev->gpu->irq, irq,
-				  ptdev->iomem + GPU_INT_BASE, "gpu",
+				  gpu->iomem + GPU_INT_BASE, "gpu",
 				  panthor_gpu_irq_threaded_handler);
 	if (ret)
 		return ret;
diff --git a/drivers/gpu/drm/panthor/panthor_gpu_regs.h b/drivers/gpu/drm/panthor/panthor_gpu_regs.h
index 4c5b953796e4f..753df87009901 100644
--- a/drivers/gpu/drm/panthor/panthor_gpu_regs.h
+++ b/drivers/gpu/drm/panthor/panthor_gpu_regs.h
@@ -4,8 +4,6 @@
 #ifndef __PANTHOR_GPU_REGS_H__
 #define __PANTHOR_GPU_REGS_H__
 
-#define GPU_CONTROL_BASE				0x0
-
 #define GPU_ID						0x0
 #define   GPU_ARCH_MAJOR(x)				((x) >> 28)
 #define   GPU_ARCH_MINOR(x)				(((x) & GENMASK(27, 24)) >> 24)
diff --git a/drivers/gpu/drm/panthor/panthor_hw.c b/drivers/gpu/drm/panthor/panthor_hw.c
index 40012ba7e23ca..2ca5a334f5817 100644
--- a/drivers/gpu/drm/panthor/panthor_hw.c
+++ b/drivers/gpu/drm/panthor/panthor_hw.c
@@ -37,6 +37,14 @@ static struct panthor_hw panthor_hw_arch_v10 = {
 		.power_changed_off = panthor_gpu_power_changed_off,
 		.power_changed_on = panthor_gpu_power_changed_on,
 	},
+	.regs = {
+		.gpu_control = {
+			.offset = 0x0,
+		},
+		.mcu_control = {
+			.offset = 0x700,
+		},
+	},
 };
 
 static struct panthor_hw panthor_hw_arch_v14 = {
@@ -45,6 +53,17 @@ static struct panthor_hw panthor_hw_arch_v14 = {
 		.l2_power_off = panthor_pwr_l2_power_off,
 		.l2_power_on = panthor_pwr_l2_power_on,
 	},
+	.regs = {
+		.gpu_control = {
+			.offset = 0x0,
+		},
+		.mcu_control = {
+			.offset = 0x700,
+		},
+		.pwr_control = {
+			.offset = 0x800,
+		},
+	},
 };
 
 static struct panthor_hw_entry panthor_hw_match[] = {
@@ -196,7 +215,7 @@ static int panthor_gpu_info_init(struct panthor_device *ptdev)
 {
 	unsigned int i;
 
-	void __iomem *gpu_iomem = ptdev->iomem + GPU_CONTROL_BASE;
+	void __iomem *gpu_iomem = ptdev->iomem + ptdev->hw->regs.gpu_control.offset;
 
 	ptdev->gpu_info.csf_id = gpu_read(gpu_iomem, GPU_CSF_ID);
 	ptdev->gpu_info.gpu_rev = gpu_read(gpu_iomem, GPU_REVID);
@@ -222,7 +241,7 @@ static int panthor_gpu_info_init(struct panthor_device *ptdev)
 	ptdev->gpu_info.gpu_features = gpu_read64(gpu_iomem, GPU_FEATURES);
 
 	if (panthor_hw_has_pwr_ctrl(ptdev)) {
-		void __iomem *pwr_iomem = gpu_iomem + PWR_CONTROL_BASE;
+		void __iomem *pwr_iomem = ptdev->iomem + ptdev->hw->regs.pwr_control.offset;
 
 		/* Introduced in arch 14.x */
 		ptdev->gpu_info.l2_present = gpu_read64(pwr_iomem, PWR_L2_PRESENT);
diff --git a/drivers/gpu/drm/panthor/panthor_hw.h b/drivers/gpu/drm/panthor/panthor_hw.h
index bdda3b10e660a..9231c18af94d1 100644
--- a/drivers/gpu/drm/panthor/panthor_hw.h
+++ b/drivers/gpu/drm/panthor/panthor_hw.h
@@ -26,14 +26,39 @@ struct panthor_hw_ops {
 	void (*power_changed_off)(struct panthor_device *ptdev);
 };
 
+/** struct panthor_hw_regbank - Register offset and instance stride information */
+struct panthor_hw_regbank {
+	/** @offset: Register offset relative to &struct panthor_device.iomem */
+	u32 offset;
+
+	/**
+	 * @stride: Register offset between instances, or 0 for non-instanced
+	 * registers
+	 */
+	u32 stride;
+};
+
+/** struct panthor_hw_regs_layout - Hardware register bank layout */
+struct panthor_hw_regs_layout {
+	/** @gpu_control: GPU_CONTROL register bank layout */
+	struct panthor_hw_regbank gpu_control;
+
+	/** @pwr_control: PWR_CONTROL register bank layout */
+	struct panthor_hw_regbank pwr_control;
+
+	/** @mcu_control: MCU_CONTROL register bank layout */
+	struct panthor_hw_regbank mcu_control;
+};
+
 /**
  * struct panthor_hw - GPU specific register mapping and functions
  */
 struct panthor_hw {
-	/** @features: Bitmap containing panthor_hw_feature */
-
 	/** @ops: Panthor HW specific operations */
 	struct panthor_hw_ops ops;
+
+	/** @regs: Hardware register bank layout */
+	struct panthor_hw_regs_layout regs;
 };
 
 int panthor_hw_init(struct panthor_device *ptdev);
diff --git a/drivers/gpu/drm/panthor/panthor_pwr.c b/drivers/gpu/drm/panthor/panthor_pwr.c
index dd7b6ef8ea209..cc2e01595f23b 100644
--- a/drivers/gpu/drm/panthor/panthor_pwr.c
+++ b/drivers/gpu/drm/panthor/panthor_pwr.c
@@ -480,7 +480,7 @@ int panthor_pwr_init(struct panthor_device *ptdev)
 	if (!pwr)
 		return -ENOMEM;
 
-	pwr->iomem = ptdev->iomem + PWR_CONTROL_BASE;
+	pwr->iomem = ptdev->iomem + ptdev->hw->regs.pwr_control.offset;
 	spin_lock_init(&pwr->reqs_lock);
 	init_waitqueue_head(&pwr->reqs_acked);
 	ptdev->pwr = pwr;
diff --git a/drivers/gpu/drm/panthor/panthor_pwr_regs.h b/drivers/gpu/drm/panthor/panthor_pwr_regs.h
index 9cf7a715066f8..05f5b48e6a39a 100644
--- a/drivers/gpu/drm/panthor/panthor_pwr_regs.h
+++ b/drivers/gpu/drm/panthor/panthor_pwr_regs.h
@@ -4,8 +4,6 @@
 #ifndef __PANTHOR_PWR_REGS_H__
 #define __PANTHOR_PWR_REGS_H__
 
-#define PWR_CONTROL_BASE				0x800
-
 #define PWR_INT_BASE					0x0
 #define   PWR_IRQ_POWER_CHANGED_SINGLE			BIT(0)
 #define   PWR_IRQ_POWER_CHANGED_ALL			BIT(1)
-- 
2.43.0

[PATCH v1 06/27] drm/panthor: Derive MMU AS register addresses from base and stride

[Karunika Choo]

Move the MMU address-space register layout into the hardware description
by storing the MMU_AS base offset and per-AS stride in the Panthor HW
map.

Use those values to compute the iomem pointer for each AS slot and make
the MMU AS register definitions relative to the per-slot register window
instead of hard-coding the slot offset in every register macro.

This prepares the MMU code for GPUs where the MMU AS register region is
not at a fixed offset while keeping the existing register accesses
scoped to a single AS window.

Signed-off-by: Karunika Choo <karunika.choo@arm.com>
---
v1:
- align with updated panthor_hw_regbank structure.
- moved AS iomem tracking into panthor_as_slot and introduced as_iomem()
  to retrieve it.

 drivers/gpu/drm/panthor/panthor_hw.c       |  8 ++++
 drivers/gpu/drm/panthor/panthor_hw.h       |  3 ++
 drivers/gpu/drm/panthor/panthor_mmu.c      | 45 ++++++++++++++--------
 drivers/gpu/drm/panthor/panthor_mmu_regs.h | 23 +++++------
 4 files changed, 50 insertions(+), 29 deletions(-)

diff --git a/drivers/gpu/drm/panthor/panthor_hw.c b/drivers/gpu/drm/panthor/panthor_hw.c
index 2ca5a334f5817..13090ff6db7b5 100644
--- a/drivers/gpu/drm/panthor/panthor_hw.c
+++ b/drivers/gpu/drm/panthor/panthor_hw.c
@@ -44,6 +44,10 @@ static struct panthor_hw panthor_hw_arch_v10 = {
 		.mcu_control = {
 			.offset = 0x700,
 		},
+		.mmu_as_control = {
+			.offset = 0x2400,
+			.stride = 0x40,
+		},
 	},
 };
 
@@ -63,6 +67,10 @@ static struct panthor_hw panthor_hw_arch_v14 = {
 		.pwr_control = {
 			.offset = 0x800,
 		},
+		.mmu_as_control = {
+			.offset = 0x2400,
+			.stride = 0x40,
+		},
 	},
 };
 
diff --git a/drivers/gpu/drm/panthor/panthor_hw.h b/drivers/gpu/drm/panthor/panthor_hw.h
index 9231c18af94d1..68627f0df7f95 100644
--- a/drivers/gpu/drm/panthor/panthor_hw.h
+++ b/drivers/gpu/drm/panthor/panthor_hw.h
@@ -48,6 +48,9 @@ struct panthor_hw_regs_layout {
 
 	/** @mcu_control: MCU_CONTROL register bank layout */
 	struct panthor_hw_regbank mcu_control;
+
+	/** @mmu_as_control: MMU_AS_CONTROL register bank layout */
+	struct panthor_hw_regbank mmu_as_control;
 };
 
 /**
diff --git a/drivers/gpu/drm/panthor/panthor_mmu.c b/drivers/gpu/drm/panthor/panthor_mmu.c
index d75d575473da4..169550413a1a5 100644
--- a/drivers/gpu/drm/panthor/panthor_mmu.c
+++ b/drivers/gpu/drm/panthor/panthor_mmu.c
@@ -35,6 +35,7 @@
 #include "panthor_gpu.h"
 #include "panthor_gpu_regs.h"
 #include "panthor_heap.h"
+#include "panthor_hw.h"
 #include "panthor_mmu.h"
 #include "panthor_mmu_regs.h"
 #include "panthor_sched.h"
@@ -49,15 +50,15 @@ struct panthor_vm;
 struct panthor_as_slot {
 	/** @vm: VM bound to this slot. NULL is no VM is bound. */
 	struct panthor_vm *vm;
+
+	/** @iomem: CPU mapping for MMU_AS_CONTROL iomem region */
+	void __iomem *iomem;
 };
 
 /**
  * struct panthor_mmu - MMU related data
  */
 struct panthor_mmu {
-	/** @iomem: CPU mapping of MMU_AS_CONTROL iomem region */
-	void __iomem *iomem;
-
 	/** @irq: The MMU irq. */
 	struct panthor_irq irq;
 
@@ -533,6 +534,11 @@ static void free_pt(void *cookie, void *data, size_t size)
 	kmem_cache_free(pt_cache, data);
 }
 
+static void __iomem *as_iomem(struct panthor_mmu *mmu, u32 as_nr)
+{
+	return mmu->as.slots[as_nr].iomem;
+}
+
 static int wait_ready(struct panthor_device *ptdev, u32 as_nr)
 {
 	struct panthor_mmu *mmu = ptdev->mmu;
@@ -542,7 +548,7 @@ static int wait_ready(struct panthor_device *ptdev, u32 as_nr)
 	/* Wait for the MMU status to indicate there is no active command, in
 	 * case one is pending.
 	 */
-	ret = gpu_read_relaxed_poll_timeout_atomic(mmu->iomem, AS_STATUS(as_nr), val,
+	ret = gpu_read_relaxed_poll_timeout_atomic(as_iomem(mmu, as_nr), AS_STATUS, val,
 						   !(val & AS_STATUS_AS_ACTIVE), 10, 100000);
 
 	if (ret) {
@@ -560,7 +566,7 @@ static int as_send_cmd_and_wait(struct panthor_device *ptdev, u32 as_nr, u32 cmd
 	/* write AS_COMMAND when MMU is ready to accept another command */
 	status = wait_ready(ptdev, as_nr);
 	if (!status) {
-		gpu_write(ptdev->mmu->iomem, AS_COMMAND(as_nr), cmd);
+		gpu_write(as_iomem(ptdev->mmu, as_nr), AS_COMMAND, cmd);
 		status = wait_ready(ptdev, as_nr);
 	}
 
@@ -609,9 +615,9 @@ static int panthor_mmu_as_enable(struct panthor_device *ptdev, u32 as_nr,
 	panthor_irq_enable_events(&ptdev->mmu->irq,
 				  panthor_mmu_as_fault_mask(ptdev, as_nr));
 
-	gpu_write64(mmu->iomem, AS_TRANSTAB(as_nr), transtab);
-	gpu_write64(mmu->iomem, AS_MEMATTR(as_nr), memattr);
-	gpu_write64(mmu->iomem, AS_TRANSCFG(as_nr), transcfg);
+	gpu_write64(as_iomem(mmu, as_nr), AS_TRANSTAB, transtab);
+	gpu_write64(as_iomem(mmu, as_nr), AS_MEMATTR, memattr);
+	gpu_write64(as_iomem(mmu, as_nr), AS_TRANSCFG, transcfg);
 
 	return as_send_cmd_and_wait(ptdev, as_nr, AS_COMMAND_UPDATE);
 }
@@ -647,9 +653,9 @@ static int panthor_mmu_as_disable(struct panthor_device *ptdev, u32 as_nr,
 	if (recycle_slot)
 		return 0;
 
-	gpu_write64(mmu->iomem, AS_TRANSTAB(as_nr), 0);
-	gpu_write64(mmu->iomem, AS_MEMATTR(as_nr), 0);
-	gpu_write64(mmu->iomem, AS_TRANSCFG(as_nr), AS_TRANSCFG_ADRMODE_UNMAPPED);
+	gpu_write64(as_iomem(mmu, as_nr), AS_TRANSTAB, 0);
+	gpu_write64(as_iomem(mmu, as_nr), AS_MEMATTR, 0);
+	gpu_write64(as_iomem(mmu, as_nr), AS_TRANSCFG, AS_TRANSCFG_ADRMODE_UNMAPPED);
 
 	return as_send_cmd_and_wait(ptdev, as_nr, AS_COMMAND_UPDATE);
 }
@@ -1808,7 +1814,7 @@ static int panthor_vm_lock_region(struct panthor_vm *vm, u64 start, u64 size)
 	mutex_lock(&ptdev->mmu->as.slots_lock);
 	if (vm->as.id >= 0 && size) {
 		/* Lock the region that needs to be updated */
-		gpu_write64(ptdev->mmu->iomem, AS_LOCKADDR(vm->as.id),
+		gpu_write64(as_iomem(ptdev->mmu, vm->as.id), AS_LOCKADDR,
 			    pack_region_range(ptdev, &start, &size));
 
 		/* If the lock succeeded, update the locked_region info. */
@@ -1871,8 +1877,8 @@ static void panthor_mmu_irq_handler(struct panthor_irq *pirq, u32 status)
 		u32 access_type;
 		u32 source_id;
 
-		fault_status = gpu_read(mmu->iomem, AS_FAULTSTATUS(as));
-		addr = gpu_read64(mmu->iomem, AS_FAULTADDRESS(as));
+		fault_status = gpu_read(as_iomem(mmu, as), AS_FAULTSTATUS);
+		addr = gpu_read64(as_iomem(mmu, as), AS_FAULTADDRESS);
 
 		/* decode the fault status */
 		exception_type = fault_status & 0xFF;
@@ -3388,8 +3394,11 @@ static void panthor_mmu_info_init(struct panthor_device *ptdev)
 int panthor_mmu_init(struct panthor_device *ptdev)
 {
 	u32 va_bits = GPU_MMU_FEATURES_VA_BITS(ptdev->gpu_info.mmu_features);
+	unsigned long as_present_mask = ptdev->gpu_info.as_present;
+	struct panthor_hw_regbank *regbank = &ptdev->hw->regs.mmu_as_control;
 	struct panthor_mmu *mmu;
 	int ret, irq;
+	u32 as_id;
 
 	panthor_mmu_info_init(ptdev);
 
@@ -3408,7 +3417,13 @@ int panthor_mmu_init(struct panthor_device *ptdev)
 	if (ret)
 		return ret;
 
-	mmu->iomem = ptdev->iomem + MMU_AS_BASE;
+	for_each_set_bit(as_id, &as_present_mask, MAX_AS_SLOTS) {
+		u64 offset = regbank->offset + (regbank->stride * as_id);
+
+		guard(mutex)(&mmu->as.slots_lock);
+		mmu->as.slots[as_id].iomem = ptdev->iomem + offset;
+	}
+
 	ptdev->mmu = mmu;
 
 	irq = platform_get_irq_byname(to_platform_device(ptdev->base.dev), "mmu");
diff --git a/drivers/gpu/drm/panthor/panthor_mmu_regs.h b/drivers/gpu/drm/panthor/panthor_mmu_regs.h
index 4e32ab931949c..9d3747601e698 100644
--- a/drivers/gpu/drm/panthor/panthor_mmu_regs.h
+++ b/drivers/gpu/drm/panthor/panthor_mmu_regs.h
@@ -10,13 +10,8 @@
 
 /* AS_COMMAND register commands */
 
-#define MMU_AS_BASE					0x2400
-
-#define MMU_AS_SHIFT					6
-#define MMU_AS(as)					((as) << MMU_AS_SHIFT)
-
-#define AS_TRANSTAB(as)					(MMU_AS(as) + 0x0)
-#define AS_MEMATTR(as)					(MMU_AS(as) + 0x8)
+#define AS_TRANSTAB					0x0
+#define AS_MEMATTR					0x8
 #define   AS_MEMATTR_AARCH64_INNER_ALLOC_IMPL		(2 << 2)
 #define   AS_MEMATTR_AARCH64_INNER_ALLOC_EXPL(w, r)	((3 << 2) | \
 							 ((w) ? BIT(0) : 0) | \
@@ -28,8 +23,8 @@
 #define   AS_MEMATTR_AARCH64_INNER_OUTER_NC		(1 << 6)
 #define   AS_MEMATTR_AARCH64_INNER_OUTER_WB		(2 << 6)
 #define   AS_MEMATTR_AARCH64_FAULT			(3 << 6)
-#define AS_LOCKADDR(as)					(MMU_AS(as) + 0x10)
-#define AS_COMMAND(as)					(MMU_AS(as) + 0x18)
+#define AS_LOCKADDR					0x10
+#define AS_COMMAND					0x18
 #define   AS_COMMAND_NOP				0
 #define   AS_COMMAND_UPDATE				1
 #define   AS_COMMAND_LOCK				2
@@ -37,16 +32,16 @@
 #define   AS_COMMAND_FLUSH_PT				4
 #define   AS_COMMAND_FLUSH_MEM				5
 #define   AS_LOCK_REGION_MIN_SIZE			(1ULL << 15)
-#define AS_FAULTSTATUS(as)				(MMU_AS(as) + 0x1C)
+#define AS_FAULTSTATUS					0x1C
 #define  AS_FAULTSTATUS_ACCESS_TYPE_MASK		(0x3 << 8)
 #define  AS_FAULTSTATUS_ACCESS_TYPE_ATOMIC		(0x0 << 8)
 #define  AS_FAULTSTATUS_ACCESS_TYPE_EX			(0x1 << 8)
 #define  AS_FAULTSTATUS_ACCESS_TYPE_READ		(0x2 << 8)
 #define  AS_FAULTSTATUS_ACCESS_TYPE_WRITE		(0x3 << 8)
-#define AS_FAULTADDRESS(as)				(MMU_AS(as) + 0x20)
-#define AS_STATUS(as)					(MMU_AS(as) + 0x28)
+#define AS_FAULTADDRESS					0x20
+#define AS_STATUS					0x28
 #define   AS_STATUS_AS_ACTIVE				BIT(0)
-#define AS_TRANSCFG(as)					(MMU_AS(as) + 0x30)
+#define AS_TRANSCFG					0x30
 #define   AS_TRANSCFG_ADRMODE_UNMAPPED			(1 << 0)
 #define   AS_TRANSCFG_ADRMODE_IDENTITY			(2 << 0)
 #define   AS_TRANSCFG_ADRMODE_AARCH64_4K		(6 << 0)
@@ -64,6 +59,6 @@
 #define   AS_TRANSCFG_DISABLE_AF_FAULT			BIT(34)
 #define   AS_TRANSCFG_WXN				BIT(35)
 #define   AS_TRANSCFG_XREADABLE				BIT(36)
-#define AS_FAULTEXTRA(as)				(MMU_AS(as) + 0x38)
+#define AS_FAULTEXTRA					0x38
 
 #endif /* __PANTHOR_MMU_REGS_H__ */
-- 
2.43.0

[PATCH v1 07/27] dt-bindings: gpu: mali-valhall-csf: Add Mali Gen5 AM compatible

[Karunika Choo]

Add the generic "arm,mali-gen5-am" compatible for Mali Gen5 AM GPU
integrations.

Mali Gen5 AM systems use the external AM_GOVERNOR block for frequency
scaling, so OPP, cooling and local GPU supply properties are not valid
for this compatible.

Add a matching example node.

Signed-off-by: Karunika Choo <karunika.choo@arm.com>
---
 .../bindings/gpu/arm,mali-valhall-csf.yaml    | 26 ++++++++++++++++++-
 1 file changed, 25 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml
index 8eccd4338a2b2..a1e85570b4b3b 100644
--- a/Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml
+++ b/Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml
@@ -22,6 +22,7 @@ properties:
               - nxp,imx95-mali            # G310
               - rockchip,rk3588-mali
           - const: arm,mali-valhall-csf   # Mali Valhall GPU model/revision is fully discoverable
+      - const: arm,mali-gen5-am
 
   reg:
     maxItems: 1
@@ -146,6 +147,19 @@ allOf:
         - nvmem-cells
         - nvmem-cell-names
         - power-domains
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: arm,mali-gen5-am
+    then:
+      properties:
+        mali-supply: false
+        sram-supply: false
+        operating-points-v2: false
+        opp-table: false
+        "#cooling-cells": false
+        dynamic-power-coefficient: false
 
 examples:
   - |
@@ -195,5 +209,15 @@ examples:
         nvmem-cell-names = "shader-present";
         power-domains = <&gpufreq>;
     };
-
+  - |
+    gpu@100000 {
+        compatible = "arm,mali-gen5-am";
+        reg = <0x100000 0x480000>;
+        interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH 0>,
+                     <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH 0>,
+                     <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH 0>;
+        interrupt-names = "job", "mmu", "gpu";
+        clocks = <&gpu_clock 0>, <&gpu_clock 1>, <&gpu_clock 2>;
+        clock-names = "core", "coregroup", "stacks";
+    };
 ...
-- 
2.43.0

[PATCH v1 08/27] drm/panthor: Add Mali v15 hardware support

[Karunika Choo]

Add the panthor hardware description for Mali v15 GPUs and hook it into
device matching.

This includes the v15 register map and product identification needed to
populate the GPU information exposed by the driver and its uAPI.

Add compatibility string for v15 GPUs.

Signed-off-by: Karunika Choo <karunika.choo@arm.com>
---
v1:
- make COHERENCY_FEATURES register read use cached gpu_info values.
- Added Mali-G2 name variants and NX aware model identification.
- fix premature reading of l2_features gpu_info field during
  panthor_hw_info_init().
- build as_present using GENMASK.

 drivers/gpu/drm/panthor/panthor_drv.c         |  1 +
 drivers/gpu/drm/panthor/panthor_fw.c          |  1 +
 drivers/gpu/drm/panthor/panthor_gpu.c         |  3 +-
 .../drm/panthor/panthor_gpu_discover_regs.h   | 25 +++++
 drivers/gpu/drm/panthor/panthor_gpu_regs.h    |  1 +
 drivers/gpu/drm/panthor/panthor_heap.c        |  3 +-
 drivers/gpu/drm/panthor/panthor_hw.c          | 98 ++++++++++++++++++-
 drivers/gpu/drm/panthor/panthor_hw.h          | 13 +++
 include/uapi/drm/panthor_drm.h                | 10 +-
 9 files changed, 147 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/panthor/panthor_drv.c b/drivers/gpu/drm/panthor/panthor_drv.c
index 8cdba0c1a14b9..3fe9f96f7755e 100644
--- a/drivers/gpu/drm/panthor/panthor_drv.c
+++ b/drivers/gpu/drm/panthor/panthor_drv.c
@@ -1886,6 +1886,7 @@ static const struct of_device_id dt_match[] = {
 	{ .compatible = "mediatek,mt8196-mali", .data = &soc_data_mediatek_mt8196, },
 	{ .compatible = "rockchip,rk3588-mali" },
 	{ .compatible = "arm,mali-valhall-csf" },
+	{ .compatible = "arm,mali-gen5-am" },
 	{}
 };
 MODULE_DEVICE_TABLE(of, dt_match);
diff --git a/drivers/gpu/drm/panthor/panthor_fw.c b/drivers/gpu/drm/panthor/panthor_fw.c
index 679ea1d233d53..1449d9a66302e 100644
--- a/drivers/gpu/drm/panthor/panthor_fw.c
+++ b/drivers/gpu/drm/panthor/panthor_fw.c
@@ -1563,3 +1563,4 @@ MODULE_FIRMWARE("arm/mali/arch11.8/mali_csffw.bin");
 MODULE_FIRMWARE("arm/mali/arch12.8/mali_csffw.bin");
 MODULE_FIRMWARE("arm/mali/arch13.8/mali_csffw.bin");
 MODULE_FIRMWARE("arm/mali/arch14.8/mali_csffw.bin");
+MODULE_FIRMWARE("arm/mali/arch15.8/mali_csffw.bin");
diff --git a/drivers/gpu/drm/panthor/panthor_gpu.c b/drivers/gpu/drm/panthor/panthor_gpu.c
index d6534fabc682e..e6e970e9b59d3 100644
--- a/drivers/gpu/drm/panthor/panthor_gpu.c
+++ b/drivers/gpu/drm/panthor/panthor_gpu.c
@@ -499,8 +499,7 @@ int panthor_gpu_coherency_init(struct panthor_device *ptdev)
 	/* Check if the ACE-Lite coherency protocol is actually supported by the GPU.
 	 * ACE protocol has never been supported for command stream frontend GPUs.
 	 */
-	if ((gpu_read(ptdev->gpu->iomem, GPU_COHERENCY_FEATURES) &
-		      GPU_COHERENCY_PROT_BIT(ACE_LITE))) {
+	if ((ptdev->gpu_info.coherency_features & GPU_COHERENCY_PROT_BIT(ACE_LITE))) {
 		ptdev->gpu_info.selected_coherency = GPU_COHERENCY_ACE_LITE;
 		return 0;
 	}
diff --git a/drivers/gpu/drm/panthor/panthor_gpu_discover_regs.h b/drivers/gpu/drm/panthor/panthor_gpu_discover_regs.h
index e6bfe1fe2c68a..c4d0cb2fca92d 100644
--- a/drivers/gpu/drm/panthor/panthor_gpu_discover_regs.h
+++ b/drivers/gpu/drm/panthor/panthor_gpu_discover_regs.h
@@ -16,4 +16,29 @@
 #define   GPU_WIDE_VER_MINOR(x)				(((x) & GENMASK_U64(15, 8)) >> 8)
 #define   GPU_WIDE_VER_STATUS(x)			((x) & GENMASK_U64(7, 0))
 
+#define DISCOVER_REVIDR					0x8
+#define DISCOVER_GPU_FEATURES				0x20
+#define   GPU_FEATURES_VARIABLE_RATE_SHADING		BIT(0)
+#define   GPU_FEATURES_SIMD_STATE			BIT(1)
+#define   GPU_FEATURES_CROSS_STREAM_SYNC		BIT(3)
+#define   GPU_FEATURES_NX				BIT(4)
+#define   GPU_FEATURES_RAY_TRAVERSAL			BIT(5)
+#define   GPU_FEATURES_LD_LEA_TENSOR_INSTRUCTIONS	BIT(6)
+#define DISCOVER_MCU_FEATURES				0x40
+#define DISCOVER_PRFCNT_FEATURES			0x50
+#define   PRFCNT_FEATURES_COUNTER_BLOCK_SIZE(x)		(((x) & GENMASK(7, 0)) << 8)
+#define DISCOVER_DOORBELL_FEATURES			0x60
+#define DISCOVER_MEM_FEATURES				0x100
+#define DISCOVER_MMU_FEATURES				0x108
+#define   MMU_FEATURES_AS_COUNT(x)			(((x) & GENMASK(23, 16)) >> 16)
+#define DISCOVER_AMBA_FEATURES				0x120
+
+#define DISCOVER_L2_FEATURES				0x128
+#define DISCOVER_TILER_FEATURES				0x200
+#define DISCOVER_CORE_FEATURES				0x300
+#define DISCOVER_THREAD_FEATURES			0x320
+#define DISCOVER_THREAD_MAX_THREADS			0x330
+#define DISCOVER_THREAD_NUM_ACTIVE_GRANULARITY		0x334
+#define DISCOVER_TEXTURE_FEATURES			0x360
+
 #endif /* __PANTHOR_GPU_DISCOVER_REGS_H__ */
diff --git a/drivers/gpu/drm/panthor/panthor_gpu_regs.h b/drivers/gpu/drm/panthor/panthor_gpu_regs.h
index 753df87009901..60819c4ace428 100644
--- a/drivers/gpu/drm/panthor/panthor_gpu_regs.h
+++ b/drivers/gpu/drm/panthor/panthor_gpu_regs.h
@@ -65,6 +65,7 @@
 
 #define GPU_FEATURES					0x60
 #define   GPU_FEATURES_RAY_INTERSECTION			BIT(2)
+#define   GPU_FEATURES_NX				BIT(4)
 #define   GPU_FEATURES_RAY_TRAVERSAL			BIT(5)
 
 #define GPU_TIMESTAMP_OFFSET				0x88
diff --git a/drivers/gpu/drm/panthor/panthor_heap.c b/drivers/gpu/drm/panthor/panthor_heap.c
index 99311abdf1e91..afb7d68abc874 100644
--- a/drivers/gpu/drm/panthor/panthor_heap.c
+++ b/drivers/gpu/drm/panthor/panthor_heap.c
@@ -11,6 +11,7 @@
 #include "panthor_gem.h"
 #include "panthor_gpu_regs.h"
 #include "panthor_heap.h"
+#include "panthor_hw.h"
 #include "panthor_mmu.h"
 
 /*
@@ -105,7 +106,7 @@ struct panthor_heap_pool {
 
 static int panthor_heap_ctx_stride(struct panthor_device *ptdev)
 {
-	u32 l2_features = ptdev->gpu_info.l2_features;
+	u64 l2_features = panthor_hw_get_l2_features(ptdev);
 	u32 gpu_cache_line_size = GPU_L2_FEATURES_LINE_SIZE(l2_features);
 
 	return ALIGN(HEAP_CONTEXT_SIZE, gpu_cache_line_size);
diff --git a/drivers/gpu/drm/panthor/panthor_hw.c b/drivers/gpu/drm/panthor/panthor_hw.c
index 13090ff6db7b5..9d539f5f80158 100644
--- a/drivers/gpu/drm/panthor/panthor_hw.c
+++ b/drivers/gpu/drm/panthor/panthor_hw.c
@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0 or MIT
 /* Copyright 2025 ARM Limited. All rights reserved. */
 
+#include <linux/bits.h>
 #include <linux/nvmem-consumer.h>
 #include <linux/platform_device.h>
 
@@ -74,6 +75,29 @@ static struct panthor_hw panthor_hw_arch_v14 = {
 	},
 };
 
+static struct panthor_hw panthor_hw_arch_v15 = {
+	.ops = {
+		.soft_reset = panthor_pwr_reset_soft,
+		.l2_power_off = panthor_pwr_l2_power_off,
+		.l2_power_on = panthor_pwr_l2_power_on,
+	},
+	.regs = {
+		.gpu_control = {
+			.offset = 0x3000,
+		},
+		.mcu_control = {
+			.offset = 0x3100,
+		},
+		.pwr_control = {
+			.offset = 0x3800,
+		},
+		.mmu_as_control = {
+			.offset = 0x2800,
+			.stride = 0x80,
+		},
+	},
+};
+
 static struct panthor_hw_entry panthor_hw_match[] = {
 	{
 		.arch_min = 10,
@@ -85,6 +109,11 @@ static struct panthor_hw_entry panthor_hw_match[] = {
 		.arch_max = 14,
 		.hwdev = &panthor_hw_arch_v14,
 	},
+	{
+		.arch_min = 15,
+		.arch_max = 15,
+		.hwdev = &panthor_hw_arch_v15,
+	}
 };
 
 static int panthor_hw_set_power_tracing(struct device *dev, void *data)
@@ -152,8 +181,11 @@ static char *get_gpu_model_name(struct panthor_device *ptdev)
 						gpu_id->prod_major);
 	const bool ray_intersection = !!(ptdev->gpu_info.gpu_features &
 					 GPU_FEATURES_RAY_INTERSECTION);
+	const bool neural_present = !!(ptdev->gpu_info.gpu_features &
+				       GPU_FEATURES_NX);
 	const u8 shader_core_count = hweight64(ptdev->gpu_info.shader_present);
 
+
 	switch (product_id) {
 	case GPU_PROD_ID_MAKE(10, 2):
 		return "Mali-G710";
@@ -196,6 +228,18 @@ static char *get_gpu_model_name(struct panthor_device *ptdev)
 		return "Mali-G1-Premium";
 	case GPU_PROD_ID_MAKE(14, 3):
 		return "Mali-G1-Pro";
+	case GPU_PROD_ID_MAKE(15, 0):
+		return "Mali-G2-Ultra-NX";
+	case GPU_PROD_ID_MAKE(15, 1):
+		if (neural_present)
+			return "Mali-G2-Premium-NX";
+
+		return "Mali-G2-Premium";
+	case GPU_PROD_ID_MAKE(15, 3):
+		if (neural_present)
+			return "Mali-G2-Pro-NX";
+
+		return "Mali-G2-Pro";
 	}
 
 	return "(Unknown Mali GPU)";
@@ -219,7 +263,7 @@ static int overload_shader_present(struct panthor_device *ptdev)
 	return 0;
 }
 
-static int panthor_gpu_info_init(struct panthor_device *ptdev)
+static void panthor_gpu_info_v10_init(struct panthor_device *ptdev)
 {
 	unsigned int i;
 
@@ -260,12 +304,55 @@ static int panthor_gpu_info_init(struct panthor_device *ptdev)
 		ptdev->gpu_info.tiler_present = gpu_read64(gpu_iomem, GPU_TILER_PRESENT);
 		ptdev->gpu_info.l2_present = gpu_read64(gpu_iomem, GPU_L2_PRESENT);
 	}
+}
+
+static void panthor_gpu_info_v15_init(struct panthor_device *ptdev)
+{
+	void __iomem *pwr_iomem = ptdev->iomem + ptdev->hw->regs.pwr_control.offset;
+	u64 texture_features;
+
+	ptdev->gpu_info.gpu_rev_wide = gpu_read64(ptdev->iomem, DISCOVER_REVIDR);
+	ptdev->gpu_info.l2_features_wide = gpu_read64(ptdev->iomem, DISCOVER_L2_FEATURES);
+
+	texture_features = gpu_read64(ptdev->iomem, DISCOVER_TEXTURE_FEATURES);
+	ptdev->gpu_info.texture_features[0] = lower_32_bits(texture_features);
+	ptdev->gpu_info.texture_features[1] = upper_32_bits(texture_features);
+
+	ptdev->gpu_info.thread_features = gpu_read(ptdev->iomem, DISCOVER_THREAD_FEATURES);
+	ptdev->gpu_info.max_threads = gpu_read(ptdev->iomem, DISCOVER_THREAD_MAX_THREADS);
+	ptdev->gpu_info.thread_num_active_granularity =
+		gpu_read(ptdev->iomem, DISCOVER_THREAD_NUM_ACTIVE_GRANULARITY);
+
+	/* The upper 32-bits of following registers do not contain any information (yet) */
+	ptdev->gpu_info.gpu_features = gpu_read64(ptdev->iomem, DISCOVER_GPU_FEATURES);
+	ptdev->gpu_info.mem_features = gpu_read(ptdev->iomem, DISCOVER_MEM_FEATURES);
+	ptdev->gpu_info.mmu_features = gpu_read(ptdev->iomem, DISCOVER_MMU_FEATURES);
+	ptdev->gpu_info.coherency_features = gpu_read(ptdev->iomem, DISCOVER_AMBA_FEATURES);
+	ptdev->gpu_info.tiler_features = gpu_read(ptdev->iomem, DISCOVER_TILER_FEATURES);
+	ptdev->gpu_info.core_features = gpu_read(ptdev->iomem, DISCOVER_CORE_FEATURES);
+
+	/* AS_PRESENT register removed on v15+ create virtual mask from MMU_FEATURES.AS_COUNT */
+	ptdev->gpu_info.as_present = GENMASK(
+		MMU_FEATURES_AS_COUNT(ptdev->gpu_info.mmu_features) - 1, 0);
+
+	ptdev->gpu_info.l2_present = gpu_read64(pwr_iomem, PWR_L2_PRESENT);
+	ptdev->gpu_info.tiler_present = gpu_read64(pwr_iomem, PWR_TILER_PRESENT);
+	ptdev->gpu_info.shader_present = gpu_read64(pwr_iomem, PWR_SHADER_PRESENT);
+}
+
+static int panthor_gpu_info_init(struct panthor_device *ptdev)
+{
+	if (panthor_hw_has_gpu_discover(ptdev))
+		panthor_gpu_info_v15_init(ptdev);
+	else
+		panthor_gpu_info_v10_init(ptdev);
 
 	return overload_shader_present(ptdev);
 }
 
 static int panthor_hw_info_init(struct panthor_device *ptdev)
 {
+	u64 l2_features;
 	u32 major, minor, status;
 	int ret;
 
@@ -273,18 +360,23 @@ static int panthor_hw_info_init(struct panthor_device *ptdev)
 	if (ret)
 		return ret;
 
+	l2_features = ptdev->gpu_info.l2_features;
+
 	major = ptdev->gpu_id.ver_major;
 	minor = ptdev->gpu_id.ver_minor;
 	status = ptdev->gpu_id.ver_status;
 
+	if (panthor_hw_has_gpu_discover(ptdev))
+		l2_features = ptdev->gpu_info.l2_features_wide;
+
 	drm_info(&ptdev->base,
 		 "%s id 0x%x major 0x%x minor 0x%x status 0x%x",
 		 get_gpu_model_name(ptdev), ptdev->gpu_id.prod_major,
 		 major, minor, status);
 
 	drm_info(&ptdev->base,
-		 "Features: L2:%#x Tiler:%#x Mem:%#x MMU:%#x AS:%#x",
-		 ptdev->gpu_info.l2_features,
+		 "Features: L2:%#llx Tiler:%#x Mem:%#x MMU:%#x AS:%#x",
+		 l2_features,
 		 ptdev->gpu_info.tiler_features,
 		 ptdev->gpu_info.mem_features,
 		 ptdev->gpu_info.mmu_features,
diff --git a/drivers/gpu/drm/panthor/panthor_hw.h b/drivers/gpu/drm/panthor/panthor_hw.h
index 68627f0df7f95..48232254fef97 100644
--- a/drivers/gpu/drm/panthor/panthor_hw.h
+++ b/drivers/gpu/drm/panthor/panthor_hw.h
@@ -88,4 +88,17 @@ static inline bool panthor_hw_has_pwr_ctrl(struct panthor_device *ptdev)
 	return ptdev->gpu_id.arch_major >= 14;
 }
 
+static inline bool panthor_hw_has_gpu_discover(struct panthor_device *ptdev)
+{
+	return ptdev->gpu_id.arch_major >= 15;
+}
+
+static inline u64 panthor_hw_get_l2_features(struct panthor_device *ptdev)
+{
+	if (panthor_hw_has_gpu_discover(ptdev))
+		return ptdev->gpu_info.l2_features_wide;
+
+	return ptdev->gpu_info.l2_features;
+}
+
 #endif /* __PANTHOR_HW_H__ */
diff --git a/include/uapi/drm/panthor_drm.h b/include/uapi/drm/panthor_drm.h
index 843a0b40e1d36..5c75dda5f0ae7 100644
--- a/include/uapi/drm/panthor_drm.h
+++ b/include/uapi/drm/panthor_drm.h
@@ -371,8 +371,8 @@ struct drm_panthor_gpu_info {
 	/** @core_features: Used to discriminate core variants when they exist. */
 	__u32 core_features;
 
-	/** @pad: MBZ. */
-	__u32 pad;
+	/** @thread_num_active_granularity: Granularity of number of active threads */
+	__u32 thread_num_active_granularity;
 
 	/** @gpu_features: Bitmask describing supported GPU-wide features */
 	__u64 gpu_features;
@@ -389,6 +389,12 @@ struct drm_panthor_gpu_info {
 #define DRM_PANTHOR_WIDE_VERSION_MAJOR(x)	(((x) >> 16) & 0xff)
 #define DRM_PANTHOR_WIDE_VERSION_MINOR(x)	(((x) >> 8) & 0xff)
 #define DRM_PANTHOR_WIDE_VERSION_STATUS(x)	((x) & 0xff)
+
+	/** @gpu_rev_wide: 64-bit GPU revision for v15 onwards */
+	__u64 gpu_rev_wide;
+
+	/** @l2_features_wide: 64-bit L2_FEATURES for v15 onwards */
+	__u64 l2_features_wide;
 };
 
 /**
-- 
2.43.0

[PATCH v1 09/27] drm/panthor: Skip devfreq when no OPP table is present

[Karunika Choo]

On Mali v15 AM systems, frequency scaling is handled outside panthor by
the AM_GOVERNOR block, so the GPU DT node may not provide an OPP table.

Make panthor_devfreq_init() return early when dev_pm_opp_get_opp_table()
returns -ENODEV, and guard the devfreq helper paths against a missing
devfreq instance. Also make it so that frequency can be queried even if
the devfreq instance is missing.

This keeps devfreq enabled for existing platforms while allowing v15 AM
systems to probe without a local devfreq setup.

Signed-off-by: Karunika Choo <karunika.choo@arm.com>
---
v1:
- Only skip panthor_devfreq init when OPP lookup returns -ENODEV instead
  of direct DT-property check.
- Support frequency query without devfreq.

 drivers/gpu/drm/panthor/panthor_devfreq.c | 31 ++++++++++++++++++-----
 drivers/gpu/drm/panthor/panthor_hw.h      |  6 +++++
 2 files changed, 30 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/panthor/panthor_devfreq.c b/drivers/gpu/drm/panthor/panthor_devfreq.c
index 2249b41ca4afe..18c1a7e56ca08 100644
--- a/drivers/gpu/drm/panthor/panthor_devfreq.c
+++ b/drivers/gpu/drm/panthor/panthor_devfreq.c
@@ -12,6 +12,7 @@
 
 #include "panthor_devfreq.h"
 #include "panthor_device.h"
+#include "panthor_hw.h"
 
 /**
  * struct panthor_devfreq - Device frequency management
@@ -164,6 +165,19 @@ int panthor_devfreq_init(struct panthor_device *ptdev)
 	 */
 	table = dev_pm_opp_get_opp_table(dev);
 	if (IS_ERR_OR_NULL(table)) {
+		/*
+		 * On v15 GPUs, frequency scaling is handled outside of panthor
+		 * by the AM_GOVERNOR block, so the GPU DT node may not provide
+		 * an OPP table. In such cases, do not initialize devfreq for
+		 * panthor.
+		 */
+		if (panthor_hw_is_gen5_am(ptdev->base.dev) &&
+		    PTR_ERR(table) == -ENODEV) {
+			drmm_kfree(&ptdev->base, pdevfreq);
+			ptdev->devfreq = NULL;
+			return 0;
+		}
+
 		ret = devm_pm_opp_set_regulators(dev, reg_names);
 		if (ret && ret != -ENODEV) {
 			if (ret != -EPROBE_DEFER)
@@ -267,7 +281,7 @@ void panthor_devfreq_resume(struct panthor_device *ptdev)
 {
 	struct panthor_devfreq *pdevfreq = ptdev->devfreq;
 
-	if (!pdevfreq->devfreq)
+	if (!pdevfreq || !pdevfreq->devfreq)
 		return;
 
 	panthor_devfreq_reset(pdevfreq);
@@ -279,7 +293,7 @@ void panthor_devfreq_suspend(struct panthor_device *ptdev)
 {
 	struct panthor_devfreq *pdevfreq = ptdev->devfreq;
 
-	if (!pdevfreq->devfreq)
+	if (!pdevfreq || !pdevfreq->devfreq)
 		return;
 
 	drm_WARN_ON(&ptdev->base, devfreq_suspend_device(pdevfreq->devfreq));
@@ -290,7 +304,7 @@ void panthor_devfreq_record_busy(struct panthor_device *ptdev)
 	struct panthor_devfreq *pdevfreq = ptdev->devfreq;
 	unsigned long irqflags;
 
-	if (!pdevfreq->devfreq)
+	if (!pdevfreq || !pdevfreq->devfreq)
 		return;
 
 	spin_lock_irqsave(&pdevfreq->lock, irqflags);
@@ -306,7 +320,7 @@ void panthor_devfreq_record_idle(struct panthor_device *ptdev)
 	struct panthor_devfreq *pdevfreq = ptdev->devfreq;
 	unsigned long irqflags;
 
-	if (!pdevfreq->devfreq)
+	if (!pdevfreq || !pdevfreq->devfreq)
 		return;
 
 	spin_lock_irqsave(&pdevfreq->lock, irqflags);
@@ -319,14 +333,17 @@ void panthor_devfreq_record_idle(struct panthor_device *ptdev)
 
 unsigned long panthor_devfreq_get_freq(struct panthor_device *ptdev)
 {
+	int (*get_cur_freq)(struct device *dev, unsigned long *freq);
 	struct panthor_devfreq *pdevfreq = ptdev->devfreq;
 	unsigned long freq = 0;
 	int ret;
 
-	if (!pdevfreq->devfreq)
-		return 0;
+	if (!pdevfreq || !pdevfreq->devfreq)
+		get_cur_freq = panthor_devfreq_get_cur_freq;
+	else
+		get_cur_freq = pdevfreq->devfreq->profile->get_cur_freq;
 
-	ret = pdevfreq->devfreq->profile->get_cur_freq(ptdev->base.dev, &freq);
+	ret = get_cur_freq(ptdev->base.dev, &freq);
 	if (ret)
 		return 0;
 
diff --git a/drivers/gpu/drm/panthor/panthor_hw.h b/drivers/gpu/drm/panthor/panthor_hw.h
index 48232254fef97..e5bcb908068cb 100644
--- a/drivers/gpu/drm/panthor/panthor_hw.h
+++ b/drivers/gpu/drm/panthor/panthor_hw.h
@@ -101,4 +101,10 @@ static inline u64 panthor_hw_get_l2_features(struct panthor_device *ptdev)
 	return ptdev->gpu_info.l2_features;
 }
 
+static inline bool panthor_hw_is_gen5_am(struct device *dev)
+{
+	return device_property_match_string(dev, "compatible",
+					    "arm,mali-gen5-am") >= 0;
+}
+
 #endif /* __PANTHOR_HW_H__ */
-- 
2.43.0

[PATCH v1 10/27] dt-bindings: gpu: panthor: Document panthor-system bindings

[Karunika Choo]

Mali 5th-Gen AM GPUs expose an AM_SYSTEM block for GPU-wide control
outside the main GPU register window.

Document the system node compatible, register and interrupt resources,
GPU clock, and optional GPU regulator supply used by the AM_SYSTEM
platform driver.

Signed-off-by: Karunika Choo <karunika.choo@arm.com>
---
 .../bindings/gpu/arm,mali-gen5-am-system.yaml | 67 +++++++++++++++++++
 MAINTAINERS                                   |  1 +
 2 files changed, 68 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/gpu/arm,mali-gen5-am-system.yaml

diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-gen5-am-system.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-gen5-am-system.yaml
new file mode 100644
index 0000000000000..f0689bb8f05a2
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpu/arm,mali-gen5-am-system.yaml
@@ -0,0 +1,67 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+# Copyright 2026 ARM Limited. All rights reserved.
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/gpu/arm,mali-gen5-am-system.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ARM Mali 5th-Gen GPU System Device
+
+maintainers:
+  - Liviu Dudau <liviu.dudau@arm.com>
+  - Boris Brezillon <boris.brezillon@collabora.com>
+
+properties:
+  $nodename:
+    pattern: '^panthor-system@[a-f0-9]+$'
+
+  compatible:
+    oneOf:
+      - items:
+          - const: arm,mali-gen5-am-system
+
+  reg:
+    items:
+      - description: System register
+
+  reg-names:
+    items:
+      - const: system
+
+  interrupts:
+    items:
+      - description: System interrupt
+
+  clocks:
+    maxItems: 1
+    description:
+      Phandle to the GPU clock.
+
+  gpu-supply: true
+
+  dma-coherent: true
+
+required:
+  - compatible
+  - reg
+  - reg-names
+  - interrupts
+  - clocks
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/irq.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+    panthor_system: panthor-system@68000000 {
+      compatible = "arm,mali-gen5-am-system";
+      reg = <0x68000000 0x10000>;
+      reg-names = "system";
+      interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
+      clocks = <&mali_gpu_clk>;
+      gpu-supply = <&gpu_supply>;
+    };
+
+...
diff --git a/MAINTAINERS b/MAINTAINERS
index 40fdb0ecc9c12..377156650580c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2324,6 +2324,7 @@ M:	Liviu Dudau <liviu.dudau@arm.com>
 L:	dri-devel@lists.freedesktop.org
 S:	Supported
 T:	git https://gitlab.freedesktop.org/drm/misc/kernel.git
+F:	Documentation/devicetree/bindings/gpu/arm,mali-gen5-am-*.yaml
 F:	Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml
 F:	drivers/gpu/drm/ci/xfails/panthor*
 F:	drivers/gpu/drm/panthor/
-- 
2.43.0

[PATCH v1 11/27] drm/panthor: Add AM_SYSTEM platform driver

[Karunika Choo]

Mali v15 AM systems expose an AM_SYSTEM block for GPU-wide control.

Add a small AM_SYSTEM platform driver, wire it into Kconfig and the
panthor build, and use it to manage the GPU clock and regulator
resources. The driver also performs the initial GPU reset sequence
during probe.

Signed-off-by: Karunika Choo <karunika.choo@arm.com>
---
v1:
- Renames panthor_system.c to panthor_system_drv.c to facilitate adding
  another source file for v15-AE support.
- Explicitly obtain named "system" IOMEM resource.
- Explicitly use "gpu-supply" regulator instead of inferring it from the
  "clock-names" DT property.
- Populate/depopulate child devices.
- Clear stale RESET_COMPLETED interrupts before reset.

 drivers/gpu/drm/panthor/Kconfig               |  10 +
 drivers/gpu/drm/panthor/Makefile              |   1 +
 drivers/gpu/drm/panthor/system/Makefile       |  13 +
 .../drm/panthor/system/panthor_system_drv.c   | 304 ++++++++++++++++++
 4 files changed, 328 insertions(+)
 create mode 100644 drivers/gpu/drm/panthor/system/Makefile
 create mode 100644 drivers/gpu/drm/panthor/system/panthor_system_drv.c

diff --git a/drivers/gpu/drm/panthor/Kconfig b/drivers/gpu/drm/panthor/Kconfig
index 911e7f4810c39..e17c93035e8b7 100644
--- a/drivers/gpu/drm/panthor/Kconfig
+++ b/drivers/gpu/drm/panthor/Kconfig
@@ -20,3 +20,13 @@ config DRM_PANTHOR
 
 	  Note that the Mali-G68 and Mali-G78, while Valhall architecture, will
 	  be supported with the panfrost driver as they are not CSF GPUs.
+
+config DRM_PANTHOR_SYSTEM
+	tristate "GPU-wide configuration for Arm Mali 5th Gen AM GPUs"
+	depends on DRM_PANTHOR
+	depends on OF
+	help
+	  Enable support for the AM_SYSTEM block found on Arm Mali 5th Gen
+	  AM GPUs. This block provides GPU-wide control outside the main GPU
+	  register window, including reset handling and management of shared
+	  clock and regulator resources.
diff --git a/drivers/gpu/drm/panthor/Makefile b/drivers/gpu/drm/panthor/Makefile
index dd15d52a88bac..488a5e03efbc4 100644
--- a/drivers/gpu/drm/panthor/Makefile
+++ b/drivers/gpu/drm/panthor/Makefile
@@ -14,5 +14,6 @@ panthor-y := \
 	panthor_sched.o
 
 obj-$(CONFIG_DRM_PANTHOR) += panthor.o
+obj-$(CONFIG_DRM_PANTHOR_SYSTEM) += system/
 
 CFLAGS_panthor_gpu.o := -I$(src)
diff --git a/drivers/gpu/drm/panthor/system/Makefile b/drivers/gpu/drm/panthor/system/Makefile
new file mode 100644
index 0000000000000..018b569655b67
--- /dev/null
+++ b/drivers/gpu/drm/panthor/system/Makefile
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0 OR MIT
+# Copyright 2026 ARM Limited. All rights reserved.
+
+obj-$(CONFIG_DRM_PANTHOR_SYSTEM) += panthor_system.o
+
+panthor_system-y := \
+	panthor_system_drv.o
+
+INCLUDES = \
+	-I$(src)/..
+
+ccflags-y += $(INCLUDES)
+subdir-ccflags-y += $(INCLUDES)
diff --git a/drivers/gpu/drm/panthor/system/panthor_system_drv.c b/drivers/gpu/drm/panthor/system/panthor_system_drv.c
new file mode 100644
index 0000000000000..1f25c7bad49b5
--- /dev/null
+++ b/drivers/gpu/drm/panthor/system/panthor_system_drv.c
@@ -0,0 +1,304 @@
+// SPDX-License-Identifier: GPL-2.0 or MIT
+/* Copyright 2026 ARM Limited. All rights reserved. */
+
+#include <linux/clk.h>
+#include <linux/iopoll.h>
+#include <linux/module.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/regulator/consumer.h>
+#include <linux/types.h>
+
+#include "panthor_device_io.h"
+
+#define AM_SYS_IRQ_RAWSTAT			0x40
+#define AM_SYS_IRQ_CLEAR			0x4C
+#define AM_SYS_IRQ_MASK				0x58
+#define AM_SYS_IRQ_STATUS			0x70
+#define   AM_SYS_IRQ_RESET_COMPLETED		BIT(1)
+#define   AM_SYS_IRQ_INVALID_COMMAND		BIT(2)
+#define   AM_SYS_IRQ_INVALID_ACCESS_MASK	GENMASK(31, 16)
+#define   AM_SYS_IRQ_INVALID_ACCESS(x)		FIELD_GET(AM_SYS_IRQ_INVALID_ACCESS_MASK, x)
+
+#define AM_SYS_STATUS				0xC0
+#define AM_SYS_COMMAND				0xC4
+#define   AM_SYS_CMD_INDEX(x)			FIELD_PREP(GENMASK(11, 8), x)
+#define   AM_SYS_CMD_SOFT_RESET			0x10
+#define   AM_SYS_CMD_HARD_RESET			0x11
+#define   AM_SYS_CMD_AW_RESET			0x12
+
+#define AM_SYS_RESET_SLEEP_US			10
+#define AM_RESET_TIMEOUT_US			(20 * USEC_PER_MSEC)
+
+/**
+ * struct panthor_system - System device
+ */
+struct panthor_system {
+	/** @dev: Device pointer */
+	struct device *dev;
+
+	/** @iomem: CPU mapping of the AM_SYSTEM IOMEM region */
+	void __iomem *iomem;
+
+	/** @regulator: Pointer to device regulator */
+	struct regulator *regulator;
+
+	/** @clk: Pointer to device clk */
+	struct clk *clk;
+};
+
+static int panthor_system_regulator_init(struct panthor_system *sdev)
+{
+	struct regulator *regulator = NULL;
+	int ret;
+
+	regulator = devm_regulator_get_optional(sdev->dev, "gpu");
+	if (IS_ERR(regulator)) {
+		ret = PTR_ERR(regulator);
+
+		/* Regulator not found. Exit */
+		if (ret == -ENODEV)
+			return 0;
+
+		return dev_err_probe(sdev->dev, ret, "Failed to get gpu-supply");
+	}
+
+	sdev->regulator = regulator;
+
+	return 0;
+}
+
+static int panthor_system_regulator_resume(struct panthor_system *sdev)
+{
+	int ret;
+
+	if (!sdev->regulator)
+		return 0;
+
+	ret = regulator_enable(sdev->regulator);
+	if (ret) {
+		dev_err(sdev->dev, "Failed to enable regulator");
+		return ret;
+	}
+
+	return 0;
+}
+
+static int panthor_system_regulator_suspend(struct panthor_system *sdev)
+{
+	int ret;
+
+	if (!sdev->regulator)
+		return 0;
+
+	ret = regulator_disable(sdev->regulator);
+	if (ret) {
+		dev_err(sdev->dev, "Failed to disable regulator");
+		return ret;
+	}
+
+	return 0;
+}
+
+static int panthor_system_clk_init(struct panthor_system *sdev)
+{
+	struct clk *clk = NULL;
+
+	clk = devm_clk_get(sdev->dev, NULL);
+	if (IS_ERR(clk))
+		return dev_err_probe(sdev->dev, PTR_ERR(clk),
+				     "Failed to get clk");
+
+	sdev->clk = clk;
+
+	return 0;
+}
+
+static int panthor_system_clk_resume(struct panthor_system *sdev)
+{
+	int ret;
+
+	ret = clk_prepare_enable(sdev->clk);
+	if (ret) {
+		dev_err(sdev->dev, "Failed to enable clk: %d", ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+static void panthor_system_clk_suspend(struct panthor_system *sdev)
+{
+	clk_disable_unprepare(sdev->clk);
+}
+
+static int __panthor_system_reset(struct panthor_system *sdev, u32 cmd)
+{
+	u64 val;
+
+	/* Clear stale RESET_COMPLETED IRQs before issuing reset */
+	gpu_write64(sdev->iomem, AM_SYS_IRQ_CLEAR, AM_SYS_IRQ_RESET_COMPLETED);
+
+	gpu_write(sdev->iomem, AM_SYS_COMMAND, cmd);
+
+	return read_poll_timeout(gpu_read64, val,
+				 (val & AM_SYS_IRQ_RESET_COMPLETED),
+				 AM_SYS_RESET_SLEEP_US, AM_RESET_TIMEOUT_US, false,
+				 sdev->iomem, AM_SYS_IRQ_RAWSTAT);
+}
+
+static int panthor_system_reset(struct panthor_system *sdev)
+{
+	int ret;
+
+	ret = __panthor_system_reset(sdev, AM_SYS_CMD_SOFT_RESET);
+	if (ret) {
+		dev_err(sdev->dev, "SOFT_RESET failed, attempting HARD_RESET");
+
+		ret = __panthor_system_reset(sdev, AM_SYS_CMD_HARD_RESET);
+		if (ret) {
+			dev_err(sdev->dev, "HARD_RESET failed");
+			return -EIO;
+		}
+	}
+
+	gpu_write64(sdev->iomem, AM_SYS_IRQ_CLEAR, AM_SYS_IRQ_RESET_COMPLETED);
+
+	return 0;
+}
+
+static int panthor_system_suspend(struct device *dev)
+{
+	struct panthor_system *sdev = dev_get_drvdata(dev);
+
+	panthor_system_clk_suspend(sdev);
+	return panthor_system_regulator_suspend(sdev);
+}
+
+static int panthor_system_resume(struct device *dev)
+{
+	struct panthor_system *sdev = dev_get_drvdata(dev);
+	int ret;
+
+	ret = panthor_system_regulator_resume(sdev);
+	if (ret)
+		return ret;
+
+	ret = panthor_system_clk_resume(sdev);
+	if (ret)
+		goto err_regulator_suspend;
+
+	return 0;
+
+err_regulator_suspend:
+	panthor_system_regulator_suspend(sdev);
+
+	return ret;
+}
+
+static int panthor_system_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct panthor_system *sdev;
+	void __iomem *iomem;
+	int ret;
+
+	sdev = devm_kzalloc(dev, sizeof(*sdev), GFP_KERNEL);
+	if (!sdev)
+		return -ENOMEM;
+
+	iomem = devm_platform_ioremap_resource_byname(pdev, "system");
+	if (IS_ERR(iomem)) {
+		return dev_err_probe(dev, PTR_ERR(iomem), "Failed to ioremap \"system\"");
+	}
+
+	sdev->dev = dev;
+	sdev->iomem = iomem;
+
+	ret = panthor_system_regulator_init(sdev);
+	if (ret)
+		return ret;
+
+	ret = panthor_system_clk_init(sdev);
+	if (ret)
+		return ret;
+
+	dev_set_drvdata(dev, sdev);
+
+	ret = devm_pm_runtime_enable(dev);
+	if (ret)
+		return dev_err_probe(dev, ret, "Failed to enable runtime PM");
+
+	ret = pm_runtime_resume_and_get(dev);
+	if (ret)
+		return dev_err_probe(dev, ret, "Failed to resume device");
+
+	ret = panthor_system_reset(sdev);
+	if (ret) {
+		dev_err(dev, "Failed to reset GPU");
+		goto err_rpm_put;
+	}
+
+	/* Probe any child devices */
+	ret = of_platform_populate(dev->of_node, NULL, NULL, dev);
+	if (ret)
+		goto err_depopulate;
+
+	pm_runtime_put_sync_suspend(dev);
+	return 0;
+
+err_depopulate:
+	of_platform_depopulate(dev);
+err_rpm_put:
+	pm_runtime_put_sync_suspend(dev);
+
+	return ret;
+}
+
+static void panthor_system_remove(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	int ret;
+
+	ret = pm_runtime_resume_and_get(dev);
+	if (ret < 0)
+		dev_warn(dev, "failed to resume during remove: %d", ret);
+
+	of_platform_depopulate(dev);
+
+	if (ret >= 0)
+		pm_runtime_put_sync_suspend(dev);
+	else
+		pm_runtime_set_suspended(dev);
+}
+
+static const struct dev_pm_ops panthor_system_pm_ops = {
+	.suspend = pm_runtime_force_suspend,
+	.resume = pm_runtime_force_resume,
+	.runtime_suspend = panthor_system_suspend,
+	.runtime_resume = panthor_system_resume,
+};
+
+static const struct of_device_id panthor_system_dt_match[] = {
+	{ .compatible = "arm,mali-gen5-am-system" },
+	{}
+};
+
+static struct platform_driver panthor_system_driver = {
+	.probe = panthor_system_probe,
+	.remove = panthor_system_remove,
+	.driver = {
+		.name = "panthor_system",
+		.pm = pm_ptr(&panthor_system_pm_ops),
+		.of_match_table = panthor_system_dt_match,
+	},
+};
+
+module_platform_driver(panthor_system_driver);
+
+MODULE_AUTHOR("ARM Ltd.");
+MODULE_DESCRIPTION("GPU system driver for AM GPUs");
+MODULE_LICENSE("Dual MIT/GPL");
-- 
2.43.0

[PATCH v1 12/27] dt-bindings: gpu: panthor: Document panthor-arbitration bindings

[Karunika Choo]

Mali 5th-Gen AM GPUs expose arbitration registers outside the GPU node.
The arbitration device contains partition-control and resource-group
register blocks used to grant, yield, and close access windows.

Document partition and resource-group child nodes, each with its own
register range, interrupt and hardware ID.

Signed-off-by: Karunika Choo <karunika.choo@arm.com>
---
 .../gpu/arm,mali-gen5-am-arbitration.yaml     | 125 ++++++++++++++++++
 .../bindings/gpu/arm,mali-gen5-am-system.yaml |   9 ++
 2 files changed, 134 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/gpu/arm,mali-gen5-am-arbitration.yaml

diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-gen5-am-arbitration.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-gen5-am-arbitration.yaml
new file mode 100644
index 0000000000000..9ea2b4bb9a344
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpu/arm,mali-gen5-am-arbitration.yaml
@@ -0,0 +1,125 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+# Copyright 2026 ARM Limited. All rights reserved.
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/gpu/arm,mali-gen5-am-arbitration.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ARM Mali 5th-Gen GPU Arbitration Device
+
+maintainers:
+  - Liviu Dudau <liviu.dudau@arm.com>
+  - Boris Brezillon <boris.brezillon@collabora.com>
+
+description:
+  The arbitration device manages partition-control and resource-group blocks.
+  Each block is described by a child node with its own register range,
+  interrupt and hardware ID. Partition and resource-group IDs are separate
+  namespaces. Access-window IDs are global to the GPU.
+
+properties:
+  $nodename:
+    const: panthor-arbitration
+
+  compatible:
+    const: arm,mali-gen5-am-arbitration
+
+  "#address-cells": true
+
+  "#size-cells": true
+
+  ranges: true
+
+patternProperties:
+  "^partition@[0-9a-f]+$":
+    type: object
+    additionalProperties: false
+    description:
+      Partition control block and its initial resource assignments.
+
+    properties:
+      reg:
+        maxItems: 1
+        description: Partition control register range.
+
+      interrupts:
+        maxItems: 1
+        description: Partition control interrupt.
+
+      arm,id:
+        $ref: /schemas/types.yaml#/definitions/uint32
+        description:
+          Hardware partition control index. Must identify a partition present on
+          the GPU and be unique among this device's partition nodes.
+
+    required:
+      - reg
+      - interrupts
+      - arm,id
+
+  "^resource-group@[0-9a-f]+$":
+    type: object
+    additionalProperties: false
+    description:
+      Resource group block used for access-window messaging.
+
+    properties:
+      reg:
+        maxItems: 1
+        description: Resource group register range.
+
+      interrupts:
+        maxItems: 1
+        description: Resource group interrupt.
+
+      arm,id:
+        $ref: /schemas/types.yaml#/definitions/uint32
+        description:
+          Hardware resource group index. Must identify a resource group
+          present on the GPU and be unique among this device's resource group
+          nodes.
+
+    required:
+      - reg
+      - interrupts
+      - arm,id
+
+  "^gpu@[0-9a-f]+$":
+    $ref: arm,mali-valhall-csf.yaml#
+    properties:
+      compatible:
+        const: arm,mali-gen5-am
+
+required:
+  - compatible
+  - "#address-cells"
+  - "#size-cells"
+  - ranges
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/irq.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+    panthor-arbitration {
+        compatible = "arm,mali-gen5-am-arbitration";
+        #address-cells = <1>;
+        #size-cells = <1>;
+        ranges;
+
+        partition@50000 {
+            reg = <0x50000 0x10000>;
+            interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH 0>;
+            arm,id = <0>;
+        };
+
+        resource-group@c0000 {
+            reg = <0xc0000 0x10000>;
+            interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH 0>;
+            arm,id = <0>;
+        };
+    };
+
+...
diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-gen5-am-system.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-gen5-am-system.yaml
index f0689bb8f05a2..a027dc5f4f890 100644
--- a/Documentation/devicetree/bindings/gpu/arm,mali-gen5-am-system.yaml
+++ b/Documentation/devicetree/bindings/gpu/arm,mali-gen5-am-system.yaml
@@ -41,6 +41,15 @@ properties:
 
   dma-coherent: true
 
+  "#address-cells": true
+
+  "#size-cells": true
+
+  ranges: true
+
+  panthor-arbitration:
+    $ref: arm,mali-gen5-am-arbitration.yaml#
+
 required:
   - compatible
   - reg
-- 
2.43.0

[PATCH v1 13/27] drm/panthor: Add AM_PARTITION_CONTROL support

[Karunika Choo]

Mali v15 AM GPUs expose AM_PARTITION_CONTROL blocks to manage partition
access windows.

Add a panthor arbitration platform driver and wire it into Kconfig and
the panthor build. The driver maps partition-control registers and
interrupts described by DT child nodes. It also provides helpers to
open, close, and yield partition access windows.

Signed-off-by: Karunika Choo <karunika.choo@arm.com>
---
v1:
- Updated DT structure and accompanying parsing to handle child nodes
  instead of named platform resources.
- Add child device population/depopulation.
- Remove blocking waits on partition open, close and yield operations.
- Adds YIELD_IDLE helper.

 drivers/gpu/drm/panthor/Kconfig               |  10 +
 drivers/gpu/drm/panthor/Makefile              |   1 +
 drivers/gpu/drm/panthor/arbitration/Makefile  |  13 +
 .../panthor/arbitration/panthor_arbitration.h |  40 +++
 .../arbitration/panthor_arbitration_drv.c     | 174 +++++++++
 .../arbitration/panthor_partition_control.c   | 333 ++++++++++++++++++
 .../arbitration/panthor_partition_control.h   |  29 ++
 7 files changed, 600 insertions(+)
 create mode 100644 drivers/gpu/drm/panthor/arbitration/Makefile
 create mode 100644 drivers/gpu/drm/panthor/arbitration/panthor_arbitration.h
 create mode 100644 drivers/gpu/drm/panthor/arbitration/panthor_arbitration_drv.c
 create mode 100644 drivers/gpu/drm/panthor/arbitration/panthor_partition_control.c
 create mode 100644 drivers/gpu/drm/panthor/arbitration/panthor_partition_control.h

diff --git a/drivers/gpu/drm/panthor/Kconfig b/drivers/gpu/drm/panthor/Kconfig
index e17c93035e8b7..04b11b933290e 100644
--- a/drivers/gpu/drm/panthor/Kconfig
+++ b/drivers/gpu/drm/panthor/Kconfig
@@ -30,3 +30,13 @@ config DRM_PANTHOR_SYSTEM
 	  AM GPUs. This block provides GPU-wide control outside the main GPU
 	  register window, including reset handling and management of shared
 	  clock and regulator resources.
+
+config DRM_PANTHOR_ARBITRATION
+	tristate "HW-assisted virtualization for Mali 5th Gen AM GPUs"
+	depends on DRM_PANTHOR
+	depends on OF
+	help
+	  Enable support for the arbitration blocks found on Arm Mali 5th Gen
+	  AM GPUs. These blocks manage partition controls, resource groups and
+	  access-window scheduling, allowing multiple access windows to share
+	  GPU resources under hardware-assisted arbitration.
diff --git a/drivers/gpu/drm/panthor/Makefile b/drivers/gpu/drm/panthor/Makefile
index 488a5e03efbc4..5d4d0ae64952e 100644
--- a/drivers/gpu/drm/panthor/Makefile
+++ b/drivers/gpu/drm/panthor/Makefile
@@ -15,5 +15,6 @@ panthor-y := \
 
 obj-$(CONFIG_DRM_PANTHOR) += panthor.o
 obj-$(CONFIG_DRM_PANTHOR_SYSTEM) += system/
+obj-$(CONFIG_DRM_PANTHOR_ARBITRATION) += arbitration/
 
 CFLAGS_panthor_gpu.o := -I$(src)
diff --git a/drivers/gpu/drm/panthor/arbitration/Makefile b/drivers/gpu/drm/panthor/arbitration/Makefile
new file mode 100644
index 0000000000000..b0b6b2e3edf8d
--- /dev/null
+++ b/drivers/gpu/drm/panthor/arbitration/Makefile
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0 OR MIT
+# Copyright 2026 ARM Limited. All rights reserved.
+
+obj-$(CONFIG_DRM_PANTHOR_ARBITRATION) += panthor_arbitration.o
+panthor_arbitration-y := \
+	panthor_arbitration_drv.o \
+	panthor_partition_control.o
+
+INCLUDES = \
+	-I$(src)/..
+
+ccflags-y += $(INCLUDES)
+subdir-ccflags-y += $(INCLUDES)
diff --git a/drivers/gpu/drm/panthor/arbitration/panthor_arbitration.h b/drivers/gpu/drm/panthor/arbitration/panthor_arbitration.h
new file mode 100644
index 0000000000000..26950e47852dd
--- /dev/null
+++ b/drivers/gpu/drm/panthor/arbitration/panthor_arbitration.h
@@ -0,0 +1,40 @@
+/* SPDX-License-Identifier: GPL-2.0 or MIT */
+/* Copyright 2026 ARM Limited. All rights reserved. */
+
+#ifndef __PANTHOR_ARBITRATION_H__
+#define __PANTHOR_ARBITRATION_H__
+
+#include <linux/ioport.h>
+#include <linux/fwnode.h>
+
+struct device;
+struct panthor_partition_control;
+
+#define AM_ARB_MAX_PC_COUNT			1
+#define AM_ARB_MAX_AW_COUNT			16
+
+/** struct panthor_arbitration_resource - Arbitration resource */
+struct panthor_arbitration_resource {
+	/** @res: resource parsed from child 'reg' property */
+	struct resource res;
+
+	/** @id: id parsed from child 'arm,id' property */
+	u32 id;
+};
+
+/**
+ * struct panthor_arbitration - Arbitration device
+ */
+struct panthor_arbitration {
+	/** @dev: Device pointer */
+	struct device *dev;
+
+	/** @pc: Pointer array to partition control data */
+	struct panthor_partition_control *pc[AM_ARB_MAX_PC_COUNT];
+};
+
+int panthor_arbitration_parse_resource(struct device *dev,
+				       const struct fwnode_handle *child,
+				       struct panthor_arbitration_resource *res);
+
+#endif
diff --git a/drivers/gpu/drm/panthor/arbitration/panthor_arbitration_drv.c b/drivers/gpu/drm/panthor/arbitration/panthor_arbitration_drv.c
new file mode 100644
index 0000000000000..09342245a47d1
--- /dev/null
+++ b/drivers/gpu/drm/panthor/arbitration/panthor_arbitration_drv.c
@@ -0,0 +1,174 @@
+// SPDX-License-Identifier: GPL-2.0 or MIT
+/* Copyright 2026 ARM Limited. All rights reserved. */
+
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/types.h>
+#include <linux/of_address.h>
+#include <linux/of.h>
+
+#include "panthor_arbitration.h"
+#include "panthor_partition_control.h"
+
+#define PANTHOR_PM_AUTOSUSPEND_DELAY_MS 100
+
+#define DT_ID					"arm,id"
+
+int panthor_arbitration_parse_resource(struct device *dev,
+				       const struct fwnode_handle *child,
+				       struct panthor_arbitration_resource *res)
+{
+	const char *name;
+	int ret;
+
+	if (!child || !res)
+		return -EINVAL;
+
+	name = fwnode_get_name(child);
+
+	if (of_address_to_resource(to_of_node(child), 0, &res->res)) {
+		dev_warn(dev, "Missing 'reg' property in %s", name);
+		return -ENODEV;
+	}
+
+	if (!fwnode_property_present(child, DT_ID)) {
+		dev_warn(dev, "Missing '%s' property in %s@%llx", DT_ID, name,
+			 res->res.start);
+		return -ENODEV;
+	}
+
+	ret = fwnode_property_read_u32(child, DT_ID, &res->id);
+	if (ret) {
+		dev_warn(dev, "Malformed '%s' property in %s@%llx", DT_ID, name,
+			 res->res.start);
+		return -ENODEV;
+	}
+
+	return 0;
+}
+
+static int panthor_arbitration_runtime_suspend(struct device *dev)
+{
+	struct panthor_arbitration *adev = dev_get_drvdata(dev);
+	int ret = 0;
+
+	ret = panthor_partition_control_suspend(adev);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+static int panthor_arbitration_runtime_resume(struct device *dev)
+{
+	struct panthor_arbitration *adev = dev_get_drvdata(dev);
+	int ret = 0;
+
+	ret = panthor_partition_control_resume(adev);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+static int panthor_arbitration_probe(struct platform_device *pdev)
+{
+	struct panthor_arbitration *adev;
+	struct device *dev = &pdev->dev;
+	int ret;
+
+	if (!pdev)
+		return -EINVAL;
+
+	adev = devm_kzalloc(dev, sizeof(*adev), GFP_KERNEL);
+	if (!adev)
+		return -ENOMEM;
+
+	adev->dev = dev;
+
+	dev_set_drvdata(dev, adev);
+
+	ret = devm_pm_runtime_enable(dev);
+	if (ret)
+		return ret;
+
+	ret = pm_runtime_resume_and_get(dev);
+	if (ret)
+		return ret;
+
+	ret = panthor_partition_control_init(adev);
+	if (ret)
+		goto err_term_pc;
+
+	ret = of_platform_populate(dev->of_node, NULL, NULL, dev);
+	if (ret)
+		goto err_depopulate;
+
+	pm_runtime_set_autosuspend_delay(dev, PANTHOR_PM_AUTOSUSPEND_DELAY_MS);
+	pm_runtime_use_autosuspend(dev);
+
+	pm_runtime_put_autosuspend(dev);
+
+	return 0;
+
+err_depopulate:
+	of_platform_depopulate(dev);
+
+err_term_pc:
+	panthor_partition_control_term(adev);
+	pm_runtime_put_noidle(dev);
+	return ret;
+}
+
+static void panthor_arbitration_remove(struct platform_device *pdev)
+{
+	struct panthor_arbitration *adev = platform_get_drvdata(pdev);
+	int ret;
+
+	if (!adev)
+		return;
+
+	ret = pm_runtime_resume_and_get(adev->dev);
+	if (ret < 0)
+		dev_warn(adev->dev, "failed to resume during remove: %d", ret);
+
+	of_platform_depopulate(adev->dev);
+
+	if (ret >= 0) {
+		panthor_partition_control_term(adev);
+		pm_runtime_put_noidle(adev->dev);
+	}
+
+	pm_runtime_set_suspended(adev->dev);
+}
+
+static const struct dev_pm_ops panthor_arbitration_pm_ops = {
+	.resume = pm_runtime_force_resume,
+	.suspend = pm_runtime_force_suspend,
+	.runtime_resume = panthor_arbitration_runtime_resume,
+	.runtime_suspend = panthor_arbitration_runtime_suspend,
+};
+
+static const struct of_device_id panthor_arbitration_of_match[] = {
+	{ .compatible = "arm,mali-gen5-am-arbitration" },
+	{ /* Sentinel */ },
+};
+
+static struct platform_driver panthor_arbitration_driver = {
+	.probe = panthor_arbitration_probe,
+	.remove = panthor_arbitration_remove,
+	.driver = {
+		.name = "panthor-arbitration",
+		.of_match_table = panthor_arbitration_of_match,
+		.pm = pm_ptr(&panthor_arbitration_pm_ops),
+	},
+};
+
+module_platform_driver(panthor_arbitration_driver);
+
+MODULE_AUTHOR("ARM Ltd.");
+MODULE_DESCRIPTION("Panthor HW-assisted virtualization Driver");
+MODULE_LICENSE("Dual MIT/GPL");
diff --git a/drivers/gpu/drm/panthor/arbitration/panthor_partition_control.c b/drivers/gpu/drm/panthor/arbitration/panthor_partition_control.c
new file mode 100644
index 0000000000000..e6fbf5e58b51a
--- /dev/null
+++ b/drivers/gpu/drm/panthor/arbitration/panthor_partition_control.c
@@ -0,0 +1,333 @@
+// SPDX-License-Identifier: GPL-2.0 or MIT
+/* Copyright 2026 ARM Limited. All rights reserved. */
+
+#include <linux/interrupt.h>
+#include <linux/iopoll.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/property.h>
+
+#include "panthor_arbitration.h"
+#include "panthor_device_io.h"
+#include "panthor_partition_control.h"
+
+#define AM_PART_IRQ_RAWSTAT			0x40
+#define AM_PART_IRQ_CLEAR			0x44
+#define AM_PART_IRQ_MASK			0x48
+#define AM_PART_IRQ_STATUS			0x4C
+#define   PART_RESET_DONE			BIT(3)
+#define   PART_INVALID_COMMAND			BIT(6)
+
+#define AM_PART_STATE				0x60
+#define   AM_PART_STATE_GET(x)			FIELD_GET(GENMASK(11, 8), x)
+#define     PART_STATE_RESET			0
+#define     PART_STATE_WINDOW_OPENING		1
+#define     PART_STATE_WINDOW_OPEN		7
+#define     PART_STATE_WINDOW_CLOSED		8
+#define   AM_PART_STATE_WINDOW_GET(x)		FIELD_GET(GENMASK(15, 12), x)
+
+#define AM_PART_COMMAND				0x100
+#define   AM_PART_SET_COMMAND(x)		FIELD_PREP(GENMASK(7, 0), x)
+#define     PART_CMD_YIELD_IDLE			0x10
+#define     PART_CMD_YIELD_NOW			0x11
+#define     PART_CMD_CLOSE_WINDOW		0x20
+#define     PART_CMD_OPEN_WINDOW		0x21
+#define   AM_PART_SET_WINDOW(x)			FIELD_PREP(GENMASK(11, 8), x)
+
+#define PART_CONTROL_IRQ_MASK \
+	(PART_RESET_DONE | PART_INVALID_COMMAND)
+
+#define PART_REG_POLL_SLEEP_US			10
+#define PART_STATE_TRANSITION_TIMEOUT_US	5000000
+
+/**
+ * struct panthor_partition_control - Partition control data
+ */
+struct panthor_partition_control {
+	/** @dev: Device pointer */
+	struct device *dev;
+
+	/** @name: Resource name */
+	char *name;
+
+	/** @iomem: CPU mapping of the partition control IOMEM region */
+	void __iomem *iomem;
+
+	/** @irq: IRQ number */
+	int irq;
+
+	/** @lock: Proctects partition control state data */
+	spinlock_t lock;
+
+	/** @current_aw: currently open access window */
+	int current_aw;
+
+	/** @closing: synchronous closing of the partition */
+	bool closing;
+};
+
+static void partition_irq_suspend(struct panthor_partition_control *pc)
+{
+	gpu_write(pc->iomem, AM_PART_IRQ_MASK, 0);
+}
+
+static void partition_irq_resume(struct panthor_partition_control *pc)
+{
+	gpu_write(pc->iomem, AM_PART_IRQ_MASK, PART_CONTROL_IRQ_MASK);
+}
+
+static u32 partition_state_get(struct panthor_partition_control *pc)
+{
+	const u32 state = gpu_read(pc->iomem, AM_PART_STATE);
+
+	return AM_PART_STATE_GET(state);
+}
+
+static u8 partition_aw_get(struct panthor_partition_control *pc)
+{
+	const u32 state = gpu_read(pc->iomem, AM_PART_STATE);
+
+	return AM_PART_STATE_WINDOW_GET(state);
+}
+
+static int partition_state_wait(struct panthor_partition_control *pc, u32 state)
+{
+	u32 partition_state;
+
+	return read_poll_timeout_atomic(partition_state_get, partition_state,
+					partition_state == state,
+					PART_REG_POLL_SLEEP_US,
+					PART_STATE_TRANSITION_TIMEOUT_US,
+					false, pc);
+}
+
+static int yield_now(struct panthor_partition_control *pc)
+{
+	gpu_write(pc->iomem, AM_PART_COMMAND,
+		  AM_PART_SET_COMMAND(PART_CMD_YIELD_NOW));
+
+	return 0;
+}
+
+static int yield_idle(struct panthor_partition_control *pc)
+{
+	gpu_write(pc->iomem, AM_PART_COMMAND,
+		  AM_PART_SET_COMMAND(PART_CMD_YIELD_IDLE));
+
+	return 0;
+}
+
+static int window_close(struct panthor_partition_control *pc)
+{
+	/* Partition already closed. */
+	if (partition_state_get(pc) == PART_STATE_RESET)
+		return 1;
+
+	guard(spinlock_irqsave)(&pc->lock);
+
+	pc->closing = true;
+
+	gpu_write(pc->iomem, AM_PART_COMMAND,
+		  AM_PART_SET_COMMAND(PART_CMD_CLOSE_WINDOW));
+
+	return 0;
+}
+
+static int window_open(struct panthor_partition_control *pc, u8 aw_id)
+{
+	if (aw_id >= AM_ARB_MAX_AW_COUNT)
+		return -EINVAL;
+
+	if (partition_state_get(pc) == PART_STATE_WINDOW_OPEN) {
+		u8 cur_aw = partition_aw_get(pc);
+
+		if (cur_aw == aw_id)
+			return 0;
+
+		dev_warn(pc->dev,
+			 "%s: OPEN_WINDOW(%u): Already opened for aw=%u, state=%u. Closing...",
+			 pc->name, aw_id, cur_aw, partition_state_get(pc));
+
+		window_close(pc);
+	}
+
+	guard(spinlock_irqsave)(&pc->lock);
+
+	gpu_write(pc->iomem, AM_PART_COMMAND,
+		  AM_PART_SET_COMMAND(PART_CMD_OPEN_WINDOW) | AM_PART_SET_WINDOW(aw_id));
+
+	pc->current_aw = aw_id;
+
+	return 0;
+}
+
+static void partition_handle_reset_done(struct panthor_partition_control *pc)
+{
+	scoped_guard(spinlock_irqsave, &pc->lock) {
+		pc->current_aw = -1;
+
+		/* RESET_DONE from CLOSE_WINDOW */
+		if (pc->closing)
+			pc->closing = false;
+	}
+}
+
+static irqreturn_t partition_irq_raw_handler(int irq, void *data)
+{
+	struct panthor_partition_control *pc = data;
+	u32 status;
+
+	status = gpu_read(pc->iomem, AM_PART_IRQ_STATUS);
+	if (!status)
+		return IRQ_NONE;
+
+	if (status & PART_RESET_DONE)
+		partition_handle_reset_done(pc);
+
+	if (status & PART_INVALID_COMMAND)
+		dev_warn(pc->dev, "%s: Invalid command", pc->name);
+
+	gpu_write(pc->iomem, AM_PART_IRQ_CLEAR, status);
+
+	return IRQ_HANDLED;
+}
+
+int panthor_partition_control_suspend(struct panthor_arbitration *adev)
+{
+	for (int i = 0; i < AM_ARB_MAX_PC_COUNT; i++) {
+		struct panthor_partition_control *pc = adev->pc[i];
+
+		if (!pc)
+			continue;
+
+		partition_irq_suspend(pc);
+	}
+
+	return 0;
+}
+
+int panthor_partition_control_resume(struct panthor_arbitration *adev)
+{
+	for (int i = 0; i < AM_ARB_MAX_PC_COUNT; i++) {
+		struct panthor_partition_control *pc = adev->pc[i];
+
+		if (!pc)
+			continue;
+
+		partition_irq_resume(pc);
+	}
+
+	return 0;
+}
+
+void panthor_partition_control_term(struct panthor_arbitration *adev)
+{
+	for (int i = 0; i < AM_ARB_MAX_PC_COUNT; i++) {
+		struct panthor_partition_control *pc = adev->pc[i];
+
+		if (!pc)
+			continue;
+
+		if (!WARN_ON(window_close(pc) < 0))
+			WARN_ON(partition_state_wait(pc, PART_STATE_RESET));
+
+		partition_irq_suspend(pc);
+	}
+}
+
+static int partition_control_init(struct panthor_arbitration *adev,
+				   const struct fwnode_handle *child)
+{
+	struct panthor_arbitration_resource res;
+	struct panthor_partition_control *pc;
+	struct device *dev = adev->dev;
+	struct irq_data *irqdata;
+	void __iomem *iomem;
+	u32 irq_flags = 0;
+	char *name;
+	int irq;
+	int ret;
+
+	ret = panthor_arbitration_parse_resource(dev, child, &res);
+	if (ret)
+		return ret;
+
+	if (res.id >= AM_ARB_MAX_PC_COUNT)
+		return -ENODEV;
+
+	if (adev->pc[res.id])
+		return dev_warn_probe(dev, -ENODEV, "partition@%llx: id (%u) already present",
+				      res.res.start, res.id);
+
+	pc = devm_kzalloc(dev, sizeof(*pc), GFP_KERNEL);
+	if (!pc)
+		return -ENOMEM;
+
+	name = devm_kasprintf(dev, GFP_KERNEL, "pc%d", res.id);
+
+	iomem = devm_ioremap_resource(dev, &res.res);
+	if (IS_ERR(iomem))
+		return dev_err_probe(dev, PTR_ERR(iomem), "%s: Failed to ioremap", name);
+
+	pc->name = name;
+	pc->dev = dev;
+	pc->iomem = iomem;
+
+	spin_lock_init(&pc->lock);
+	pc->current_aw = -1;
+
+	irq = fwnode_irq_get(child, 0);
+	if (irq < 0)
+		return dev_err_probe(dev, irq, "%s: Failed to get IRQ", name);
+
+	irqdata = irq_get_irq_data(irq);
+	if (irqdata)
+		irq_flags = irqd_get_trigger_type(irqdata);
+
+	ret = devm_request_irq(
+		dev, irq, partition_irq_raw_handler, irq_flags | IRQF_SHARED,
+		devm_kasprintf(dev, GFP_KERNEL, "panthor-%s-irq", name), pc);
+	if (ret)
+		return ret;
+
+	adev->pc[res.id] = pc;
+
+	partition_irq_resume(pc);
+
+	return 0;
+}
+
+int panthor_partition_control_init(struct panthor_arbitration *adev)
+{
+	device_for_each_named_child_node_scoped(adev->dev, child, "partition") {
+		int ret = partition_control_init(adev, child);
+
+		if (ret == -ENODEV)
+			continue;
+
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
+int panthor_partition_control_open_window(struct panthor_partition_control *pc, u8 aw_id)
+{
+	return window_open(pc, aw_id);
+}
+
+int panthor_partition_control_close_window(struct panthor_partition_control *pc)
+{
+	return window_close(pc);
+}
+
+int panthor_partition_control_yield_now(struct panthor_partition_control *pc)
+{
+	return yield_now(pc);
+}
+
+int panthor_partition_control_yield_idle(struct panthor_partition_control *pc)
+{
+	return yield_idle(pc);
+}
diff --git a/drivers/gpu/drm/panthor/arbitration/panthor_partition_control.h b/drivers/gpu/drm/panthor/arbitration/panthor_partition_control.h
new file mode 100644
index 0000000000000..9a688d7bbdb1f
--- /dev/null
+++ b/drivers/gpu/drm/panthor/arbitration/panthor_partition_control.h
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0 or MIT */
+/* Copyright 2026 ARM Limited. All rights reserved. */
+
+#ifndef __PANTHOR_PARTITION_CONTROL_H__
+#define __PANTHOR_PARTITION_CONTROL_H__
+
+#include <linux/types.h>
+
+struct device;
+struct panthor_arbitration;
+struct panthor_partition_control;
+
+int panthor_partition_control_init(struct panthor_arbitration *adev);
+
+void panthor_partition_control_term(struct panthor_arbitration *adev);
+
+int panthor_partition_control_suspend(struct panthor_arbitration *adev);
+
+int panthor_partition_control_resume(struct panthor_arbitration *adev);
+
+int panthor_partition_control_open_window(struct panthor_partition_control *pc, u8 aw_id);
+
+int panthor_partition_control_close_window(struct panthor_partition_control *pc);
+
+int panthor_partition_control_yield_now(struct panthor_partition_control *pc);
+
+int panthor_partition_control_yield_idle(struct panthor_partition_control *pc);
+
+#endif
-- 
2.43.0

[PATCH v1 14/27] drm/panthor: Add AM message helpers

[Karunika Choo]

Add a shared helper layer for the AM_MESSAGE registers used by v15 GPUs
to coordinate between access windows to enable virtualisation of the
GPU.

The helper defines message IDs, register accessors, version negotiation,
and FIFO-backed sending. Outgoing messages are serialized with a
spinlock, written in the required register order, and queued for later
retry when the hardware outgoing slot is busy.

Signed-off-by: Karunika Choo <karunika.choo@arm.com>
---
v1:
- Raises minimum/current protocol support to v2. (v1 was for G78AE)
- Removes ARB_VM_GPU_STOP.
- Return -ENOSPC instead of -ENOMEM on full outgoing FIFO.

 drivers/gpu/drm/panthor/panthor_am_msg.h | 159 +++++++++++++++++++++++
 1 file changed, 159 insertions(+)
 create mode 100644 drivers/gpu/drm/panthor/panthor_am_msg.h

diff --git a/drivers/gpu/drm/panthor/panthor_am_msg.h b/drivers/gpu/drm/panthor/panthor_am_msg.h
new file mode 100644
index 0000000000000..fc1e3f1051fe5
--- /dev/null
+++ b/drivers/gpu/drm/panthor/panthor_am_msg.h
@@ -0,0 +1,159 @@
+/* SPDX-License-Identifier: GPL-2.0 or MIT */
+/* Copyright 2026 ARM Limited. All rights reserved. */
+
+#ifndef __PANTHOR_AM_H__
+#define __PANTHOR_AM_H__
+
+#include <linux/bitfield.h>
+#include <linux/bits.h>
+#include <linux/cleanup.h>
+#include <linux/kfifo.h>
+#include <linux/types.h>
+
+#include "panthor_device_io.h"
+
+/* Protocol versioning */
+#define ARB_VM_PROTOCOL_V1			0x1
+#define ARB_VM_PROTOCOL_V2			0x2
+
+#define AM_MSG_MIN_SUPPORTED_VERSION		ARB_VM_PROTOCOL_V2
+#define AM_MSG_CURRENT_VERSION			ARB_VM_PROTOCOL_V2
+
+#define AM_INCOMING_MESSAGE0			0x0
+#define AM_INCOMING_MESSAGE1			0x4
+#define AM_OUTGOING_MESSAGE_STATUS		0x8
+#define AM_OUTGOING_MESSAGE0			0xc
+#define AM_OUTGOING_MESSAGE1			0x10
+
+/* Arbiter to VM message IDs */
+#define ARB_VM_INIT				0x04
+
+/* VM to Arbiter message IDs */
+#define VM_ARB_INIT				0x05
+#define VM_ARB_GPU_REQUEST			0x08
+#define VM_ARB_GPU_STOPPED			0x09
+
+#define AM_MSG_ID_MASK				GENMASK(7, 0)
+#define AM_MSG_ACK_MASK				BIT(8)
+#define AM_MSG_VERSION_MASK			GENMASK(15, 9)
+
+#define AM_MSG_ID_GET(x)			FIELD_GET(AM_MSG_ID_MASK, x)
+#define AM_MSG_ACK_GET(x)			FIELD_GET(AM_MSG_ACK_MASK, x)
+#define AM_MSG_VERSION_GET(x)			FIELD_GET(AM_MSG_VERSION_MASK, x)
+
+#define AM_MSG_INIT_MAKE(_id, _ack, _version) \
+	((_id) | FIELD_PREP(AM_MSG_ACK_MASK, _ack) | FIELD_PREP(AM_MSG_VERSION_MASK, _version))
+
+#define ARB_VM_INIT_MAKE(_ack, _version)	AM_MSG_INIT_MAKE(ARB_VM_INIT, _ack, _version)
+#define VM_ARB_INIT_MAKE(_ack, _version)	AM_MSG_INIT_MAKE(VM_ARB_INIT, _ack, _version)
+
+#define AM_MSG_DEFAULT_FIFO_SIZE		4
+
+struct panthor_am_msg {
+	/** @iomem: CPU mapping of the AM_MESSAGE registers */
+	void __iomem *iomem;
+
+	/** @lock: Lock for send_fifo and outgoing message register */
+	spinlock_t lock;
+
+	/** @send_fifo: FIFO to queue of messages to send */
+	DECLARE_KFIFO(send_fifo, u64, AM_MSG_DEFAULT_FIFO_SIZE);
+
+	/** @version: Protocol version */
+	u8 version;
+};
+
+static inline void panthor_am_msg_init(struct panthor_am_msg *msg,
+				       void __iomem *iomem)
+{
+	spin_lock_init(&msg->lock);
+	INIT_KFIFO(msg->send_fifo);
+	msg->iomem = iomem;
+}
+
+static inline bool panthor_am_msg_pending(struct panthor_am_msg *msg)
+{
+	return !!gpu_read(msg->iomem, AM_OUTGOING_MESSAGE_STATUS);
+}
+
+static inline u64 panthor_am_msg_read(struct panthor_am_msg *msg)
+{
+	return gpu_read64(msg->iomem, AM_INCOMING_MESSAGE0);
+}
+
+static inline void panthor_am_msg_write(struct panthor_am_msg *msg, u64 message)
+{
+	lockdep_assert_held(&msg->lock);
+
+	/*
+	 * Registers must be written in this exact order to prevent interrupts
+	 * being raised before the complete message is written.
+	 */
+	gpu_write(msg->iomem, AM_OUTGOING_MESSAGE0, lower_32_bits(message));
+	gpu_write(msg->iomem, AM_OUTGOING_MESSAGE1, upper_32_bits(message));
+}
+
+static inline int panthor_am_msg_retry(struct panthor_am_msg *msg)
+{
+	u64 message;
+
+	guard(spinlock_irqsave)(&msg->lock);
+
+	if (kfifo_is_empty(&msg->send_fifo))
+		return 0;
+
+	if (panthor_am_msg_pending(msg))
+		return -EBUSY;
+
+	/* FIFO should never be empty at this point */
+	if (!kfifo_get(&msg->send_fifo, &message))
+		return -EINVAL;
+
+	panthor_am_msg_write(msg, message);
+
+	/* There are still messages in the FIFO, notify caller to retry again */
+	if (!kfifo_is_empty(&msg->send_fifo))
+		return -EAGAIN;
+
+	return 0;
+}
+
+static inline int panthor_am_msg_send(struct panthor_am_msg *msg, u64 message)
+{
+	guard(spinlock_irqsave)(&msg->lock);
+
+	/*
+	 * If there already is a pending message in the FIFO or the outgoing
+	 * message is still not read by the receipient, add to the FIFO.
+	 */
+	if (!kfifo_is_empty(&msg->send_fifo) || panthor_am_msg_pending(msg)) {
+		if (!kfifo_put(&msg->send_fifo, message))
+			return -ENOSPC;
+
+		/*
+		 * return -EBUSY to indicate to the caller to schedule work to
+		 * retry sending messages in the FIFO.
+		 */
+		return -EBUSY;
+	}
+
+	/* We are free to write to AM_OUTGOING_MESSAGE */
+	panthor_am_msg_write(msg, message);
+
+	return 0;
+}
+
+static inline int panthor_am_msg_version_validate(struct panthor_am_msg *msg,
+						  u8 version)
+{
+	if (version < AM_MSG_MIN_SUPPORTED_VERSION) {
+		msg->version = AM_MSG_MIN_SUPPORTED_VERSION;
+		return -EOPNOTSUPP;
+	}
+
+	msg->version = min(version, AM_MSG_CURRENT_VERSION);
+
+	return 0;
+}
+
+#endif
-- 
2.43.0

[PATCH v1 15/27] drm/panthor: Add AM_RESOURCE_GROUP support

[Karunika Choo]

Add resource-group probing for the arbitration device, including MMIO
resources, IRQ handling, per-AW AM message helpers, handshake
negotiation, and retry work for deferred outgoing messages.

Hook resource groups into arbitration init, teardown, and runtime PM.

Signed-off-by: Karunika Choo <karunika.choo@arm.com>
---
v1:
- Updated DT structure and accompanying parsing to handle child nodes
  instead of named platform resources.
- Hold runtime PM reference during message retries.
- Fix suspend resume ordering.

 drivers/gpu/drm/panthor/arbitration/Makefile  |   3 +-
 .../panthor/arbitration/panthor_arbitration.h |   5 +
 .../arbitration/panthor_arbitration_drv.c     |  19 +-
 .../arbitration/panthor_resource_group.c      | 323 ++++++++++++++++++
 .../arbitration/panthor_resource_group.h      |  22 ++
 5 files changed, 370 insertions(+), 2 deletions(-)
 create mode 100644 drivers/gpu/drm/panthor/arbitration/panthor_resource_group.c
 create mode 100644 drivers/gpu/drm/panthor/arbitration/panthor_resource_group.h

diff --git a/drivers/gpu/drm/panthor/arbitration/Makefile b/drivers/gpu/drm/panthor/arbitration/Makefile
index b0b6b2e3edf8d..2d2684321d978 100644
--- a/drivers/gpu/drm/panthor/arbitration/Makefile
+++ b/drivers/gpu/drm/panthor/arbitration/Makefile
@@ -4,7 +4,8 @@
 obj-$(CONFIG_DRM_PANTHOR_ARBITRATION) += panthor_arbitration.o
 panthor_arbitration-y := \
 	panthor_arbitration_drv.o \
-	panthor_partition_control.o
+	panthor_partition_control.o \
+	panthor_resource_group.o
 
 INCLUDES = \
 	-I$(src)/..
diff --git a/drivers/gpu/drm/panthor/arbitration/panthor_arbitration.h b/drivers/gpu/drm/panthor/arbitration/panthor_arbitration.h
index 26950e47852dd..dfeab1b078d06 100644
--- a/drivers/gpu/drm/panthor/arbitration/panthor_arbitration.h
+++ b/drivers/gpu/drm/panthor/arbitration/panthor_arbitration.h
@@ -9,8 +9,10 @@
 
 struct device;
 struct panthor_partition_control;
+struct panthor_resource_group;
 
 #define AM_ARB_MAX_PC_COUNT			1
+#define AM_ARB_MAX_RG_COUNT			1
 #define AM_ARB_MAX_AW_COUNT			16
 
 /** struct panthor_arbitration_resource - Arbitration resource */
@@ -31,6 +33,9 @@ struct panthor_arbitration {
 
 	/** @pc: Pointer array to partition control data */
 	struct panthor_partition_control *pc[AM_ARB_MAX_PC_COUNT];
+
+	/** @rg: Pointer array to resource group data */
+	struct panthor_resource_group *rg[AM_ARB_MAX_RG_COUNT];
 };
 
 int panthor_arbitration_parse_resource(struct device *dev,
diff --git a/drivers/gpu/drm/panthor/arbitration/panthor_arbitration_drv.c b/drivers/gpu/drm/panthor/arbitration/panthor_arbitration_drv.c
index 09342245a47d1..a1068a2c78f1a 100644
--- a/drivers/gpu/drm/panthor/arbitration/panthor_arbitration_drv.c
+++ b/drivers/gpu/drm/panthor/arbitration/panthor_arbitration_drv.c
@@ -12,6 +12,7 @@
 
 #include "panthor_arbitration.h"
 #include "panthor_partition_control.h"
+#include "panthor_resource_group.h"
 
 #define PANTHOR_PM_AUTOSUSPEND_DELAY_MS 100
 
@@ -55,6 +56,10 @@ static int panthor_arbitration_runtime_suspend(struct device *dev)
 	struct panthor_arbitration *adev = dev_get_drvdata(dev);
 	int ret = 0;
 
+	ret = panthor_resource_group_suspend(adev);
+	if (ret)
+		return ret;
+
 	ret = panthor_partition_control_suspend(adev);
 	if (ret)
 		return ret;
@@ -71,6 +76,10 @@ static int panthor_arbitration_runtime_resume(struct device *dev)
 	if (ret)
 		return ret;
 
+	ret = panthor_resource_group_resume(adev);
+	if (ret)
+		return ret;
+
 	return 0;
 }
 
@@ -103,6 +112,10 @@ static int panthor_arbitration_probe(struct platform_device *pdev)
 	if (ret)
 		goto err_term_pc;
 
+	ret = panthor_resource_group_init(adev);
+	if (ret)
+		goto err_term_rg;
+
 	ret = of_platform_populate(dev->of_node, NULL, NULL, dev);
 	if (ret)
 		goto err_depopulate;
@@ -116,7 +129,9 @@ static int panthor_arbitration_probe(struct platform_device *pdev)
 
 err_depopulate:
 	of_platform_depopulate(dev);
-
+err_term_rg:
+	panthor_resource_group_cancel_work(adev);
+	panthor_resource_group_term(adev);
 err_term_pc:
 	panthor_partition_control_term(adev);
 	pm_runtime_put_noidle(dev);
@@ -136,8 +151,10 @@ static void panthor_arbitration_remove(struct platform_device *pdev)
 		dev_warn(adev->dev, "failed to resume during remove: %d", ret);
 
 	of_platform_depopulate(adev->dev);
+	panthor_resource_group_cancel_work(adev);
 
 	if (ret >= 0) {
+		panthor_resource_group_term(adev);
 		panthor_partition_control_term(adev);
 		pm_runtime_put_noidle(adev->dev);
 	}
diff --git a/drivers/gpu/drm/panthor/arbitration/panthor_resource_group.c b/drivers/gpu/drm/panthor/arbitration/panthor_resource_group.c
new file mode 100644
index 0000000000000..9bdd0876dd457
--- /dev/null
+++ b/drivers/gpu/drm/panthor/arbitration/panthor_resource_group.c
@@ -0,0 +1,323 @@
+// SPDX-License-Identifier: GPL-2.0 or MIT
+/* Copyright 2026 ARM Limited. All rights reserved. */
+
+#include <linux/interrupt.h>
+#include <linux/iopoll.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/property.h>
+#include <linux/workqueue.h>
+
+#include "panthor_am_msg.h"
+#include "panthor_arbitration.h"
+#include "panthor_device_io.h"
+#include "panthor_resource_group.h"
+
+#define AM_RG_IRQ_RAWSTAT			0x80
+#define AM_RG_IRQ_CLEAR				0x84
+#define AM_RG_IRQ_MASK				0x88
+#define AM_RG_IRQ_STATUS			0x8C
+#define   AM_RG_MESSAGE_MASK			GENMASK(15, 0)
+
+#define AM_RG_AW_MESSAGE(n)			(0x100 + (n) * 0x20)
+
+struct rg_aw_data {
+	/** @msg: Messaging data */
+	struct panthor_am_msg msg;
+};
+
+struct panthor_resource_group {
+	/** @dev: Device pointer */
+	struct device *dev;
+
+	/** @name: Resource name */
+	char *name;
+
+	/** @iomem: CPU mapping of the partition control IOMEM region */
+	void __iomem *iomem;
+
+	/** @irq: IRQ number */
+	int irq;
+
+	/** @aw_data: Data for each access window */
+	struct rg_aw_data aw_data[AM_ARB_MAX_AW_COUNT];
+
+	/** @wq: Resource group workqueue */
+	struct workqueue_struct *wq;
+
+	/** @msg_retry_work: Work to retry sending pending messages */
+	struct work_struct msg_retry_work;
+};
+
+static void rg_retry_messages(struct work_struct *work)
+{
+	struct panthor_resource_group *rg = container_of(
+		work, struct panthor_resource_group, msg_retry_work);
+	bool retry = false;
+	int ret;
+
+	ret = pm_runtime_resume_and_get(rg->dev);
+	if (ret) {
+		dev_warn(rg->dev, "Failed to resume to retry messages");
+		return;
+	}
+
+	for (u8 aw_id = 0; aw_id < AM_ARB_MAX_AW_COUNT; aw_id++) {
+		struct panthor_am_msg *msg = &rg->aw_data[aw_id].msg;
+		int ret;
+
+		ret = panthor_am_msg_retry(msg);
+		if (ret == -EBUSY || ret == -EAGAIN)
+			retry = true;
+
+		if (ret == -EINVAL)
+			dev_warn(rg->dev, "AW%u send FIFO unexpectedly empty", aw_id);
+	}
+
+	if (retry)
+		queue_work(rg->wq, &rg->msg_retry_work);
+
+	pm_runtime_put_autosuspend(rg->dev);
+}
+
+static void rg_send_msg(struct panthor_resource_group *rg, u8 aw_id,
+			u64 message)
+{
+	int ret;
+
+	ret = panthor_am_msg_send(&rg->aw_data[aw_id].msg, message);
+	if (ret == -ENOSPC)
+		dev_err(rg->dev, "AW%u send FIFO is full", aw_id);
+
+	if (ret == -EBUSY) {
+		dev_dbg(rg->dev, "AW%u has pending messages, scheduling retry work", aw_id);
+		queue_work(rg->wq, &rg->msg_retry_work);
+	}
+}
+
+static void rg_send_init_msg(struct panthor_resource_group *rg, u8 aw_id,
+			     u8 ack, u8 version)
+{
+	u64 message = ARB_VM_INIT_MAKE(ack, version);
+
+	rg_send_msg(rg, aw_id, message);
+}
+
+static void rg_respond_to_handshake(struct panthor_resource_group *rg,
+				    u8 aw_id, u64 message)
+{
+	struct rg_aw_data *aw_data = &rg->aw_data[aw_id];
+	bool acked = AM_MSG_ACK_GET(message);
+	u8 version = AM_MSG_VERSION_GET(message);
+	int ret;
+
+	ret = panthor_am_msg_version_validate(&aw_data->msg, version);
+	if (ret == -EOPNOTSUPP)
+		dev_warn(rg->dev,
+			 "AW%u protocol version less than minimum supported (%u < %u)",
+			 aw_id, version, AM_MSG_MIN_SUPPORTED_VERSION);
+
+	/* AW initiated the handshake, reply with supported version */
+	if (!acked)
+		rg_send_init_msg(rg, aw_id, 1, aw_data->msg.version);
+}
+
+static void rg_handshake_init(struct panthor_resource_group *rg)
+{
+	for (u8 aw_id = 0; aw_id < AM_ARB_MAX_AW_COUNT; aw_id++)
+		rg_send_init_msg(rg, aw_id, 0, AM_MSG_CURRENT_VERSION);
+}
+
+static void rg_handle_message(struct panthor_resource_group *rg, u8 aw_id,
+			      u64 message)
+{
+	u8 msg_id = AM_MSG_ID_GET(message);
+	if (!msg_id)
+		return;
+
+	switch (msg_id) {
+	case VM_ARB_INIT:
+		rg_respond_to_handshake(rg, aw_id, message);
+		break;
+	case VM_ARB_GPU_REQUEST:
+		/* TODO: on_request */
+		break;
+	case VM_ARB_GPU_STOPPED:
+		/* TODO: on_idle */
+		break;
+	default:
+		dev_warn(rg->dev, "Invalid message (0x%llx)", message);
+		break;
+	}
+}
+
+static irqreturn_t rg_irq_raw_handler(int irq, void *data)
+{
+	struct panthor_resource_group *rg = data;
+	unsigned long message_mask;
+	u32 status;
+	u8 aw_id;
+
+	status = gpu_read(rg->iomem, AM_RG_IRQ_STATUS);
+	if (!status)
+		return IRQ_NONE;
+
+	message_mask = status;
+	for_each_set_bit(aw_id, &message_mask, AM_ARB_MAX_AW_COUNT) {
+		u64 message = panthor_am_msg_read(&rg->aw_data[aw_id].msg);
+
+		rg_handle_message(rg, aw_id, message);
+	}
+
+	gpu_write(rg->iomem, AM_RG_IRQ_CLEAR, status);
+
+	return IRQ_HANDLED;
+}
+
+static void rg_irq_suspend(struct panthor_resource_group *rg)
+{
+	gpu_write(rg->iomem, AM_RG_IRQ_MASK, 0);
+}
+
+static void rg_irq_resume(struct panthor_resource_group *rg)
+{
+	gpu_write(rg->iomem, AM_RG_IRQ_MASK, AM_RG_MESSAGE_MASK);
+}
+
+int panthor_resource_group_suspend(struct panthor_arbitration *adev)
+{
+	for (int i = 0; i < AM_ARB_MAX_RG_COUNT; i++) {
+		struct panthor_resource_group *rg = adev->rg[i];
+
+		if (!rg)
+			continue;
+
+		rg_irq_suspend(rg);
+	}
+
+	return 0;
+}
+
+int panthor_resource_group_resume(struct panthor_arbitration *adev)
+{
+	for (int i = 0; i < AM_ARB_MAX_RG_COUNT; i++) {
+		struct panthor_resource_group *rg = adev->rg[i];
+
+		if (!rg)
+			continue;
+
+		rg_irq_resume(rg);
+	}
+
+	return 0;
+}
+
+void panthor_resource_group_cancel_work(struct panthor_arbitration *adev)
+{
+	for (int i = 0; i < AM_ARB_MAX_RG_COUNT; i++) {
+		struct panthor_resource_group *rg = adev->rg[i];
+
+		if (!rg)
+			continue;
+
+		disable_work_sync(&rg->msg_retry_work);
+	}
+}
+
+void panthor_resource_group_term(struct panthor_arbitration *adev)
+{
+	for (int i = 0; i < AM_ARB_MAX_RG_COUNT; i++) {
+		struct panthor_resource_group *rg = adev->rg[i];
+
+		if (!rg)
+			continue;
+
+		rg_irq_suspend(rg);
+	}
+}
+
+static int resource_group_init(struct panthor_arbitration *adev,
+			       const struct fwnode_handle *child)
+{
+	struct panthor_arbitration_resource res;
+	struct panthor_resource_group *rg;
+	struct device *dev = adev->dev;
+	struct irq_data *irqdata;
+	void __iomem *iomem;
+	u32 irq_flags = 0;
+	char *name;
+	int irq;
+	int ret;
+
+	ret = panthor_arbitration_parse_resource(dev, child, &res);
+	if (ret)
+		return ret;
+
+	if (res.id >= AM_ARB_MAX_RG_COUNT)
+		return -ENODEV;
+
+	if (adev->rg[res.id])
+		return dev_warn_probe(dev, -ENODEV, "resource-group@%llx: id (%u) already present",
+				      res.res.start, res.id);
+
+	rg = devm_kzalloc(dev, sizeof(*rg), GFP_KERNEL);
+	if (!rg)
+		return -ENOMEM;
+
+	name = devm_kasprintf(dev, GFP_KERNEL, "rg%d", res.id);
+
+	iomem = devm_ioremap_resource(dev, &res.res);
+	if (IS_ERR(iomem))
+		return dev_err_probe(dev, PTR_ERR(iomem), "%s: Failed to ioremap", name);
+
+	rg->name = name;
+	rg->dev = dev;
+	rg->iomem = iomem;
+
+	rg->wq = devm_alloc_ordered_workqueue(dev, "panthor-%s-wq", 0, name);
+	if (!rg->wq)
+		return -ENOMEM;
+
+	INIT_WORK(&rg->msg_retry_work, rg_retry_messages);
+
+	for (int i = 0; i < AM_ARB_MAX_AW_COUNT; i++)
+		panthor_am_msg_init(&rg->aw_data[i].msg,
+				    rg->iomem + AM_RG_AW_MESSAGE(i));
+
+	irq = fwnode_irq_get(child, 0);
+	if (irq < 0)
+		return dev_err_probe(dev, irq, "%s: Failed to get IRQ", name);
+
+	irqdata = irq_get_irq_data(irq);
+	if (irqdata)
+		irq_flags = irqd_get_trigger_type(irqdata);
+
+	ret = devm_request_irq(
+		dev, irq, rg_irq_raw_handler, irq_flags | IRQF_SHARED,
+		devm_kasprintf(dev, GFP_KERNEL, "panthor-%s-irq", name), rg);
+	if (ret)
+		return ret;
+
+	adev->rg[res.id] = rg;
+
+	rg_irq_resume(rg);
+
+	rg_handshake_init(rg);
+
+	return 0;
+}
+
+int panthor_resource_group_init(struct panthor_arbitration *adev)
+{
+	device_for_each_named_child_node_scoped(adev->dev, child, "resource-group") {
+		int ret = resource_group_init(adev, child);
+
+		if (ret == -ENODEV)
+			continue;
+
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
diff --git a/drivers/gpu/drm/panthor/arbitration/panthor_resource_group.h b/drivers/gpu/drm/panthor/arbitration/panthor_resource_group.h
new file mode 100644
index 0000000000000..ad85cd171c4a3
--- /dev/null
+++ b/drivers/gpu/drm/panthor/arbitration/panthor_resource_group.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0 or MIT */
+/* Copyright 2026 ARM Limited. All rights reserved. */
+
+#ifndef __PANTHOR_RESOURCE_GROUP_H__
+#define __PANTHOR_RESOURCE_GROUP_H__
+
+#include <linux/types.h>
+
+struct device;
+struct panthor_arbitration;
+
+int panthor_resource_group_init(struct panthor_arbitration *adev);
+
+void panthor_resource_group_term(struct panthor_arbitration *adev);
+
+int panthor_resource_group_suspend(struct panthor_arbitration *adev);
+
+int panthor_resource_group_resume(struct panthor_arbitration *adev);
+
+void panthor_resource_group_cancel_work(struct panthor_arbitration *adev);
+
+#endif
-- 
2.43.0

[PATCH v1 16/27] drm/panthor: Add arbitration scheduler

[Karunika Choo]

Add a per-partition arbitration scheduler that queues access-window GPU
requests, grants the active window, asks it to stop when its lease
expires, and force-closes it if it does not yield in time.

An uncontended access window can retain access even after its timeslice
expires.

Track grant, stop and close deadlines with hrtimers so scheduler
progress remains bounded.

Use scheduler reset work to recover from unrecoverable arbitration
errors and stale timeout state.

Signed-off-by: Karunika Choo <karunika.choo@arm.com>
---
v1:
- Move grant, stop and close operations from workqueues into IRQ-safe
  paths. Retains work for scheduler recovery.
- Add closing phase and timer to ensure CLOSE_WINDOW completes in due
  time, otherwise enter recovery handling.
- Rename "grant_timeout_us" to "request_timeout" and "yield_timeout_us"
  to "yield_timeout". Both units are now in milliseconds.
- Add ABI documentation

 .../testing/sysfs-driver-panthor-arbitration  |  18 +
 MAINTAINERS                                   |   1 +
 drivers/gpu/drm/panthor/arbitration/Makefile  |   1 +
 .../panthor/arbitration/panthor_arbitration.h |  12 +
 .../arbitration/panthor_arbitration_drv.c     |  47 +-
 .../arbitration/panthor_arbitration_sched.c   | 729 ++++++++++++++++++
 .../arbitration/panthor_arbitration_sched.h   |  39 +
 7 files changed, 843 insertions(+), 4 deletions(-)
 create mode 100644 Documentation/ABI/testing/sysfs-driver-panthor-arbitration
 create mode 100644 drivers/gpu/drm/panthor/arbitration/panthor_arbitration_sched.c
 create mode 100644 drivers/gpu/drm/panthor/arbitration/panthor_arbitration_sched.h

diff --git a/Documentation/ABI/testing/sysfs-driver-panthor-arbitration b/Documentation/ABI/testing/sysfs-driver-panthor-arbitration
new file mode 100644
index 0000000000000..fbd21270a2412
--- /dev/null
+++ b/Documentation/ABI/testing/sysfs-driver-panthor-arbitration
@@ -0,0 +1,18 @@
+What:		/sys/module/panthor_arbitration/parameters/request_timeout
+Date:		September 2026
+KernelVersion:	7.2.0
+Contact:	Arm Ltd.
+Description:
+		Controls how long, in milliseconds, the arbitration scheduler
+		allows an access window to keep the GPU before asking it to
+		yield when another access window is waiting.
+
+What:		/sys/module/panthor_arbitration/parameters/yield_timeout
+Date:		September 2026
+KernelVersion:	7.2.0
+Contact:	Arm Ltd.
+Description:
+		Controls how long, in milliseconds, the arbitration scheduler
+		waits for an access window to yield the GPU after a stop request.
+		If the timeout expires, the scheduler force-closes the access
+		window.
diff --git a/MAINTAINERS b/MAINTAINERS
index 377156650580c..af7da4c08bf8a 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2324,6 +2324,7 @@ M:	Liviu Dudau <liviu.dudau@arm.com>
 L:	dri-devel@lists.freedesktop.org
 S:	Supported
 T:	git https://gitlab.freedesktop.org/drm/misc/kernel.git
+F:	Documentation/ABI/testing/sysfs-driver-panthor-arbitration
 F:	Documentation/devicetree/bindings/gpu/arm,mali-gen5-am-*.yaml
 F:	Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml
 F:	drivers/gpu/drm/ci/xfails/panthor*
diff --git a/drivers/gpu/drm/panthor/arbitration/Makefile b/drivers/gpu/drm/panthor/arbitration/Makefile
index 2d2684321d978..22ed68948fee3 100644
--- a/drivers/gpu/drm/panthor/arbitration/Makefile
+++ b/drivers/gpu/drm/panthor/arbitration/Makefile
@@ -4,6 +4,7 @@
 obj-$(CONFIG_DRM_PANTHOR_ARBITRATION) += panthor_arbitration.o
 panthor_arbitration-y := \
 	panthor_arbitration_drv.o \
+	panthor_arbitration_sched.o \
 	panthor_partition_control.o \
 	panthor_resource_group.o
 
diff --git a/drivers/gpu/drm/panthor/arbitration/panthor_arbitration.h b/drivers/gpu/drm/panthor/arbitration/panthor_arbitration.h
index dfeab1b078d06..eeae8219b2894 100644
--- a/drivers/gpu/drm/panthor/arbitration/panthor_arbitration.h
+++ b/drivers/gpu/drm/panthor/arbitration/panthor_arbitration.h
@@ -6,8 +6,10 @@
 
 #include <linux/ioport.h>
 #include <linux/fwnode.h>
+#include <linux/types.h>
 
 struct device;
+struct panthor_arbitration_sched;
 struct panthor_partition_control;
 struct panthor_resource_group;
 
@@ -31,15 +33,25 @@ struct panthor_arbitration {
 	/** @dev: Device pointer */
 	struct device *dev;
 
+	/** @tearing_down: Driver remove in progress */
+	bool tearing_down;
+
 	/** @pc: Pointer array to partition control data */
 	struct panthor_partition_control *pc[AM_ARB_MAX_PC_COUNT];
 
 	/** @rg: Pointer array to resource group data */
 	struct panthor_resource_group *rg[AM_ARB_MAX_RG_COUNT];
+
+	/** @sched: Pointer to scheduler data. 1 sched per partition */
+	struct panthor_arbitration_sched *sched[AM_ARB_MAX_PC_COUNT];
 };
 
 int panthor_arbitration_parse_resource(struct device *dev,
 				       const struct fwnode_handle *child,
 				       struct panthor_arbitration_resource *res);
 
+int panthor_arbitration_on_grant(struct panthor_arbitration *adev, u8 aw_id);
+int panthor_arbitration_on_stop(struct panthor_arbitration *adev, u8 aw_id);
+int panthor_arbitration_on_close(struct panthor_arbitration *adev, u8 aw_id);
+
 #endif
diff --git a/drivers/gpu/drm/panthor/arbitration/panthor_arbitration_drv.c b/drivers/gpu/drm/panthor/arbitration/panthor_arbitration_drv.c
index a1068a2c78f1a..2d0c8d95f1abd 100644
--- a/drivers/gpu/drm/panthor/arbitration/panthor_arbitration_drv.c
+++ b/drivers/gpu/drm/panthor/arbitration/panthor_arbitration_drv.c
@@ -11,6 +11,7 @@
 #include <linux/of.h>
 
 #include "panthor_arbitration.h"
+#include "panthor_arbitration_sched.h"
 #include "panthor_partition_control.h"
 #include "panthor_resource_group.h"
 
@@ -56,6 +57,13 @@ static int panthor_arbitration_runtime_suspend(struct device *dev)
 	struct panthor_arbitration *adev = dev_get_drvdata(dev);
 	int ret = 0;
 
+	if (adev->tearing_down)
+		return 0;
+
+	ret = panthor_arbitration_sched_suspend(adev);
+	if (ret)
+		return ret;
+
 	ret = panthor_resource_group_suspend(adev);
 	if (ret)
 		return ret;
@@ -80,6 +88,26 @@ static int panthor_arbitration_runtime_resume(struct device *dev)
 	if (ret)
 		return ret;
 
+	ret = panthor_arbitration_sched_resume(adev);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+/* Arbiter to AW events */
+int panthor_arbitration_on_grant(struct panthor_arbitration *adev, u8 aw_id)
+{
+	return 0;
+}
+
+int panthor_arbitration_on_stop(struct panthor_arbitration *adev, u8 aw_id)
+{
+	return 0;
+}
+
+int panthor_arbitration_on_close(struct panthor_arbitration *adev, u8 aw_id)
+{
 	return 0;
 }
 
@@ -116,6 +144,10 @@ static int panthor_arbitration_probe(struct platform_device *pdev)
 	if (ret)
 		goto err_term_rg;
 
+	ret = panthor_arbitration_sched_init(adev);
+	if (ret)
+		goto err_term_sched;
+
 	ret = of_platform_populate(dev->of_node, NULL, NULL, dev);
 	if (ret)
 		goto err_depopulate;
@@ -129,6 +161,8 @@ static int panthor_arbitration_probe(struct platform_device *pdev)
 
 err_depopulate:
 	of_platform_depopulate(dev);
+err_term_sched:
+	panthor_arbitration_sched_term(adev);
 err_term_rg:
 	panthor_resource_group_cancel_work(adev);
 	panthor_resource_group_term(adev);
@@ -151,15 +185,20 @@ static void panthor_arbitration_remove(struct platform_device *pdev)
 		dev_warn(adev->dev, "failed to resume during remove: %d", ret);
 
 	of_platform_depopulate(adev->dev);
-	panthor_resource_group_cancel_work(adev);
 
 	if (ret >= 0) {
+		adev->tearing_down = true;
+
+		panthor_arbitration_sched_term(adev);
+		panthor_resource_group_cancel_work(adev);
 		panthor_resource_group_term(adev);
 		panthor_partition_control_term(adev);
-		pm_runtime_put_noidle(adev->dev);
+		pm_runtime_put_sync_suspend(adev->dev);
+	} else {
+		panthor_arbitration_sched_cancel(adev);
+		panthor_resource_group_cancel_work(adev);
+		pm_runtime_set_suspended(adev->dev);
 	}
-
-	pm_runtime_set_suspended(adev->dev);
 }
 
 static const struct dev_pm_ops panthor_arbitration_pm_ops = {
diff --git a/drivers/gpu/drm/panthor/arbitration/panthor_arbitration_sched.c b/drivers/gpu/drm/panthor/arbitration/panthor_arbitration_sched.c
new file mode 100644
index 0000000000000..41f06af92ce0c
--- /dev/null
+++ b/drivers/gpu/drm/panthor/arbitration/panthor_arbitration_sched.c
@@ -0,0 +1,729 @@
+// SPDX-License-Identifier: GPL-2.0 or MIT
+/* Copyright 2026 ARM Limited. All rights reserved. */
+
+#include <linux/bits.h>
+#include <linux/device.h>
+#include <linux/kfifo.h>
+#include <linux/moduleparam.h>
+#include <linux/time.h>
+#include <linux/types.h>
+
+#include "panthor_arbitration.h"
+#include "panthor_arbitration_sched.h"
+#include "panthor_resource_group.h"
+
+static u64 request_timeout = 1 * MSEC_PER_SEC;
+static u64 yield_timeout = 1 * MSEC_PER_SEC;
+
+module_param(request_timeout, ullong, 0644);
+MODULE_PARM_DESC(request_timeout, "Time the GPU will be granted to the AW in milliseconds.");
+
+module_param(yield_timeout, ullong, 0644);
+MODULE_PARM_DESC(yield_timeout, "Time, in milliseconds, within which the AW must yield the GPU.");
+
+enum arbitration_sched_phase {
+	ARB_SCHED_PHASE_IDLE = 0,
+	ARB_SCHED_PHASE_GRANTING,
+	ARB_SCHED_PHASE_GRANTED,
+	ARB_SCHED_PHASE_STOPPING,
+	ARB_SCHED_PHASE_CLOSING,
+	ARB_SCHED_PHASE_LOST,
+};
+
+struct panthor_arbitration_timer {
+	/** @timer: High-resolution timer */
+	struct hrtimer timer;
+
+	/** @epoch: The lease generation for which the timer was triggered */
+	u32 epoch;
+};
+
+struct panthor_arbitration_work {
+	/** @work: Work struct */
+	struct work_struct work;
+
+	/** @aw_id: Window for which the work was queued */
+	u8 aw_id;
+
+	/** @epoch: The lease generation for which the work was queued */
+	u32 epoch;
+};
+
+struct panthor_arbitration_sched {
+	/** @dev: Device pointer */
+	struct device *dev;
+
+	/** @name: Scheduler name */
+	char *name;
+
+	/** @waitqueue: Event wait queue. Not IRQ safe */
+	wait_queue_head_t waitqueue;
+
+	/** @lock: Protects scheduler state */
+	spinlock_t lock;
+
+	/** @queue: Pending request FIFO */
+	DECLARE_KFIFO(queue, u8, 16);
+
+	/** @queued_mask: Mask of currently queued AWs */
+	DECLARE_BITMAP(queued_mask, AM_ARB_MAX_AW_COUNT);
+
+	/** @active_aw_id: Currently active AW. Can be -1 */
+	s8 active_aw_id;
+
+	/** @phase: Current scheduling phase */
+	enum arbitration_sched_phase phase;
+
+	/** @epoch: Current active lease generation */
+	u32 epoch;
+
+	/** @wq: Scheduler workqueue to dispatch events */
+	struct workqueue_struct *wq;
+
+	/** @reset_work: Work to reset the scheduler */
+	struct panthor_arbitration_work reset_work;
+
+	/** @grant_timer: Timer to indicate grant window has lapsed */
+	struct panthor_arbitration_timer grant_timer;
+
+	/** @stop_timer: Timer to indicate yield window has lapsed */
+	struct panthor_arbitration_timer stop_timer;
+
+	/** @close_timer: Timer to indicate close window has lapsed */
+	struct panthor_arbitration_timer close_timer;
+
+	/** @disabled: Scheduler disabled. No further scheduling can happen */
+	u32 disabled;
+
+	/**
+	 * @grant_previously_expired: Grant period previously expired but was
+	 * not asked to stop
+	 */
+	bool grant_previously_expired;
+};
+
+static int arb_sched_on_stopped_locked(struct panthor_arbitration_sched *sched, u8 aw_id);
+
+static inline struct panthor_arbitration *
+to_adev(struct panthor_arbitration_sched *sched)
+{
+	return dev_get_drvdata(sched->dev);
+}
+
+static inline struct panthor_arbitration_work *to_work(struct work_struct *w)
+{
+	return container_of(w, struct panthor_arbitration_work, work);
+}
+
+static bool arb_sched_phase_reached(struct panthor_arbitration_sched *sched,
+				    enum arbitration_sched_phase phase)
+{
+	guard(spinlock_irqsave)(&sched->lock);
+
+	return sched->phase == phase;
+}
+
+/* This method is not IRQ safe as it sleeps. */
+static int arb_sched_wait_phase(struct panthor_arbitration_sched *sched,
+				enum arbitration_sched_phase phase,
+				u64 timeout_ms)
+{
+	if (!wait_event_timeout(
+		    sched->waitqueue, arb_sched_phase_reached(sched, phase),
+		    msecs_to_jiffies(timeout_ms))) {
+
+		if (!arb_sched_phase_reached(sched, phase))
+			return -ETIMEDOUT;
+	}
+
+	return 0;
+}
+
+static void arb_sched_queue_work(struct panthor_arbitration_sched *sched,
+				 struct panthor_arbitration_work *work)
+{
+	lockdep_assert_held(&sched->lock);
+
+	work->aw_id = sched->active_aw_id;
+	work->epoch = sched->epoch;
+	queue_work(sched->wq, &work->work);
+}
+
+static int __arb_sched_stop_locked(struct panthor_arbitration_sched *sched)
+{
+	int ret;
+
+	lockdep_assert_held(&sched->lock);
+
+	ret = panthor_arbitration_on_stop(to_adev(sched), sched->active_aw_id);
+	if (ret) {
+		dev_err(sched->dev, "%s: Failed to send yield to AW%u",
+			sched->name, sched->active_aw_id);
+
+		arb_sched_queue_work(sched, &sched->reset_work);
+	}
+
+	return ret;
+}
+
+static void arb_sched_stop_locked(struct panthor_arbitration_sched *sched)
+{
+	int ret;
+
+	lockdep_assert_held(&sched->lock);
+
+	ret = __arb_sched_stop_locked(sched);
+	if (!ret) {
+		if (sched->phase != ARB_SCHED_PHASE_STOPPING) {
+			dev_warn(sched->dev, "%s: Stop ACKED when not yielding",
+				 sched->name);
+			return;
+		}
+
+		sched->stop_timer.epoch = sched->epoch;
+		hrtimer_start(&sched->stop_timer.timer,
+			      ms_to_ktime(yield_timeout), HRTIMER_MODE_REL);
+	}
+}
+
+static void arb_sched_grant_locked(struct panthor_arbitration_sched *sched)
+{
+	int ret;
+
+	lockdep_assert_held(&sched->lock);
+
+	ret = panthor_arbitration_on_grant(to_adev(sched), sched->active_aw_id);
+	if (!ret) {
+		if (sched->phase != ARB_SCHED_PHASE_GRANTING) {
+			dev_warn(sched->dev, "%s: Grant ACKED when not granting",
+				 sched->name);
+			return;
+		}
+
+		if (sched->disabled) {
+			sched->phase = ARB_SCHED_PHASE_STOPPING;
+			arb_sched_stop_locked(sched);
+		} else {
+			sched->phase = ARB_SCHED_PHASE_GRANTED;
+
+			sched->grant_timer.epoch = sched->epoch;
+			hrtimer_start(&sched->grant_timer.timer,
+				      ms_to_ktime(request_timeout),
+				      HRTIMER_MODE_REL);
+		}
+
+		wake_up_all(&sched->waitqueue);
+	} else if (ret < 0) {
+		dev_err(sched->dev, "%s: Failed to grant access to AW%u",
+			sched->name, sched->active_aw_id);
+
+		arb_sched_queue_work(sched, &sched->reset_work);
+	}
+}
+
+static int __arb_sched_close_locked(struct panthor_arbitration_sched *sched)
+{
+	int ret;
+
+	lockdep_assert_held(&sched->lock);
+
+	ret = panthor_arbitration_on_close(to_adev(sched), sched->active_aw_id);
+	if (ret < 0) {
+		dev_err(sched->dev, "%s: Failed to close AW%u", sched->name,
+			sched->active_aw_id);
+
+		arb_sched_queue_work(sched, &sched->reset_work);
+	}
+
+	return ret;
+}
+
+static void arb_sched_close_locked(struct panthor_arbitration_sched *sched)
+{
+	int ret;
+
+	lockdep_assert_held(&sched->lock);
+
+	ret = __arb_sched_close_locked(sched);
+	if (!ret) {
+		sched->close_timer.epoch = sched->epoch;
+		hrtimer_start(&sched->close_timer.timer,
+			      ms_to_ktime(yield_timeout), HRTIMER_MODE_REL);
+	} else if (ret > 0) {
+		/*
+		 * Window alread closed. We need to manually transition the
+		 * phase back to IDLE.
+		 */
+		arb_sched_on_stopped_locked(sched, sched->active_aw_id);
+	}
+}
+
+static void arb_sched_request_stop_locked(struct panthor_arbitration_sched *sched)
+{
+	lockdep_assert_held(&sched->lock);
+
+	if (sched->phase != ARB_SCHED_PHASE_GRANTED)
+		return;
+
+	if (sched->active_aw_id < 0)
+		return;
+
+	/*
+	 * In the event of a single requesting AW, let it continue to
+	 * lease the GPU until another request comes in.
+	 */
+	if (!sched->disabled && kfifo_is_empty(&sched->queue)) {
+		sched->grant_previously_expired = true;
+		return;
+	}
+
+	sched->phase = ARB_SCHED_PHASE_STOPPING;
+	arb_sched_stop_locked(sched);
+
+	wake_up_all(&sched->waitqueue);
+}
+
+static void arb_sched_request_stop(struct panthor_arbitration_sched *sched)
+{
+	guard(spinlock_irqsave)(&sched->lock);
+
+	arb_sched_request_stop_locked(sched);
+}
+
+static void arb_sched_force_close_locked(struct panthor_arbitration_sched *sched)
+{
+	lockdep_assert_held(&sched->lock);
+
+	if (sched->phase == ARB_SCHED_PHASE_IDLE)
+		return;
+
+	if (sched->active_aw_id < 0)
+		return;
+
+	sched->phase = ARB_SCHED_PHASE_LOST;
+
+	arb_sched_close_locked(sched);
+
+	wake_up_all(&sched->waitqueue);
+}
+
+static void arb_sched_force_close(struct panthor_arbitration_sched *sched)
+{
+	scoped_guard(spinlock_irqsave, &sched->lock)
+		arb_sched_force_close_locked(sched);
+
+	arb_sched_wait_phase(sched, ARB_SCHED_PHASE_IDLE,
+			     request_timeout + yield_timeout);
+}
+
+static int arb_sched_next_locked(struct panthor_arbitration_sched *sched)
+{
+	u8 aw_id;
+
+	lockdep_assert_held(&sched->lock);
+
+	if (sched->disabled)
+		return 0;
+
+	/* already have a running aw */
+	if (sched->active_aw_id >= 0)
+		return 0;
+
+	/* nothing to schedule */
+	if (kfifo_is_empty(&sched->queue))
+		return 0;
+
+	if (!kfifo_get(&sched->queue, &aw_id)) {
+		dev_warn(sched->dev, "%s: queue unexpectedly empty",
+				sched->name);
+		return -EINVAL;
+	}
+
+	clear_bit(aw_id, sched->queued_mask);
+
+	sched->active_aw_id = aw_id;
+	sched->epoch++;
+	sched->phase = ARB_SCHED_PHASE_GRANTING;
+
+	arb_sched_grant_locked(sched);
+
+	wake_up_all(&sched->waitqueue);
+
+	return 0;
+}
+
+static int arb_sched_next(struct panthor_arbitration_sched *sched)
+{
+	guard(spinlock_irqsave)(&sched->lock);
+
+	return arb_sched_next_locked(sched);
+}
+
+static void arb_sched_reset_work(struct work_struct *work)
+{
+	struct panthor_arbitration_work *w = to_work(work);
+	struct panthor_arbitration_sched *sched =
+		container_of(w, struct panthor_arbitration_sched, reset_work);
+
+	guard(spinlock_irqsave)(&sched->lock);
+	if (sched->epoch != w->epoch)
+		return;
+
+	if (sched->active_aw_id != w->aw_id)
+		return;
+
+	dev_warn(sched->dev, "%s: scheduler reset. active_aw=%u",
+			sched->name, sched->active_aw_id);
+
+	arb_sched_force_close_locked(sched);
+}
+
+static enum hrtimer_restart
+panthor_arbitration_sched_on_stop_timeout(struct hrtimer *timer)
+{
+	struct panthor_arbitration_timer *atmr = container_of(
+		timer, struct panthor_arbitration_timer, timer);
+	struct panthor_arbitration_sched *sched = container_of(
+		atmr, struct panthor_arbitration_sched, stop_timer);
+
+	guard(spinlock_irqsave)(&sched->lock);
+
+	if (sched->epoch != atmr->epoch ||
+	    sched->phase != ARB_SCHED_PHASE_STOPPING)
+		return HRTIMER_NORESTART;
+
+	dev_warn(sched->dev,
+		 "%s: AW%d failed to stop in time. Force closing...",
+		 sched->name, sched->active_aw_id);
+	arb_sched_force_close_locked(sched);
+
+	return HRTIMER_NORESTART;
+}
+
+static enum hrtimer_restart
+panthor_arbitration_sched_on_grant_timeout(struct hrtimer *timer)
+{
+	struct panthor_arbitration_timer *atmr = container_of(
+		timer, struct panthor_arbitration_timer, timer);
+	struct panthor_arbitration_sched *sched = container_of(
+		atmr, struct panthor_arbitration_sched, grant_timer);
+
+	guard(spinlock_irqsave)(&sched->lock);
+
+	if (sched->epoch != atmr->epoch)
+		return HRTIMER_NORESTART;
+
+	arb_sched_request_stop_locked(sched);
+
+	return HRTIMER_NORESTART;
+}
+
+static enum hrtimer_restart
+panthor_arbitration_sched_on_close_timeout(struct hrtimer *timer)
+{
+	struct panthor_arbitration_timer *atmr = container_of(
+		timer, struct panthor_arbitration_timer, timer);
+	struct panthor_arbitration_sched *sched = container_of(
+		atmr, struct panthor_arbitration_sched, close_timer);
+
+	guard(spinlock_irqsave)(&sched->lock);
+
+	if (sched->epoch != atmr->epoch)
+		return HRTIMER_NORESTART;
+
+	if (sched->phase != ARB_SCHED_PHASE_CLOSING &&
+	    sched->phase != ARB_SCHED_PHASE_LOST)
+		return HRTIMER_NORESTART;
+
+	dev_warn(sched->dev,
+		 "%s: AW%d failed to close in time. Resetting scheduler...",
+		 sched->name, sched->active_aw_id);
+
+	arb_sched_queue_work(sched, &sched->reset_work);
+
+	return HRTIMER_NORESTART;
+}
+
+int panthor_arbitration_sched_on_request(struct panthor_arbitration_sched *sched, u8 aw_id)
+{
+	guard(spinlock_irqsave)(&sched->lock);
+
+	if (aw_id >= AM_ARB_MAX_AW_COUNT)
+		return -EINVAL;
+
+	if (test_bit(aw_id, sched->queued_mask) ||
+	    (sched->active_aw_id == aw_id &&
+	     sched->phase != ARB_SCHED_PHASE_STOPPING)) {
+		dev_warn(sched->dev, "%s: AW%u already in request queue.",
+			 sched->name, aw_id);
+		return -EEXIST;
+	}
+
+	/* Always put onto queue */
+	if (!kfifo_put(&sched->queue, aw_id)) {
+		dev_err(sched->dev, "%s: request queue unexpectedly full",
+			sched->name);
+		return -ENOSPC;
+	}
+	set_bit(aw_id, sched->queued_mask);
+
+	/* No active AW, schedule next AW */
+	if (sched->active_aw_id < 0)
+		return arb_sched_next_locked(sched);
+
+	/*
+	 * Grant timer for the current AW has previously expired, request it to
+	 * yield the GPU.
+	 */
+	if (sched->grant_previously_expired)
+		arb_sched_request_stop_locked(sched);
+
+	return 0;
+}
+
+int panthor_arbitration_sched_on_idle(struct panthor_arbitration_sched *sched, u8 aw_id)
+{
+	guard(spinlock_irqsave)(&sched->lock);
+
+	if (aw_id >= AM_ARB_MAX_AW_COUNT)
+		return -EINVAL;
+
+	if (sched->active_aw_id != aw_id)
+		return 0;
+
+	if (sched->phase != ARB_SCHED_PHASE_GRANTED &&
+	    sched->phase != ARB_SCHED_PHASE_STOPPING)
+		return 0;
+
+	sched->phase = ARB_SCHED_PHASE_CLOSING;
+	arb_sched_close_locked(sched);
+
+	return 0;
+}
+
+static int arb_sched_on_stopped_locked(struct panthor_arbitration_sched *sched, u8 aw_id)
+{
+	if (aw_id >= AM_ARB_MAX_AW_COUNT)
+		return -EINVAL;
+
+	if (sched->phase == ARB_SCHED_PHASE_IDLE)
+		return 0;
+
+	if (sched->active_aw_id != aw_id)
+		return 0;
+
+	/* retire old lease */
+	sched->epoch++;
+
+	sched->grant_previously_expired = false;
+	sched->active_aw_id = -1;
+	sched->phase = ARB_SCHED_PHASE_IDLE;
+
+	wake_up_all(&sched->waitqueue);
+
+	return arb_sched_next_locked(sched);
+}
+
+int panthor_arbitration_sched_on_stopped(struct panthor_arbitration_sched *sched, u8 aw_id)
+{
+	guard(spinlock_irqsave)(&sched->lock);
+
+	return arb_sched_on_stopped_locked(sched, aw_id);
+}
+
+static void arbitration_sched_disable_work(struct panthor_arbitration_sched *sched)
+{
+	disable_work_sync(&sched->reset_work.work);
+}
+
+void panthor_arbitration_sched_cancel(struct panthor_arbitration *adev)
+{
+	for (int i = 0; i < AM_ARB_MAX_PC_COUNT; i++) {
+		struct panthor_arbitration_sched *sched = adev->sched[i];
+
+		if (!sched)
+			continue;
+
+		panthor_arbitration_sched_disable_set(sched, ARB_SCHED_DISABLE_PM);
+		hrtimer_cancel(&sched->grant_timer.timer);
+		hrtimer_cancel(&sched->stop_timer.timer);
+		hrtimer_cancel(&sched->close_timer.timer);
+		arbitration_sched_disable_work(sched);
+	}
+}
+
+static void arbitration_sched_term(struct panthor_arbitration_sched *sched)
+{
+	panthor_arbitration_sched_disable_set(sched, ARB_SCHED_DISABLE_TERM);
+
+	WARN_ON(panthor_arbitration_sched_stop(sched));
+
+	arbitration_sched_disable_work(sched);
+}
+
+static int arbitration_sched_init(struct panthor_arbitration *adev, int i)
+{
+	struct device *dev = adev->dev;
+	struct panthor_arbitration_sched *sched;
+
+	sched = devm_kzalloc(dev, sizeof(*sched), GFP_KERNEL);
+	if (!sched)
+		return -ENOMEM;
+
+	sched->name = devm_kasprintf(dev, GFP_KERNEL, "sched%d", i);
+	sched->dev = dev;
+
+	sched->wq = devm_alloc_ordered_workqueue(dev, "%s-wq", 0, sched->name);
+	if (!sched->wq)
+		return -ENOMEM;
+
+	INIT_WORK(&sched->reset_work.work, arb_sched_reset_work);
+
+	init_waitqueue_head(&sched->waitqueue);
+
+	spin_lock_init(&sched->lock);
+	INIT_KFIFO(sched->queue);
+	sched->active_aw_id = -1;
+	sched->phase = ARB_SCHED_PHASE_IDLE;
+
+	hrtimer_setup(&sched->grant_timer.timer,
+		      panthor_arbitration_sched_on_grant_timeout,
+		      CLOCK_MONOTONIC, HRTIMER_MODE_REL);
+	hrtimer_setup(&sched->stop_timer.timer,
+		      panthor_arbitration_sched_on_stop_timeout,
+		      CLOCK_MONOTONIC, HRTIMER_MODE_REL);
+	hrtimer_setup(&sched->close_timer.timer,
+		      panthor_arbitration_sched_on_close_timeout,
+		      CLOCK_MONOTONIC, HRTIMER_MODE_REL);
+
+	adev->sched[i] = sched;
+
+	return 0;
+}
+
+void panthor_arbitration_sched_term(struct panthor_arbitration *adev)
+{
+	for (int i = 0; i < AM_ARB_MAX_PC_COUNT; i++) {
+		struct panthor_arbitration_sched *sched = adev->sched[i];
+
+		if (!sched)
+			continue;
+
+		arbitration_sched_term(sched);
+	}
+}
+
+int panthor_arbitration_sched_init(struct panthor_arbitration *adev)
+{
+
+	for (int i = 0; i < AM_ARB_MAX_PC_COUNT; i++) {
+		int ret = arbitration_sched_init(adev, i);
+
+		if (ret == -ENODEV)
+			continue;
+
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
+int panthor_arbitration_sched_suspend(struct panthor_arbitration *adev)
+{
+	for (int i = 0; i < AM_ARB_MAX_PC_COUNT; i++) {
+		struct panthor_arbitration_sched *sched = adev->sched[i];
+		int ret;
+
+		if (!sched)
+			continue;
+
+		panthor_arbitration_sched_disable_set(sched, ARB_SCHED_DISABLE_PM);
+		ret = panthor_arbitration_sched_stop(sched);
+		if (ret) {
+			panthor_arbitration_sched_disable_clear(
+				sched, ARB_SCHED_DISABLE_PM);
+			return ret;
+		}
+	}
+
+	return 0;
+}
+
+int panthor_arbitration_sched_resume(struct panthor_arbitration *adev)
+{
+	for (int i = 0; i < AM_ARB_MAX_PC_COUNT; i++) {
+		struct panthor_arbitration_sched *sched = adev->sched[i];
+		int ret;
+
+		if (!sched)
+			continue;
+
+		panthor_arbitration_sched_disable_clear(sched, ARB_SCHED_DISABLE_PM);
+		ret = panthor_arbitration_sched_start(sched);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
+/**
+ * panthor_arbitration_sched_stop - Stop active aw and pause scheduler
+ *
+ * @sched: Pointer to arbitration scheduler
+ *
+ * This method is not IRQ safe as it waits for on_stopped() to be called.
+ */
+int panthor_arbitration_sched_stop(struct panthor_arbitration_sched *sched)
+{
+	int ret;
+
+	arb_sched_request_stop(sched);
+
+	/*
+	 * Provisionally waiting for up to 2x yield_timeout, but path may
+	 * include time taken for panthor_arbitration_on_grant() to complete
+	 * if sched_request_stop() is called while in the GRANTING state.
+	 *
+	 * Realistically, if granting takes more than yield_timeout, HW is in
+	 * bad state either way. Best continue and stop the scheduler.
+	 */
+	ret = arb_sched_wait_phase(sched, ARB_SCHED_PHASE_IDLE,
+				   request_timeout + yield_timeout);
+	if (ret)
+		arb_sched_force_close(sched);
+
+	/* Should no longer have any further activity. Cancel timer. */
+	hrtimer_cancel(&sched->grant_timer.timer);
+	hrtimer_cancel(&sched->stop_timer.timer);
+	hrtimer_cancel(&sched->close_timer.timer);
+	flush_workqueue(sched->wq);
+
+	scoped_guard(spinlock_irqsave, &sched->lock)
+		if (sched->phase == ARB_SCHED_PHASE_IDLE)
+			return 0;
+
+	return ret;
+}
+
+int panthor_arbitration_sched_start(struct panthor_arbitration_sched *sched)
+{
+	return arb_sched_next(sched);
+}
+
+void panthor_arbitration_sched_disable_set(struct panthor_arbitration_sched *sched,
+					   enum panthor_arb_sched_disable_reason reason)
+{
+	guard(spinlock_irqsave)(&sched->lock);
+
+	sched->disabled |= BIT(reason);
+}
+
+void panthor_arbitration_sched_disable_clear(struct panthor_arbitration_sched *sched,
+					     enum panthor_arb_sched_disable_reason reason)
+{
+	guard(spinlock_irqsave)(&sched->lock);
+
+	sched->disabled &= ~BIT(reason);
+}
diff --git a/drivers/gpu/drm/panthor/arbitration/panthor_arbitration_sched.h b/drivers/gpu/drm/panthor/arbitration/panthor_arbitration_sched.h
new file mode 100644
index 0000000000000..f1f50316a2fff
--- /dev/null
+++ b/drivers/gpu/drm/panthor/arbitration/panthor_arbitration_sched.h
@@ -0,0 +1,39 @@
+/* SPDX-License-Identifier: GPL-2.0 or MIT */
+/* Copyright 2026 ARM Limited. All rights reserved. */
+
+#ifndef __PANTHOR_ARBITRATION_SCHED_H__
+#define __PANTHOR_ARBITRATION_SCHED_H__
+
+#include <linux/types.h>
+
+struct panthor_arbitration;
+struct panthor_arbitration_sched;
+
+enum panthor_arb_sched_disable_reason {
+	/** @ARB_SCHED_DISABLE_PM: scheduler disabled due to PM suspend */
+	ARB_SCHED_DISABLE_PM = 0,
+
+	/** @ARB_SCHED_DISABLE_TERM: scheduler disabled for termination */
+	ARB_SCHED_DISABLE_TERM,
+};
+
+int panthor_arbitration_sched_init(struct panthor_arbitration *adev);
+void panthor_arbitration_sched_term(struct panthor_arbitration *adev);
+void panthor_arbitration_sched_cancel(struct panthor_arbitration *adev);
+
+int panthor_arbitration_sched_suspend(struct panthor_arbitration *adev);
+int panthor_arbitration_sched_resume(struct panthor_arbitration *adev);
+
+int panthor_arbitration_sched_stop(struct panthor_arbitration_sched *sched);
+int panthor_arbitration_sched_start(struct panthor_arbitration_sched *sched);
+
+void panthor_arbitration_sched_disable_set(struct panthor_arbitration_sched *sched,
+					   enum panthor_arb_sched_disable_reason reason);
+void panthor_arbitration_sched_disable_clear(struct panthor_arbitration_sched *sched,
+					     enum panthor_arb_sched_disable_reason reason);
+
+int panthor_arbitration_sched_on_request(struct panthor_arbitration_sched *sched, u8 aw_id);
+int panthor_arbitration_sched_on_idle(struct panthor_arbitration_sched *sched, u8 aw_id);
+int panthor_arbitration_sched_on_stopped(struct panthor_arbitration_sched *sched, u8 aw_id);
+
+#endif
-- 
2.43.0

[PATCH v1 17/27] drm/panthor: Route arbitration events

[Karunika Choo]

Wire the resource-group, scheduler, and partition-control blocks
together. Resource-group messages now feed request and idle events into
the scheduler, while partition RESET_DONE from a YIELD_DONE or
CLOSE_WINDOW reports the active access window as stopped.

Add the arbiter-to-window callbacks used by the scheduler to grant,
yield, and close partition windows.

Signed-off-by: Karunika Choo <karunika.choo@arm.com>
---
v1:
- Notify arbitration scheduler when RESET_DONE completes due to
  close_window, as well as due to yield by Panthor FW.

 .../panthor/arbitration/panthor_arbitration.h |  6 ++++
 .../arbitration/panthor_arbitration_drv.c     | 28 +++++++++++++++++--
 .../arbitration/panthor_partition_control.c   |  9 ++++++
 .../arbitration/panthor_resource_group.c      |  4 +--
 4 files changed, 42 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/panthor/arbitration/panthor_arbitration.h b/drivers/gpu/drm/panthor/arbitration/panthor_arbitration.h
index eeae8219b2894..149221333eb1e 100644
--- a/drivers/gpu/drm/panthor/arbitration/panthor_arbitration.h
+++ b/drivers/gpu/drm/panthor/arbitration/panthor_arbitration.h
@@ -50,6 +50,12 @@ int panthor_arbitration_parse_resource(struct device *dev,
 				       const struct fwnode_handle *child,
 				       struct panthor_arbitration_resource *res);
 
+/* AW to Arbiter events */
+int panthor_arbitration_on_request(struct panthor_arbitration *adev, u8 aw_id);
+int panthor_arbitration_on_idle(struct panthor_arbitration *adev, u8 aw_id);
+int panthor_arbitration_on_stopped(struct panthor_arbitration *adev, u8 aw_id);
+
+/* Arbiter to AW events */
 int panthor_arbitration_on_grant(struct panthor_arbitration *adev, u8 aw_id);
 int panthor_arbitration_on_stop(struct panthor_arbitration *adev, u8 aw_id);
 int panthor_arbitration_on_close(struct panthor_arbitration *adev, u8 aw_id);
diff --git a/drivers/gpu/drm/panthor/arbitration/panthor_arbitration_drv.c b/drivers/gpu/drm/panthor/arbitration/panthor_arbitration_drv.c
index 2d0c8d95f1abd..723cf605e16a3 100644
--- a/drivers/gpu/drm/panthor/arbitration/panthor_arbitration_drv.c
+++ b/drivers/gpu/drm/panthor/arbitration/panthor_arbitration_drv.c
@@ -95,20 +95,42 @@ static int panthor_arbitration_runtime_resume(struct device *dev)
 	return 0;
 }
 
+/* AW to Arbiter events */
+int panthor_arbitration_on_request(struct panthor_arbitration *adev, u8 aw_id)
+{
+	/* TODO: AW to PC assignment */
+	return panthor_arbitration_sched_on_request(adev->sched[0], aw_id);
+}
+
+int panthor_arbitration_on_idle(struct panthor_arbitration *adev, u8 aw_id)
+{
+	/* TODO: AW to PC assignment */
+	return panthor_arbitration_sched_on_idle(adev->sched[0], aw_id);
+}
+
+int panthor_arbitration_on_stopped(struct panthor_arbitration *adev, u8 aw_id)
+{
+	/* TODO: AW to PC assignment */
+	return panthor_arbitration_sched_on_stopped(adev->sched[0], aw_id);
+}
+
 /* Arbiter to AW events */
 int panthor_arbitration_on_grant(struct panthor_arbitration *adev, u8 aw_id)
 {
-	return 0;
+	/* TODO: AW to PC assignment */
+	return panthor_partition_control_open_window(adev->pc[0], aw_id);
 }
 
 int panthor_arbitration_on_stop(struct panthor_arbitration *adev, u8 aw_id)
 {
-	return 0;
+	/* TODO: AW to PC assignment */
+	return panthor_partition_control_yield_now(adev->pc[0]);
 }
 
 int panthor_arbitration_on_close(struct panthor_arbitration *adev, u8 aw_id)
 {
-	return 0;
+	/* TODO: AW to PC assignment */
+	return panthor_partition_control_close_window(adev->pc[0]);
 }
 
 static int panthor_arbitration_probe(struct platform_device *pdev)
diff --git a/drivers/gpu/drm/panthor/arbitration/panthor_partition_control.c b/drivers/gpu/drm/panthor/arbitration/panthor_partition_control.c
index e6fbf5e58b51a..95c26015cb637 100644
--- a/drivers/gpu/drm/panthor/arbitration/panthor_partition_control.c
+++ b/drivers/gpu/drm/panthor/arbitration/panthor_partition_control.c
@@ -163,13 +163,22 @@ static int window_open(struct panthor_partition_control *pc, u8 aw_id)
 
 static void partition_handle_reset_done(struct panthor_partition_control *pc)
 {
+	bool notify_stopped = false;
+	int aw_id;
+
 	scoped_guard(spinlock_irqsave, &pc->lock) {
+		aw_id = pc->current_aw;
 		pc->current_aw = -1;
 
 		/* RESET_DONE from CLOSE_WINDOW */
 		if (pc->closing)
 			pc->closing = false;
+		if (aw_id >= 0)
+			notify_stopped = true;
 	}
+
+	if (notify_stopped)
+		panthor_arbitration_on_stopped(dev_get_drvdata(pc->dev), aw_id);
 }
 
 static irqreturn_t partition_irq_raw_handler(int irq, void *data)
diff --git a/drivers/gpu/drm/panthor/arbitration/panthor_resource_group.c b/drivers/gpu/drm/panthor/arbitration/panthor_resource_group.c
index 9bdd0876dd457..ba345233c7db2 100644
--- a/drivers/gpu/drm/panthor/arbitration/panthor_resource_group.c
+++ b/drivers/gpu/drm/panthor/arbitration/panthor_resource_group.c
@@ -140,10 +140,10 @@ static void rg_handle_message(struct panthor_resource_group *rg, u8 aw_id,
 		rg_respond_to_handshake(rg, aw_id, message);
 		break;
 	case VM_ARB_GPU_REQUEST:
-		/* TODO: on_request */
+		panthor_arbitration_on_request(dev_get_drvdata(rg->dev), aw_id);
 		break;
 	case VM_ARB_GPU_STOPPED:
-		/* TODO: on_idle */
+		panthor_arbitration_on_idle(dev_get_drvdata(rg->dev), aw_id);
 		break;
 	default:
 		dev_warn(rg->dev, "Invalid message (0x%llx)", message);
-- 
2.43.0

[PATCH v1 18/27] dt-bindings: gpu: panthor: Document AW assignment DT property

[Karunika Choo]

Introduce arm,access-window-mask property to allow partitions to define
the assigned access windows at probe time.

Signed-off-by: Karunika Choo <karunika.choo@arm.com>
---
 .../bindings/gpu/arm,mali-gen5-am-arbitration.yaml     | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-gen5-am-arbitration.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-gen5-am-arbitration.yaml
index 9ea2b4bb9a344..4e7933829e2be 100644
--- a/Documentation/devicetree/bindings/gpu/arm,mali-gen5-am-arbitration.yaml
+++ b/Documentation/devicetree/bindings/gpu/arm,mali-gen5-am-arbitration.yaml
@@ -52,6 +52,15 @@ patternProperties:
           Hardware partition control index. Must identify a partition present on
           the GPU and be unique among this device's partition nodes.
 
+      arm,access-window-mask:
+        $ref: /schemas/types.yaml#/definitions/uint32
+        maximum: 0xffff
+        default: 0
+        description:
+          Initial access window assignment mask. Bit N selects global
+          access window ID N. Masks must be disjoint across partitions.
+          If omitted, no access windows are assigned by default.
+
     required:
       - reg
       - interrupts
@@ -113,6 +122,7 @@ examples:
             reg = <0x50000 0x10000>;
             interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH 0>;
             arm,id = <0>;
+            arm,access-window-mask = <0xffff>;
         };
 
         resource-group@c0000 {
-- 
2.43.0

[PATCH v1 19/27] drm/panthor: Add AW assignment tracking

[Karunika Choo]

Track the scheduler assignment for each access window using the default
access-window masks parsed from device properties.

Use the mapping to route request, idle, stopped, grant, stop, and close
events through the scheduler associated with the access window, and keep
schedulers disabled while they have no assigned access windows.

Signed-off-by: Karunika Choo <karunika.choo@arm.com>
---
 .../panthor/arbitration/panthor_arbitration.h |  15 ++
 .../arbitration/panthor_arbitration_drv.c     | 201 ++++++++++++++++--
 .../arbitration/panthor_arbitration_sched.c   |   2 +
 .../arbitration/panthor_arbitration_sched.h   |   3 +
 4 files changed, 209 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/panthor/arbitration/panthor_arbitration.h b/drivers/gpu/drm/panthor/arbitration/panthor_arbitration.h
index 149221333eb1e..e1d569158ac6c 100644
--- a/drivers/gpu/drm/panthor/arbitration/panthor_arbitration.h
+++ b/drivers/gpu/drm/panthor/arbitration/panthor_arbitration.h
@@ -7,6 +7,7 @@
 #include <linux/ioport.h>
 #include <linux/fwnode.h>
 #include <linux/types.h>
+#include <linux/mutex.h>
 
 struct device;
 struct panthor_arbitration_sched;
@@ -26,6 +27,11 @@ struct panthor_arbitration_resource {
 	u32 id;
 };
 
+struct panthor_arbitration_dt_info {
+	/** @default_aw_masks: Default per-partition AW assignments */
+	u32 default_aw_masks[AM_ARB_MAX_PC_COUNT];
+};
+
 /**
  * struct panthor_arbitration - Arbitration device
  */
@@ -44,6 +50,15 @@ struct panthor_arbitration {
 
 	/** @sched: Pointer to scheduler data. 1 sched per partition */
 	struct panthor_arbitration_sched *sched[AM_ARB_MAX_PC_COUNT];
+
+	/** @dt_info: Properties parsed from the device tree */
+	struct panthor_arbitration_dt_info dt_info;
+
+	/** @assignment_lock: Protects AW and slice assignment */
+	struct mutex assignment_lock;
+
+	/** @aw_sched_map: Tracks assignment of AW to sched instance */
+	s8 aw_sched_map[AM_ARB_MAX_AW_COUNT];
 };
 
 int panthor_arbitration_parse_resource(struct device *dev,
diff --git a/drivers/gpu/drm/panthor/arbitration/panthor_arbitration_drv.c b/drivers/gpu/drm/panthor/arbitration/panthor_arbitration_drv.c
index 723cf605e16a3..f44cd45ea342e 100644
--- a/drivers/gpu/drm/panthor/arbitration/panthor_arbitration_drv.c
+++ b/drivers/gpu/drm/panthor/arbitration/panthor_arbitration_drv.c
@@ -1,11 +1,13 @@
 // SPDX-License-Identifier: GPL-2.0 or MIT
 /* Copyright 2026 ARM Limited. All rights reserved. */
 
+#include <linux/bits.h>
 #include <linux/module.h>
 #include <linux/of_device.h>
 #include <linux/of_platform.h>
 #include <linux/platform_device.h>
 #include <linux/pm_runtime.h>
+#include <linux/property.h>
 #include <linux/types.h>
 #include <linux/of_address.h>
 #include <linux/of.h>
@@ -17,8 +19,27 @@
 
 #define PANTHOR_PM_AUTOSUSPEND_DELAY_MS 100
 
+#define DT_ASSIGNED_AW				"arm,access-window-mask"
 #define DT_ID					"arm,id"
 
+static int to_assigned_sched_idx(struct panthor_arbitration *adev, u8 aw_id)
+{
+	int idx = -1;
+
+	if (aw_id >= AM_ARB_MAX_AW_COUNT) {
+		dev_err(adev->dev, "Invalid AW ID (%u)", aw_id);
+		return -EINVAL;
+	}
+
+	idx = READ_ONCE(adev->aw_sched_map[aw_id]);
+	if (idx < 0 || idx >= AM_ARB_MAX_PC_COUNT || !adev->sched[idx]) {
+		dev_warn(adev->dev, "AW%u not assigned to any sched", aw_id);
+		return -ENOENT;
+	}
+
+	return idx;
+};
+
 int panthor_arbitration_parse_resource(struct device *dev,
 				       const struct fwnode_handle *child,
 				       struct panthor_arbitration_resource *res)
@@ -95,42 +116,186 @@ static int panthor_arbitration_runtime_resume(struct device *dev)
 	return 0;
 }
 
+static u32 arbitration_get_sched_aw_mask(struct panthor_arbitration *adev,
+					 u8 sched_id)
+{
+	u32 aw_mask = 0;
+
+	lockdep_assert_held(&adev->assignment_lock);
+
+	for (int i = 0; i < AM_ARB_MAX_AW_COUNT; i++) {
+		if (adev->aw_sched_map[i] == sched_id)
+			aw_mask |= BIT(i);
+	}
+
+	return aw_mask;
+}
+
+static int arbitration_dt_parse_assigned_aw(struct panthor_arbitration *adev)
+{
+	struct panthor_arbitration_dt_info *dt_info = &adev->dt_info;
+	struct device *dev = adev->dev;
+	u32 seen_mask = 0;
+	u8 seen_partitions = 0;
+	int ret;
+
+	device_for_each_named_child_node_scoped(dev, child, "partition") {
+		struct panthor_arbitration_resource res;
+
+		if (panthor_arbitration_parse_resource(dev, child, &res))
+			continue;
+
+		if (res.id >= AM_ARB_MAX_PC_COUNT) {
+			dev_warn(dev,
+				 "partition@%llx: id (%u) >= %u not supported",
+				 res.res.start, res.id, AM_ARB_MAX_PC_COUNT);
+			continue;
+		}
+
+		if (BIT(res.id) & seen_partitions) {
+			dev_warn(dev, "partition@%llx: id (%u) already present",
+				 res.res.start, res.id);
+			continue;
+		}
+
+		seen_partitions |= BIT(res.id);
+
+		if (!fwnode_property_present(child, DT_ASSIGNED_AW))
+			continue;
+
+		ret = fwnode_property_read_u32(child, DT_ASSIGNED_AW,
+					       &dt_info->default_aw_masks[res.id]);
+		if (ret)
+			continue;
+	}
+
+	for (int i = 0; i < AM_ARB_MAX_PC_COUNT; i++) {
+		u32 aw_mask = dt_info->default_aw_masks[i];
+
+		if (aw_mask & ~GENMASK(AM_ARB_MAX_AW_COUNT - 1, 0))
+			return dev_err_probe(dev, -EINVAL, "%s[%d] entry exceeds max AW count",
+					     DT_ASSIGNED_AW, i);
+
+		if (aw_mask & seen_mask)
+			return dev_err_probe(dev, -EINVAL, "%s entries overlap",
+					     DT_ASSIGNED_AW);
+
+		seen_mask |= aw_mask;
+	}
+
+	return 0;
+}
+
+static int arbitration_dt_parse_properties(struct panthor_arbitration *adev)
+{
+	return arbitration_dt_parse_assigned_aw(adev);
+}
+
+static int arbitration_sched_try_start(struct panthor_arbitration *adev, u8 sched_id)
+{
+	struct panthor_arbitration_sched *sched;
+	u32 aw_mask;
+
+	if (!adev->sched[sched_id])
+		return -EINVAL;
+
+	sched = adev->sched[sched_id];
+
+	scoped_guard(mutex, &adev->assignment_lock)
+		aw_mask = arbitration_get_sched_aw_mask(adev, sched_id);
+
+	if (aw_mask)
+		panthor_arbitration_sched_disable_clear(sched, ARB_SCHED_DISABLE_RESOURCE);
+	else
+		panthor_arbitration_sched_disable_set(sched, ARB_SCHED_DISABLE_RESOURCE);
+
+	return panthor_arbitration_sched_start(sched);
+}
+
+static int arbitration_resource_init(struct panthor_arbitration *adev)
+{
+	struct panthor_arbitration_dt_info *dt_info = &adev->dt_info;
+
+	for (int i = 0; i < AM_ARB_MAX_PC_COUNT; i++) {
+		unsigned long pc_aw_mask = dt_info->default_aw_masks[i];
+		u8 aw_id;
+		int ret;
+
+		if (!adev->pc[i] || !adev->sched[i])
+			continue;
+
+		scoped_guard(mutex, &adev->assignment_lock) {
+			for_each_set_bit(aw_id, &pc_aw_mask, AM_ARB_MAX_AW_COUNT)
+				WRITE_ONCE(adev->aw_sched_map[aw_id], i);
+		}
+
+		ret = arbitration_sched_try_start(adev, i);
+		if (ret)
+			return ret;
+	}
+	return 0;
+}
+
 /* AW to Arbiter events */
 int panthor_arbitration_on_request(struct panthor_arbitration *adev, u8 aw_id)
 {
-	/* TODO: AW to PC assignment */
-	return panthor_arbitration_sched_on_request(adev->sched[0], aw_id);
+	int idx = to_assigned_sched_idx(adev, aw_id);
+
+	if (idx < 0)
+		return idx;
+
+	return panthor_arbitration_sched_on_request(adev->sched[idx], aw_id);
 }
 
 int panthor_arbitration_on_idle(struct panthor_arbitration *adev, u8 aw_id)
 {
-	/* TODO: AW to PC assignment */
-	return panthor_arbitration_sched_on_idle(adev->sched[0], aw_id);
+	int idx = to_assigned_sched_idx(adev, aw_id);
+
+	if (idx < 0)
+		return idx;
+
+	return panthor_arbitration_sched_on_idle(adev->sched[idx], aw_id);
 }
 
 int panthor_arbitration_on_stopped(struct panthor_arbitration *adev, u8 aw_id)
 {
-	/* TODO: AW to PC assignment */
-	return panthor_arbitration_sched_on_stopped(adev->sched[0], aw_id);
+	int idx = to_assigned_sched_idx(adev, aw_id);
+
+	if (idx < 0)
+		return idx;
+
+	return panthor_arbitration_sched_on_stopped(adev->sched[idx], aw_id);
 }
 
 /* Arbiter to AW events */
 int panthor_arbitration_on_grant(struct panthor_arbitration *adev, u8 aw_id)
 {
-	/* TODO: AW to PC assignment */
-	return panthor_partition_control_open_window(adev->pc[0], aw_id);
+	int idx = to_assigned_sched_idx(adev, aw_id);
+
+	if (idx < 0)
+		return idx;
+
+	return panthor_partition_control_open_window(adev->pc[idx], aw_id);
 }
 
 int panthor_arbitration_on_stop(struct panthor_arbitration *adev, u8 aw_id)
 {
-	/* TODO: AW to PC assignment */
-	return panthor_partition_control_yield_now(adev->pc[0]);
+	int idx = to_assigned_sched_idx(adev, aw_id);
+
+	if (idx < 0)
+		return idx;
+
+	return panthor_partition_control_yield_now(adev->pc[idx]);
 }
 
 int panthor_arbitration_on_close(struct panthor_arbitration *adev, u8 aw_id)
 {
-	/* TODO: AW to PC assignment */
-	return panthor_partition_control_close_window(adev->pc[0]);
+	int idx = to_assigned_sched_idx(adev, aw_id);
+
+	if (idx < 0)
+		return idx;
+
+	return panthor_partition_control_close_window(adev->pc[idx]);
 }
 
 static int panthor_arbitration_probe(struct platform_device *pdev)
@@ -148,8 +313,16 @@ static int panthor_arbitration_probe(struct platform_device *pdev)
 
 	adev->dev = dev;
 
+	mutex_init(&adev->assignment_lock);
+	for (int i = 0; i < AM_ARB_MAX_AW_COUNT; i++)
+		adev->aw_sched_map[i] = -1;
+
 	dev_set_drvdata(dev, adev);
 
+	ret = arbitration_dt_parse_properties(adev);
+	if (ret)
+		return ret;
+
 	ret = devm_pm_runtime_enable(dev);
 	if (ret)
 		return ret;
@@ -170,6 +343,10 @@ static int panthor_arbitration_probe(struct platform_device *pdev)
 	if (ret)
 		goto err_term_sched;
 
+	ret = arbitration_resource_init(adev);
+	if (ret)
+		goto err_term_sched;
+
 	ret = of_platform_populate(dev->of_node, NULL, NULL, dev);
 	if (ret)
 		goto err_depopulate;
diff --git a/drivers/gpu/drm/panthor/arbitration/panthor_arbitration_sched.c b/drivers/gpu/drm/panthor/arbitration/panthor_arbitration_sched.c
index 41f06af92ce0c..9e26b8f92b69a 100644
--- a/drivers/gpu/drm/panthor/arbitration/panthor_arbitration_sched.c
+++ b/drivers/gpu/drm/panthor/arbitration/panthor_arbitration_sched.c
@@ -585,6 +585,8 @@ static int arbitration_sched_init(struct panthor_arbitration *adev, int i)
 	INIT_KFIFO(sched->queue);
 	sched->active_aw_id = -1;
 	sched->phase = ARB_SCHED_PHASE_IDLE;
+	/* Scheduler is disabled until its resources are configured */
+	sched->disabled = BIT(ARB_SCHED_DISABLE_RESOURCE);
 
 	hrtimer_setup(&sched->grant_timer.timer,
 		      panthor_arbitration_sched_on_grant_timeout,
diff --git a/drivers/gpu/drm/panthor/arbitration/panthor_arbitration_sched.h b/drivers/gpu/drm/panthor/arbitration/panthor_arbitration_sched.h
index f1f50316a2fff..803a405964a4e 100644
--- a/drivers/gpu/drm/panthor/arbitration/panthor_arbitration_sched.h
+++ b/drivers/gpu/drm/panthor/arbitration/panthor_arbitration_sched.h
@@ -15,6 +15,9 @@ enum panthor_arb_sched_disable_reason {
 
 	/** @ARB_SCHED_DISABLE_TERM: scheduler disabled for termination */
 	ARB_SCHED_DISABLE_TERM,
+
+	/** @ARB_SCHED_DISABLE_RESOURCE: No resource assigned. scheduler disabled. */
+	ARB_SCHED_DISABLE_RESOURCE,
 };
 
 int panthor_arbitration_sched_init(struct panthor_arbitration *adev);
-- 
2.43.0

[PATCH v1 20/27] drm/panthor: Handle partition control INVALID_COMMAND interrupt

[Karunika Choo]

Partition control commands have specific partition state requirements
to be valid. We cannot afford to wait for the states to complete
transitions before sending these commands as it would work against the
arbitration scheduler's goal of handling phase transitions as fast as
possible (i.e. in IRQ context).

Fortunately, the hardware raises INVALID_COMMAND interrupts in cases
where the partition state requirements are not met. In such cases, retry
commands when the partition state permits, and request scheduler
recovery when an open-window command encounters an inconsistent
assignment.

Signed-off-by: Karunika Choo <karunika.choo@arm.com>
---
 .../panthor/arbitration/panthor_arbitration.h |   2 +
 .../arbitration/panthor_arbitration_drv.c     |  12 ++
 .../arbitration/panthor_arbitration_sched.c   |  10 ++
 .../arbitration/panthor_arbitration_sched.h   |   4 +
 .../arbitration/panthor_partition_control.c   | 108 ++++++++++++++++--
 5 files changed, 125 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/panthor/arbitration/panthor_arbitration.h b/drivers/gpu/drm/panthor/arbitration/panthor_arbitration.h
index e1d569158ac6c..53d64abb50379 100644
--- a/drivers/gpu/drm/panthor/arbitration/panthor_arbitration.h
+++ b/drivers/gpu/drm/panthor/arbitration/panthor_arbitration.h
@@ -75,4 +75,6 @@ int panthor_arbitration_on_grant(struct panthor_arbitration *adev, u8 aw_id);
 int panthor_arbitration_on_stop(struct panthor_arbitration *adev, u8 aw_id);
 int panthor_arbitration_on_close(struct panthor_arbitration *adev, u8 aw_id);
 
+int panthor_arbitration_notify_err(struct panthor_arbitration *adev, u8 aw_id);
+
 #endif
diff --git a/drivers/gpu/drm/panthor/arbitration/panthor_arbitration_drv.c b/drivers/gpu/drm/panthor/arbitration/panthor_arbitration_drv.c
index f44cd45ea342e..3cdf03f3f4879 100644
--- a/drivers/gpu/drm/panthor/arbitration/panthor_arbitration_drv.c
+++ b/drivers/gpu/drm/panthor/arbitration/panthor_arbitration_drv.c
@@ -298,6 +298,18 @@ int panthor_arbitration_on_close(struct panthor_arbitration *adev, u8 aw_id)
 	return panthor_partition_control_close_window(adev->pc[idx]);
 }
 
+int panthor_arbitration_notify_err(struct panthor_arbitration *adev, u8 aw_id)
+{
+	int idx = to_assigned_sched_idx(adev, aw_id);
+
+	if (idx < 0)
+		return idx;
+
+	panthor_arbitration_sched_reset(adev->sched[idx], aw_id);
+
+	return 0;
+}
+
 static int panthor_arbitration_probe(struct platform_device *pdev)
 {
 	struct panthor_arbitration *adev;
diff --git a/drivers/gpu/drm/panthor/arbitration/panthor_arbitration_sched.c b/drivers/gpu/drm/panthor/arbitration/panthor_arbitration_sched.c
index 9e26b8f92b69a..df0785a80442c 100644
--- a/drivers/gpu/drm/panthor/arbitration/panthor_arbitration_sched.c
+++ b/drivers/gpu/drm/panthor/arbitration/panthor_arbitration_sched.c
@@ -729,3 +729,13 @@ void panthor_arbitration_sched_disable_clear(struct panthor_arbitration_sched *s
 
 	sched->disabled &= ~BIT(reason);
 }
+
+void panthor_arbitration_sched_reset(struct panthor_arbitration_sched *sched, u8 aw_id)
+{
+	guard(spinlock_irqsave)(&sched->lock);
+
+	if (aw_id != sched->active_aw_id)
+		return;
+
+	arb_sched_queue_work(sched, &sched->reset_work);
+}
diff --git a/drivers/gpu/drm/panthor/arbitration/panthor_arbitration_sched.h b/drivers/gpu/drm/panthor/arbitration/panthor_arbitration_sched.h
index 803a405964a4e..ba43cc19f0eff 100644
--- a/drivers/gpu/drm/panthor/arbitration/panthor_arbitration_sched.h
+++ b/drivers/gpu/drm/panthor/arbitration/panthor_arbitration_sched.h
@@ -6,6 +6,8 @@
 
 #include <linux/types.h>
 
+#include "panthor_arbitration.h"
+
 struct panthor_arbitration;
 struct panthor_arbitration_sched;
 
@@ -35,6 +37,8 @@ void panthor_arbitration_sched_disable_set(struct panthor_arbitration_sched *sch
 void panthor_arbitration_sched_disable_clear(struct panthor_arbitration_sched *sched,
 					     enum panthor_arb_sched_disable_reason reason);
 
+void panthor_arbitration_sched_reset(struct panthor_arbitration_sched *sched, u8 aw_id);
+
 int panthor_arbitration_sched_on_request(struct panthor_arbitration_sched *sched, u8 aw_id);
 int panthor_arbitration_sched_on_idle(struct panthor_arbitration_sched *sched, u8 aw_id);
 int panthor_arbitration_sched_on_stopped(struct panthor_arbitration_sched *sched, u8 aw_id);
diff --git a/drivers/gpu/drm/panthor/arbitration/panthor_partition_control.c b/drivers/gpu/drm/panthor/arbitration/panthor_partition_control.c
index 95c26015cb637..446f77fc67891 100644
--- a/drivers/gpu/drm/panthor/arbitration/panthor_partition_control.c
+++ b/drivers/gpu/drm/panthor/arbitration/panthor_partition_control.c
@@ -28,6 +28,7 @@
 
 #define AM_PART_COMMAND				0x100
 #define   AM_PART_SET_COMMAND(x)		FIELD_PREP(GENMASK(7, 0), x)
+#define   AM_PART_GET_COMMAND(x)		FIELD_GET(GENMASK(7, 0), x)
 #define     PART_CMD_YIELD_IDLE			0x10
 #define     PART_CMD_YIELD_NOW			0x11
 #define     PART_CMD_CLOSE_WINDOW		0x20
@@ -40,6 +41,15 @@
 #define PART_REG_POLL_SLEEP_US			10
 #define PART_STATE_TRANSITION_TIMEOUT_US	5000000
 
+/** struct panthor_partition_cmd - Partition command data */
+struct panthor_partition_cmd {
+	/** @cmd: AM_PARTITION_COMMAND value */
+	u32 cmd;
+
+	/** @aw_id: AW ID the command was sent for */
+	int aw_id;
+};
+
 /**
  * struct panthor_partition_control - Partition control data
  */
@@ -64,6 +74,9 @@ struct panthor_partition_control {
 
 	/** @closing: synchronous closing of the partition */
 	bool closing;
+
+	/** @last_cmd: Last sent command */
+	struct panthor_partition_cmd last_cmd;
 };
 
 static void partition_irq_suspend(struct panthor_partition_control *pc)
@@ -101,18 +114,45 @@ static int partition_state_wait(struct panthor_partition_control *pc, u32 state)
 					false, pc);
 }
 
+static inline void
+partition_command_write_untracked(struct panthor_partition_control *pc, u32 cmd)
+{
+	gpu_write(pc->iomem, AM_PART_COMMAND, cmd);
+}
+
+static void partition_command_write(struct panthor_partition_control *pc,
+				    u32 cmd, int aw_id)
+{
+	lockdep_assert_held(&pc->lock);
+
+	partition_command_write_untracked(pc, cmd);
+
+	pc->last_cmd.cmd = cmd;
+	pc->last_cmd.aw_id = aw_id;
+}
+
 static int yield_now(struct panthor_partition_control *pc)
 {
-	gpu_write(pc->iomem, AM_PART_COMMAND,
-		  AM_PART_SET_COMMAND(PART_CMD_YIELD_NOW));
+	guard(spinlock_irqsave)(&pc->lock);
+
+	partition_command_write(pc, AM_PART_SET_COMMAND(PART_CMD_YIELD_NOW),
+				pc->current_aw);
 
 	return 0;
 }
 
 static int yield_idle(struct panthor_partition_control *pc)
 {
-	gpu_write(pc->iomem, AM_PART_COMMAND,
-		  AM_PART_SET_COMMAND(PART_CMD_YIELD_IDLE));
+	guard(spinlock_irqsave)(&pc->lock);
+
+	/*
+	 * This is a notification to yield the GPU once FW is idle. It is not
+	 * a command that must succeed. Nothing of note is lost if the command
+	 * fails apart from some minor scheduling optimisation losses. We can
+	 * skip tracking this command.
+	 */
+	partition_command_write_untracked(
+		pc, AM_PART_SET_COMMAND(PART_CMD_YIELD_IDLE));
 
 	return 0;
 }
@@ -127,8 +167,8 @@ static int window_close(struct panthor_partition_control *pc)
 
 	pc->closing = true;
 
-	gpu_write(pc->iomem, AM_PART_COMMAND,
-		  AM_PART_SET_COMMAND(PART_CMD_CLOSE_WINDOW));
+	partition_command_write(pc, AM_PART_SET_COMMAND(PART_CMD_CLOSE_WINDOW),
+				pc->current_aw);
 
 	return 0;
 }
@@ -153,8 +193,8 @@ static int window_open(struct panthor_partition_control *pc, u8 aw_id)
 
 	guard(spinlock_irqsave)(&pc->lock);
 
-	gpu_write(pc->iomem, AM_PART_COMMAND,
-		  AM_PART_SET_COMMAND(PART_CMD_OPEN_WINDOW) | AM_PART_SET_WINDOW(aw_id));
+	partition_command_write(pc, (AM_PART_SET_COMMAND(PART_CMD_OPEN_WINDOW) |
+				     AM_PART_SET_WINDOW(aw_id)), aw_id);
 
 	pc->current_aw = aw_id;
 
@@ -166,6 +206,8 @@ static void partition_handle_reset_done(struct panthor_partition_control *pc)
 	bool notify_stopped = false;
 	int aw_id;
 
+	gpu_write(pc->iomem, AM_PART_IRQ_CLEAR, PART_RESET_DONE);
+
 	scoped_guard(spinlock_irqsave, &pc->lock) {
 		aw_id = pc->current_aw;
 		pc->current_aw = -1;
@@ -181,6 +223,52 @@ static void partition_handle_reset_done(struct panthor_partition_control *pc)
 		panthor_arbitration_on_stopped(dev_get_drvdata(pc->dev), aw_id);
 }
 
+static void partition_handle_invalid_cmd(struct panthor_partition_control *pc)
+{
+	bool on_err = false;
+	int aw_id;
+
+	gpu_write(pc->iomem, AM_PART_IRQ_CLEAR, PART_INVALID_COMMAND);
+
+	scoped_guard(spinlock_irqsave, &pc->lock) {
+		if (!pc->last_cmd.cmd)
+			return;
+
+		if (pc->last_cmd.aw_id < 0)
+			return;
+
+		if (pc->last_cmd.aw_id != pc->current_aw)
+			return;
+
+		switch (AM_PART_GET_COMMAND(pc->last_cmd.cmd)) {
+		case PART_CMD_YIELD_NOW:
+		case PART_CMD_CLOSE_WINDOW:
+			if (partition_state_get(pc) == PART_STATE_WINDOW_OPEN) {
+				partition_command_write_untracked(pc, pc->last_cmd.cmd);
+				return;
+			}
+			break;
+		case PART_CMD_OPEN_WINDOW:
+			if (partition_state_get(pc) == PART_STATE_RESET) {
+				partition_command_write_untracked(pc, pc->last_cmd.cmd);
+				return;
+			} else if (partition_aw_get(pc) == pc->last_cmd.aw_id) {
+				return;
+			}
+
+			on_err = true;
+			aw_id = pc->last_cmd.aw_id;
+
+			break;
+		default:
+			return;
+		}
+	}
+
+	if (on_err)
+		panthor_arbitration_notify_err(dev_get_drvdata(pc->dev), aw_id);
+}
+
 static irqreturn_t partition_irq_raw_handler(int irq, void *data)
 {
 	struct panthor_partition_control *pc = data;
@@ -194,9 +282,7 @@ static irqreturn_t partition_irq_raw_handler(int irq, void *data)
 		partition_handle_reset_done(pc);
 
 	if (status & PART_INVALID_COMMAND)
-		dev_warn(pc->dev, "%s: Invalid command", pc->name);
-
-	gpu_write(pc->iomem, AM_PART_IRQ_CLEAR, status);
+		partition_handle_invalid_cmd(pc);
 
 	return IRQ_HANDLED;
 }
-- 
2.43.0

[PATCH v1 21/27] drm/panthor: Request AW to yield GPU access on idle

[Karunika Choo]

v15 GPU introduces a YIELD_IDLE command/interrupt to signal an access
window to relinquish GPU access as soon as it is idle. With FW v2, the
GPU is immediately yielded when it detects the GPU is idle and the
YIELD_IDLE interrupt is raised.

For latency and CPU scheduling reasons, we want to avoid constantly
yielding the GPU the moment it goes idle when there is only a singular
access window requesting access. As such, we only send YIELD_IDLE when:

- The GPU is granted to an access window and there are other access
  windows requesting GPU access.
- A new GPU_REQUEST was received and the currently active access window
  was the singular requesting AW.

Signed-off-by: Karunika Choo <karunika.choo@arm.com>
---
 .../panthor/arbitration/panthor_arbitration.h    |  1 +
 .../arbitration/panthor_arbitration_drv.c        | 10 ++++++++++
 .../arbitration/panthor_arbitration_sched.c      | 16 +++++++++++++++-
 3 files changed, 26 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/panthor/arbitration/panthor_arbitration.h b/drivers/gpu/drm/panthor/arbitration/panthor_arbitration.h
index 53d64abb50379..c0e93f940fccb 100644
--- a/drivers/gpu/drm/panthor/arbitration/panthor_arbitration.h
+++ b/drivers/gpu/drm/panthor/arbitration/panthor_arbitration.h
@@ -75,6 +75,7 @@ int panthor_arbitration_on_grant(struct panthor_arbitration *adev, u8 aw_id);
 int panthor_arbitration_on_stop(struct panthor_arbitration *adev, u8 aw_id);
 int panthor_arbitration_on_close(struct panthor_arbitration *adev, u8 aw_id);
 
+int panthor_arbitration_notify_yield_idle(struct panthor_arbitration *adev, u8 aw_id);
 int panthor_arbitration_notify_err(struct panthor_arbitration *adev, u8 aw_id);
 
 #endif
diff --git a/drivers/gpu/drm/panthor/arbitration/panthor_arbitration_drv.c b/drivers/gpu/drm/panthor/arbitration/panthor_arbitration_drv.c
index 3cdf03f3f4879..058fe39cbc002 100644
--- a/drivers/gpu/drm/panthor/arbitration/panthor_arbitration_drv.c
+++ b/drivers/gpu/drm/panthor/arbitration/panthor_arbitration_drv.c
@@ -298,6 +298,16 @@ int panthor_arbitration_on_close(struct panthor_arbitration *adev, u8 aw_id)
 	return panthor_partition_control_close_window(adev->pc[idx]);
 }
 
+int panthor_arbitration_notify_yield_idle(struct panthor_arbitration *adev, u8 aw_id)
+{
+	int idx = to_assigned_sched_idx(adev, aw_id);
+
+	if (idx < 0)
+		return idx;
+
+	return panthor_partition_control_yield_idle(adev->pc[idx]);
+}
+
 int panthor_arbitration_notify_err(struct panthor_arbitration *adev, u8 aw_id)
 {
 	int idx = to_assigned_sched_idx(adev, aw_id);
diff --git a/drivers/gpu/drm/panthor/arbitration/panthor_arbitration_sched.c b/drivers/gpu/drm/panthor/arbitration/panthor_arbitration_sched.c
index df0785a80442c..df58fcc56e375 100644
--- a/drivers/gpu/drm/panthor/arbitration/panthor_arbitration_sched.c
+++ b/drivers/gpu/drm/panthor/arbitration/panthor_arbitration_sched.c
@@ -347,6 +347,10 @@ static int arb_sched_next_locked(struct panthor_arbitration_sched *sched)
 
 	arb_sched_grant_locked(sched);
 
+	if (sched->phase == ARB_SCHED_PHASE_GRANTED &&
+	    !kfifo_is_empty(&sched->queue))
+		panthor_arbitration_notify_yield_idle(to_adev(sched), aw_id);
+
 	wake_up_all(&sched->waitqueue);
 
 	return 0;
@@ -475,8 +479,18 @@ int panthor_arbitration_sched_on_request(struct panthor_arbitration_sched *sched
 	 * Grant timer for the current AW has previously expired, request it to
 	 * yield the GPU.
 	 */
-	if (sched->grant_previously_expired)
+	if (sched->grant_previously_expired) {
 		arb_sched_request_stop_locked(sched);
+		return 0;
+	}
+
+	/*
+	 * GPU was previously granted to a lone requesting AW, YIELD_IDLE was
+	 * not sent to it. Send YIELD_IDLE to it now that multiple AWs are
+	 * requesting for the GPU.
+	 */
+	if (sched->phase == ARB_SCHED_PHASE_GRANTED && kfifo_len(&sched->queue) == 1)
+		panthor_arbitration_notify_yield_idle(to_adev(sched), sched->active_aw_id);
 
 	return 0;
 }
-- 
2.43.0

[PATCH v1 22/27] drm/panthor: Add access-window support

[Karunika Choo]

Add the VM-side access-window component for v15 GPUs. The new code
handles AM message handshakes, requests GPU access from the arbiter,
waits for the window-open interrupt, and yields access on suspend.

Split panthor_hw_init into bind device and initialize gpu_info after
panthor_aw has ensured GPU access.

Signed-off-by: Karunika Choo <karunika.choo@arm.com>
---
v1:
- Adapt AW IRQ handling to the updated IRQ locking/state interfaces and
  reuse panthor_irq_suspend().
- Handle -ENOSPC from AM message sending when the outgoing FIFO is full.

 drivers/gpu/drm/panthor/Makefile         |   1 +
 drivers/gpu/drm/panthor/panthor_aw.c     | 416 +++++++++++++++++++++++
 drivers/gpu/drm/panthor/panthor_aw.h     |  42 +++
 drivers/gpu/drm/panthor/panthor_device.c |  15 +-
 drivers/gpu/drm/panthor/panthor_device.h |   4 +
 drivers/gpu/drm/panthor/panthor_hw.c     |   8 +-
 drivers/gpu/drm/panthor/panthor_hw.h     |   2 +
 7 files changed, 481 insertions(+), 7 deletions(-)
 create mode 100644 drivers/gpu/drm/panthor/panthor_aw.c
 create mode 100644 drivers/gpu/drm/panthor/panthor_aw.h

diff --git a/drivers/gpu/drm/panthor/Makefile b/drivers/gpu/drm/panthor/Makefile
index 5d4d0ae64952e..aa48212653dc3 100644
--- a/drivers/gpu/drm/panthor/Makefile
+++ b/drivers/gpu/drm/panthor/Makefile
@@ -1,6 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0 or MIT
 
 panthor-y := \
+	panthor_aw.o \
 	panthor_devfreq.o \
 	panthor_device.o \
 	panthor_drv.o \
diff --git a/drivers/gpu/drm/panthor/panthor_aw.c b/drivers/gpu/drm/panthor/panthor_aw.c
new file mode 100644
index 0000000000000..848fd64eb51b5
--- /dev/null
+++ b/drivers/gpu/drm/panthor/panthor_aw.c
@@ -0,0 +1,416 @@
+// SPDX-License-Identifier: GPL-2.0 or MIT
+/* Copyright 2026 ARM Limited. All rights reserved. */
+
+#include <linux/platform_device.h>
+
+#include <drm/drm_managed.h>
+#include <drm/drm_print.h>
+#include <drm/drm_drv.h>
+
+#include "panthor_am_msg.h"
+#include "panthor_aw.h"
+#include "panthor_device.h"
+#include "panthor_fw.h"
+#include "panthor_hw.h"
+#include "panthor_sched.h"
+
+#include "panthor_trace.h"
+
+#define WINDOW_CONTROL_BASE				0x0
+#define WINDOW_CONTROL_SIZE				0x1000
+
+#define WINDOW_STATUS					0x43c
+#define   WINDOW_STATUS_IRQ_WINDOW_CONTROL		BIT(0)
+#define   WINDOW_STATUS_IRQ_GPU_CONTROL			BIT(1)
+#define   WINDOW_STATUS_IRQ_GPU_POWER			BIT(2)
+#define   WINDOW_STATUS_IRQ_JOB_CONTROL			BIT(3)
+#define   WINDOW_STATUS_IRQ_MMU_CONTROL			BIT(4)
+#define   WINDOW_STATUS_WINDOW_OPEN			BIT(31)
+
+#define WINDOW_INT_BASE					0x440
+#define   WINDOW_IRQ_MESSAGE				BIT(0)
+#define   WINDOW_IRQ_INVALID_ACCESS			BIT(1)
+#define   WINDOW_IRQ_WINDOW_OPENING			BIT(2)
+#define   WINDOW_IRQ_WINDOW_OPENED			BIT(3)
+#define   WINDOW_IRQ_WINDOW_CLOSED			BIT(4)
+
+#define WINDOW_MESSAGE_BASE				0x460
+
+#define WINDOW_IRQ_MASK \
+	(WINDOW_IRQ_MESSAGE | WINDOW_IRQ_WINDOW_OPENED | WINDOW_IRQ_WINDOW_CLOSED)
+
+#define PANTHOR_AW_HANDSHAKE_TIMEOUT_MS			(5 * MSEC_PER_SEC)
+#define PANTHOR_AW_GPU_REQUEST_TIMEOUT_MS		(5 * MSEC_PER_SEC)
+#define PANTHOR_AW_STATE_TRANSITION_TIMEOUT_MS		(5 * MSEC_PER_SEC)
+
+#define panthor_aw_wait_cond(_aw, _cond, _timeout_ms)				\
+({										\
+	int __ret = 0;								\
+	if (!wait_event_timeout((_aw)->waitqueue, _cond,			\
+				msecs_to_jiffies(_timeout_ms)))			\
+		if (!(_cond))							\
+			__ret = -ETIMEDOUT;					\
+	__ret;									\
+})
+
+struct panthor_aw {
+	/** @ptdev: Pointer to Panthor device */
+	struct panthor_device *ptdev;
+
+	/** @iomem: CPU mapping of WINDOW_CONTROL iomem region */
+	void __iomem *iomem;
+
+	/** @irq: IRQ data */
+	struct panthor_irq irq;
+
+	/** @msg: Messaging data */
+	struct panthor_am_msg msg;
+
+	/** @waitqueue: Event wait queue. Not IRQ safe */
+	wait_queue_head_t waitqueue;
+
+	/** @state: Current state of the AW */
+	atomic_t state;
+
+	/** @wq: Scheduler workqueue to dispatch events */
+	struct workqueue_struct *wq;
+
+	/** @msg_retry_work: Work to resend messages */
+	struct work_struct msg_retry_work;
+};
+
+static bool panthor_aw_is_open(struct panthor_aw *aw)
+{
+	return gpu_read(aw->iomem, WINDOW_STATUS) & WINDOW_STATUS_WINDOW_OPEN;
+}
+
+static void panthor_aw_state_set(struct panthor_aw *aw, enum aw_states new)
+{
+	atomic_set(&aw->state, new);
+
+	wake_up_all(&aw->waitqueue);
+}
+
+static bool panthor_aw_state_try_set(struct panthor_aw *aw,
+				     enum aw_states expected,
+				     enum aw_states new)
+{
+	int old_state = atomic_cmpxchg(&aw->state, expected, new);
+	bool res = (old_state == expected);
+
+	if (res)
+		wake_up_all(&aw->waitqueue);
+
+	return res;
+}
+
+static int panthor_aw_state_wait(struct panthor_aw *aw, enum aw_states target, u32 timeout_ms)
+{
+	return panthor_aw_wait_cond(aw, atomic_read(&aw->state) == target, timeout_ms);
+}
+
+static int panthor_aw_state_wait_transition(struct panthor_aw *aw, u32 timeout_ms)
+{
+	return panthor_aw_wait_cond(
+		aw,
+		(atomic_read(&aw->state) == PANTHOR_AW_STATE_READY ||
+		 atomic_read(&aw->state) == PANTHOR_AW_STATE_GPU_GRANTED),
+		timeout_ms);
+}
+
+static void panthor_aw_msg_retry_work(struct work_struct *work)
+{
+	struct panthor_aw *aw =
+		container_of(work, struct panthor_aw, msg_retry_work);
+	struct panthor_am_msg *msg = &aw->msg;
+	int ret;
+
+	ret = panthor_am_msg_retry(msg);
+	if (ret == -EINVAL)
+		drm_warn(&aw->ptdev->base, "Send FIFO unexpectedly empty");
+
+	if (ret == -EBUSY || ret == -EAGAIN)
+		queue_work(aw->wq, &aw->msg_retry_work);
+}
+
+static void panthor_aw_send_msg(struct panthor_aw *aw, u64 message)
+{
+	struct panthor_device *ptdev = aw->ptdev;
+	int ret;
+
+	ret = panthor_am_msg_send(&aw->msg, message);
+	if (ret == -ENOSPC)
+		drm_err(&ptdev->base, "Send FIFO is full");
+
+	if (ret == -EBUSY) {
+		drm_dbg(&ptdev->base, "Pending messages, scheduling retry work");
+		queue_work(aw->wq, &aw->msg_retry_work);
+	}
+}
+
+static void panthor_aw_handshake_handle(struct panthor_aw *aw, u64 message)
+{
+	struct panthor_device *ptdev = aw->ptdev;
+	bool acked = AM_MSG_ACK_GET(message);
+	u8 version = AM_MSG_VERSION_GET(message);
+	int ret;
+
+	ret = panthor_am_msg_version_validate(&aw->msg, version);
+	if (ret == -EOPNOTSUPP)
+		drm_warn(&ptdev->base,
+			 "Msg protocol version less than minimum supported (%u < %u)",
+			 version, AM_MSG_MIN_SUPPORTED_VERSION);
+
+	if (!acked) {
+		u64 reply = VM_ARB_INIT_MAKE(1, aw->msg.version);
+
+		panthor_aw_send_msg(aw, reply);
+
+		/* TODO: Handle AW restart */
+	}
+
+	panthor_aw_state_try_set(aw, PANTHOR_AW_STATE_INIT, PANTHOR_AW_STATE_READY);
+}
+
+static void panthor_aw_handshake_init(struct panthor_aw *aw)
+{
+	u64 message = VM_ARB_INIT_MAKE(0, AM_MSG_CURRENT_VERSION);
+
+	panthor_aw_send_msg(aw, message);
+}
+
+static void panthor_aw_handle_message(struct panthor_aw *aw)
+{
+	struct panthor_device *ptdev = aw->ptdev;
+	const u64 message = panthor_am_msg_read(&aw->msg);
+	const u8 msg_id = AM_MSG_ID_GET(message);
+
+	/* currently only support ARB_VM_INIT */
+	if (msg_id == ARB_VM_INIT)
+		panthor_aw_handshake_handle(aw, message);
+	else
+		drm_warn(&ptdev->base, "Unsupported msg id (0x%x)", msg_id);
+}
+
+
+static irqreturn_t panthor_aw_irq_raw_hander(int irq, void *data)
+{
+	struct panthor_irq *pirq = data;
+	struct panthor_device *ptdev = pirq->ptdev;
+	struct panthor_aw *aw = ptdev->aw;
+	u32 status;
+
+	scoped_guard(spinlock_irqsave, &pirq->lock) {
+		if (pirq->state != PANTHOR_IRQ_STATE_ACTIVE)
+		return IRQ_NONE;
+	}
+
+	status = gpu_read(pirq->iomem, INT_STAT);
+	if (!status)
+		return IRQ_NONE;
+
+	if (status & WINDOW_IRQ_MESSAGE)
+		panthor_aw_handle_message(aw);
+
+	/* TODO: handle WINDOW_CLOSED*/
+
+	if ((status & WINDOW_IRQ_WINDOW_OPENED) && panthor_aw_is_open(aw))
+		panthor_aw_state_try_set(aw, PANTHOR_AW_STATE_GPU_REQUEST,
+					 PANTHOR_AW_STATE_GPU_GRANTED);
+
+	gpu_write(pirq->iomem, INT_CLEAR, status);
+
+	return IRQ_HANDLED;
+}
+
+static void panthor_aw_irq_suspend(struct panthor_irq *pirq)
+{
+	panthor_irq_suspend(pirq);
+}
+
+static void panthor_aw_irq_resume(struct panthor_irq *pirq)
+{
+	guard(spinlock_irqsave)(&pirq->lock);
+
+	pirq->state = PANTHOR_IRQ_STATE_ACTIVE;
+	gpu_write(pirq->iomem, INT_MASK, pirq->mask);
+}
+
+static int panthor_request_aw_irq(struct panthor_device *ptdev,
+				  struct panthor_irq *pirq, int irq, u32 mask,
+				  void __iomem *iomem)
+{
+	int ret;
+
+	pirq->ptdev = ptdev;
+	pirq->irq = irq;
+	pirq->mask = mask;
+	pirq->iomem = iomem;
+	spin_lock_init(&pirq->lock);
+
+	ret = devm_request_irq(ptdev->base.dev, irq, panthor_aw_irq_raw_hander,
+			       IRQF_SHARED, "panthor-aw", pirq);
+	if (ret)
+		return ret;
+
+	panthor_aw_irq_resume(pirq);
+
+	return 0;
+}
+
+static int panthor_aw_request(struct panthor_aw *aw)
+{
+	int ret;
+
+again:
+	switch (atomic_read(&aw->state)) {
+	case PANTHOR_AW_STATE_GPU_GRANTED:
+		return 0;
+
+	case PANTHOR_AW_STATE_READY:
+		break;
+
+	case PANTHOR_AW_STATE_INIT:
+		panthor_aw_handshake_init(aw);
+		ret = panthor_aw_state_wait(aw, PANTHOR_AW_STATE_READY,
+					    PANTHOR_AW_HANDSHAKE_TIMEOUT_MS);
+		if (ret)
+			return ret;
+		goto again;
+	default:
+		ret = panthor_aw_state_wait_transition(
+			aw, PANTHOR_AW_STATE_TRANSITION_TIMEOUT_MS);
+		if (ret)
+			return ret;
+		goto again;
+	}
+
+	if (!panthor_aw_state_try_set(aw, PANTHOR_AW_STATE_READY,
+				      PANTHOR_AW_STATE_GPU_REQUEST))
+		goto again;
+
+	panthor_aw_send_msg(aw, VM_ARB_GPU_REQUEST);
+
+	/* Wait for GPU to be granted */
+	ret = panthor_aw_state_wait(aw, PANTHOR_AW_STATE_GPU_GRANTED,
+				    PANTHOR_AW_GPU_REQUEST_TIMEOUT_MS);
+	if (ret) {
+		panthor_aw_state_set(aw, PANTHOR_AW_STATE_READY);
+		return ret;
+	}
+
+	return 0;
+}
+
+static int panthor_aw_yield(struct panthor_aw *aw)
+{
+	panthor_aw_send_msg(aw, VM_ARB_GPU_STOPPED);
+
+	return panthor_aw_state_wait(aw, PANTHOR_AW_STATE_READY,
+				     PANTHOR_AW_STATE_TRANSITION_TIMEOUT_MS);
+}
+
+int panthor_aw_init(struct panthor_device *ptdev)
+{
+	struct panthor_aw *aw;
+	int irq;
+	int ret;
+
+	if (!panthor_hw_has_gpu_discover(ptdev))
+		return 0;
+
+	aw = drmm_kzalloc(&ptdev->base, sizeof(*aw), GFP_KERNEL);
+	if (!aw)
+		return -ENOMEM;
+
+	aw->wq = drmm_alloc_ordered_workqueue(&ptdev->base, "panthor-aw-wq", 0);
+	if (!aw->wq)
+		return -ENOMEM;
+
+	aw->ptdev = ptdev;
+	aw->iomem = ptdev->iomem;
+
+	INIT_WORK(&aw->msg_retry_work, panthor_aw_msg_retry_work);
+
+	init_waitqueue_head(&aw->waitqueue);
+	atomic_set(&aw->state, PANTHOR_AW_STATE_INIT);
+
+	panthor_am_msg_init(&aw->msg, aw->iomem + WINDOW_MESSAGE_BASE);
+
+	ptdev->aw = aw;
+
+	irq = platform_get_irq_byname(to_platform_device(ptdev->base.dev), "gpu");
+	if (irq < 0)
+		return irq;
+
+	ret = panthor_request_aw_irq(ptdev, &aw->irq, irq, WINDOW_IRQ_MASK,
+				     aw->iomem + WINDOW_INT_BASE);
+	if (ret)
+		return ret;
+
+	ret = panthor_aw_request(aw);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+void panthor_aw_unplug(struct panthor_device *ptdev)
+{
+	struct panthor_aw *aw = ptdev->aw;
+
+	if (!aw)
+		return;
+
+	disable_work_sync(&aw->msg_retry_work);
+
+	panthor_aw_irq_suspend(&aw->irq);
+}
+
+int panthor_aw_resume(struct panthor_device *ptdev)
+{
+	struct panthor_aw *aw = ptdev->aw;
+	int ret;
+
+	if (!aw)
+		return 0;
+
+	panthor_aw_irq_resume(&aw->irq);
+
+	ret = panthor_aw_request(aw);
+	if (ret) {
+		drm_warn(&ptdev->base, "Timedout waiting for GPU to be granted");
+		goto err_out;
+	}
+
+	return 0;
+
+err_out:
+	panthor_aw_irq_suspend(&aw->irq);
+	return ret;
+}
+
+int panthor_aw_suspend(struct panthor_device *ptdev)
+{
+	struct panthor_aw *aw = ptdev->aw;
+	int ret = 0;
+
+	/* suspend hw components directly if AW is not supported */
+	if (!aw)
+		return 0;
+
+	if (atomic_read(&aw->state) == PANTHOR_AW_STATE_READY)
+		goto out_irq_suspend;
+
+	if (panthor_aw_state_try_set(aw, PANTHOR_AW_STATE_GPU_GRANTED,
+		PANTHOR_AW_STATE_GPU_STOPPED))
+		ret = panthor_aw_yield(aw);
+	else
+		ret = panthor_aw_state_wait(
+			aw, PANTHOR_AW_STATE_READY,
+			PANTHOR_AW_STATE_TRANSITION_TIMEOUT_MS);
+
+out_irq_suspend:
+	panthor_aw_irq_suspend(&aw->irq);
+	return ret;
+}
diff --git a/drivers/gpu/drm/panthor/panthor_aw.h b/drivers/gpu/drm/panthor/panthor_aw.h
new file mode 100644
index 0000000000000..c2b89caa87c48
--- /dev/null
+++ b/drivers/gpu/drm/panthor/panthor_aw.h
@@ -0,0 +1,42 @@
+/* SPDX-License-Identifier: GPL-2.0 or MIT */
+/* Copyright 2026 ARM Limited. All rights reserved. */
+
+#ifndef __PANTHOR_AW_H__
+#define __PANTHOR_AW_H__
+
+#include <linux/types.h>
+
+struct panthor_device;
+
+/**
+ * enum aw_states - Enumeration of possible Access Window states
+ */
+enum aw_states {
+	/** @PANTHOR_AW_STATE_INIT: Initial state, prior to handshake. */
+	PANTHOR_AW_STATE_INIT = 0,
+
+	/** @PANTHOR_AW_STATE_READY: Handshake with Resource Group completed. */
+	PANTHOR_AW_STATE_READY,
+
+	/** @PANTHOR_AW_STATE_GPU_REQUEST: AW requested for GPU access. */
+	PANTHOR_AW_STATE_GPU_REQUEST,
+
+	/** @PANTHOR_AW_STATE_GPU_GRANTED: AW is granted GPU access. */
+	PANTHOR_AW_STATE_GPU_GRANTED,
+
+	/** @PANTHOR_AW_STATE_GPU_STOP: AW is requested to stop GPU access. */
+	PANTHOR_AW_STATE_GPU_STOP,
+
+	/** @PANTHOR_AW_STATE_GPU_STOPPED: AW has stopped GPU access. */
+	PANTHOR_AW_STATE_GPU_STOPPED,
+};
+
+int panthor_aw_init(struct panthor_device *ptdev);
+
+void panthor_aw_unplug(struct panthor_device *ptdev);
+
+int panthor_aw_resume(struct panthor_device *ptdev);
+
+int panthor_aw_suspend(struct panthor_device *ptdev);
+
+#endif
diff --git a/drivers/gpu/drm/panthor/panthor_device.c b/drivers/gpu/drm/panthor/panthor_device.c
index 9687c59de3505..98c0dd3ce7bcb 100644
--- a/drivers/gpu/drm/panthor/panthor_device.c
+++ b/drivers/gpu/drm/panthor/panthor_device.c
@@ -16,6 +16,7 @@
 #include <drm/drm_managed.h>
 #include <drm/drm_print.h>
 
+#include "panthor_aw.h"
 #include "panthor_devfreq.h"
 #include "panthor_device.h"
 #include "panthor_fw.h"
@@ -100,6 +101,7 @@ void panthor_device_unplug(struct panthor_device *ptdev)
 	panthor_gem_shrinker_unplug(ptdev);
 	panthor_gpu_unplug(ptdev);
 	panthor_pwr_unplug(ptdev);
+	panthor_aw_unplug(ptdev);
 
 	pm_runtime_dont_use_autosuspend(ptdev->base.dev);
 	pm_runtime_put_sync_suspend(ptdev->base.dev);
@@ -259,10 +261,18 @@ int panthor_device_init(struct panthor_device *ptdev)
 	if (ret)
 		goto err_rpm_put;
 
-	ret = panthor_pwr_init(ptdev);
+	ret = panthor_aw_init(ptdev);
 	if (ret)
 		goto err_rpm_put;
 
+	ret = panthor_hw_info_init(ptdev);
+	if (ret)
+		goto err_unplug_aw;
+
+	ret = panthor_pwr_init(ptdev);
+	if (ret)
+		goto err_unplug_aw;
+
 	ret = panthor_gpu_init(ptdev);
 	if (ret)
 		goto err_unplug_pwr;
@@ -322,6 +332,9 @@ int panthor_device_init(struct panthor_device *ptdev)
 err_unplug_pwr:
 	panthor_pwr_unplug(ptdev);
 
+err_unplug_aw:
+	panthor_aw_unplug(ptdev);
+
 err_rpm_put:
 	pm_runtime_put_sync_suspend(ptdev->base.dev);
 	return ret;
diff --git a/drivers/gpu/drm/panthor/panthor_device.h b/drivers/gpu/drm/panthor/panthor_device.h
index ba93a100ceda2..960e06236fc03 100644
--- a/drivers/gpu/drm/panthor/panthor_device.h
+++ b/drivers/gpu/drm/panthor/panthor_device.h
@@ -20,6 +20,7 @@
 
 #include "panthor_device_io.h"
 
+struct panthor_aw;
 struct panthor_csf;
 struct panthor_csf_ctx;
 struct panthor_device;
@@ -201,6 +202,9 @@ struct panthor_device {
 	/** @hw: GPU-specific data. */
 	struct panthor_hw *hw;
 
+	/** @aw: AW-specific data */
+	struct panthor_aw *aw;
+
 	/** @pwr: Power control management data. */
 	struct panthor_pwr *pwr;
 
diff --git a/drivers/gpu/drm/panthor/panthor_hw.c b/drivers/gpu/drm/panthor/panthor_hw.c
index 9d539f5f80158..0bbd102fa1890 100644
--- a/drivers/gpu/drm/panthor/panthor_hw.c
+++ b/drivers/gpu/drm/panthor/panthor_hw.c
@@ -350,7 +350,7 @@ static int panthor_gpu_info_init(struct panthor_device *ptdev)
 	return overload_shader_present(ptdev);
 }
 
-static int panthor_hw_info_init(struct panthor_device *ptdev)
+int panthor_hw_info_init(struct panthor_device *ptdev)
 {
 	u64 l2_features;
 	u32 major, minor, status;
@@ -463,9 +463,5 @@ int panthor_hw_init(struct panthor_device *ptdev)
 	if (ret)
 		return ret;
 
-	ret = panthor_hw_bind_device(ptdev);
-	if (ret)
-		return ret;
-
-	return panthor_hw_info_init(ptdev);
+	return panthor_hw_bind_device(ptdev);
 }
diff --git a/drivers/gpu/drm/panthor/panthor_hw.h b/drivers/gpu/drm/panthor/panthor_hw.h
index e5bcb908068cb..8972b510287a4 100644
--- a/drivers/gpu/drm/panthor/panthor_hw.h
+++ b/drivers/gpu/drm/panthor/panthor_hw.h
@@ -65,6 +65,8 @@ struct panthor_hw {
 };
 
 int panthor_hw_init(struct panthor_device *ptdev);
+int panthor_hw_info_init(struct panthor_device *ptdev);
+
 int panthor_hw_power_status_register(void);
 void panthor_hw_power_status_unregister(void);
 
-- 
2.43.0

[PATCH v1 23/27] drm/panthor: Synchronize HW component PM transitions

[Karunika Choo]

Split hardware component suspend/resume from the top-level device PM
path and protect those transitions with a dedicated mutex and state
flag.

This lets access-window arbitration suspend or resume GPU components
while runtime PM state remains controlled by the outer PM path.

Signed-off-by: Karunika Choo <karunika.choo@arm.com>
---
 drivers/gpu/drm/panthor/panthor_aw.c     |  1 -
 drivers/gpu/drm/panthor/panthor_device.c | 50 +++++++++++++++++++++---
 drivers/gpu/drm/panthor/panthor_device.h |  9 +++++
 3 files changed, 53 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/panthor/panthor_aw.c b/drivers/gpu/drm/panthor/panthor_aw.c
index 848fd64eb51b5..40122bb4b83af 100644
--- a/drivers/gpu/drm/panthor/panthor_aw.c
+++ b/drivers/gpu/drm/panthor/panthor_aw.c
@@ -192,7 +192,6 @@ static void panthor_aw_handle_message(struct panthor_aw *aw)
 		drm_warn(&ptdev->base, "Unsupported msg id (0x%x)", msg_id);
 }
 
-
 static irqreturn_t panthor_aw_irq_raw_hander(int irq, void *data)
 {
 	struct panthor_irq *pirq = data;
diff --git a/drivers/gpu/drm/panthor/panthor_device.c b/drivers/gpu/drm/panthor/panthor_device.c
index 98c0dd3ce7bcb..2ccd8ad6318d1 100644
--- a/drivers/gpu/drm/panthor/panthor_device.c
+++ b/drivers/gpu/drm/panthor/panthor_device.c
@@ -179,6 +179,10 @@ int panthor_device_init(struct panthor_device *ptdev)
 	if (ret)
 		return ret;
 
+	ret = drmm_mutex_init(&ptdev->base, &ptdev->pm.hw_component_lock);
+	if (ret)
+		return ret;
+
 	ret = drmm_mutex_init(&ptdev->base, &ptdev->pm.mmio_lock);
 	if (ret)
 		return ret;
@@ -293,6 +297,9 @@ int panthor_device_init(struct panthor_device *ptdev)
 	if (ret)
 		goto err_unplug_mmu;
 
+	atomic_set(&ptdev->pm.hw_component_state,
+		   PANTHOR_DEVICE_PM_STATE_ACTIVE);
+
 	ret = panthor_sched_init(ptdev);
 	if (ret)
 		goto err_unplug_fw;
@@ -484,21 +491,55 @@ int panthor_device_mmap_io(struct panthor_device *ptdev, struct vm_area_struct *
 	return 0;
 }
 
-static int panthor_device_resume_hw_components(struct panthor_device *ptdev)
+int panthor_device_suspend_hw_components(struct panthor_device *ptdev)
+{
+	guard(mutex)(&ptdev->pm.hw_component_lock);
+
+	if (atomic_read(&ptdev->pm.hw_component_state) ==
+	    PANTHOR_DEVICE_PM_STATE_SUSPENDED)
+		return 0;
+
+	if (!pm_runtime_suspended(ptdev->base.dev)) {
+		panthor_fw_suspend(ptdev);
+		panthor_mmu_suspend(ptdev);
+		panthor_gpu_suspend(ptdev);
+		panthor_pwr_suspend(ptdev);
+	}
+
+	atomic_set(&ptdev->pm.hw_component_state,
+		   PANTHOR_DEVICE_PM_STATE_SUSPENDED);
+
+	return 0;
+}
+
+int panthor_device_resume_hw_components(struct panthor_device *ptdev)
 {
 	int ret;
 
+	guard(mutex)(&ptdev->pm.hw_component_lock);
+
+	if (atomic_read(&ptdev->pm.hw_component_state) ==
+	    PANTHOR_DEVICE_PM_STATE_ACTIVE)
+		return 0;
+
 	panthor_pwr_resume(ptdev);
 	panthor_gpu_resume(ptdev);
 	panthor_mmu_resume(ptdev);
 
 	ret = panthor_fw_resume(ptdev);
-	if (!ret)
+	if (!ret) {
+		atomic_set(&ptdev->pm.hw_component_state,
+			   PANTHOR_DEVICE_PM_STATE_ACTIVE);
 		return 0;
+	}
 
 	panthor_mmu_suspend(ptdev);
 	panthor_gpu_suspend(ptdev);
 	panthor_pwr_suspend(ptdev);
+
+	atomic_set(&ptdev->pm.hw_component_state,
+		   PANTHOR_DEVICE_PM_STATE_SUSPENDED);
+
 	return ret;
 }
 
@@ -609,10 +650,7 @@ int panthor_device_suspend(struct device *dev)
 		 * The end of the reset will happen in the resume path though.
 		 */
 		panthor_sched_suspend(ptdev);
-		panthor_fw_suspend(ptdev);
-		panthor_mmu_suspend(ptdev);
-		panthor_gpu_suspend(ptdev);
-		panthor_pwr_suspend(ptdev);
+		panthor_device_suspend_hw_components(ptdev);
 		drm_dev_exit(cookie);
 	}
 
diff --git a/drivers/gpu/drm/panthor/panthor_device.h b/drivers/gpu/drm/panthor/panthor_device.h
index 960e06236fc03..42c5052ac83b9 100644
--- a/drivers/gpu/drm/panthor/panthor_device.h
+++ b/drivers/gpu/drm/panthor/panthor_device.h
@@ -352,6 +352,12 @@ struct panthor_device {
 
 		/** @recovery_needed: True when a resume attempt failed. */
 		atomic_t recovery_needed;
+
+		/** @hw_component_lock: Lock protects HW component PM state transitions */
+		struct mutex hw_component_lock;
+
+		/** @hw_component_state: HW component PM state */
+		atomic_t hw_component_state;
 	} pm;
 
 	/** @profile_mask: User-set profiling flags for job accounting. */
@@ -441,6 +447,9 @@ int panthor_device_mmap_io(struct panthor_device *ptdev,
 int panthor_device_resume(struct device *dev);
 int panthor_device_suspend(struct device *dev);
 
+int panthor_device_suspend_hw_components(struct panthor_device *ptdev);
+int panthor_device_resume_hw_components(struct panthor_device *ptdev);
+
 static inline int panthor_device_resume_and_get(struct panthor_device *ptdev)
 {
 	int ret = pm_runtime_resume_and_get(ptdev->base.dev);
-- 
2.43.0

[PATCH v1 24/27] drm/panthor: Route HW component PM through access windows

[Karunika Choo]

Make access-window resume and suspend own GPU access when AW support is
present, while keeping the direct HW component PM path for older GPUs.

Handle WINDOW_CLOSED and arbiter restart events, defer post-yield
cleanup to workqueue context, and make panthor_device_resume_and_get()
ensure that GPU access is obtained before callers touch hardware.

Signed-off-by: Karunika Choo <karunika.choo@arm.com>
---
v1:
- update panthor_aw_ensure_gpu_access() to wait for AW state transitions
  and retry on -EAGAIN.

 drivers/gpu/drm/panthor/panthor_aw.c     | 194 +++++++++++++++++++++--
 drivers/gpu/drm/panthor/panthor_aw.h     |   8 +-
 drivers/gpu/drm/panthor/panthor_device.c |   6 +-
 drivers/gpu/drm/panthor/panthor_device.h |  15 +-
 4 files changed, 198 insertions(+), 25 deletions(-)

diff --git a/drivers/gpu/drm/panthor/panthor_aw.c b/drivers/gpu/drm/panthor/panthor_aw.c
index 40122bb4b83af..4fcfb3ad05073 100644
--- a/drivers/gpu/drm/panthor/panthor_aw.c
+++ b/drivers/gpu/drm/panthor/panthor_aw.c
@@ -77,6 +77,9 @@ struct panthor_aw {
 
 	/** @msg_retry_work: Work to resend messages */
 	struct work_struct msg_retry_work;
+
+	/** @post_yield_work: Work to yield the GPU */
+	struct work_struct post_yield_work;
 };
 
 static bool panthor_aw_is_open(struct panthor_aw *aw)
@@ -118,6 +121,52 @@ static int panthor_aw_state_wait_transition(struct panthor_aw *aw, u32 timeout_m
 		timeout_ms);
 }
 
+static void panthor_aw_post_yield_work(struct work_struct *work)
+{
+	struct panthor_aw *aw =
+		container_of(work, struct panthor_aw, post_yield_work);
+	struct panthor_device *ptdev = aw->ptdev;
+	struct device *dev = ptdev->base.dev;
+	int ret;
+
+	/* Something else has progressed the state to READY. */
+	if (atomic_read(&aw->state) != PANTHOR_AW_STATE_GPU_STOPPED)
+		return;
+
+	/*
+	 * Ensure in-progress resume is completed and prevent future RPM suspend
+	 * to keep the clocks turned on when accessing HW registers.
+	 */
+	pm_runtime_get_noresume(dev);
+	pm_runtime_barrier(dev);
+
+	ret = panthor_device_suspend_hw_components(ptdev);
+	if (ret)
+		dev_warn(dev, "Failed to suspend hardware components.");
+
+	panthor_aw_state_set(aw, PANTHOR_AW_STATE_READY);
+
+	/*
+	 * schedule an immediate tick to re-evaluate if there is any additional
+	 * work. This will request access to the GPU again and if the driver has
+	 * gone idle, it will yield GPU access via the runtime suspend path.
+	 */
+	panthor_sched_resume(ptdev);
+
+	pm_runtime_put_noidle(dev);
+}
+
+static bool panthor_aw_schedule_post_yield_work(struct panthor_aw *aw)
+{
+	if (panthor_aw_state_try_set(aw, PANTHOR_AW_STATE_GPU_GRANTED,
+				     PANTHOR_AW_STATE_GPU_STOPPED)) {
+		queue_work(aw->wq, &aw->post_yield_work);
+		return true;
+	}
+
+	return false;
+}
+
 static void panthor_aw_msg_retry_work(struct work_struct *work)
 {
 	struct panthor_aw *aw =
@@ -166,7 +215,9 @@ static void panthor_aw_handshake_handle(struct panthor_aw *aw, u64 message)
 
 		panthor_aw_send_msg(aw, reply);
 
-		/* TODO: Handle AW restart */
+		/* Arbiter was restarted. Window is no longer granted access. */
+		if (panthor_aw_schedule_post_yield_work(aw))
+			drm_info(&ptdev->base, "Arbiter was restarted, yielding GPU");
 	}
 
 	panthor_aw_state_try_set(aw, PANTHOR_AW_STATE_INIT, PANTHOR_AW_STATE_READY);
@@ -192,6 +243,38 @@ static void panthor_aw_handle_message(struct panthor_aw *aw)
 		drm_warn(&ptdev->base, "Unsupported msg id (0x%x)", msg_id);
 }
 
+static void panthor_aw_handle_window_closed(struct panthor_aw *aw)
+{
+	struct panthor_device *ptdev = aw->ptdev;
+
+	/* Ignore this WINDOW_CLOSED as part of reset operation. */
+	if (panthor_device_reset_is_pending(ptdev))
+		return;
+
+	if (atomic_read(&aw->state) == PANTHOR_AW_STATE_GPU_STOPPED ||
+	    atomic_read(&aw->state) == PANTHOR_AW_STATE_READY ||
+	    atomic_read(&aw->state) == PANTHOR_AW_STATE_INIT) {
+		drm_warn(&ptdev->base, "Unexpected WINDOW_CLOSED received");
+		return;
+	}
+
+	/*
+	 * Window may have been closed immediately after opening.
+	 * Setting state back to READY will prevent WINDOW_OPENDED from
+	 * mistakenly transitioning the state to GRANTED.
+	 */
+	if (panthor_aw_state_try_set(aw, PANTHOR_AW_STATE_GPU_REQUEST,
+				     PANTHOR_AW_STATE_READY))
+		return;
+
+	/* Triggerred from messaged-based yield. Unblock its wait */
+	if (panthor_aw_state_try_set(aw, PANTHOR_AW_STATE_STOPPED_IDLE,
+				     PANTHOR_AW_STATE_READY))
+		return;
+
+	panthor_aw_schedule_post_yield_work(aw);
+}
+
 static irqreturn_t panthor_aw_irq_raw_hander(int irq, void *data)
 {
 	struct panthor_irq *pirq = data;
@@ -211,7 +294,9 @@ static irqreturn_t panthor_aw_irq_raw_hander(int irq, void *data)
 	if (status & WINDOW_IRQ_MESSAGE)
 		panthor_aw_handle_message(aw);
 
-	/* TODO: handle WINDOW_CLOSED*/
+	if (status & WINDOW_IRQ_WINDOW_CLOSED)
+		panthor_aw_handle_window_closed(aw);
+
 
 	if ((status & WINDOW_IRQ_WINDOW_OPENED) && panthor_aw_is_open(aw))
 		panthor_aw_state_try_set(aw, PANTHOR_AW_STATE_GPU_REQUEST,
@@ -259,6 +344,7 @@ static int panthor_request_aw_irq(struct panthor_device *ptdev,
 
 static int panthor_aw_request(struct panthor_aw *aw)
 {
+	struct panthor_device *ptdev = aw->ptdev;
 	int ret;
 
 again:
@@ -266,6 +352,9 @@ static int panthor_aw_request(struct panthor_aw *aw)
 	case PANTHOR_AW_STATE_GPU_GRANTED:
 		return 0;
 
+	case PANTHOR_AW_STATE_GPU_STOPPED:
+		return -EAGAIN;
+
 	case PANTHOR_AW_STATE_READY:
 		break;
 
@@ -273,14 +362,22 @@ static int panthor_aw_request(struct panthor_aw *aw)
 		panthor_aw_handshake_init(aw);
 		ret = panthor_aw_state_wait(aw, PANTHOR_AW_STATE_READY,
 					    PANTHOR_AW_HANDSHAKE_TIMEOUT_MS);
-		if (ret)
+		if (ret) {
+			drm_err(&ptdev->base,
+				"Timed out waiting for handshake to complete");
 			return ret;
+		}
+
 		goto again;
 	default:
 		ret = panthor_aw_state_wait_transition(
 			aw, PANTHOR_AW_STATE_TRANSITION_TIMEOUT_MS);
-		if (ret)
+		if (ret) {
+			drm_err(&ptdev->base,
+				"Timed out waiting for AW state transition");
 			return ret;
+		}
+
 		goto again;
 	}
 
@@ -290,15 +387,20 @@ static int panthor_aw_request(struct panthor_aw *aw)
 
 	panthor_aw_send_msg(aw, VM_ARB_GPU_REQUEST);
 
-	/* Wait for GPU to be granted */
-	ret = panthor_aw_state_wait(aw, PANTHOR_AW_STATE_GPU_GRANTED,
-				    PANTHOR_AW_GPU_REQUEST_TIMEOUT_MS);
+	ret = panthor_aw_wait_cond(
+		aw, atomic_read(&aw->state) != PANTHOR_AW_STATE_GPU_REQUEST,
+		PANTHOR_AW_GPU_REQUEST_TIMEOUT_MS);
 	if (ret) {
-		panthor_aw_state_set(aw, PANTHOR_AW_STATE_READY);
+		if (!panthor_aw_state_try_set(aw, PANTHOR_AW_STATE_GPU_REQUEST,
+					      PANTHOR_AW_STATE_READY))
+			goto again;
+
+		drm_err(&ptdev->base,
+				"Timed out waiting for AW GPU to be granted");
 		return ret;
 	}
 
-	return 0;
+	goto again;
 }
 
 static int panthor_aw_yield(struct panthor_aw *aw)
@@ -330,6 +432,7 @@ int panthor_aw_init(struct panthor_device *ptdev)
 	aw->iomem = ptdev->iomem;
 
 	INIT_WORK(&aw->msg_retry_work, panthor_aw_msg_retry_work);
+	INIT_WORK(&aw->post_yield_work, panthor_aw_post_yield_work);
 
 	init_waitqueue_head(&aw->waitqueue);
 	atomic_set(&aw->state, PANTHOR_AW_STATE_INIT);
@@ -362,6 +465,7 @@ void panthor_aw_unplug(struct panthor_device *ptdev)
 		return;
 
 	disable_work_sync(&aw->msg_retry_work);
+	disable_work_sync(&aw->post_yield_work);
 
 	panthor_aw_irq_suspend(&aw->irq);
 }
@@ -371,17 +475,48 @@ int panthor_aw_resume(struct panthor_device *ptdev)
 	struct panthor_aw *aw = ptdev->aw;
 	int ret;
 
+	/* resume hw components directly if AW is not supported */
 	if (!aw)
-		return 0;
+		return panthor_device_resume_hw_components(ptdev);
 
 	panthor_aw_irq_resume(&aw->irq);
 
+again:
 	ret = panthor_aw_request(aw);
+	if (ret)
+		goto err_out;
+
+	ret = panthor_device_resume_hw_components(ptdev);
 	if (ret) {
-		drm_warn(&ptdev->base, "Timedout waiting for GPU to be granted");
+		/* Yield GPU access if HW components failed to resume */
+		if (panthor_aw_state_try_set(aw, PANTHOR_AW_STATE_GPU_GRANTED,
+					     PANTHOR_AW_STATE_STOPPED_IDLE)) {
+			/*
+			 * If failure is caused by WINDOW_CLOSED and the IRQ is
+			 * handled after this condition, AW may emit a rogue
+			 * idle event that will be ignored by the arbitration
+			 * scheduler. WINDOW_CLOSED handler will then transition
+			 * the state back to READY.
+			 */
+			panthor_aw_yield(aw);
+		}
+
+		goto err_out;
+	}
+
+	/*
+	 * WINDOW_CLOSED won the race. post_yield_work owns component cleanup
+	 * and will transition state to READY after this PM transition is
+	 * complete.
+	 */
+	if (atomic_read(&aw->state) == PANTHOR_AW_STATE_GPU_STOPPED) {
+		ret = -EAGAIN;
 		goto err_out;
 	}
 
+	if (atomic_read(&aw->state) != PANTHOR_AW_STATE_GPU_GRANTED)
+		goto again;
+
 	return 0;
 
 err_out:
@@ -396,20 +531,45 @@ int panthor_aw_suspend(struct panthor_device *ptdev)
 
 	/* suspend hw components directly if AW is not supported */
 	if (!aw)
-		return 0;
+		return panthor_device_suspend_hw_components(ptdev);
 
 	if (atomic_read(&aw->state) == PANTHOR_AW_STATE_READY)
 		goto out_irq_suspend;
 
+	if (atomic_read(&aw->state) == PANTHOR_AW_STATE_GPU_GRANTED) {
+		ret = panthor_device_suspend_hw_components(ptdev);
+		if (ret)
+			goto out_irq_suspend;
+	}
+
 	if (panthor_aw_state_try_set(aw, PANTHOR_AW_STATE_GPU_GRANTED,
-		PANTHOR_AW_STATE_GPU_STOPPED))
+		PANTHOR_AW_STATE_STOPPED_IDLE)) {
 		ret = panthor_aw_yield(aw);
-	else
-		ret = panthor_aw_state_wait(
-			aw, PANTHOR_AW_STATE_READY,
-			PANTHOR_AW_STATE_TRANSITION_TIMEOUT_MS);
+		if (ret)
+			panthor_aw_state_set(aw, PANTHOR_AW_STATE_READY);
+	}
 
 out_irq_suspend:
 	panthor_aw_irq_suspend(&aw->irq);
 	return ret;
 }
+
+int panthor_aw_ensure_gpu_access(struct panthor_device *ptdev)
+{
+	int ret;
+
+	if (!ptdev->aw)
+		return 0;
+
+again:
+	ret = panthor_aw_resume(ptdev);
+	if (ret != -EAGAIN)
+		return ret;
+
+	ret = panthor_aw_state_wait_transition(
+		ptdev->aw, PANTHOR_AW_STATE_TRANSITION_TIMEOUT_MS);
+	if (ret)
+		return ret;
+
+	goto again;
+}
diff --git a/drivers/gpu/drm/panthor/panthor_aw.h b/drivers/gpu/drm/panthor/panthor_aw.h
index c2b89caa87c48..7a46a1e18093a 100644
--- a/drivers/gpu/drm/panthor/panthor_aw.h
+++ b/drivers/gpu/drm/panthor/panthor_aw.h
@@ -24,10 +24,10 @@ enum aw_states {
 	/** @PANTHOR_AW_STATE_GPU_GRANTED: AW is granted GPU access. */
 	PANTHOR_AW_STATE_GPU_GRANTED,
 
-	/** @PANTHOR_AW_STATE_GPU_STOP: AW is requested to stop GPU access. */
-	PANTHOR_AW_STATE_GPU_STOP,
+	/** @PANTHOR_AW_STATE_STOPPED_IDLE: AW has stopped GPU access. */
+	PANTHOR_AW_STATE_STOPPED_IDLE,
 
-	/** @PANTHOR_AW_STATE_GPU_STOPPED: AW has stopped GPU access. */
+	/** @PANTHOR_AW_STATE_GPU_STOPPED: Window was closed, cleanup required. */
 	PANTHOR_AW_STATE_GPU_STOPPED,
 };
 
@@ -39,4 +39,6 @@ int panthor_aw_resume(struct panthor_device *ptdev);
 
 int panthor_aw_suspend(struct panthor_device *ptdev);
 
+int panthor_aw_ensure_gpu_access(struct panthor_device *ptdev);
+
 #endif
diff --git a/drivers/gpu/drm/panthor/panthor_device.c b/drivers/gpu/drm/panthor/panthor_device.c
index 2ccd8ad6318d1..ea35c5e1d87b4 100644
--- a/drivers/gpu/drm/panthor/panthor_device.c
+++ b/drivers/gpu/drm/panthor/panthor_device.c
@@ -577,11 +577,11 @@ int panthor_device_resume(struct device *dev)
 			atomic_set(&ptdev->reset.pending, 0);
 		}
 
-		ret = panthor_device_resume_hw_components(ptdev);
+		ret = panthor_aw_resume(ptdev);
 		if (ret && ptdev->reset.fast) {
 			drm_err(&ptdev->base, "Fast reset failed, trying a slow reset");
 			ptdev->reset.fast = false;
-			ret = panthor_device_resume_hw_components(ptdev);
+			ret = panthor_aw_resume(ptdev);
 		}
 
 		if (!ret)
@@ -650,7 +650,7 @@ int panthor_device_suspend(struct device *dev)
 		 * The end of the reset will happen in the resume path though.
 		 */
 		panthor_sched_suspend(ptdev);
-		panthor_device_suspend_hw_components(ptdev);
+		panthor_aw_suspend(ptdev);
 		drm_dev_exit(cookie);
 	}
 
diff --git a/drivers/gpu/drm/panthor/panthor_device.h b/drivers/gpu/drm/panthor/panthor_device.h
index 42c5052ac83b9..59bc48d05eb1e 100644
--- a/drivers/gpu/drm/panthor/panthor_device.h
+++ b/drivers/gpu/drm/panthor/panthor_device.h
@@ -19,6 +19,7 @@
 #include <drm/panthor_drm.h>
 
 #include "panthor_device_io.h"
+#include "panthor_aw.h"
 
 struct panthor_aw;
 struct panthor_csf;
@@ -466,8 +467,18 @@ static inline int panthor_device_resume_and_get(struct panthor_device *ptdev)
 	 * succeeded. Given resume errors are not expected, this is probably
 	 * something we can live with.
 	 */
-	if (ret && atomic_cmpxchg(&ptdev->pm.recovery_needed, 1, 0) == 1)
-		pm_runtime_set_suspended(ptdev->base.dev);
+	if (ret) {
+		if (atomic_cmpxchg(&ptdev->pm.recovery_needed, 1, 0) == 1)
+			pm_runtime_set_suspended(ptdev->base.dev);
+
+		return ret;
+	}
+
+	ret = panthor_aw_ensure_gpu_access(ptdev);
+	if (ret) {
+		pm_runtime_put_autosuspend(ptdev->base.dev);
+		return ret;
+	}
 
 	return ret;
 }
-- 
2.43.0

[PATCH v1 25/27] drm/panthor: Tolerate access-window loss during HW waits

[Karunika Choo]

The arbiter can close the access window while the driver is waiting for
GPU, power, or firmware acknowledgements. In that case the pending MMIO
wait cannot complete, but it should not be treated as a hardware timeout
or trigger recovery.

Add a helper to report whether the access window still owns GPU access
and use it to suppress timeout handling once access has been revoked.
Skip firmware-event processing when GPU access is unavailable.

Signed-off-by: Karunika Choo <karunika.choo@arm.com>
---
v1:
- extend access-window loss handling to fw boot wait.

 drivers/gpu/drm/panthor/panthor_aw.c    |  8 ++++++++
 drivers/gpu/drm/panthor/panthor_aw.h    |  2 ++
 drivers/gpu/drm/panthor/panthor_fw.c    |  5 +++--
 drivers/gpu/drm/panthor/panthor_gpu.c   |  4 +++-
 drivers/gpu/drm/panthor/panthor_pwr.c   | 27 +++++++++++++++++++------
 drivers/gpu/drm/panthor/panthor_sched.c |  5 +++++
 6 files changed, 42 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/panthor/panthor_aw.c b/drivers/gpu/drm/panthor/panthor_aw.c
index 4fcfb3ad05073..9ebb23eadfec5 100644
--- a/drivers/gpu/drm/panthor/panthor_aw.c
+++ b/drivers/gpu/drm/panthor/panthor_aw.c
@@ -573,3 +573,11 @@ int panthor_aw_ensure_gpu_access(struct panthor_device *ptdev)
 
 	goto again;
 }
+
+bool panthor_aw_has_gpu_access(struct panthor_device *ptdev)
+{
+	if (!ptdev->aw)
+		return true;
+
+	return (atomic_read(&ptdev->aw->state) == PANTHOR_AW_STATE_GPU_GRANTED);
+}
diff --git a/drivers/gpu/drm/panthor/panthor_aw.h b/drivers/gpu/drm/panthor/panthor_aw.h
index 7a46a1e18093a..1da613fa330a0 100644
--- a/drivers/gpu/drm/panthor/panthor_aw.h
+++ b/drivers/gpu/drm/panthor/panthor_aw.h
@@ -41,4 +41,6 @@ int panthor_aw_suspend(struct panthor_device *ptdev);
 
 int panthor_aw_ensure_gpu_access(struct panthor_device *ptdev);
 
+bool panthor_aw_has_gpu_access(struct panthor_device *ptdev);
+
 #endif
diff --git a/drivers/gpu/drm/panthor/panthor_fw.c b/drivers/gpu/drm/panthor/panthor_fw.c
index 1449d9a66302e..b4c234f3d3ea4 100644
--- a/drivers/gpu/drm/panthor/panthor_fw.c
+++ b/drivers/gpu/drm/panthor/panthor_fw.c
@@ -1140,9 +1140,10 @@ static int panthor_fw_start(struct panthor_device *ptdev)
 	gpu_write(fw->iomem, MCU_CONTROL, MCU_CONTROL_AUTO);
 
 	if (!wait_event_timeout(ptdev->fw->req_waitqueue,
-				ptdev->fw->booted,
+				(ptdev->fw->booted ||
+				 !panthor_aw_has_gpu_access(ptdev)),
 				msecs_to_jiffies(1000))) {
-		if (!ptdev->fw->booted &&
+		if (!ptdev->fw->booted && panthor_aw_has_gpu_access(ptdev) &&
 		    !(gpu_read(fw->irq.iomem, INT_STAT) & JOB_INT_GLOBAL_IF))
 			timedout = true;
 	}
diff --git a/drivers/gpu/drm/panthor/panthor_gpu.c b/drivers/gpu/drm/panthor/panthor_gpu.c
index e6e970e9b59d3..25fe7c77f8763 100644
--- a/drivers/gpu/drm/panthor/panthor_gpu.c
+++ b/drivers/gpu/drm/panthor/panthor_gpu.c
@@ -17,6 +17,7 @@
 #include <drm/drm_managed.h>
 #include <drm/drm_print.h>
 
+#include "panthor_aw.h"
 #include "panthor_device.h"
 #include "panthor_gpu.h"
 #include "panthor_gpu_regs.h"
@@ -376,7 +377,8 @@ int panthor_gpu_flush_caches(struct panthor_device *ptdev,
 				msecs_to_jiffies(100))) {
 		scoped_guard(spinlock, &ptdev->gpu->reqs_lock) {
 			if ((ptdev->gpu->pending_reqs & GPU_IRQ_CLEAN_CACHES_COMPLETED) != 0 &&
-			    !(gpu_read(gpu->irq.iomem, INT_RAWSTAT) & GPU_IRQ_CLEAN_CACHES_COMPLETED))
+			    !(gpu_read(gpu->irq.iomem, INT_RAWSTAT) &
+			      GPU_IRQ_CLEAN_CACHES_COMPLETED) && panthor_aw_has_gpu_access(ptdev))
 				ret = -ETIMEDOUT;
 			else
 				ptdev->gpu->pending_reqs &= ~GPU_IRQ_CLEAN_CACHES_COMPLETED;
diff --git a/drivers/gpu/drm/panthor/panthor_pwr.c b/drivers/gpu/drm/panthor/panthor_pwr.c
index cc2e01595f23b..2a0feb0b39ece 100644
--- a/drivers/gpu/drm/panthor/panthor_pwr.c
+++ b/drivers/gpu/drm/panthor/panthor_pwr.c
@@ -10,6 +10,7 @@
 #include <drm/drm_managed.h>
 #include <drm/drm_print.h>
 
+#include "panthor_aw.h"
 #include "panthor_device.h"
 #include "panthor_gpu_regs.h"
 #include "panthor_hw.h"
@@ -122,7 +123,8 @@ static int panthor_pwr_reset(struct panthor_device *ptdev, u32 reset_cmd)
 				msecs_to_jiffies(PWR_RESET_TIMEOUT_MS))) {
 		guard(spinlock_irqsave)(&ptdev->pwr->reqs_lock);
 
-		if (reset_pending(ptdev) && !reset_irq_raised(ptdev)) {
+		if (reset_pending(ptdev) && !reset_irq_raised(ptdev) &&
+		    panthor_aw_has_gpu_access(ptdev)) {
 			drm_err(&ptdev->base, "RESET timed out (0x%x)", reset_cmd);
 			return -ETIMEDOUT;
 		}
@@ -266,9 +268,14 @@ static int panthor_pwr_domain_transition(struct panthor_device *ptdev, u32 cmd,
 
 	panthor_pwr_write_command(ptdev, pwr_cmd, mask);
 
-	ret = gpu_read64_poll_timeout(pwr->iomem, ready_reg, val, (mask & val) == expected_val,
+	ret = gpu_read64_poll_timeout(pwr->iomem, ready_reg, val,
+				      ((mask & val) == expected_val ||
+				       !panthor_aw_has_gpu_access(ptdev)),
 				      100, timeout_us);
 	if (ret) {
+		if (!panthor_aw_has_gpu_access(ptdev))
+			return 0;
+
 		drm_err(&ptdev->base,
 			"timeout waiting on %s power domain transition, cmd(0x%x), arg(0x%llx)",
 			get_domain_name(domain), pwr_cmd, mask);
@@ -330,9 +337,13 @@ static int retract_domain(struct panthor_device *ptdev, u32 domain)
 	 * allow-flag will be set with delegated-flag being cleared.
 	 */
 	ret = gpu_read64_poll_timeout(pwr->iomem, PWR_STATUS, val,
-				      ((delegated_mask | allow_mask) & val) == allow_mask, 10,
-				      PWR_TRANSITION_TIMEOUT_US);
+				      (((delegated_mask | allow_mask) & val) == allow_mask ||
+				       !panthor_aw_has_gpu_access(ptdev)),
+				      10, PWR_TRANSITION_TIMEOUT_US);
 	if (ret) {
+		if (!panthor_aw_has_gpu_access(ptdev))
+			return 0;
+
 		drm_err(&ptdev->base, "Retracting %s domain timeout, cmd(0x%x)",
 			get_domain_name(domain), pwr_cmd);
 		return ret;
@@ -387,9 +398,13 @@ static int delegate_domain(struct panthor_device *ptdev, u32 domain)
 	 * allow-flag will be cleared with delegated-flag being set.
 	 */
 	ret = gpu_read64_poll_timeout(pwr->iomem, PWR_STATUS, val,
-				      ((delegated_mask | allow_mask) & val) == delegated_mask,
+				      (((delegated_mask | allow_mask) & val) == delegated_mask ||
+				       !panthor_aw_has_gpu_access(ptdev)),
 				      10, PWR_TRANSITION_TIMEOUT_US);
 	if (ret) {
+		if (!panthor_aw_has_gpu_access(ptdev))
+			return 0;
+
 		drm_err(&ptdev->base, "Delegating %s domain timeout, cmd(0x%x)",
 			get_domain_name(domain), pwr_cmd);
 		return ret;
@@ -519,7 +534,7 @@ void panthor_pwr_l2_power_off(struct panthor_device *ptdev)
 	const u64 pwr_status = gpu_read64(pwr->iomem, PWR_STATUS);
 
 	/* Abort if L2 power off constraints are not satisfied */
-	if (!(pwr_status & l2_allow_mask)) {
+	if (!(pwr_status & l2_allow_mask) && panthor_aw_has_gpu_access(ptdev)) {
 		drm_warn(&ptdev->base, "Power off L2 domain not allowed");
 		return;
 	}
diff --git a/drivers/gpu/drm/panthor/panthor_sched.c b/drivers/gpu/drm/panthor/panthor_sched.c
index ac6aee554820e..6d801329514e0 100644
--- a/drivers/gpu/drm/panthor/panthor_sched.c
+++ b/drivers/gpu/drm/panthor/panthor_sched.c
@@ -1887,6 +1887,9 @@ void panthor_sched_report_fw_events(struct panthor_device *ptdev, u32 events)
 
 	guard(spinlock)(&ptdev->scheduler->events_lock);
 
+	if (!panthor_aw_has_gpu_access(ptdev))
+		return;
+
 	if (events & JOB_INT_GLOBAL_IF) {
 		sched_process_global_irq_locked(ptdev);
 		events &= ~JOB_INT_GLOBAL_IF;
@@ -2060,6 +2063,8 @@ static int csgs_upd_ctx_apply_locked(struct panthor_device *ptdev,
 		csg_iface = panthor_fw_get_csg_iface(ptdev, csg_id);
 
 		ret = panthor_fw_csg_wait_acks(ptdev, csg_id, req_mask, &acked, 100);
+		if (ret && !panthor_aw_has_gpu_access(ptdev))
+			ret = 0;
 
 		if (acked & CSG_ENDPOINT_CONFIG)
 			csg_slot_sync_priority_locked(ptdev, csg_id);
-- 
2.43.0

[PATCH v1 26/27] drm/panthor: Prevent missed post-yield cleanup due to reset

[Karunika Choo]

With v15 GPUs, FW can yield GPU access at any point. This includes when
panthor has scheduled a reset. If a WINDOW_CLOSED event is received
after reset work is scheduled but before the actual RESET_SOFT command
is sent, panthor_aw can end up assuming that the WINDOW_CLOSED is a
result of the reset and fail to schedule the post-yield cleanup.

Introduce pre_reset and post_reset helpers for panthor_aw which marks a
granted AW as reset-active so reset-originated WINDOW_CLOSED handling
does not suppress post-yield cleanup when FW yield wins the race.

Signed-off-by: Karunika Choo <karunika.choo@arm.com>
---
 drivers/gpu/drm/panthor/panthor_aw.c     | 54 +++++++++++++++++++++---
 drivers/gpu/drm/panthor/panthor_aw.h     |  7 +++
 drivers/gpu/drm/panthor/panthor_device.c | 13 +++++-
 3 files changed, 65 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/panthor/panthor_aw.c b/drivers/gpu/drm/panthor/panthor_aw.c
index 9ebb23eadfec5..7ef13db4acf50 100644
--- a/drivers/gpu/drm/panthor/panthor_aw.c
+++ b/drivers/gpu/drm/panthor/panthor_aw.c
@@ -248,7 +248,7 @@ static void panthor_aw_handle_window_closed(struct panthor_aw *aw)
 	struct panthor_device *ptdev = aw->ptdev;
 
 	/* Ignore this WINDOW_CLOSED as part of reset operation. */
-	if (panthor_device_reset_is_pending(ptdev))
+	if (atomic_read(&aw->state) == PANTHOR_AW_STATE_RESET_ACTIVE)
 		return;
 
 	if (atomic_read(&aw->state) == PANTHOR_AW_STATE_GPU_STOPPED ||
@@ -260,14 +260,14 @@ static void panthor_aw_handle_window_closed(struct panthor_aw *aw)
 
 	/*
 	 * Window may have been closed immediately after opening.
-	 * Setting state back to READY will prevent WINDOW_OPENDED from
+	 * Setting state back to READY will prevent WINDOW_OPENED from
 	 * mistakenly transitioning the state to GRANTED.
 	 */
 	if (panthor_aw_state_try_set(aw, PANTHOR_AW_STATE_GPU_REQUEST,
 				     PANTHOR_AW_STATE_READY))
 		return;
 
-	/* Triggerred from messaged-based yield. Unblock its wait */
+	/* Triggered from messaged-based yield. Unblock its wait */
 	if (panthor_aw_state_try_set(aw, PANTHOR_AW_STATE_STOPPED_IDLE,
 				     PANTHOR_AW_STATE_READY))
 		return;
@@ -275,6 +275,17 @@ static void panthor_aw_handle_window_closed(struct panthor_aw *aw)
 	panthor_aw_schedule_post_yield_work(aw);
 }
 
+static void panthor_aw_handle_window_opened(struct panthor_aw *aw)
+{
+	/* Ignore this WINDOW_OPENED as part of reset operation. */
+	if (atomic_read(&aw->state) == PANTHOR_AW_STATE_RESET_ACTIVE)
+		return;
+
+	/* Window opened due to GPU_REQUEST */
+	panthor_aw_state_try_set(aw, PANTHOR_AW_STATE_GPU_REQUEST,
+				     PANTHOR_AW_STATE_GPU_GRANTED);
+}
+
 static irqreturn_t panthor_aw_irq_raw_hander(int irq, void *data)
 {
 	struct panthor_irq *pirq = data;
@@ -297,10 +308,8 @@ static irqreturn_t panthor_aw_irq_raw_hander(int irq, void *data)
 	if (status & WINDOW_IRQ_WINDOW_CLOSED)
 		panthor_aw_handle_window_closed(aw);
 
-
 	if ((status & WINDOW_IRQ_WINDOW_OPENED) && panthor_aw_is_open(aw))
-		panthor_aw_state_try_set(aw, PANTHOR_AW_STATE_GPU_REQUEST,
-					 PANTHOR_AW_STATE_GPU_GRANTED);
+		panthor_aw_handle_window_opened(aw);
 
 	gpu_write(pirq->iomem, INT_CLEAR, status);
 
@@ -579,5 +588,36 @@ bool panthor_aw_has_gpu_access(struct panthor_device *ptdev)
 	if (!ptdev->aw)
 		return true;
 
-	return (atomic_read(&ptdev->aw->state) == PANTHOR_AW_STATE_GPU_GRANTED);
+	switch (atomic_read(&ptdev->aw->state)) {
+	case PANTHOR_AW_STATE_GPU_GRANTED:
+	case PANTHOR_AW_STATE_RESET_ACTIVE:
+		return true;
+	}
+
+	return false;
+}
+
+void panthor_aw_pre_reset(struct panthor_device *ptdev)
+{
+	struct panthor_aw *aw = ptdev->aw;
+
+	if (!aw)
+		return;
+
+	panthor_aw_state_try_set(ptdev->aw, PANTHOR_AW_STATE_GPU_GRANTED,
+				 PANTHOR_AW_STATE_RESET_ACTIVE);
+}
+
+void panthor_aw_post_reset(struct panthor_device *ptdev)
+{
+	struct panthor_aw *aw = ptdev->aw;
+
+	if (!aw)
+		return;
+
+	panthor_aw_state_try_set(aw, PANTHOR_AW_STATE_RESET_ACTIVE,
+				 PANTHOR_AW_STATE_GPU_GRANTED);
+
+	if (!panthor_aw_is_open(aw))
+		panthor_aw_schedule_post_yield_work(aw);
 }
diff --git a/drivers/gpu/drm/panthor/panthor_aw.h b/drivers/gpu/drm/panthor/panthor_aw.h
index 1da613fa330a0..0269bbbbdc165 100644
--- a/drivers/gpu/drm/panthor/panthor_aw.h
+++ b/drivers/gpu/drm/panthor/panthor_aw.h
@@ -24,6 +24,9 @@ enum aw_states {
 	/** @PANTHOR_AW_STATE_GPU_GRANTED: AW is granted GPU access. */
 	PANTHOR_AW_STATE_GPU_GRANTED,
 
+	/** @PANTHOR_AW_STATE_RESET_ACTIVE: AW is being reset. */
+	PANTHOR_AW_STATE_RESET_ACTIVE,
+
 	/** @PANTHOR_AW_STATE_STOPPED_IDLE: AW has stopped GPU access. */
 	PANTHOR_AW_STATE_STOPPED_IDLE,
 
@@ -43,4 +46,8 @@ int panthor_aw_ensure_gpu_access(struct panthor_device *ptdev);
 
 bool panthor_aw_has_gpu_access(struct panthor_device *ptdev);
 
+void panthor_aw_pre_reset(struct panthor_device *ptdev);
+
+void panthor_aw_post_reset(struct panthor_device *ptdev);
+
 #endif
diff --git a/drivers/gpu/drm/panthor/panthor_device.c b/drivers/gpu/drm/panthor/panthor_device.c
index ea35c5e1d87b4..86eb4e9a61789 100644
--- a/drivers/gpu/drm/panthor/panthor_device.c
+++ b/drivers/gpu/drm/panthor/panthor_device.c
@@ -138,18 +138,27 @@ static void panthor_device_reset_work(struct work_struct *work)
 	if (!drm_dev_enter(&ptdev->base, &cookie))
 		return;
 
+	if (!panthor_aw_has_gpu_access(ptdev))
+		goto out_clear_pending;
+
 	panthor_sched_pre_reset(ptdev);
+	panthor_aw_pre_reset(ptdev);
 	panthor_fw_pre_reset(ptdev, true);
 	panthor_mmu_pre_reset(ptdev);
+
 	panthor_hw_soft_reset(ptdev);
+
 	panthor_hw_l2_power_on(ptdev);
 	panthor_mmu_post_reset(ptdev);
 	ret = panthor_fw_post_reset(ptdev);
-	atomic_set(&ptdev->reset.pending, 0);
+	panthor_aw_post_reset(ptdev);
 	panthor_sched_post_reset(ptdev, ret != 0);
+
+out_clear_pending:
+	atomic_set(&ptdev->reset.pending, 0);
 	drm_dev_exit(cookie);
 
-	if (ret) {
+	if (ret && panthor_aw_has_gpu_access(ptdev)) {
 		panthor_device_unplug(ptdev);
 		drm_err(&ptdev->base, "Failed to boot MCU after reset, making device unusable.");
 	}
-- 
2.43.0

[PATCH v1 27/27] drm/panthor: Release GPU access immediately for out-of-band grants

[Karunika Choo]

A late grant can arrive after the request has timed out and the access
window has returned to READY. Report GPU_STOPPED so the arbiter can
release the unused grant.

Signed-off-by: Karunika Choo <karunika.choo@arm.com>
---
 drivers/gpu/drm/panthor/panthor_aw.c | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/panthor/panthor_aw.c b/drivers/gpu/drm/panthor/panthor_aw.c
index 7ef13db4acf50..27787c0b2f3a2 100644
--- a/drivers/gpu/drm/panthor/panthor_aw.c
+++ b/drivers/gpu/drm/panthor/panthor_aw.c
@@ -282,8 +282,13 @@ static void panthor_aw_handle_window_opened(struct panthor_aw *aw)
 		return;
 
 	/* Window opened due to GPU_REQUEST */
-	panthor_aw_state_try_set(aw, PANTHOR_AW_STATE_GPU_REQUEST,
-				     PANTHOR_AW_STATE_GPU_GRANTED);
+	if (panthor_aw_state_try_set(aw, PANTHOR_AW_STATE_GPU_REQUEST,
+				     PANTHOR_AW_STATE_GPU_GRANTED))
+		return;
+
+	if (panthor_aw_state_try_set(aw, PANTHOR_AW_STATE_READY,
+				     PANTHOR_AW_STATE_STOPPED_IDLE))
+		panthor_aw_send_msg(aw, VM_ARB_GPU_STOPPED);
 }
 
 static irqreturn_t panthor_aw_irq_raw_hander(int irq, void *data)
-- 
2.43.0

Re: [PATCH v1 02/27] drm/panthor: Move register access helpers out of panthor_device.h

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] drm/panthor: missing and incorrect header dependencies in panthor_device_io.h
--

commit 4a15e81aefbe1480e274e929d06e5e1ad5234842
Author: Karunika Choo <karunika.choo@arm.com>

drm/panthor: Move register access helpers out of panthor_device.h

Move register access helpers out of panthor_device.h to allow reuse by
other panthor drivers that will be added to enable v15 support.

> diff --git a/drivers/gpu/drm/panthor/panthor_device.h b/drivers/gpu/drm/panthor/panthor_device.h
> index b55a3f9edd414..54031c5252473 100644
> --- a/drivers/gpu/drm/panthor/panthor_device.h
> +++ b/drivers/gpu/drm/panthor/panthor_device.h
> @@ -6,7 +6,6 @@
>  #ifndef __PANTHOR_DEVICE_H__
>  #define __PANTHOR_DEVICE_H__
>  
> -#include <linux/atomic.h>

[Severity: Low]
Is it okay to remove <linux/atomic.h> here? struct panthor_device (defined
further down in this file) relies heavily on atomic_t, such as for
retry_count and pending reset state. It seems to currently rely on
transitive inclusion from the newly added panthor_device_io.h.

>  #include <linux/io-pgtable.h>
>  #include <linux/regulator/consumer.h>
>  #include <linux/pm_runtime.h>

[ ... ]

> diff --git a/drivers/gpu/drm/panthor/panthor_device_io.h b/drivers/gpu/drm/panthor/panthor_device_io.h
> new file mode 100644
> index 0000000000000..2287a0d9f86c2
> --- /dev/null
> +++ b/drivers/gpu/drm/panthor/panthor_device_io.h
> @@ -0,0 +1,83 @@
> +/* SPDX-License-Identifier: GPL-2.0 or MIT */
> +/* Copyright 2026 ARM Limited. All rights reserved. */
> +
> +#ifndef __PANTHOR_DEVICE_IO_H__
> +#define __PANTHOR_DEVICE_IO_H__
> +
> +#include <linux/atomic.h>

[Severity: Low]
Does this file actually need <linux/atomic.h>? It doesn't appear to use any
atomic types.

> +#include <linux/io.h>
> +
> +
> +static inline void gpu_write(void __iomem *iomem, u32 reg, u32 data)
> +{
> +	writel(data, iomem + reg);
> +}

[ ... ]

> +static inline void gpu_write64(void __iomem *iomem, u32 reg, u64 data)
> +{
> +	gpu_write(iomem, reg, lower_32_bits(data));
> +	gpu_write(iomem, reg + 4, upper_32_bits(data));
> +}

[Severity: Low]
Should <linux/wordpart.h> be included for lower_32_bits() and
upper_32_bits()? Files including this header directly might fail to build if
the dependency isn't met transitively.

> +static inline u64 gpu_read64(void __iomem *iomem, u32 reg)
> +{
> +	return (gpu_read(iomem, reg) | ((u64)gpu_read(iomem, reg + 4) << 32));
> +}

[ ... ]

> +static inline u64 gpu_read64_counter(void __iomem *iomem, u32 reg)
> +{
> +	u32 lo, hi1, hi2;
> +	do {
> +		hi1 = gpu_read(iomem, reg + 4);
> +		lo = gpu_read(iomem, reg);
> +		hi2 = gpu_read(iomem, reg + 4);
> +	} while (hi1 != hi2);
> +	return lo | ((u64)hi2 << 32);
> +}
> +
> +#define gpu_read_poll_timeout(iomem, reg, val, cond, delay_us, timeout_us)	\
> +	read_poll_timeout(gpu_read, val, cond, delay_us, timeout_us, false,	\
> +			  iomem, reg)

[Severity: Low]
Should <linux/iopoll.h> be included here for the read_poll_timeout() macros?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260922204535.2850094-1-karunika.choo@arm.com?part=2

Re: [PATCH v1 10/27] dt-bindings: gpu: panthor: Document panthor-system bindings

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] dt-bindings: use of OS-specific driver name 'panthor' in DT node name
--

commit ee6d231b5dc0544f3b9572b62d9e84b81e33eedd
Author: Karunika Choo <karunika.choo@arm.com>

dt-bindings: gpu: panthor: Document panthor-system bindings

This commit introduces DT bindings for the ARM Mali 5th-Gen AM GPU's
AM_SYSTEM block. It documents the compatible string, registers, interrupts,
clocks, and regulators for this system node.

> diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-gen5-am-system.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-gen5-am-system.yaml
> new file mode 100644
> index 0000000000000..f0689bb8f05a2
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/gpu/arm,mali-gen5-am-system.yaml
[ ... ]
> +properties:
> +  $nodename:
> +    pattern: '^panthor-system@[a-f0-9]+$'

[Severity: Low]
Does this node name pattern violate the Device Tree specification's generic
names recommendation?

Device tree bindings are expected to describe the underlying hardware in an
OS-agnostic manner. Since 'panthor' is the name of the Linux DRM driver
rather than the hardware itself (ARM Mali 5th-Gen AM GPU's AM_SYSTEM block),
should this use a generic class name like '^gpu-system@[a-f0-9]+$' or
'^system-controller@[a-f0-9]+$' instead?

[ ... ]
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/interrupt-controller/irq.h>
> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +    panthor_system: panthor-system@68000000 {

[Severity: Low]
Similarly, this example demonstrates the OS-specific node name. Should it
be updated to match a generic functional name as well?

> +      compatible = "arm,mali-gen5-am-system";
> +      reg = <0x68000000 0x10000>;
[ ... ]

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260922204535.2850094-1-karunika.choo@arm.com?part=10

Re: [PATCH v1 15/27] drm/panthor: Add AM_RESOURCE_GROUP support

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 5 potential issue(s) to consider:
- [High] Runtime PM handling missing in shared IRQ handler
- [High] Missing synchronize_irq() during runtime suspend
- [High] CPU busy-loop in message retry workqueue
- [Medium] Missing NULL pointer checks for devm_kasprintf allocations
- [Low] Uninitialized irq field in panthor_resource_group
--

commit 97f87eba41075ad8e7f232b378d4561b841f68e5
Author: Karunika Choo <karunika.choo@arm.com>

drm/panthor: Add AM_RESOURCE_GROUP support

Add resource-group probing for the arbitration device, including MMIO
resources, IRQ handling, per-AW AM message helpers, handshake
negotiation, and retry work for deferred outgoing messages. Hook
resource groups into arbitration init, teardown, and runtime PM.

> diff --git a/drivers/gpu/drm/panthor/arbitration/panthor_resource_group.c b/drivers/gpu/drm/panthor/arbitration/panthor_resource_group.c
> new file mode 100644
> --- /dev/null
> +++ b/drivers/gpu/drm/panthor/arbitration/panthor_resource_group.c
> @@ -0,0 +1,323 @@
[ ... ]
> +static void rg_retry_messages(struct work_struct *work)
> +{
[ ... ]
> +	if (retry)
> +		queue_work(rg->wq, &rg->msg_retry_work);

[Severity: High]
Could this sequence lead to a CPU busy-loop? If the hardware has pending
messages and panthor_am_msg_retry() returns -EBUSY or -EAGAIN, this will
immediately requeue the work. Because it is an ordered workqueue and no
delay is specified, does this cause the worker thread to monopolize the
CPU at 100% until the hardware processes the messages?

[ ... ]
> +static irqreturn_t rg_irq_raw_handler(int irq, void *data)
> +{
> +	struct panthor_resource_group *rg = data;
> +	unsigned long message_mask;
> +	u32 status;
> +	u8 aw_id;
> +
> +	status = gpu_read(rg->iomem, AM_RG_IRQ_STATUS);
> +	if (!status)
> +		return IRQ_NONE;

[Severity: High]
Is it safe to perform this MMIO read without verifying device activity?
Since the IRQ is registered with IRQF_SHARED, this handler can be invoked
by other devices on the same line while this device is in runtime suspend.

If the device is powered down, the read will typically return ~0u, which
bypasses the !status check and could result in spurious processing of 16
pending messages. Should this use pm_runtime_get_if_active() to verify
the device is awake before accessing hardware?

[ ... ]
> +int panthor_resource_group_suspend(struct panthor_arbitration *adev)
> +{
> +	for (int i = 0; i < AM_ARB_MAX_RG_COUNT; i++) {
> +		struct panthor_resource_group *rg = adev->rg[i];
> +
> +		if (!rg)
> +			continue;
> +
> +		rg_irq_suspend(rg);
> +	}
> +
> +	return 0;
> +}

[Severity: High]
Does this suspend sequence need to wait for in-flight interrupts? The IRQ
is masked at the device level, but since it is registered as IRQF_SHARED,
rg_irq_raw_handler() might still be executing concurrently on another CPU.
Should there be a synchronize_irq() call here to prevent the device from
powering down while the handler is still running?

[ ... ]
> +static int resource_group_init(struct panthor_arbitration *adev,
> +			       const struct fwnode_handle *child)
> +{
[ ... ]
> +	rg = devm_kzalloc(dev, sizeof(*rg), GFP_KERNEL);
> +	if (!rg)
> +		return -ENOMEM;
> +
> +	name = devm_kasprintf(dev, GFP_KERNEL, "rg%d", res.id);

[Severity: Medium]
Could name be NULL here under memory pressure? devm_kasprintf() isn't
checked for allocation failure before being passed into functions expecting
valid strings, like devm_alloc_ordered_workqueue() below.

[ ... ]
> +	irq = fwnode_irq_get(child, 0);
> +	if (irq < 0)
> +		return dev_err_probe(dev, irq, "%s: Failed to get IRQ", name);
> +
> +	irqdata = irq_get_irq_data(irq);
> +	if (irqdata)
> +		irq_flags = irqd_get_trigger_type(irqdata);

[Severity: Low]
Should the retrieved IRQ number be stored in rg->irq here? The local irq
variable is populated and used for requesting the interrupt, but it doesn't
appear to be assigned to the structure field for future use.

> +
> +	ret = devm_request_irq(
> +		dev, irq, rg_irq_raw_handler, irq_flags | IRQF_SHARED,
> +		devm_kasprintf(dev, GFP_KERNEL, "panthor-%s-irq", name), rg);

[Severity: Medium]
Similar to the earlier devm_kasprintf() call, could this inner allocation
fail and pass a NULL device name to devm_request_irq()?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260922204535.2850094-1-karunika.choo@arm.com?part=15

Re: [PATCH v1 03/27] drm/panthor: Parse and store GPU_ID fields

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] drm/panthor: diagnostic info loss in GPU ID log
--

commit 18159d0a7677f6cb80f96ffd38fefa04603df0e5
Author: Karunika Choo <karunika.choo@arm.com>

drm/panthor: Parse and store GPU_ID fields
    
Prepare for Mali v15 by expanding GPU_ID to 64 bits and caching fields
during initialization.

> diff --git a/drivers/gpu/drm/panthor/panthor_hw.c b/drivers/gpu/drm/panthor/panthor_hw.c
> index 4c96573b649a1..2143e57d48106 100644
> --- a/drivers/gpu/drm/panthor/panthor_hw.c
> +++ b/drivers/gpu/drm/panthor/panthor_hw.c
> @@ -245,13 +245,13 @@ static int panthor_hw_info_init(struct panthor_device *ptdev)
>  	if (ret)
>  		return ret;
>  
> -	major = GPU_VER_MAJOR(ptdev->gpu_info.gpu_id);
> -	minor = GPU_VER_MINOR(ptdev->gpu_info.gpu_id);
> -	status = GPU_VER_STATUS(ptdev->gpu_info.gpu_id);
> +	major = ptdev->gpu_id.ver_major;
> +	minor = ptdev->gpu_id.ver_minor;
> +	status = ptdev->gpu_id.ver_status;
>  
>  	drm_info(&ptdev->base,
>  		 "%s id 0x%x major 0x%x minor 0x%x status 0x%x",
> -		 get_gpu_model_name(ptdev), ptdev->gpu_info.gpu_id >> 16,
> +		 get_gpu_model_name(ptdev), ptdev->gpu_id.prod_major,
>  		 major, minor, status);

[Severity: Low]
Does this unintentionally drop the architecture major, minor, and revision
values from the printed GPU ID?

Since ptdev->gpu_info.gpu_id >> 16 contains more than just the product major,
replacing it with only ptdev->gpu_id.prod_major causes an information loss in
the boot logs. 

For unknown GPUs, this makes it harder to identify the unsupported hardware
because it will log as id 0x2 instead of id 0xa002 (if arch=10, prod=2).

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260922204535.2850094-1-karunika.choo@arm.com?part=3

Re: [PATCH v1 18/27] dt-bindings: gpu: panthor: Document AW assignment DT property

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] dt-bindings: gpu: software resource policy in device tree
--

commit c9c432471efad1a2abcbaf062de9fa8ddb5708c3
Author: Karunika Choo <karunika.choo@arm.com>

dt-bindings: gpu: panthor: Document AW assignment DT property
    
Introduce arm,access-window-mask property to allow partitions to define
the assigned access windows at probe time.

> diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-gen5-am-arbitration.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-gen5-am-arbitration.yaml
> index 9ea2b4bb9a344..4e7933829e2be 100644
> --- a/Documentation/devicetree/bindings/gpu/arm,mali-gen5-am-arbitration.yaml
> +++ b/Documentation/devicetree/bindings/gpu/arm,mali-gen5-am-arbitration.yaml
> @@ -52,6 +52,15 @@ patternProperties:
>            Hardware partition control index. Must identify a partition present on
>            the GPU and be unique among this device's partition nodes.
>  
> +      arm,access-window-mask:
> +        $ref: /schemas/types.yaml#/definitions/uint32
> +        maximum: 0xffff
> +        default: 0
> +        description:
> +          Initial access window assignment mask. Bit N selects global
> +          access window ID N. Masks must be disjoint across partitions.
> +          If omitted, no access windows are assigned by default.
> +

[Severity: Low]
Does this new property improperly introduce software policy into the
hardware description bindings?

Encoding dynamic resource assignment with arm,access-window-mask in the
device tree dictates software policy rather than describing pure hardware
topology. 

This restricts the kernel's flexibility to dynamically assign resources
based on runtime workloads, as it forces an initial hardcoded allocation
upon driver probe.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260922204535.2850094-1-karunika.choo@arm.com?part=18

Re: [PATCH v1 13/27] drm/panthor: Add AM_PARTITION_CONTROL support

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 7 potential issue(s) to consider:
- [High] pm: Unsafe shared IRQ handling without Runtime PM validation
- [High] drm/panthor: CPU soft lockup risk in partition_state_wait()
- [Medium] pm: Hardware power leak due to pm_runtime_put_noidle() on teardown paths
- [Medium] drm/panthor: OPEN_WINDOW command issued without waiting for hardware reset
- [Medium] drm/panthor: TOCTOU race in window_open() and window_close()
- [Medium] drm/panthor: Type mismatch passing resource_size_t to %llx format specifier
- [Low] drm/panthor: Missing NULL check for devm_kasprintf() string allocation
--

commit aae06968ea5bf0c6d7a668bdeb14d91ee2943a9e
Author: Karunika Choo <karunika.choo@arm.com>

drm/panthor: Add AM_PARTITION_CONTROL support

Mali v15 AM GPUs expose AM_PARTITION_CONTROL blocks to manage partition
access windows. Add a panthor arbitration platform driver and wire it into
Kconfig and the panthor build.

> diff --git a/drivers/gpu/drm/panthor/arbitration/panthor_arbitration_drv.c b/drivers/gpu/drm/panthor/arbitration/panthor_arbitration_drv.c
> new file mode 100644
> index 0000000000000..09342245a47d1
> --- /dev/null
> +++ b/drivers/gpu/drm/panthor/arbitration/panthor_arbitration_drv.c

[ ... ]

> +int panthor_arbitration_parse_resource(struct device *dev,
> +				       const struct fwnode_handle *child,
> +				       struct panthor_arbitration_resource *res)
> +{

[ ... ]

> +	if (!fwnode_property_present(child, DT_ID)) {
> +		dev_warn(dev, "Missing '%s' property in %s@%llx", DT_ID, name,
> +			 res->res.start);
> +		return -ENODEV;
> +	}
> +
> +	ret = fwnode_property_read_u32(child, DT_ID, &res->id);
> +	if (ret) {
> +		dev_warn(dev, "Malformed '%s' property in %s@%llx", DT_ID, name,
> +			 res->res.start);

[Severity: Medium]
Will passing res->res.start (a resource_size_t) to a %llx format specifier
corrupt the variadic stack arguments on 32-bit builds?

[ ... ]

> +static int panthor_arbitration_probe(struct platform_device *pdev)
> +{

[ ... ]

> +	ret = panthor_partition_control_init(adev);
> +	if (ret)
> +		goto err_term_pc;
> +
> +	ret = of_platform_populate(dev->of_node, NULL, NULL, dev);
> +	if (ret)
> +		goto err_depopulate;
> +
> +	pm_runtime_set_autosuspend_delay(dev, PANTHOR_PM_AUTOSUSPEND_DELAY_MS);
> +	pm_runtime_use_autosuspend(dev);
> +
> +	pm_runtime_put_autosuspend(dev);
> +
> +	return 0;
> +
> +err_depopulate:
> +	of_platform_depopulate(dev);
> +
> +err_term_pc:
> +	panthor_partition_control_term(adev);
> +	pm_runtime_put_noidle(dev);
> +	return ret;

[Severity: Medium]
Does using pm_runtime_put_noidle() here leave the hardware permanently
powered on during a probe failure?

Since devres cleanup will invoke pm_runtime_disable() and cancel any pending
PM operations, using put_noidle instead of put_sync_suspend() drops the usage
count but doesn't schedule an idle check.

[ ... ]

> diff --git a/drivers/gpu/drm/panthor/arbitration/panthor_partition_control.c b/drivers/gpu/drm/panthor/arbitration/panthor_partition_control.c
> new file mode 100644
> index 0000000000000..e6fbf5e58b51a
> --- /dev/null
> +++ b/drivers/gpu/drm/panthor/arbitration/panthor_partition_control.c

[ ... ]

> +static int partition_state_wait(struct panthor_partition_control *pc, u32 state)
> +{
> +	u32 partition_state;
> +
> +	return read_poll_timeout_atomic(partition_state_get, partition_state,
> +					partition_state == state,
> +					PART_REG_POLL_SLEEP_US,
> +					PART_STATE_TRANSITION_TIMEOUT_US,
> +					false, pc);
> +}

[Severity: High]
Can read_poll_timeout_atomic() trigger CPU soft lockups if it busy-waits for
up to 5 seconds?

The PART_STATE_TRANSITION_TIMEOUT_US macro is set to 5,000,000 (5 seconds).
The atomic variant disables preemption and uses udelay(). Since callers run
in a sleepable context, should this use read_poll_timeout() instead?

[ ... ]

> +static int window_close(struct panthor_partition_control *pc)
> +{
> +	/* Partition already closed. */
> +	if (partition_state_get(pc) == PART_STATE_RESET)
> +		return 1;
> +
> +	guard(spinlock_irqsave)(&pc->lock);

[Severity: Medium]
Is there a time-of-check to time-of-use (TOCTOU) race here since the
hardware state is checked before the pc->lock is acquired?

[ ... ]

> +static int window_open(struct panthor_partition_control *pc, u8 aw_id)
> +{
> +	if (aw_id >= AM_ARB_MAX_AW_COUNT)
> +		return -EINVAL;
> +
> +	if (partition_state_get(pc) == PART_STATE_WINDOW_OPEN) {
> +		u8 cur_aw = partition_aw_get(pc);
> +
> +		if (cur_aw == aw_id)
> +			return 0;
> +
> +		dev_warn(pc->dev,
> +			 "%s: OPEN_WINDOW(%u): Already opened for aw=%u, state=%u. Closing...",
> +			 pc->name, aw_id, cur_aw, partition_state_get(pc));
> +
> +		window_close(pc);
> +	}
> +
> +	guard(spinlock_irqsave)(&pc->lock);

[Severity: Medium]
Similar to window_close(), we check the hardware state locklessly before
acquiring pc->lock. Can concurrent calls observe the state incorrectly?

> +
> +	gpu_write(pc->iomem, AM_PART_COMMAND,
> +		  AM_PART_SET_COMMAND(PART_CMD_OPEN_WINDOW) | AM_PART_SET_WINDOW(aw_id));

[Severity: Medium]
Does window_close() ensure the hardware has reached PART_STATE_RESET before
we issue the OPEN_WINDOW command here?

If window_close() asynchronously processes the close command, sending an open
command immediately to the exact same register might create a race condition,
potentially causing a PART_INVALID_COMMAND fault.

[ ... ]

> +static irqreturn_t partition_irq_raw_handler(int irq, void *data)
> +{
> +	struct panthor_partition_control *pc = data;
> +	u32 status;
> +
> +	status = gpu_read(pc->iomem, AM_PART_IRQ_STATUS);
> +	if (!status)
> +		return IRQ_NONE;

[Severity: High]
Since this handler is registered with IRQF_SHARED, could reading from the
hardware register without Runtime PM validation cause issues?

Other devices on the same interrupt line can trigger this handler. If the
device is runtime-suspended, this unconditional read could result in a bus
fault or return garbage data. Should this use pm_runtime_get_if_active()
first?

[ ... ]

> +static int partition_control_init(struct panthor_arbitration *adev,
> +				   const struct fwnode_handle *child)
> +{

[ ... ]

> +	pc = devm_kzalloc(dev, sizeof(*pc), GFP_KERNEL);
> +	if (!pc)
> +		return -ENOMEM;
> +
> +	name = devm_kasprintf(dev, GFP_KERNEL, "pc%d", res.id);
> +
> +	iomem = devm_ioremap_resource(dev, &res.res);

[Severity: Low]
Is there a missing NULL check for the name allocation here?

If devm_kasprintf() fails, name will be NULL, which is later passed to
another devm_kasprintf() for the IRQ name.

[ ... ]

> +	irqdata = irq_get_irq_data(irq);
> +	if (irqdata)
> +		irq_flags = irqd_get_trigger_type(irqdata);
> +
> +	ret = devm_request_irq(
> +		dev, irq, partition_irq_raw_handler, irq_flags | IRQF_SHARED,
> +		devm_kasprintf(dev, GFP_KERNEL, "panthor-%s-irq", name), pc);
> +	if (ret)
> +		return ret;

[Severity: High]
The irq is requested here, but it doesn't seem to be saved into pc->irq.

Without storing it, panthor_partition_control_suspend() cannot call
synchronize_irq() during power down, which risks suspending the hardware
while an interrupt is mid-flight.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260922204535.2850094-1-karunika.choo@arm.com?part=13

Re: [PATCH v1 14/27] drm/panthor: Add AM message helpers

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [High] Hardware race condition in panthor_am_msg_send() allows mailbox overwrite
- [Medium] gpu_read64() unspecified evaluation order in panthor_am_msg_read()
--

commit f795794def90956d30543ae04795a4ad4e76dd7e
Author: Karunika Choo <karunika.choo@arm.com>

drm/panthor: Add AM message helpers

This commit adds a shared helper layer for the AM_MESSAGE registers used by
v15 GPUs. It defines message IDs, register accessors, and a FIFO-backed
sending mechanism with spinlock serialization.

> diff --git a/drivers/gpu/drm/panthor/panthor_am_msg.h b/drivers/gpu/drm/panthor/panthor_am_msg.h
> new file mode 100644
> index 0000000000000..fc1e3f1051fe5
> --- /dev/null
> +++ b/drivers/gpu/drm/panthor/panthor_am_msg.h
[ ... ]
> +static inline u64 panthor_am_msg_read(struct panthor_am_msg *msg)
> +{
> +	return gpu_read64(msg->iomem, AM_INCOMING_MESSAGE0);
> +}

[Severity: Medium]
Could the unspecified evaluation order of the bitwise OR in gpu_read64()
cause hardware side-effect issues here?

Looking at gpu_read64() in panthor_device_io.h:

static inline u64 gpu_read64(void __iomem *iomem, u32 reg)
{
	return (gpu_read(iomem, reg) | ((u64)gpu_read(iomem, reg + 4) << 32));
}

The C standard leaves the evaluation order of bitwise OR operands unspecified.

If reading AM_INCOMING_MESSAGE0 has side effects (like clearing an interrupt
or popping a message queue), could the compiler evaluating the upper word
read before the lower word read lead to corrupted data or desynchronized
hardware state?

[ ... ]
> +static inline int panthor_am_msg_retry(struct panthor_am_msg *msg)
> +{
> +	u64 message;
> +
> +	guard(spinlock_irqsave)(&msg->lock);
> +
> +	if (kfifo_is_empty(&msg->send_fifo))
> +		return 0;
> +
> +	if (panthor_am_msg_pending(msg))
> +		return -EBUSY;

[Severity: High]
Is it possible for a race condition to occur with the hardware status update
here?

If the workqueue executes rapidly after a previous write,
panthor_am_msg_pending() might read as not busy due to hardware or internal
firmware propagation delays.

If the hardware status hasn't updated yet, could this cause the software to
overwrite the previous message in the mailbox?

> +
> +	/* FIFO should never be empty at this point */
> +	if (!kfifo_get(&msg->send_fifo, &message))
> +		return -EINVAL;
> +
> +	panthor_am_msg_write(msg, message);
> +
> +	/* There are still messages in the FIFO, notify caller to retry again */
> +	if (!kfifo_is_empty(&msg->send_fifo))
> +		return -EAGAIN;
> +
> +	return 0;
> +}
> +
> +static inline int panthor_am_msg_send(struct panthor_am_msg *msg, u64 message)
> +{
> +	guard(spinlock_irqsave)(&msg->lock);
> +
> +	/*
> +	 * If there already is a pending message in the FIFO or the outgoing
> +	 * message is still not read by the receipient, add to the FIFO.
> +	 */
> +	if (!kfifo_is_empty(&msg->send_fifo) || panthor_am_msg_pending(msg)) {

[Severity: High]
Similar to panthor_am_msg_retry(), could back-to-back calls to
panthor_am_msg_send() fail to observe the busy state from a preceding write?

If a CPU sends a message and another CPU (or the same CPU) immediately
acquires the lock to send a second message, the hardware status might
falsely read as 0.

Could this cause the second message to overwrite the first message in the
hardware mailbox before the firmware has processed it, leading to lost
messages?

> +		if (!kfifo_put(&msg->send_fifo, message))
> +			return -ENOSPC;
> +
> +		/*
> +		 * return -EBUSY to indicate to the caller to schedule work to
> +		 * retry sending messages in the FIFO.
> +		 */
> +		return -EBUSY;
> +	}
> +
> +	/* We are free to write to AM_OUTGOING_MESSAGE */
> +	panthor_am_msg_write(msg, message);
> +
> +	return 0;
> +}

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260922204535.2850094-1-karunika.choo@arm.com?part=14

Re: [PATCH v1 08/27] drm/panthor: Add Mali v15 hardware support

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] gpu: panthor: UB in GENMASK due to unvalidated MMU_FEATURES.AS_COUNT
--

commit f2f7bbf0c9994aff62f62839c8644ec4028839eb
Author: Karunika Choo <karunika.choo@arm.com>
Subject: drm/panthor: Add Mali v15 hardware support

This commit adds hardware support for Mali v15 GPUs in the panthor driver.
It introduces device matching, register definitions, and logic for populating
GPU information for the v15 architecture.

> diff --git a/drivers/gpu/drm/panthor/panthor_hw.c b/drivers/gpu/drm/panthor/panthor_hw.c
> index 13090ff6db7b5..9d539f5f80158 100644
> --- a/drivers/gpu/drm/panthor/panthor_hw.c
> +++ b/drivers/gpu/drm/panthor/panthor_hw.c
[ ... ]
> @@ -260,12 +304,55 @@ static int panthor_gpu_info_init(struct panthor_device *ptdev)
[ ... ]
> +static void panthor_gpu_info_v15_init(struct panthor_device *ptdev)
> +{
[ ... ]
> +	ptdev->gpu_info.core_features = gpu_read(ptdev->iomem, DISCOVER_CORE_FEATURES);
> +
> +	/* AS_PRESENT register removed on v15+ create virtual mask from MMU_FEATURES.AS_COUNT */
> +	ptdev->gpu_info.as_present = GENMASK(
> +		MMU_FEATURES_AS_COUNT(ptdev->gpu_info.mmu_features) - 1, 0);

[Severity: Medium]
Can this result in undefined behavior if the hardware reports an AS_COUNT
of 0?

If the DISCOVER_MMU_FEATURES register returns 0 (e.g., due to a hardware
fault, PCI/bus read failure, or uninitialized clock state),
MMU_FEATURES_AS_COUNT(ptdev->gpu_info.mmu_features) will evaluate to 0.
This would cause the code to evaluate GENMASK(-1, 0).

The GENMASK(h, l) macro invokes undefined behavior when h < l because it
results in a shift out of bounds (shifting ~UL(0) by BITS_PER_LONG). This
could produce an unpredictable value for the as_present bitmask, which may
lead to crashes or out-of-bounds accesses if the driver later attempts to
initialize non-existent address spaces based on a garbage mask.

> +
> +	ptdev->gpu_info.l2_present = gpu_read64(pwr_iomem, PWR_L2_PRESENT);
> +	ptdev->gpu_info.tiler_present = gpu_read64(pwr_iomem, PWR_TILER_PRESENT);
> +	ptdev->gpu_info.shader_present = gpu_read64(pwr_iomem, PWR_SHADER_PRESENT);
> +}

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260922204535.2850094-1-karunika.choo@arm.com?part=8

Re: [PATCH v1 11/27] drm/panthor: Add AM_SYSTEM platform driver

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 4 potential issue(s) to consider:
- [High] gpu: out-of-bounds 64-bit access on 32-bit AM_SYS_IRQ registers
- [High] pm: missing clock re-enablement in panthor_system_suspend() error path
- [Medium] driver: missing MODULE_DEVICE_TABLE prevents module autoloading
- [Medium] pm: missing hibernation callbacks in panthor_system_pm_ops
--

commit c920f013092a669426d1524348fe769140c7f85d
Author: Karunika Choo <karunika.choo@arm.com>

drm/panthor: Add AM_SYSTEM platform driver

This commit introduces a small AM_SYSTEM platform driver for Mali v15 AM
systems. It provides GPU-wide control, managing shared clock and regulator
resources, and performs the initial GPU reset sequence during probe.

> diff --git a/drivers/gpu/drm/panthor/system/panthor_system_drv.c b/drivers/gpu/drm/panthor/system/panthor_system_drv.c
> new file mode 100644
> --- /dev/null
> +++ b/drivers/gpu/drm/panthor/system/panthor_system_drv.c
[ ... ]
> +static int __panthor_system_reset(struct panthor_system *sdev, u32 cmd)
> +{
> +	u64 val;
> +
> +	/* Clear stale RESET_COMPLETED IRQs before issuing reset */
> +	gpu_write64(sdev->iomem, AM_SYS_IRQ_CLEAR, AM_SYS_IRQ_RESET_COMPLETED);

[Severity: High]
Does this code perform an out-of-bounds access? The AM_SYS_IRQ registers
such as AM_SYS_IRQ_CLEAR (at 0x4C) appear to be 32-bit registers. Using
gpu_write64 splits the access across two 32-bit registers, which might
clobber the adjacent register at 0x50 with the upper 32 bits.

> +
> +	gpu_write(sdev->iomem, AM_SYS_COMMAND, cmd);
> +
> +	return read_poll_timeout(gpu_read64, val,
> +				 (val & AM_SYS_IRQ_RESET_COMPLETED),
> +				 AM_SYS_RESET_SLEEP_US, AM_RESET_TIMEOUT_US, false,
> +				 sdev->iomem, AM_SYS_IRQ_RAWSTAT);

[Severity: High]
Can this similarly cause unintended side-effects? AM_SYS_IRQ_RAWSTAT (at
0x40) is also a 32-bit register. Using gpu_read64 will read from both
0x40 and 0x44, which might not be safe for hardware registers.

> +}
> +
> +static int panthor_system_reset(struct panthor_system *sdev)
> +{
> +	int ret;
> +
> +	ret = __panthor_system_reset(sdev, AM_SYS_CMD_SOFT_RESET);
> +	if (ret) {
> +		dev_err(sdev->dev, "SOFT_RESET failed, attempting HARD_RESET");
> +
> +		ret = __panthor_system_reset(sdev, AM_SYS_CMD_HARD_RESET);
> +		if (ret) {
> +			dev_err(sdev->dev, "HARD_RESET failed");
> +			return -EIO;
> +		}
> +	}
> +
> +	gpu_write64(sdev->iomem, AM_SYS_IRQ_CLEAR, AM_SYS_IRQ_RESET_COMPLETED);

[Severity: High]
As mentioned above, should this use the 32-bit gpu_write instead of
gpu_write64 to avoid clobbering the register at 0x50?

> +
> +	return 0;
> +}
> +
> +static int panthor_system_suspend(struct device *dev)
> +{
> +	struct panthor_system *sdev = dev_get_drvdata(dev);
> +
> +	panthor_system_clk_suspend(sdev);
> +	return panthor_system_regulator_suspend(sdev);

[Severity: High]
What happens if the regulator suspension fails? The function will return
the error directly, but the clock has already been suspended. 

The PM core might interpret the error to mean the device is still in the
RPM_ACTIVE state, but the hardware is physically unclocked. Could this
cause bus faults or system crashes on subsequent accesses? 

Should the clock be re-enabled in the error path?

> +}
[ ... ]
> +static const struct dev_pm_ops panthor_system_pm_ops = {
> +	.suspend = pm_runtime_force_suspend,
> +	.resume = pm_runtime_force_resume,
> +	.runtime_suspend = panthor_system_suspend,
> +	.runtime_resume = panthor_system_resume,
> +};

[Severity: Medium]
Does this code handle hibernation correctly? The panthor_system_pm_ops
structure manually assigns .suspend and .resume but leaves the hibernation
callbacks (.freeze, .thaw, .poweroff, .restore) undefined. 

During system hibernation or hybrid sleep, the PM core might skip freezing
or restoring the device. Should this use DEFINE_RUNTIME_DEV_PM_OPS or
SYSTEM_SLEEP_PM_OPS to wire all required sleep callbacks?

> +
> +static const struct of_device_id panthor_system_dt_match[] = {
> +	{ .compatible = "arm,mali-gen5-am-system" },
> +	{}
> +};

[Severity: Medium]
Is the MODULE_DEVICE_TABLE declaration missing here? Without exporting
the match table via MODULE_DEVICE_TABLE(of, panthor_system_dt_match),
the module will not have the necessary aliases generated, which prevents
udev from automatically loading the module when the compatible hardware
is detected.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260922204535.2850094-1-karunika.choo@arm.com?part=11

Re: [PATCH v1 12/27] dt-bindings: gpu: panthor: Document panthor-arbitration bindings

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [Low] dt-bindings: hardcoded driver-specific node name 'panthor-arbitration'
- [Low] dt-bindings: missing const constraints on #address-cells and #size-cells
--

commit 5958d9241a2d1add1102ff00e882946446a4e494
Author: Karunika Choo <karunika.choo@arm.com>

dt-bindings: gpu: panthor: Document panthor-arbitration bindings

Mali 5th-Gen AM GPUs expose arbitration registers outside the GPU node.
The arbitration device contains partition-control and resource-group
register blocks used to grant, yield, and close access windows.

Document partition and resource-group child nodes, each with its own
register range, interrupt and hardware ID.

> diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-gen5-am-arbitration.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-gen5-am-arbitration.yaml
> new file mode 100644
> index 0000000000000..9ea2b4bb9a344
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/gpu/arm,mali-gen5-am-arbitration.yaml

[ ... ]

> +properties:
> +  $nodename:
> +    const: panthor-arbitration

[Severity: Low]
Does this enforce an invalid, driver-specific naming convention on all
devicetrees using this hardware?

Any devicetree author attempting to instantiate this hardware must use the
Linux-specific driver name panthor-arbitration to pass schema validation.
This violates the DT specification requirement for generic,
hardware-reflective naming. 

Could this be changed to use a generic term like arbitrator or
gpu-arbitrator instead of incorporating the DRM driver name?

> +
> +  compatible:
> +    const: arm,mali-gen5-am-arbitration
> +
> +  "#address-cells": true
> +
> +  "#size-cells": true

[Severity: Low]
Should these cell-count properties have a strict const constraint matching
the hardware, such as const: 1 as shown in the examples, rather than just
true?

Without a strict constraint, the schema allows arbitrary integers for cell
counts. This weakens schema validation for child nodes' reg array dimensions,
and a device tree with incorrectly sized reg properties might silently pass
the dt_binding_check.

> +
> +  ranges: true

[ ... ]

> diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-gen5-am-system.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-gen5-am-system.yaml
> index f0689bb8f05a2..a027dc5f4f890 100644
> --- a/Documentation/devicetree/bindings/gpu/arm,mali-gen5-am-system.yaml
> +++ b/Documentation/devicetree/bindings/gpu/arm,mali-gen5-am-system.yaml

[ ... ]

> @@ -41,6 +41,15 @@ properties:
>  
>    dma-coherent: true
>  
> +  "#address-cells": true
> +
> +  "#size-cells": true

[Severity: Low]
Similar to the arbitration bindings, should these cell-count properties also
be defined with strict const constraints?

Allowing arbitrary integers weakens schema validation for child nodes' reg
array dimensions.

> +
> +  ranges: true
> +
> +  panthor-arbitration:
> +    $ref: arm,mali-gen5-am-arbitration.yaml#

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260922204535.2850094-1-karunika.choo@arm.com?part=12

Re: [PATCH v1 06/27] drm/panthor: Derive MMU AS register addresses from base and stride

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] panthor: NULL pointer dereference in MMU IRQ handler on spurious interrupts
--

commit 9aecd8c0de2222b2839590424b986eaecb02eee6
Author: Karunika Choo <karunika.choo@arm.com>

drm/panthor: Derive MMU AS register addresses from base and stride

This commit moves the MMU address-space register layout into the hardware
description. It computes the iomem pointer for each AS slot based on the base
offset and per-AS stride to prepare for GPUs with non-fixed MMU AS register
regions.

> diff --git a/drivers/gpu/drm/panthor/panthor_mmu.c b/drivers/gpu/drm/panthor/panthor_mmu.c
> index d75d575473da4..169550413a1a5 100644
> --- a/drivers/gpu/drm/panthor/panthor_mmu.c
> +++ b/drivers/gpu/drm/panthor/panthor_mmu.c
> @@ -1871,8 +1877,8 @@ static void panthor_mmu_irq_handler(struct panthor_irq *pirq, u32 status)
>  		u32 access_type;
>  		u32 source_id;
>  
> -		fault_status = gpu_read(mmu->iomem, AS_FAULTSTATUS(as));
> -		addr = gpu_read64(mmu->iomem, AS_FAULTADDRESS(as));
> +		fault_status = gpu_read(as_iomem(mmu, as), AS_FAULTSTATUS);
> +		addr = gpu_read64(as_iomem(mmu, as), AS_FAULTADDRESS);

[Severity: High]
Could this lead to a NULL pointer dereference on a spurious interrupt?

If the MMU interrupt status register has bits set for non-present AS slots
(such as from a hardware glitch, or reading 0xFFFFFFFF during a device
unplug or reset state), the loop in panthor_mmu_irq_handler() will process
these unpopulated slots.

Since as_iomem() returns NULL for slots that weren't initialized, passing
that NULL pointer to gpu_read() would trigger a kernel crash.

[ ... ]

> @@ -3408,7 +3417,13 @@ int panthor_mmu_init(struct panthor_device *ptdev)
>  	if (ret)
>  		return ret;
>  
> -	mmu->iomem = ptdev->iomem + MMU_AS_BASE;
> +	for_each_set_bit(as_id, &as_present_mask, MAX_AS_SLOTS) {
> +		u64 offset = regbank->offset + (regbank->stride * as_id);
> +
> +		guard(mutex)(&mmu->as.slots_lock);
> +		mmu->as.slots[as_id].iomem = ptdev->iomem + offset;
> +	}
> +

[Severity: High]
Because we only initialize the iomem pointers for present AS slots here,
the remaining array elements are left as NULL. Is there a need to guard
against accessing uninitialized slots in panthor_mmu_irq_handler() before
calling as_iomem() to prevent the issue mentioned above?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260922204535.2850094-1-karunika.choo@arm.com?part=6

Re: [PATCH v1 16/27] drm/panthor: Add arbitration scheduler

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 6 potential issue(s) to consider:
- [High] workqueue: infinite loop in reset_work on hardware unresponsiveness
- [High] timers: use-after-free due to timer re-arming by reset_work during teardown
- [High] timers: use-after-free due to missing IRQ teardown in remove error path
- [Medium] pm: incomplete error rollback in panthor_arbitration_sched_suspend()
- [Medium] probe: missing NULL check for devm_kasprintf() return
- [Medium] time: truncation of 64-bit module parameters in msecs_to_jiffies()
--

commit 48cf2a79eb3e38b7bf9c8fdb322edaecd8d1e020
Author: Karunika Choo <karunika.choo@arm.com>

drm/panthor: Add arbitration scheduler

Add a per-partition arbitration scheduler that queues access-window GPU
requests, grants the active window, asks it to stop when its lease
expires, and force-closes it if it does not yield in time.

Track grant, stop and close deadlines with hrtimers so scheduler
progress remains bounded. Use scheduler reset work to recover from
unrecoverable arbitration errors and stale timeout state.

> diff --git a/drivers/gpu/drm/panthor/arbitration/panthor_arbitration_drv.c b/drivers/gpu/drm/panthor/arbitration/panthor_arbitration_drv.c
> index a1068a2c78f1a..2d0c8d95f1abd 100644
> --- a/drivers/gpu/drm/panthor/arbitration/panthor_arbitration_drv.c
> +++ b/drivers/gpu/drm/panthor/arbitration/panthor_arbitration_drv.c
> @@ -56,6 +57,13 @@ static int panthor_arbitration_runtime_suspend(struct device *dev)
>  	struct panthor_arbitration *adev = dev_get_drvdata(dev);
>  	int ret = 0;
>  
> +	if (adev->tearing_down)
> +		return 0;
> +
> +	ret = panthor_arbitration_sched_suspend(adev);
> +	if (ret)
> +		return ret;
> +

[Severity: Medium]
Does returning early here leave the state partially broken?

In panthor_arbitration_sched_suspend(), if panthor_arbitration_sched_stop()
fails for scheduler N, the loop returns an error. Schedulers 0 to N-1 keep
the ARB_SCHED_DISABLE_PM flag. Propagating the error to the PM core here
means it considers the device active and won't call the resume path, which
permanently disables the successful schedulers from scheduling new access
windows.

>  	ret = panthor_resource_group_suspend(adev);
>  	if (ret)
>  		return ret;

[ ... ]

> @@ -151,15 +185,20 @@ static void panthor_arbitration_remove(struct platform_device *pdev)
>  		dev_warn(adev->dev, "failed to resume during remove: %d", ret);
>  
>  	of_platform_depopulate(adev->dev);
> -	panthor_resource_group_cancel_work(adev);
>  
>  	if (ret >= 0) {
> +		adev->tearing_down = true;
> +
> +		panthor_arbitration_sched_term(adev);
> +		panthor_resource_group_cancel_work(adev);
>  		panthor_resource_group_term(adev);
>  		panthor_partition_control_term(adev);
> -		pm_runtime_put_noidle(adev->dev);
> +		pm_runtime_put_sync_suspend(adev->dev);
> +	} else {
> +		panthor_arbitration_sched_cancel(adev);
> +		panthor_resource_group_cancel_work(adev);
> +		pm_runtime_set_suspended(adev->dev);
>  	}

[Severity: High]
Does this error path leave hardware interrupts registered and active?

If pm_runtime_resume_and_get() fails, the error path is taken, but it misses
calling panthor_partition_control_term() or panthor_resource_group_term().

A late shared interrupt could trigger the handler and invoke
panthor_arbitration_sched_on_idle(). Because the scheduler's phase is not
reset in panthor_arbitration_sched_cancel(), it can proceed to
arb_sched_close_locked() which re-arms the timer on a soon-to-be-freed
object, leading to a use-after-free.

> -
> -	pm_runtime_set_suspended(adev->dev);
>  }
>  
>  static const struct dev_pm_ops panthor_arbitration_pm_ops = {
> diff --git a/drivers/gpu/drm/panthor/arbitration/panthor_arbitration_sched.c b/drivers/gpu/drm/panthor/arbitration/panthor_arbitration_sched.c
> new file mode 100644
> index 0000000000000..41f06af92ce0c
> --- /dev/null
> +++ b/drivers/gpu/drm/panthor/arbitration/panthor_arbitration_sched.c

[ ... ]

> +/* This method is not IRQ safe as it sleeps. */
> +static int arb_sched_wait_phase(struct panthor_arbitration_sched *sched,
> +				enum arbitration_sched_phase phase,
> +				u64 timeout_ms)
> +{
> +	if (!wait_event_timeout(
> +		    sched->waitqueue, arb_sched_phase_reached(sched, phase),
> +		    msecs_to_jiffies(timeout_ms))) {

[Severity: Medium]
Will this truncate the 64-bit timeout values?

The module parameters request_timeout and yield_timeout are defined as u64.
In arb_sched_wait_phase(), their sum is passed to msecs_to_jiffies(), which
takes an unsigned int. If userspace sets excessively large timeouts, the
value could truncate silently, resulting in an unexpectedly short or zero
timeout.

> +
> +		if (!arb_sched_phase_reached(sched, phase))
> +			return -ETIMEDOUT;
> +	}

[ ... ]

> +static int __arb_sched_close_locked(struct panthor_arbitration_sched *sched)
> +{
> +	int ret;
> +
> +	lockdep_assert_held(&sched->lock);
> +
> +	ret = panthor_arbitration_on_close(to_adev(sched), sched->active_aw_id);
> +	if (ret < 0) {
> +		dev_err(sched->dev, "%s: Failed to close AW%u", sched->name,
> +			sched->active_aw_id);
> +
> +		arb_sched_queue_work(sched, &sched->reset_work);
> +	}

[Severity: High]
Can this cause an infinite loop in the workqueue?

If the hardware becomes unresponsive and panthor_arbitration_on_close()
persistently returns an error, __arb_sched_close_locked() queues reset_work. 

The reset_work executes arb_sched_force_close_locked(), which recursively
attempts __arb_sched_close_locked(). This fails again and re-queues
reset_work ad infinitum.

> +
> +	return ret;
> +}
> +
> +static void arb_sched_close_locked(struct panthor_arbitration_sched *sched)
> +{
> +	int ret;
> +
> +	lockdep_assert_held(&sched->lock);
> +
> +	ret = __arb_sched_close_locked(sched);
> +	if (!ret) {
> +		sched->close_timer.epoch = sched->epoch;
> +		hrtimer_start(&sched->close_timer.timer,
> +			      ms_to_ktime(yield_timeout), HRTIMER_MODE_REL);
> +	} else if (ret > 0) {

[Severity: High]
Is it safe to unconditionally re-arm the timer here?

During panthor_arbitration_sched_stop(), all timers are cancelled and
flush_workqueue() is called. If a reset_work is pending, it executes and
calls arb_sched_close_locked(), which re-arms the close_timer unconditionally.

Without checking if a teardown is in progress (such as checking for
ARB_SCHED_DISABLE_TERM), this can lead to a use-after-free when the re-armed
hrtimer expires and its callback executes on a freed object.

[ ... ]

> +static int arbitration_sched_init(struct panthor_arbitration *adev, int i)
> +{
> +	struct device *dev = adev->dev;
> +	struct panthor_arbitration_sched *sched;
> +
> +	sched = devm_kzalloc(dev, sizeof(*sched), GFP_KERNEL);
> +	if (!sched)
> +		return -ENOMEM;
> +
> +	sched->name = devm_kasprintf(dev, GFP_KERNEL, "sched%d", i);
> +	sched->dev = dev;
> +
> +	sched->wq = devm_alloc_ordered_workqueue(dev, "%s-wq", 0, sched->name);

[Severity: Medium]
Could devm_kasprintf() return NULL here?

If memory allocation fails, sched->name will be NULL. It is immediately
passed to devm_alloc_ordered_workqueue() which will dereference it for
string formatting, leading to a kernel crash.

> +	if (!sched->wq)
> +		return -ENOMEM;

[ ... ]

> +int panthor_arbitration_sched_suspend(struct panthor_arbitration *adev)
> +{
> +	for (int i = 0; i < AM_ARB_MAX_PC_COUNT; i++) {
> +		struct panthor_arbitration_sched *sched = adev->sched[i];
> +		int ret;
> +
> +		if (!sched)
> +			continue;
> +
> +		panthor_arbitration_sched_disable_set(sched, ARB_SCHED_DISABLE_PM);
> +		ret = panthor_arbitration_sched_stop(sched);
> +		if (ret) {
> +			panthor_arbitration_sched_disable_clear(
> +				sched, ARB_SCHED_DISABLE_PM);
> +			return ret;
> +		}

[Severity: Medium]
Does this properly roll back the state of previously processed schedulers?

If panthor_arbitration_sched_stop() fails for scheduler N, the loop returns
an error. Schedulers 0 to N-1 will remain permanently disabled because
ARB_SCHED_DISABLE_PM is not cleared for them.

> +	}
> +
> +	return 0;
> +}

[ ... ]

> +int panthor_arbitration_sched_stop(struct panthor_arbitration_sched *sched)
> +{
> +	int ret;
> +
> +	arb_sched_request_stop(sched);
> +
> +	/*
> +	 * Provisionally waiting for up to 2x yield_timeout, but path may
> +	 * include time taken for panthor_arbitration_on_grant() to complete
> +	 * if sched_request_stop() is called while in the GRANTING state.
> +	 *
> +	 * Realistically, if granting takes more than yield_timeout, HW is in
> +	 * bad state either way. Best continue and stop the scheduler.
> +	 */
> +	ret = arb_sched_wait_phase(sched, ARB_SCHED_PHASE_IDLE,
> +				   request_timeout + yield_timeout);
> +	if (ret)
> +		arb_sched_force_close(sched);
> +
> +	/* Should no longer have any further activity. Cancel timer. */
> +	hrtimer_cancel(&sched->grant_timer.timer);
> +	hrtimer_cancel(&sched->stop_timer.timer);
> +	hrtimer_cancel(&sched->close_timer.timer);
> +	flush_workqueue(sched->wq);

[Severity: High]
Will this hang indefinitely if reset_work is trapped in a re-queuing loop?

As noted earlier, if the hardware becomes unresponsive,
__arb_sched_close_locked() queues reset_work which recursively fails and
re-queues itself. This unthrottled infinite loop will block
flush_workqueue() indefinitely during system suspend or driver removal.

> +
> +	scoped_guard(spinlock_irqsave, &sched->lock)
> +		if (sched->phase == ARB_SCHED_PHASE_IDLE)
> +			return 0;
> +
> +	return ret;
> +}

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260922204535.2850094-1-karunika.choo@arm.com?part=16

Re: [PATCH v1 04/27] drm/panthor: Add 64-bit GPU_ID decoding for v15 GPUs

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [Medium] drm/panthor: missing driver version bump for UAPI addition
- [Low] drm/tyr: build failure due to exhaustive struct initialization
--

commit 543a83f06edb5e6a777b3ef1eefcac27b352d2c8
Author: Karunika Choo <karunika.choo@arm.com>

drm/panthor: Add 64-bit GPU_ID decoding for v15 GPUs

Mali v15 exposes a 64-bit GPU_ID register with a different field layout
from earlier GPUs. This patch adds the register definitions, decoding helpers,
and populates the new uAPI gpu_wide_id field.

> diff --git a/include/uapi/drm/panthor_drm.h b/include/uapi/drm/panthor_drm.h
> index a2ff0f4ec6915..843a0b40e1d36 100644
> --- a/include/uapi/drm/panthor_drm.h
> +++ b/include/uapi/drm/panthor_drm.h
[ ... ]
> @@ -376,6 +376,19 @@ struct drm_panthor_gpu_info {
>  
>  	/** @gpu_features: Bitmask describing supported GPU-wide features */
>  	__u64 gpu_features;
> +
> +	/**
> +	 * @gpu_wide_id: 64-bit GPU ID for v15 and later GPUs. @gpu_id is 0 when
> +	 * this is populated.
> +	 */
> +	__u64 gpu_wide_id;

[Severity: Medium]
Does the addition of this new UAPI field require a driver version bump?

The UAPI documentation for Panthor mandates that each new flag or field
addition must come with a driver version update, so the userspace driver
doesn't have to rely on trial and error to know which flags are supported.

However, the driver minor version in panthor_drm_driver within
drivers/gpu/drm/panthor/panthor_drv.c remains at 9:

	.major = 1,
	.minor = 9,

Will userspace be forced to use trial and error to determine support for
this field without an incremented minor version?

[Severity: Low]
Will this UAPI structure modification cause a build failure in the Rust tyr
driver?

The Rust driver utilizes this structure via bindgen and initializes it
exhaustively in GpuInfo::new() within drivers/gpu/drm/tyr/gpu.rs:

        Self(uapi::drm_panthor_gpu_info {
            gpu_id: io.read(GPU_ID).into_raw(),
            gpu_rev: io.read(REVIDR).into_raw(),

Because the exhaustive initializer lacks the new gpu_wide_id field, the
Rust compiler will fail with a missing field error. Has this compile-time
regression been addressed?

> +#define DRM_PANTHOR_WIDE_ARCH_MAJOR(x)		(((x) >> 56) & 0xff)
> +#define DRM_PANTHOR_WIDE_ARCH_MINOR(x)		(((x) >> 48) & 0xff)

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260922204535.2850094-1-karunika.choo@arm.com?part=4

Re: [PATCH v1 20/27] drm/panthor: Handle partition control INVALID_COMMAND interrupt

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 4 potential issue(s) to consider:
- [High] drm/panthor: stale pc->last_cmd state from untracked yield_idle() causes spurious command handling
- [High] drm/panthor: synchronous state evaluation in INVALID_COMMAND handler races with hardware transitions
- [High] drm/panthor: lockless state check in window_close() causes permanently leaked windows
- [High] drm/panthor: overwriting pc->current_aw before CLOSE_WINDOW completes breaks state machine
--

commit 137cc070e4a25e7d342b37a597b27e601b15068c
Author: Karunika Choo <karunika.choo@arm.com>

drm/panthor: Handle partition control INVALID_COMMAND interrupt

This commit introduces handling for INVALID_COMMAND interrupts when partition
state requirements are not met. It retries commands when the partition state
permits, or requests scheduler recovery for open-window commands with
inconsistent assignments.

> diff --git a/drivers/gpu/drm/panthor/arbitration/panthor_partition_control.c b/drivers/gpu/drm/panthor/arbitration/panthor_partition_control.c
> index 95c26015cb637..446f77fc67891 100644
> --- a/drivers/gpu/drm/panthor/arbitration/panthor_partition_control.c
> +++ b/drivers/gpu/drm/panthor/arbitration/panthor_partition_control.c
[ ... ]
> @@ -101,18 +114,45 @@ static int partition_state_wait(struct panthor_partition_control *pc, u32 state)
[ ... ]
>  static int yield_idle(struct panthor_partition_control *pc)
>  {
> -	gpu_write(pc->iomem, AM_PART_COMMAND,
> -		  AM_PART_SET_COMMAND(PART_CMD_YIELD_IDLE));
> +	guard(spinlock_irqsave)(&pc->lock);
> +
> +	/*
> +	 * This is a notification to yield the GPU once FW is idle. It is not
> +	 * a command that must succeed. Nothing of note is lost if the command
> +	 * fails apart from some minor scheduling optimisation losses. We can
> +	 * skip tracking this command.
> +	 */
> +	partition_command_write_untracked(
> +		pc, AM_PART_SET_COMMAND(PART_CMD_YIELD_IDLE));

[Severity: High]
Does sending PART_CMD_YIELD_IDLE untracked leave stale state in pc->last_cmd?

If the scheduler calls yield_idle() and the hardware rejects the command,
raising PART_INVALID_COMMAND, the interrupt handler will read the stale
pc->last_cmd (for instance, from a previous OPEN_WINDOW) and act upon it.
Can this lead to spurious command retries or fatal scheduler resets?

>  
>  	return 0;
>  }
> @@ -127,8 +167,8 @@ static int window_close(struct panthor_partition_control *pc)
>  

[Severity: High]
Does the lockless hardware state check at the beginning of window_close()
race with pending commands?

If called immediately after window_open(), the hardware state may still be
PART_STATE_RESET because the OPEN_WINDOW command is still in flight.
window_close() assumes the window is already closed and returns early
without sending CLOSE_WINDOW, leaving the window permanently open and
leaking hardware resources.

>  	pc->closing = true;
>  
> -	gpu_write(pc->iomem, AM_PART_COMMAND,
> -		  AM_PART_SET_COMMAND(PART_CMD_CLOSE_WINDOW));
> +	partition_command_write(pc, AM_PART_SET_COMMAND(PART_CMD_CLOSE_WINDOW),
> +				pc->current_aw);
>  
>  	return 0;
>  }
> @@ -153,8 +193,8 @@ static int window_open(struct panthor_partition_control *pc, u8 aw_id)
>  
>  	guard(spinlock_irqsave)(&pc->lock);
>  
> -	gpu_write(pc->iomem, AM_PART_COMMAND,
> -		  AM_PART_SET_COMMAND(PART_CMD_OPEN_WINDOW) | AM_PART_SET_WINDOW(aw_id));
> +	partition_command_write(pc, (AM_PART_SET_COMMAND(PART_CMD_OPEN_WINDOW) |
> +				     AM_PART_SET_WINDOW(aw_id)), aw_id);
>  
>  	pc->current_aw = aw_id;

[Severity: High]
Does overwriting pc->current_aw before CLOSE_WINDOW completes break the
state machine?

In window_open(), if the window is already open, it calls window_close()
and then immediately overwrites pc->current_aw with the new aw_id. When
the hardware finishes closing and raises PART_RESET_DONE, the handler
consumes the new current_aw, clears it to -1, and sends a spurious stop
notification for the new window. Subsequent INVALID_COMMAND interrupts
for the new window will be ignored.

>  
> @@ -166,6 +206,8 @@ static void partition_handle_reset_done(struct panthor_partition_control *pc)
[ ... ]
> +static void partition_handle_invalid_cmd(struct panthor_partition_control *pc)
> +{
[ ... ]
> +		switch (AM_PART_GET_COMMAND(pc->last_cmd.cmd)) {
> +		case PART_CMD_YIELD_NOW:
> +		case PART_CMD_CLOSE_WINDOW:
> +			if (partition_state_get(pc) == PART_STATE_WINDOW_OPEN) {
> +				partition_command_write_untracked(pc, pc->last_cmd.cmd);
> +				return;
> +			}
> +			break;
> +		case PART_CMD_OPEN_WINDOW:
> +			if (partition_state_get(pc) == PART_STATE_RESET) {
> +				partition_command_write_untracked(pc, pc->last_cmd.cmd);
> +				return;
> +			} else if (partition_aw_get(pc) == pc->last_cmd.aw_id) {
> +				return;
> +			}
> +
> +			on_err = true;

[Severity: High]
Does this synchronous state evaluation race with hardware transitions?

When OPEN_WINDOW is sent back-to-back after CLOSE_WINDOW, the hardware
rejects it because it hasn't reached PART_STATE_RESET yet. The IRQ fires,
and the handler synchronously reads the hardware state. If the hardware is
still transitioning and hasn't reached RESET, the handler falls through to
setting on_err = true, causing a fatal scheduler reset instead of retrying.

> +			aw_id = pc->last_cmd.aw_id;
> +
> +			break;
> +		default:
> +			return;
> +		}
> +	}
> +
> +	if (on_err)
> +		panthor_arbitration_notify_err(dev_get_drvdata(pc->dev), aw_id);
> +}

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260922204535.2850094-1-karunika.choo@arm.com?part=20

Re: [PATCH v1 17/27] drm/panthor: Route arbitration events

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] drm/panthor: UAF in arbitration IRQ handlers due to devres ordering
--

commit 35b5829f1e7e37f44df0de386a8d626358959c51
Author: Karunika Choo <karunika.choo@arm.com>

drm/panthor: Route arbitration events

This commit wires the resource-group, scheduler, and partition-control blocks
together. It routes resource-group messages and partition reset events to the
scheduler, and adds callbacks for granting, yielding, and closing partition
windows.

> diff --git a/drivers/gpu/drm/panthor/arbitration/panthor_arbitration_drv.c b/drivers/gpu/drm/panthor/arbitration/panthor_arbitration_drv.c
> index 2d0c8d95f1abd..723cf605e16a3 100644
> --- a/drivers/gpu/drm/panthor/arbitration/panthor_arbitration_drv.c
> +++ b/drivers/gpu/drm/panthor/arbitration/panthor_arbitration_drv.c
> @@ -95,20 +95,42 @@ static int panthor_arbitration_runtime_resume(struct device *dev)
>  	return 0;
>  }
>  
> +/* AW to Arbiter events */
> +int panthor_arbitration_on_request(struct panthor_arbitration *adev, u8 aw_id)
> +{
> +	/* TODO: AW to PC assignment */
> +	return panthor_arbitration_sched_on_request(adev->sched[0], aw_id);
> +}

[Severity: High]
Does this introduce a use-after-free risk during driver teardown if a
pending interrupt fires?

In panthor_arbitration_probe(), the driver registers rg_irq_raw_handler and 
partition_irq_raw_handler using devm_request_irq() inside 
panthor_resource_group_init() before the sched structures are allocated using
devm_kzalloc() in panthor_arbitration_sched_init().

Because devres releases resources in LIFO order on probe failure or driver 
removal, the scheduler memory is freed before the IRQs are unregistered. 

If an interrupt fires or is pending during this teardown window, the active 
handler can route the event to panthor_arbitration_on_request(), which will 
dereference the already-freed adev->sched[0] pointer.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260922204535.2850094-1-karunika.choo@arm.com?part=17

Re: [PATCH v1 22/27] drm/panthor: Add access-window support

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 6 potential issue(s) to consider:
- [High] drm/panthor: missing AW IRQ cleanup in panthor_device_init() error path
- [High] drm/panthor: background msg_retry_work runs concurrently with suspend
- [Medium] workqueue: 100% CPU busy loop in panthor_aw_msg_retry_work
- [Medium] drm/panthor: 5-second stall during device unplug due to disabled AW IRQs
- [Medium] drm/panthor: dropped AM messages cause 5-second timeout stalls
- [Low] drm/panthor: ignored -EOPNOTSUPP in AW handshake leads to unsupported protocol usage
--

commit 3a133f64881fd3095e93885e724b739d725e86af
Author: Karunika Choo <karunika.choo@arm.com>

drm/panthor: Add access-window support

Add the VM-side access-window component for v15 GPUs. The new code
handles AM message handshakes, requests GPU access from the arbiter,
waits for the window-open interrupt, and yields access on suspend.
Split panthor_hw_init into bind device and initialize gpu_info after
panthor_aw has ensured GPU access.

> diff --git a/drivers/gpu/drm/panthor/panthor_aw.c b/drivers/gpu/drm/panthor/panthor_aw.c
> index 0000000000000..848fd64eb51b5
> --- /dev/null
> +++ b/drivers/gpu/drm/panthor/panthor_aw.c
[ ... ]
> @@ -118,17 +118,16 @@ static void panthor_aw_msg_retry_work(struct work_struct *work)
>  	struct panthor_aw *aw =
>  		container_of(work, struct panthor_aw, msg_retry_work);
>  	struct panthor_am_msg *msg = &aw->msg;
>  	int ret;
>  
>  	ret = panthor_am_msg_retry(msg);
>  	if (ret == -EINVAL)
>  		drm_warn(&aw->ptdev->base, "Send FIFO unexpectedly empty");
>  
>  	if (ret == -EBUSY || ret == -EAGAIN)
>  		queue_work(aw->wq, &aw->msg_retry_work);

[Severity: Medium]
Will this cause a busy loop pegging a CPU core? If panthor_am_msg_retry() 
returns -EBUSY (because the hardware AM_OUTGOING_MESSAGE FIFO is not empty), 
the workqueue immediately re-queues itself without any delay. Should this use
queue_delayed_work() or an interrupt-driven mechanism to back off while
hardware processes the request?

>  }
>  
>  static void panthor_aw_send_msg(struct panthor_aw *aw, u64 message)
>  {
>  	struct panthor_device *ptdev = aw->ptdev;
>  	int ret;
>  
>  	ret = panthor_am_msg_send(&aw->msg, message);
>  	if (ret == -ENOSPC)
>  		drm_err(&ptdev->base, "Send FIFO is full");

[Severity: Medium]
Should we handle this error instead of silently swallowing it? If the FIFO is
full, the request is never buffered or dispatched, meaning callers will 
unnecessarily stall for 5 seconds waiting for a state transition response that
will never arrive.

>  
>  	if (ret == -EBUSY) {
>  		drm_dbg(&ptdev->base, "Pending messages, scheduling retry work");
>  		queue_work(aw->wq, &aw->msg_retry_work);
>  	}
>  }
>  
>  static void panthor_aw_handshake_handle(struct panthor_aw *aw, u64 message)
>  {
>  	struct panthor_device *ptdev = aw->ptdev;
>  	bool acked = AM_MSG_ACK_GET(message);
>  	u8 version = AM_MSG_VERSION_GET(message);
>  	int ret;
>  
>  	ret = panthor_am_msg_version_validate(&aw->msg, version);
>  	if (ret == -EOPNOTSUPP)
>  		drm_warn(&ptdev->base,
>  			 "Msg protocol version less than minimum supported (%u < %u)",
>  			 version, AM_MSG_MIN_SUPPORTED_VERSION);

[Severity: Low]
Is it safe to ignore the -EOPNOTSUPP error and continue? Operating with an
unsupported firmware protocol version may cause undefined behavior or firmware
crashes. Should the code explicitly fail the initialization rather than
assuming it is safe to interact with an incompatible Arbiter version?

>  
>  	if (!acked) {
>  		u64 reply = VM_ARB_INIT_MAKE(1, aw->msg.version);
>  
>  		panthor_aw_send_msg(aw, reply);
[ ... ]
> @@ -303,17 +302,15 @@ int panthor_aw_init(struct panthor_device *ptdev)
>  
>  	ret = panthor_request_aw_irq(ptdev, &aw->irq, irq, WINDOW_IRQ_MASK,
>  				     aw->iomem + WINDOW_INT_BASE);
>  	if (ret)
>  		return ret;
>  
>  	ret = panthor_aw_request(aw);
>  	if (ret)
>  		return ret;

[Severity: High]
Does this error path leak the active AW IRQ state? If panthor_aw_request() 
fails, we return without unwinding the active IRQ or pending work queue. 

In panthor_device_init(), if this function returns an error, we jump directly
to err_rpm_put, bypassing panthor_aw_unplug():

drivers/gpu/drm/panthor/panthor_device.c:panthor_device_init() {
    ...
	ret = panthor_aw_init(ptdev);
	if (ret)
		goto err_rpm_put;
    ...
}

Leaving a shared hardware IRQ unmasked while the device may be partially 
initialized or powered off could cause kernel panics, such as bus errors on 
MMIO access in the handler.

>  
>  	return 0;
>  }
>  
>  void panthor_aw_unplug(struct panthor_device *ptdev)
>  {
>  	struct panthor_aw *aw = ptdev->aw;
>  
>  	if (!aw)
>  		return;
>  
>  	disable_work_sync(&aw->msg_retry_work);
>  
>  	panthor_aw_irq_suspend(&aw->irq);

[Severity: Medium]
Will this sequence cause a 5-second stall during device unplug? 

In panthor_device_unplug(), panthor_aw_unplug() is called before
pm_runtime_put_sync_suspend():

drivers/gpu/drm/panthor/panthor_device.c:panthor_device_unplug() {
    ...
	panthor_aw_unplug(ptdev);

	pm_runtime_dont_use_autosuspend(ptdev->base.dev);
	pm_runtime_put_sync_suspend(ptdev->base.dev);
    ...
}

panthor_aw_unplug() disables and masks the AW IRQ. Then, the PM suspend path 
calls panthor_aw_suspend() which uses panthor_aw_state_wait() to wait for an 
interrupt-driven state transition to READY. Since the IRQ is masked before 
the suspend yield happens, the completion interrupt is never handled, 
guaranteeing a full 5-second timeout stall.

>  }
>  
>  int panthor_aw_resume(struct panthor_device *ptdev)
[ ... ]
> @@ -333,16 +332,15 @@ int panthor_aw_suspend(struct panthor_device *ptdev)
>  
>  	if (atomic_read(&aw->state) == PANTHOR_AW_STATE_READY)
>  		goto out_irq_suspend;
>  
>  	if (panthor_aw_state_try_set(aw, PANTHOR_AW_STATE_GPU_GRANTED,
>  		PANTHOR_AW_STATE_GPU_STOPPED))
>  		ret = panthor_aw_yield(aw);
>  	else
>  		ret = panthor_aw_state_wait(
>  			aw, PANTHOR_AW_STATE_READY,
>  			PANTHOR_AW_STATE_TRANSITION_TIMEOUT_MS);
>  
>  out_irq_suspend:
>  	panthor_aw_irq_suspend(&aw->irq);
>  	return ret;

[Severity: High]
Does this exit path omit flushing or canceling the background work? If a
message is sent just before or during device suspend, msg_retry_work could be
queued. 

Unlike in panthor_aw_unplug(), panthor_aw_suspend() does not call 
disable_work_sync(&aw->msg_retry_work) before the device transitions to a 
suspended state. Since aw->wq is not allocated with WQ_FREEZABLE, the work
can run after the device's clocks and power domains are disabled, and
accessing powered-off MMIO registers would cause a bus error (kernel panic).

>  }

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260922204535.2850094-1-karunika.choo@arm.com?part=22

Re: [PATCH v1 27/27] drm/panthor: Release GPU access immediately for out-of-band grants

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] drm/panthor: AW state machine wedges in STOPPED_IDLE on ENOSPC
--

commit fc59dcd4da161e6f76c5425461851d01153db172
Author: Karunika Choo <karunika.choo@arm.com>

    drm/panthor: Release GPU access immediately for out-of-band grants

This commit modifies the window-opened IRQ handler to immediately release
the GPU access when a late grant arrives for a request that has already
timed out and returned to the READY state.

> diff --git a/drivers/gpu/drm/panthor/panthor_aw.c b/drivers/gpu/drm/panthor/panthor_aw.c
> index 7ef13db4acf50..27787c0b2f3a2 100644
> --- a/drivers/gpu/drm/panthor/panthor_aw.c
> +++ b/drivers/gpu/drm/panthor/panthor_aw.c
[ ... ]
> @@ -282,8 +282,13 @@ static void panthor_aw_handle_window_opened(struct panthor_aw *aw)
>  		return;
>  
>  	/* Window opened due to GPU_REQUEST */
> -	panthor_aw_state_try_set(aw, PANTHOR_AW_STATE_GPU_REQUEST,
> -				     PANTHOR_AW_STATE_GPU_GRANTED);
> +	if (panthor_aw_state_try_set(aw, PANTHOR_AW_STATE_GPU_REQUEST,
> +				     PANTHOR_AW_STATE_GPU_GRANTED))
> +		return;
> +
> +	if (panthor_aw_state_try_set(aw, PANTHOR_AW_STATE_READY,
> +				     PANTHOR_AW_STATE_STOPPED_IDLE))
> +		panthor_aw_send_msg(aw, VM_ARB_GPU_STOPPED);

[Severity: High]
If panthor_aw_send_msg() drops the message due to the 4-entry message FIFO
being full (-ENOSPC), does the state machine become permanently wedged in
PANTHOR_AW_STATE_STOPPED_IDLE?

Looking at panthor_aw_send_msg(), if the send FIFO is full, it returns
-ENOSPC and simply logs an error without retrying.

Because this runs in the atomic context of panthor_aw_irq_raw_hander(), it
lacks the wait-and-revert timeout fallback that thread-context callers use.
Since the state was already transitioned to PANTHOR_AW_STATE_STOPPED_IDLE
before the message was sent, dropping the message means the hardware is never
told to stop and the software state never reverts to PANTHOR_AW_STATE_READY.
This could cause all future GPU requests to timeout indefinitely under heavy
GPU load.

>  }
>  
>  static irqreturn_t panthor_aw_irq_raw_hander(int irq, void *data)

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260922204535.2850094-1-karunika.choo@arm.com?part=27

Re: [PATCH v1 24/27] drm/panthor: Route HW component PM through access windows

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 5 potential issue(s) to consider:
- [High] panthor: panthor_device_resume() incorrectly propagates -EAGAIN on AW race
- [High] panthor: post-yield worker accesses hardware with clocks disabled during system suspend
- [High] panthor: hardware fails to re-initialize on system resume if suspended while GPU_STOPPED
- [Medium] panthor: hardware components skip graceful teardown on runtime suspend race
- [Medium] panthor: pm_runtime_put_noidle() in post_yield_work stalls autosuspend indefinitely
--

commit 8aa28a6a344b704e733c2685619e190f808b85d0
Author: Karunika Choo <karunika.choo@arm.com>

drm/panthor: Route HW component PM through access windows

This commit makes access-window resume and suspend own GPU access when AW
support is present, while keeping the direct HW component PM path for older
GPUs. It also handles WINDOW_CLOSED and arbiter restart events and defers
post-yield cleanup to a workqueue context.

> diff --git a/drivers/gpu/drm/panthor/panthor_aw.c b/drivers/gpu/drm/panthor/panthor_aw.c
> index 40122bb4b83af..4fcfb3ad05073 100644
> --- a/drivers/gpu/drm/panthor/panthor_aw.c
> +++ b/drivers/gpu/drm/panthor/panthor_aw.c

[ ... ]

> @@ -118,6 +121,52 @@ static int panthor_aw_state_wait_transition(struct panthor_aw *aw, u32 timeout_m
>  		timeout_ms);
>  }
>  
> +static void panthor_aw_post_yield_work(struct work_struct *work)
> +{
> +	struct panthor_aw *aw =
> +		container_of(work, struct panthor_aw, post_yield_work);
> +	struct panthor_device *ptdev = aw->ptdev;
> +	struct device *dev = ptdev->base.dev;
> +	int ret;
> +
> +	/* Something else has progressed the state to READY. */
> +	if (atomic_read(&aw->state) != PANTHOR_AW_STATE_GPU_STOPPED)
> +		return;
> +
> +	/*
> +	 * Ensure in-progress resume is completed and prevent future RPM suspend
> +	 * to keep the clocks turned on when accessing HW registers.
> +	 */
> +	pm_runtime_get_noresume(dev);
> +	pm_runtime_barrier(dev);
> +
> +	ret = panthor_device_suspend_hw_components(ptdev);

[Severity: Medium]
If a WINDOW_CLOSED event queues panthor_aw_post_yield_work() and races with a
runtime suspend, could this skip the graceful hardware teardown?

Since panthor_aw_suspend() skips panthor_device_suspend_hw_components() when
the state is PANTHOR_AW_STATE_GPU_STOPPED, the clocks would be disabled and
the device becomes RPM_SUSPENDED. When this worker executes,
pm_runtime_get_noresume() does not wake the device. Will
panthor_device_suspend_hw_components() then see pm_runtime_suspended() as
true and skip the teardown entirely, leaving caches and firmware improperly
halted?

[Severity: High]
Could this worker also access hardware registers with clocks disabled during a
system suspend?

If a system suspend races with this worker, panthor_device_suspend() could call
panthor_aw_suspend(), which skips the teardown due to the GPU_STOPPED state.
Clocks are then disabled, but since system PM leaves the runtime status as
RPM_ACTIVE, panthor_device_suspend_hw_components() might proceed to access
hardware registers without clocks, potentially causing a bus fault.

> +	if (ret)
> +		dev_warn(dev, "Failed to suspend hardware components.");
> +
> +	panthor_aw_state_set(aw, PANTHOR_AW_STATE_READY);
> +
> +	/*
> +	 * schedule an immediate tick to re-evaluate if there is any additional
> +	 * work. This will request access to the GPU again and if the driver has
> +	 * gone idle, it will yield GPU access via the runtime suspend path.
> +	 */
> +	panthor_sched_resume(ptdev);
> +
> +	pm_runtime_put_noidle(dev);

[Severity: Medium]
Does pm_runtime_put_noidle() drop the PM reference without re-arming the
autosuspend timer?

If the autosuspend timer fires while the temporary reference is held in this
function, the suspend aborts due to a non-zero usage count. Using
pm_runtime_put_noidle() drops the usage count but does not queue an idle
notification. Could this leave the device actively powered on indefinitely
until another explicit PM transition occurs?

> +}

[ ... ]

> @@ -396,20 +531,45 @@ int panthor_aw_suspend(struct panthor_device *ptdev)
>  
>  	/* suspend hw components directly if AW is not supported */
>  	if (!aw)
> -		return 0;
> +		return panthor_device_suspend_hw_components(ptdev);
>  
>  	if (atomic_read(&aw->state) == PANTHOR_AW_STATE_READY)
>  		goto out_irq_suspend;
>  
> +	if (atomic_read(&aw->state) == PANTHOR_AW_STATE_GPU_GRANTED) {
> +		ret = panthor_device_suspend_hw_components(ptdev);
> +		if (ret)
> +			goto out_irq_suspend;
> +	}
> +
>  	if (panthor_aw_state_try_set(aw, PANTHOR_AW_STATE_GPU_GRANTED,
> -		PANTHOR_AW_STATE_GPU_STOPPED))
> +		PANTHOR_AW_STATE_STOPPED_IDLE)) {

[Severity: High]
If a system suspend occurs while aw->state is PANTHOR_AW_STATE_GPU_STOPPED,
could this fail to re-initialize the hardware on resume?

Since this skips panthor_device_suspend_hw_components(), the
ptdev->pm.hw_component_state remains PANTHOR_DEVICE_PM_STATE_ACTIVE.
During system resume, panthor_device_resume_hw_components() will check if the
state is ACTIVE and immediately return 0. Does this leave the firmware, MMU,
and GPU uninitialized after losing power in S3?

>  		ret = panthor_aw_yield(aw);

[ ... ]

> diff --git a/drivers/gpu/drm/panthor/panthor_device.c b/drivers/gpu/drm/panthor/panthor_device.c
> index 2ccd8ad6318d1..ea35c5e1d87b4 100644
> --- a/drivers/gpu/drm/panthor/panthor_device.c
> +++ b/drivers/gpu/drm/panthor/panthor_device.c

[ ... ]

> @@ -577,11 +577,11 @@ int panthor_device_resume(struct device *dev)
>  			atomic_set(&ptdev->reset.pending, 0);
>  		}
>  
> -		ret = panthor_device_resume_hw_components(ptdev);
> +		ret = panthor_aw_resume(ptdev);
>  		if (ret && ptdev->reset.fast) {
>  			drm_err(&ptdev->base, "Fast reset failed, trying a slow reset");
>  			ptdev->reset.fast = false;
> -			ret = panthor_device_resume_hw_components(ptdev);
> +			ret = panthor_aw_resume(ptdev);
>  		}

[Severity: High]
Does panthor_device_resume() incorrectly propagate -EAGAIN on an AW race?

If a WINDOW_CLOSED event races with a runtime PM resume, panthor_aw_resume()
observes PANTHOR_AW_STATE_GPU_STOPPED and returns -EAGAIN. Propagating this
directly to the PM core here causes the runtime resume to fail entirely.

[ ... ]

> diff --git a/drivers/gpu/drm/panthor/panthor_device.h b/drivers/gpu/drm/panthor/panthor_device.h
> index 42c5052ac83b9..59bc48d05eb1e 100644
> --- a/drivers/gpu/drm/panthor/panthor_device.h
> +++ b/drivers/gpu/drm/panthor/panthor_device.h

[ ... ]

> @@ -466,8 +467,18 @@ static inline int panthor_device_resume_and_get(struct panthor_device *ptdev)
>  	 * succeeded. Given resume errors are not expected, this is probably
>  	 * something we can live with.
>  	 */
> -	if (ret && atomic_cmpxchg(&ptdev->pm.recovery_needed, 1, 0) == 1)
> -		pm_runtime_set_suspended(ptdev->base.dev);
> +	if (ret) {
> +		if (atomic_cmpxchg(&ptdev->pm.recovery_needed, 1, 0) == 1)
> +			pm_runtime_set_suspended(ptdev->base.dev);
> +
> +		return ret;
> +	}
> +
> +	ret = panthor_aw_ensure_gpu_access(ptdev);

[Severity: High]
Does this early bailout bypass the intended retry logic?

Because panthor_device_resume() propagates the -EAGAIN failure directly,
the initial pm_runtime_resume_and_get() call fails and populates ret. Returning
ret here completely bypasses the panthor_aw_ensure_gpu_access() retry loop that
was specifically designed to handle the -EAGAIN state.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260922204535.2850094-1-karunika.choo@arm.com?part=24

Re: [PATCH v1 21/27] drm/panthor: Request AW to yield GPU access on idle

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] gpu: back-to-back command writes and untracked YIELD_IDLE cause spurious resets
--

commit fadb8e77c6f0f320ae209ccd68ac1719dfdd7041
Author: Karunika Choo <karunika.choo@arm.com>

drm/panthor: Request AW to yield GPU access on idle
    
v15 GPU introduces a YIELD_IDLE command/interrupt to signal an access
window to relinquish GPU access as soon as it is idle. With FW v2, the
GPU is immediately yielded when it detects the GPU is idle and the
YIELD_IDLE interrupt is raised.

For latency and CPU scheduling reasons, we want to avoid constantly
yielding the GPU the moment it goes idle when there is only a singular
access window requesting access. As such, we only send YIELD_IDLE when:

- The GPU is granted to an access window and there are other access
  windows requesting GPU access.
- A new GPU_REQUEST was received and the currently active access window
  was the singular requesting AW.

[ ... ]

> diff --git a/drivers/gpu/drm/panthor/arbitration/panthor_arbitration_sched.c b/drivers/gpu/drm/panthor/arbitration/panthor_arbitration_sched.c
> index df0785a80442c..df58fcc56e375 100644
> --- a/drivers/gpu/drm/panthor/arbitration/panthor_arbitration_sched.c
> +++ b/drivers/gpu/drm/panthor/arbitration/panthor_arbitration_sched.c
> @@ -347,6 +347,10 @@ static int arb_sched_next_locked(struct panthor_arbitration_sched *sched)
>  
>  	arb_sched_grant_locked(sched);
>  
> +	if (sched->phase == ARB_SCHED_PHASE_GRANTED &&
> +	    !kfifo_is_empty(&sched->queue))
> +		panthor_arbitration_notify_yield_idle(to_adev(sched), aw_id);

[Severity: High]
Does this sequence cause back-to-back command writes that can trigger spurious
resets?

When multiple AWs are queued, arb_sched_next_locked() grants the GPU to one
AW, which writes the PART_CMD_OPEN_WINDOW command to the hardware register via
arb_sched_grant_locked(), and then immediately issues PART_CMD_YIELD_IDLE here
without waiting for the hardware to process the window state.

The immediate write to the same register can physically overwrite the
PART_CMD_OPEN_WINDOW command before the hardware processes it. If the hardware
instead rejects PART_CMD_YIELD_IDLE (for example, because it's still in the
PART_STATE_WINDOW_OPENING state), it raises PART_INVALID_COMMAND.

Because panthor_arbitration_notify_yield_idle() eventually calls yield_idle(),
which uses an untracked command write:

drivers/gpu/drm/panthor/arbitration/panthor_partition_control.c:yield_idle() {
	...
	partition_command_write_untracked(
		pc, AM_PART_SET_COMMAND(PART_CMD_YIELD_IDLE));
	...
}

The pc->last_cmd remains set to the previously tracked command
(PART_CMD_OPEN_WINDOW). The IRQ handler partition_handle_invalid_cmd() then
mistakenly believes the PART_CMD_OPEN_WINDOW command failed, sees the state is
not PART_STATE_RESET or fully open, and resets the scheduler.

Can we wait for the hardware to process PART_CMD_OPEN_WINDOW or for the window
state to settle before sending PART_CMD_YIELD_IDLE?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260922204535.2850094-1-karunika.choo@arm.com?part=21

Re: [PATCH v1 26/27] drm/panthor: Prevent missed post-yield cleanup due to reset

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider:
- [High] drm: scheduler deadlock on reset due to missed post-reset hooks
- [High] drm: failed reset bypasses device unplug due to AW state transition
- [High] drm: TOCTOU race in reset causes invalid MMIO access
--

commit c5cc732c23a490baff27bd3657a378e7ad65a4e4
Author: Karunika Choo <karunika.choo@arm.com>

drm/panthor: Prevent missed post-yield cleanup due to reset

With v15 GPUs, FW can yield GPU access at any point. This commit introduces
pre_reset and post_reset helpers for panthor_aw which marks a granted AW as
reset-active, aiming to prevent a race condition between reset and FW yield
from suppressing post-yield cleanup.

> diff --git a/drivers/gpu/drm/panthor/panthor_aw.c b/drivers/gpu/drm/panthor/panthor_aw.c
> index 9ebb23eadfec5..7ef13db4acf50 100644
> --- a/drivers/gpu/drm/panthor/panthor_aw.c
> +++ b/drivers/gpu/drm/panthor/panthor_aw.c
[ ... ]
> @@ -579,5 +588,36 @@ bool panthor_aw_has_gpu_access(struct panthor_device *ptdev)
[ ... ]
> +void panthor_aw_pre_reset(struct panthor_device *ptdev)
> +{
> +	struct panthor_aw *aw = ptdev->aw;
> +
> +	if (!aw)
> +		return;
> +
> +	panthor_aw_state_try_set(ptdev->aw, PANTHOR_AW_STATE_GPU_GRANTED,
> +				 PANTHOR_AW_STATE_RESET_ACTIVE);
> +}
> +
> +void panthor_aw_post_reset(struct panthor_device *ptdev)
> +{
> +	struct panthor_aw *aw = ptdev->aw;
> +
> +	if (!aw)
> +		return;
> +
> +	panthor_aw_state_try_set(aw, PANTHOR_AW_STATE_RESET_ACTIVE,
> +				 PANTHOR_AW_STATE_GPU_GRANTED);
> +
> +	if (!panthor_aw_is_open(aw))
> +		panthor_aw_schedule_post_yield_work(aw);
>  }
> diff --git a/drivers/gpu/drm/panthor/panthor_device.c b/drivers/gpu/drm/panthor/panthor_device.c
> index ea35c5e1d87b4..86eb4e9a61789 100644
> --- a/drivers/gpu/drm/panthor/panthor_device.c
> +++ b/drivers/gpu/drm/panthor/panthor_device.c
> @@ -138,18 +138,27 @@ static void panthor_device_reset_work(struct work_struct *work)
>  	if (!drm_dev_enter(&ptdev->base, &cookie))
>  		return;
>  
> +	if (!panthor_aw_has_gpu_access(ptdev))
> +		goto out_clear_pending;

[Severity: High]
If a GPU reset is scheduled (e.g., due to a job timeout), and just before
panthor_device_reset_work() runs, the firmware yields the GPU, this check
returns false and causes a jump to out_clear_pending.

Since out_clear_pending clears the reset.pending flag but skips calling
panthor_sched_post_reset(), does this leave the scheduler's tick work and
firmware watchdog permanently deadlocked, causing all jobs to hang forever
without recovery?

Additionally, does this introduce a Time-Of-Check to Time-Of-Use (TOCTOU)
race condition?

If an IRQ fires after panthor_aw_has_gpu_access(ptdev) is checked but before
panthor_aw_pre_reset(ptdev) is called, changing the state to STOPPED_IDLE,
panthor_aw_pre_reset() will silently fail to update the state since it
ignores the return value of panthor_aw_state_try_set().

Will this allow the reset sequence to continue against unpowered MMIO,
leading to bus faults because GPU access has been revoked?

> +
>  	panthor_sched_pre_reset(ptdev);
> +	panthor_aw_pre_reset(ptdev);
>  	panthor_fw_pre_reset(ptdev, true);
>  	panthor_mmu_pre_reset(ptdev);
> +
>  	panthor_hw_soft_reset(ptdev);
> +
>  	panthor_hw_l2_power_on(ptdev);
>  	panthor_mmu_post_reset(ptdev);
>  	ret = panthor_fw_post_reset(ptdev);
> -	atomic_set(&ptdev->reset.pending, 0);
> +	panthor_aw_post_reset(ptdev);
>  	panthor_sched_post_reset(ptdev, ret != 0);
> +
> +out_clear_pending:
> +	atomic_set(&ptdev->reset.pending, 0);
>  	drm_dev_exit(cookie);
>  
> -	if (ret) {
> +	if (ret && panthor_aw_has_gpu_access(ptdev)) {

[Severity: High]
If the MCU fails to boot during reset, panthor_fw_post_reset() will return an
error. Then panthor_aw_post_reset() executes and, seeing the window is not
open, calls panthor_aw_schedule_post_yield_work() which transitions the AW
state to PANTHOR_AW_STATE_GPU_STOPPED.

Since the state is now GPU_STOPPED, panthor_aw_has_gpu_access() will evaluate
to false. Will this completely bypass the device unplug operation, leaving a
broken device registered and accessible?

>  		panthor_device_unplug(ptdev);
>  		drm_err(&ptdev->base, "Failed to boot MCU after reset, making device unusable.");
>  	}

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260922204535.2850094-1-karunika.choo@arm.com?part=26

Re: [PATCH v1 25/27] drm/panthor: Tolerate access-window loss during HW waits

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider:
- [High] panthor: false success returned when hardware waits are interrupted by AW loss
- [High] panthor: firmware events dropped or IRQ livelock on AW loss
- [High] panthor: threads block for full timeout duration on AW loss due to missing wakeups
--

commit 4e7abd3f16aae357d6bd8c91a0c0d4c8218b1fcc
Author: Karunika Choo <karunika.choo@arm.com>

drm/panthor: Tolerate access-window loss during HW waits

The patch handles access window (AW) loss during hardware waits to prevent
false hardware timeouts or recoveries. It uses panthor_aw_has_gpu_access
to suppress timeout handling once access is revoked.

> diff --git a/drivers/gpu/drm/panthor/panthor_fw.c b/drivers/gpu/drm/panthor/panthor_fw.c
> index 1449d9a66302e..b4c234f3d3ea4 100644
> --- a/drivers/gpu/drm/panthor/panthor_fw.c
> +++ b/drivers/gpu/drm/panthor/panthor_fw.c
> @@ -1140,9 +1140,10 @@ static int panthor_fw_start(struct panthor_device *ptdev)
>  	gpu_write(fw->iomem, MCU_CONTROL, MCU_CONTROL_AUTO);
>  
>  	if (!wait_event_timeout(ptdev->fw->req_waitqueue,
> -				ptdev->fw->booted,
> +				(ptdev->fw->booted ||
> +				 !panthor_aw_has_gpu_access(ptdev)),
>  				msecs_to_jiffies(1000))) {
> -		if (!ptdev->fw->booted &&
> +		if (!ptdev->fw->booted && panthor_aw_has_gpu_access(ptdev) &&
>  		    !(gpu_read(fw->irq.iomem, INT_STAT) & JOB_INT_GLOBAL_IF))
>  			timedout = true;
>  	}

[Severity: High]
Does this code silently fail to boot but return success? If the AW is lost
during the wait, panthor_aw_has_gpu_access() returns false, preventing
timedout from being set to true. As a result, panthor_fw_start() returns
success even though the firmware is not actually booted.

Additionally, because there is no wakeup mechanism triggered upon AW loss,
will this thread stall in wait_event_timeout() for the full 1000ms duration
when AW access is revoked?

[ ... ]

> diff --git a/drivers/gpu/drm/panthor/panthor_gpu.c b/drivers/gpu/drm/panthor/panthor_gpu.c
> index e6e970e9b59d3..25fe7c77f8763 100644
> --- a/drivers/gpu/drm/panthor/panthor_gpu.c
> +++ b/drivers/gpu/drm/panthor/panthor_gpu.c
> @@ -376,7 +377,8 @@ int panthor_gpu_flush_caches(struct panthor_device *ptdev,
>  				msecs_to_jiffies(100))) {
>  		scoped_guard(spinlock, &ptdev->gpu->reqs_lock) {
>  			if ((ptdev->gpu->pending_reqs & GPU_IRQ_CLEAN_CACHES_COMPLETED) != 0 &&
> -			    !(gpu_read(gpu->irq.iomem, INT_RAWSTAT) & GPU_IRQ_CLEAN_CACHES_COMPLETED))
> +			    !(gpu_read(gpu->irq.iomem, INT_RAWSTAT) &
> +			      GPU_IRQ_CLEAN_CACHES_COMPLETED) && panthor_aw_has_gpu_access(ptdev))
>  				ret = -ETIMEDOUT;
>  			else
>  				ptdev->gpu->pending_reqs &= ~GPU_IRQ_CLEAN_CACHES_COMPLETED;

[Severity: High]
Can this deceive callers into assuming caches were successfully flushed?
If AW is lost, the timeout error is suppressed and the pending request flag
is cleared, causing panthor_gpu_flush_caches() to return 0. This could cause
divergence if callers proceed assuming the flush completed in the hardware.

Also, wait_event_timeout() lacks an AW check in the condition and has no
associated wakeup on AW loss, which will cause a 100ms stall.

[ ... ]

> diff --git a/drivers/gpu/drm/panthor/panthor_pwr.c b/drivers/gpu/drm/panthor/panthor_pwr.c
> index cc2e01595f23b..2a0feb0b39ece 100644
> --- a/drivers/gpu/drm/panthor/panthor_pwr.c
> +++ b/drivers/gpu/drm/panthor/panthor_pwr.c
> @@ -122,7 +123,8 @@ static int panthor_pwr_reset(struct panthor_device *ptdev, u32 reset_cmd)
>  				msecs_to_jiffies(PWR_RESET_TIMEOUT_MS))) {
>  		guard(spinlock_irqsave)(&ptdev->pwr->reqs_lock);
>  
> -		if (reset_pending(ptdev) && !reset_irq_raised(ptdev)) {
> +		if (reset_pending(ptdev) && !reset_irq_raised(ptdev) &&
> +		    panthor_aw_has_gpu_access(ptdev)) {
>  			drm_err(&ptdev->base, "RESET timed out (0x%x)", reset_cmd);
>  			return -ETIMEDOUT;
>  		}

[Severity: High]
Is the thread blocked for the full PWR_RESET_TIMEOUT_MS when AW is lost?
The wait_event_timeout() lacks an AW check in its condition, and without a
corresponding wakeup mechanism for AW loss, it appears this will stall
the thread unnecessarily in panthor_pwr_reset().

[ ... ]

> @@ -266,9 +268,14 @@ static int panthor_pwr_domain_transition(struct panthor_device *ptdev, u32 cmd,
>  
>  	panthor_pwr_write_command(ptdev, pwr_cmd, mask);
>  
> -	ret = gpu_read64_poll_timeout(pwr->iomem, ready_reg, val, (mask & val) == expected_val,
> +	ret = gpu_read64_poll_timeout(pwr->iomem, ready_reg, val,
> +				      ((mask & val) == expected_val ||
> +				       !panthor_aw_has_gpu_access(ptdev)),
>  				      100, timeout_us);
>  	if (ret) {
> +		if (!panthor_aw_has_gpu_access(ptdev))
> +			return 0;
> +

[Severity: High]
Does returning success here break the power domain transition sequence?
If the AW arbiter revokes access before the transition finishes, this will
return 0 even though the hardware power domain transition failed to complete.

[ ... ]

> diff --git a/drivers/gpu/drm/panthor/panthor_sched.c b/drivers/gpu/drm/panthor/panthor_sched.c
> index 60b2417deb81b..e13553ec97ec9 100644
> --- a/drivers/gpu/drm/panthor/panthor_sched.c
> +++ b/drivers/gpu/drm/panthor/panthor_sched.c
> @@ -1886,6 +1886,9 @@ void panthor_sched_report_fw_events(struct panthor_device *ptdev, u32 events)
>  
>  	guard(spinlock)(&ptdev->scheduler->events_lock);
>  
> +	if (!panthor_aw_has_gpu_access(ptdev))
> +		return;
> +

[Severity: High]
Could this early return cause an IRQ livelock or dropped firmware events?

If a hardware interrupt occurs and panthor_job_irq_handler() successfully
clears the interrupt from the hardware, but then AW access is lost, this
returns early. The cleared events would be permanently dropped.

If AW access is lost before the hardware is cleared in the IRQ handler,
the interrupt remains asserted but this function ignores it, which may cause
the threaded IRQ handler to enter an infinite loop.

[ ... ]

> @@ -2059,6 +2062,8 @@ static int csgs_upd_ctx_apply_locked(struct panthor_device *ptdev,
>  		csg_iface = panthor_fw_get_csg_iface(ptdev, csg_id);
>  
>  		ret = panthor_fw_csg_wait_acks(ptdev, csg_id, req_mask, &acked, 100);
> +		if (ret && !panthor_aw_has_gpu_access(ptdev))
> +			ret = 0;
>  

[Severity: High]
Does this override the timeout error with success, causing the scheduler to
erroneously assume the firmware processed the CSG state change?

Also, panthor_fw_csg_wait_acks() relies on panthor_fw_wait_acks() which uses
wait_event_timeout(). Since this is called in a loop while holding the
scheduler lock, will the lack of AW wakeups cause compounded delays
(N * 100ms) that block the entire scheduler?

[ ... ]

Regarding panthor_job_irq_handler() in drivers/gpu/drm/panthor/panthor_fw.c:

static void panthor_job_irq_handler(struct panthor_irq *pirq, u32 status)
{
    ...
	if (!ptdev->fw->booted && (status & JOB_INT_GLOBAL_IF))
		ptdev->fw->booted = true;
    ...
}

[Severity: Medium]
This is a pre-existing issue, but does this logic spuriously set the firmware
state to booted on an AW loss? When AW access is lost, the MMIO read for the
interrupt status will return 0xFFFFFFFF, which has JOB_INT_GLOBAL_IF set.
This would incorrectly flag the firmware as booted during early execution.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260922204535.2850094-1-karunika.choo@arm.com?part=25

Re: [PATCH v1 04/27] drm/panthor: Add 64-bit GPU_ID decoding for v15 GPUs

[Deborah Brouwer]

On Tue, Sep 22, 2026 at 09:44:58PM +0100, Karunika Choo wrote:
> Mali v15 exposes a 64-bit GPU_ID register with a different field layout
> from earlier GPUs.
> 
> Add the register definitions and decoding helpers for the new format,
> read GPU_WIDE_ID when the compatibility value indicates a v15 GPU, and
> populate both the cached GPU_ID fields and the uAPI gpu_wide_id field.
> 
> This allows userspace and the driver to identify v15 GPUs correctly.
> 
> Signed-off-by: Karunika Choo <karunika.choo@arm.com>
> ---
> v1:
> - Decode selected GPU_ID format after checking compatibility value.
> - Document GPU_DISCOVER and GPU_CONTROL register offset differences
>   between GPUs.
> - Fix mask generation in panthor_gpu_discover_regs.h
> 
>  .../drm/panthor/panthor_gpu_discover_regs.h   | 19 +++++++++
>  drivers/gpu/drm/panthor/panthor_hw.c          | 42 +++++++++++++++----
>  include/uapi/drm/panthor_drm.h                | 13 ++++++
>  3 files changed, 65 insertions(+), 9 deletions(-)
>  create mode 100644 drivers/gpu/drm/panthor/panthor_gpu_discover_regs.h
> 
> diff --git a/drivers/gpu/drm/panthor/panthor_gpu_discover_regs.h b/drivers/gpu/drm/panthor/panthor_gpu_discover_regs.h
> new file mode 100644
> index 0000000000000..e6bfe1fe2c68a
> --- /dev/null
> +++ b/drivers/gpu/drm/panthor/panthor_gpu_discover_regs.h
> @@ -0,0 +1,19 @@
> +/* SPDX-License-Identifier: GPL-2.0 or MIT */
> +/* Copyright 2026 ARM Limited. All rights reserved. */
> +
> +#ifndef __PANTHOR_GPU_DISCOVER_REGS_H__
> +#define __PANTHOR_GPU_DISCOVER_REGS_H__
> +
> +#include <linux/bits.h>
> +
> +#define GPU_WIDE_ID					0x0
> +#define   GPU_WIDE_COMPAT				0xF
> +#define   GPU_WIDE_ARCH_MAJOR(x)			(((x) & GENMASK_U64(63, 56)) >> 56)
> +#define   GPU_WIDE_ARCH_MINOR(x)			(((x) & GENMASK_U64(55, 48)) >> 48)
> +#define   GPU_WIDE_ARCH_REV(x)				(((x) & GENMASK_U64(47, 40)) >> 40)
> +#define   GPU_WIDE_PROD_MAJOR(x)			(((x) & GENMASK_U64(39, 32)) >> 32)
> +#define   GPU_WIDE_VER_MAJOR(x)				(((x) & GENMASK_U64(23, 16)) >> 16)
> +#define   GPU_WIDE_VER_MINOR(x)				(((x) & GENMASK_U64(15, 8)) >> 8)
> +#define   GPU_WIDE_VER_STATUS(x)			((x) & GENMASK_U64(7, 0))
> +
> +#endif /* __PANTHOR_GPU_DISCOVER_REGS_H__ */
> diff --git a/drivers/gpu/drm/panthor/panthor_hw.c b/drivers/gpu/drm/panthor/panthor_hw.c
> index 2143e57d48106..40012ba7e23ca 100644
> --- a/drivers/gpu/drm/panthor/panthor_hw.c
> +++ b/drivers/gpu/drm/panthor/panthor_hw.c
> @@ -8,6 +8,7 @@
>  
>  #include "panthor_device.h"
>  #include "panthor_gpu.h"
> +#include "panthor_gpu_discover_regs.h"
>  #include "panthor_gpu_regs.h"
>  #include "panthor_hw.h"
>  #include "panthor_pwr.h"
> @@ -296,18 +297,41 @@ static int panthor_hw_bind_device(struct panthor_device *ptdev)
>  static int panthor_hw_gpu_id_init(struct panthor_device *ptdev)
>  {
>  	struct panthor_gpu_id *gpu_id = &ptdev->gpu_id;
> -	ptdev->gpu_info.gpu_id = gpu_read(ptdev->iomem, GPU_ID);
> +	u32 gpu_id32 = gpu_read(ptdev->iomem, GPU_ID);
>  
> -	if (!ptdev->gpu_info.gpu_id)
> +	if (!gpu_id32)
>  		return -ENXIO;
>  
> -	gpu_id->arch_major = GPU_ARCH_MAJOR(ptdev->gpu_info.gpu_id);
> -	gpu_id->arch_minor = GPU_ARCH_MINOR(ptdev->gpu_info.gpu_id);
> -	gpu_id->arch_rev = GPU_ARCH_REV(ptdev->gpu_info.gpu_id);
> -	gpu_id->prod_major = GPU_PROD_MAJOR(ptdev->gpu_info.gpu_id);
> -	gpu_id->ver_major = GPU_VER_MAJOR(ptdev->gpu_info.gpu_id);
> -	gpu_id->ver_minor = GPU_VER_MINOR(ptdev->gpu_info.gpu_id);
> -	gpu_id->ver_status = GPU_VER_STATUS(ptdev->gpu_info.gpu_id);
> +	if (GPU_ARCH_MAJOR(gpu_id32) == GPU_WIDE_COMPAT) {
> +		/*
> +		 * GPU_DISCOVER register block always starts at offset zero,
> +		 * so does the GPU_CONTROL register block on pre-v15 GPUs.
> +		 */
> +		void __iomem *discover = ptdev->iomem;
> +		u64 gpu_id64 = gpu_read64(discover, GPU_WIDE_ID);
> +		if (!gpu_id64)
> +			return -ENXIO;
> +
> +		ptdev->gpu_info.gpu_wide_id = gpu_id64;
> +
> +		gpu_id->arch_major = GPU_WIDE_ARCH_MAJOR(gpu_id64);
> +		gpu_id->arch_minor = GPU_WIDE_ARCH_MINOR(gpu_id64);
> +		gpu_id->arch_rev = GPU_WIDE_ARCH_REV(gpu_id64);
> +		gpu_id->prod_major = GPU_WIDE_PROD_MAJOR(gpu_id64);
> +		gpu_id->ver_major = GPU_WIDE_VER_MAJOR(gpu_id64);
> +		gpu_id->ver_minor = GPU_WIDE_VER_MINOR(gpu_id64);
> +		gpu_id->ver_status = GPU_WIDE_VER_STATUS(gpu_id64);
> +	} else {
> +		ptdev->gpu_info.gpu_id = gpu_id32;
> +
> +		gpu_id->arch_major = GPU_ARCH_MAJOR(gpu_id32);
> +		gpu_id->arch_minor = GPU_ARCH_MINOR(gpu_id32);
> +		gpu_id->arch_rev = GPU_ARCH_REV(gpu_id32);
> +		gpu_id->prod_major = GPU_PROD_MAJOR(gpu_id32);
> +		gpu_id->ver_major = GPU_VER_MAJOR(gpu_id32);
> +		gpu_id->ver_minor = GPU_VER_MINOR(gpu_id32);
> +		gpu_id->ver_status = GPU_VER_STATUS(gpu_id32);
> +	}
>  
>  	return 0;
>  }
> diff --git a/include/uapi/drm/panthor_drm.h b/include/uapi/drm/panthor_drm.h
> index a2ff0f4ec6915..843a0b40e1d36 100644
> --- a/include/uapi/drm/panthor_drm.h
> +++ b/include/uapi/drm/panthor_drm.h
> @@ -376,6 +376,19 @@ struct drm_panthor_gpu_info {
>  
>  	/** @gpu_features: Bitmask describing supported GPU-wide features */
>  	__u64 gpu_features;
> +
> +	/**
> +	 * @gpu_wide_id: 64-bit GPU ID for v15 and later GPUs. @gpu_id is 0 when
> +	 * this is populated.
> +	 */
> +	__u64 gpu_wide_id;
> +#define DRM_PANTHOR_WIDE_ARCH_MAJOR(x)		(((x) >> 56) & 0xff)
> +#define DRM_PANTHOR_WIDE_ARCH_MINOR(x)		(((x) >> 48) & 0xff)
> +#define DRM_PANTHOR_WIDE_ARCH_REV(x)		(((x) >> 40) & 0xff)
> +#define DRM_PANTHOR_WIDE_PRODUCT_MAJOR(x)	(((x) >> 32) & 0xff)
> +#define DRM_PANTHOR_WIDE_VERSION_MAJOR(x)	(((x) >> 16) & 0xff)
> +#define DRM_PANTHOR_WIDE_VERSION_MINOR(x)	(((x) >> 8) & 0xff)
> +#define DRM_PANTHOR_WIDE_VERSION_STATUS(x)	((x) & 0xff)
>  };

This patch is meant to pre-emptively prevent a compile failure for tyr
that sashiko-bot pointed out will happen from this patch (or anything
similar :))

https://lore.kernel.org/rust-for-linux/20260922-b4-gpu_info_zero-v1-1-7259840069c6@collabora.com/T/#u


>  
>  /**
> -- 
> 2.43.0
> 

Re: [PATCH v1 07/27] dt-bindings: gpu: mali-valhall-csf: Add Mali Gen5 AM compatible

[Krzysztof Kozlowski]

On Tue, Sep 22, 2026 at 09:45:01PM +0100, Karunika Choo wrote:
> Add the generic "arm,mali-gen5-am" compatible for Mali Gen5 AM GPU
> integrations.
> 
> Mali Gen5 AM systems use the external AM_GOVERNOR block for frequency
> scaling, so OPP, cooling and local GPU supply properties are not valid
> for this compatible.
> 
> Add a matching example node.
> 
> Signed-off-by: Karunika Choo <karunika.choo@arm.com>
> ---
>  .../bindings/gpu/arm,mali-valhall-csf.yaml    | 26 ++++++++++++++++++-
>  1 file changed, 25 insertions(+), 1 deletion(-)
> 
> diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml
> index 8eccd4338a2b2..a1e85570b4b3b 100644
> --- a/Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml
> +++ b/Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml
> @@ -22,6 +22,7 @@ properties:
>                - nxp,imx95-mali            # G310
>                - rockchip,rk3588-mali
>            - const: arm,mali-valhall-csf   # Mali Valhall GPU model/revision is fully discoverable
> +      - const: arm,mali-gen5-am

Why no SoC specific compatibles? Which platform uses this alone (without
SoC integration)?

>  
>    reg:
>      maxItems: 1
> @@ -146,6 +147,19 @@ allOf:
>          - nvmem-cells
>          - nvmem-cell-names
>          - power-domains
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            const: arm,mali-gen5-am
> +    then:
> +      properties:
> +        mali-supply: false
> +        sram-supply: false
> +        operating-points-v2: false
> +        opp-table: false
> +        "#cooling-cells": false
> +        dynamic-power-coefficient: false

That's way too much, you need a new binding file.

Best regards,
Krzysztof

Re: [PATCH v1 10/27] dt-bindings: gpu: panthor: Document panthor-system bindings

[Krzysztof Kozlowski]

On Tue, Sep 22, 2026 at 09:45:04PM +0100, Karunika Choo wrote:
> Mali 5th-Gen AM GPUs expose an AM_SYSTEM block for GPU-wide control
> outside the main GPU register window.

A nit, subject: drop second/last, redundant "bindings". The
"dt-bindings" prefix is already stating that these are bindings.
See also:
https://elixir.bootlin.com/linux/v7.1-rc7/source/Documentation/devicetree/bindings/submitting-patches.rst#L23

> 
> Document the system node compatible, register and interrupt resources,
> GPU clock, and optional GPU regulator supply used by the AM_SYSTEM
> platform driver.
> 
> Signed-off-by: Karunika Choo <karunika.choo@arm.com>
> ---
>  .../bindings/gpu/arm,mali-gen5-am-system.yaml | 67 +++++++++++++++++++
>  MAINTAINERS                                   |  1 +
>  2 files changed, 68 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/gpu/arm,mali-gen5-am-system.yaml
> 
> diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-gen5-am-system.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-gen5-am-system.yaml
> new file mode 100644
> index 0000000000000..f0689bb8f05a2
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/gpu/arm,mali-gen5-am-system.yaml
> @@ -0,0 +1,67 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +# Copyright 2026 ARM Limited. All rights reserved.
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/gpu/arm,mali-gen5-am-system.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: ARM Mali 5th-Gen GPU System Device
> +
> +maintainers:
> +  - Liviu Dudau <liviu.dudau@arm.com>
> +  - Boris Brezillon <boris.brezillon@collabora.com>
> +
> +properties:
> +  $nodename:
> +    pattern: '^panthor-system@[a-f0-9]+$'

Nope. Why would we name devices based on driver?

Node names should be generic. See also an explanation and list of
examples (not exhaustive) in DT specification:
https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation
If you cannot find a name matching your device, please check in kernel
sources for similar cases or you can grow the spec (via pull request to
DT spec repo).

Drop the nodename completely.

> +
> +  compatible:
> +    oneOf:

Drop

> +      - items:

Probably drop... but:

> +          - const: arm,mali-gen5-am-system

How can this be used alone?


> +
> +  reg:
> +    items:
> +      - description: System register

so just maxItems: 1

> +
> +  reg-names:
> +    items:
> +      - const: system

Drop entire reg-names

> +
> +  interrupts:
> +    items:
> +      - description: System interrupt

keep it simple, maxItems: 1

> +
> +  clocks:
> +    maxItems: 1
> +    description:
> +      Phandle to the GPU clock.

Drop description, obvious. Can this be something else than phandle? Can
a single clock for GPU can be something else than GPU clock?

> +
> +  gpu-supply: true

This should rather be named based on the pins/domains. Are you sure the
domain is called GPU?

> +
> +  dma-coherent: true
> +
> +required:
> +  - compatible
> +  - reg
> +  - reg-names
> +  - interrupts
> +  - clocks
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/interrupt-controller/irq.h>
> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +    panthor_system: panthor-system@68000000 {

Drop unused label

Best regards,
Krzysztof

Re: [PATCH v1 12/27] dt-bindings: gpu: panthor: Document panthor-arbitration bindings

[Krzysztof Kozlowski]

On Tue, Sep 22, 2026 at 09:45:06PM +0100, Karunika Choo wrote:
> Mali 5th-Gen AM GPUs expose arbitration registers outside the GPU node.
> The arbitration device contains partition-control and resource-group
> register blocks used to grant, yield, and close access windows.
> 
> Document partition and resource-group child nodes, each with its own
> register range, interrupt and hardware ID.
> 
> Signed-off-by: Karunika Choo <karunika.choo@arm.com>
> ---
>  .../gpu/arm,mali-gen5-am-arbitration.yaml     | 125 ++++++++++++++++++
>  .../bindings/gpu/arm,mali-gen5-am-system.yaml |   9 ++
>  2 files changed, 134 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/gpu/arm,mali-gen5-am-arbitration.yaml
> 
> diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-gen5-am-arbitration.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-gen5-am-arbitration.yaml
> new file mode 100644
> index 0000000000000..9ea2b4bb9a344
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/gpu/arm,mali-gen5-am-arbitration.yaml
> @@ -0,0 +1,125 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +# Copyright 2026 ARM Limited. All rights reserved.
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/gpu/arm,mali-gen5-am-arbitration.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: ARM Mali 5th-Gen GPU Arbitration Device
> +
> +maintainers:
> +  - Liviu Dudau <liviu.dudau@arm.com>
> +  - Boris Brezillon <boris.brezillon@collabora.com>
> +
> +description:
> +  The arbitration device manages partition-control and resource-group blocks.
> +  Each block is described by a child node with its own register range,
> +  interrupt and hardware ID. Partition and resource-group IDs are separate
> +  namespaces. Access-window IDs are global to the GPU.
> +
> +properties:
> +  $nodename:
> +    const: panthor-arbitration

Same comments. I stopped review here except one more point:


> +
> +  compatible:
> +    const: arm,mali-gen5-am-arbitration
> +
> +  "#address-cells": true
> +
> +  "#size-cells": true
> +
> +  ranges: true
> +
> +patternProperties:
> +  "^partition@[0-9a-f]+$":
> +    type: object
> +    additionalProperties: false
> +    description:
> +      Partition control block and its initial resource assignments.
> +
> +    properties:
> +      reg:
> +        maxItems: 1
> +        description: Partition control register range.
> +
> +      interrupts:
> +        maxItems: 1
> +        description: Partition control interrupt.
> +
> +      arm,id:
> +        $ref: /schemas/types.yaml#/definitions/uint32

IDs are not allowed. See writing bindings or DTS101 slides.

Best regards,
Krzysztof

Re: [PATCH v1 18/27] dt-bindings: gpu: panthor: Document AW assignment DT property

[Krzysztof Kozlowski]

On Tue, Sep 22, 2026 at 09:45:12PM +0100, Karunika Choo wrote:
> Introduce arm,access-window-mask property to allow partitions to define
> the assigned access windows at probe time.
> 
> Signed-off-by: Karunika Choo <karunika.choo@arm.com>
> ---
>  .../bindings/gpu/arm,mali-gen5-am-arbitration.yaml     | 10 ++++++++++
>  1 file changed, 10 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-gen5-am-arbitration.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-gen5-am-arbitration.yaml
> index 9ea2b4bb9a344..4e7933829e2be 100644
> --- a/Documentation/devicetree/bindings/gpu/arm,mali-gen5-am-arbitration.yaml
> +++ b/Documentation/devicetree/bindings/gpu/arm,mali-gen5-am-arbitration.yaml
> @@ -52,6 +52,15 @@ patternProperties:
>            Hardware partition control index. Must identify a partition present on
>            the GPU and be unique among this device's partition nodes.
>  
> +      arm,access-window-mask:
> +        $ref: /schemas/types.yaml#/definitions/uint32
> +        maximum: 0xffff
> +        default: 0
> +        description:
> +          Initial access window assignment mask. Bit N selects global
> +          access window ID N. Masks must be disjoint across partitions.
> +          If omitted, no access windows are assigned by default.

You just added this file!

Please read writing bindings document. The bindings MUST BE complete.

Best regards,
Krzysztof